Memory dynamic error correction method and system supporting hybrid check mode

Abstract

The invention discloses a memory dynamic error correction method and system supporting a hybrid check mode, and the method comprises the steps: distributing a predefined number of check structural bodies, and forming an initial linked list; writing a memory initial address, a data length, an error correction code array, a cyclic redundancy check code and a self-checking cyclic redundancy check code of each protected data, and a linked list pointer pointing to a next checking structure body of the same functional block into the initial linked list to obtain a final linked list; in the interrupt thread of the program, a preset error correction code verification mode is adopted in real time, whether the protected data corresponding to the interrupt thread or the data of the structural body is abnormal or not is verified through the final linked list, and when the abnormality occurs, an error mark is marked; and adopting a preset CRC (Cyclic Redundancy Check) mode in a main loop thread of the program, checking the data based on the final linked list, and correcting the protected data marked with the error mark. The method has the outstanding advantages that cost controllability and resource utilization efficiency can be both considered, the application range is large, and safety and stability are high.

Description

Technical Field

[0001] This invention relates to the technical field of power system relay protection, and more specifically, to a memory-based dynamic error correction method and system that supports hybrid verification modes. Background Technology

[0002] In integrated circuits, soft errors refer to temporary errors in memory data caused by high-energy particles or electromagnetic interference. These errors do not cause permanent hardware damage and can be repaired after a system restart. A single event upset (SEU) refers to a bit flip in a memory cell (i.e., a 1 becomes a 0, or a 0 becomes a 1), and is a typical manifestation of a soft error. Past research on soft errors has primarily focused on the aerospace field, where high radiation and reliability requirements are paramount. However, with increasing integration and the ever-expanding chip size in embedded systems, the likelihood of soft errors occurring in embedded systems has significantly increased.

[0003] As my country's power system continues to develop towards intelligence, digitalization, and a high proportion of renewable energy, higher demands are placed on its reliability. Relay protection systems, as a crucial component ensuring the stable operation of smart grids, have seen significant improvements in digitalization and chip-based architecture to meet these requirements and support more advanced and intelligent analysis and decision-making algorithms. Simultaneously, with more devices operating in high-altitude renewable energy power plants, the probability of soft errors in these devices has greatly increased. Soft errors can lead to malfunctions or failures to operate, with consequences ranging from minor grid fluctuations to damage to critical equipment, resulting in significant safety accidents and economic losses. Therefore, preventing soft errors in relay protection devices provides a more solid guarantee for the high-quality development of the new power system.

[0004] To address the issue of memory soft error protection, current methods exist at the hardware, system, and software levels. For hardware, new radiation-resistant technologies can be employed to improve the single-event tolerance of devices. At the system level, built-in error-correcting codes (ECCs), such as parity bits and Hamming codes, can be used to detect and correct errors. At the software level, triple modular redundancy (TMR) can be adopted, which involves copying data three times and using a majority-rule approach to mask errors. Currently, hardware and system-level protection significantly increases production and usage costs, while TMR, although relatively easy to implement, results in substantial resource waste due to the three-part data copying.

[0005] CN117234789A discloses a verification and error correction method, apparatus, electronic device, and storage medium, including burning verification data and error correction data into flash memory; injecting software errors into the verification data to obtain second verification data; generating an error correction test set based on the second verification data and the error correction data; or injecting software errors into the error correction data to obtain second error correction data; generating an error correction test set based on the verification data and the second error correction data; performing an error correction test on the memory to be tested based on the error correction test set; verifying the firmware data for error correction when the error correction test of the memory to be tested is successful; and transferring the firmware data to the storage device when the firmware data passes the error correction verification. However, this patent is a patent application for memory error correction hardware equipment and does not involve an error correction algorithm.

[0006] CN118733312A discloses a memory error correction method, a memory module, a memory controller, and a processor. The method involves the memory controller identifying faulty memory chips in the memory module when error correction of data retrieved from the memory module fails, and then performing error correction again based on the faulty memory chips. However, this patent is for a hardware device for memory error correction and does not involve an error correction algorithm. Summary of the Invention

[0007] To address the shortcomings of existing technologies, such as the inability to balance cost controllability and resource utilization efficiency, limited applicability, and low security and stability, this invention provides a memory dynamic error correction method and system that supports hybrid verification modes.

[0008] The present invention adopts the following technical solution.

[0009] This invention discloses a memory dynamic error correction method supporting mixed verification modes, comprising: Step 1: Allocate a predefined number of verification structures to form an initial linked list; each verification structure includes the memory starting address of the protected data, data length, error correction code array, cyclic redundancy check code, self-checking cyclic redundancy check code, and a linked list pointer pointing to the next verification structure in the same functional block; the functional blocks include the program main loop, Goose deployment, Goose reception, and SV reception. Step 2: Generate the corresponding error correction code array, cyclic redundancy check (CRC) code of the protected data, and self-checking CRC code based on each protected data; write the memory start address, data length, error correction code array, CRC code, self-checking CRC code of each protected data, and the linked list pointer pointing to the next check structure in the same functional block into the initial linked list to obtain the final linked list; Step 3: In the interrupted thread of the program, a preset error correction code verification method is used in real time to verify whether the protected data or the data of the verification structure corresponding to the interrupted thread has an anomaly. When an anomaly occurs, an error flag is marked. In the main loop thread of the program, a preset CRC verification method is used to verify the data based on the final linked list and to correct the protected data marked with an error flag. The interrupted thread includes goose publishing, goose receiving, and SV receiving.

[0010] More preferably, In step 1, the verification structure also includes verification mode and verification status; The verification modes include direct storage mode and 32-bit unsigned integer error correction code mode; The verification status includes normal operation, paused operation requiring error correction, and error correction code recalculation required.

[0011] More preferably, In step 1, the verification structure is divided into a data protection verification structure and a self-verification structure; The preset request protection data is used as the protected data corresponding to the data protection verification structure; the data protection verification structure is used to verify and correct the request protection data. The data protection verification structure is used as the protected data corresponding to the self-verification structure; the self-verification structure is used to verify and correct the data protection verification structure. The number of self-checking structures is calculated based on the number of predefined checking structures and the maximum memory space size that a structure can verify and correct.

[0012] More preferably, After calculating the number of self-checking structures, the memory space occupied by the data protection check structure is divided into segments equal to the number of self-checking structures. Each segment is treated as protected data corresponding to a self-checking structure, and the starting address and data length of each segment are filled into the corresponding self-checking structure.

[0013] More preferably, In step 2, based on the functional block to which the requested protection data belongs, the final linked list to which the data protection verification structure corresponding to the requested protection data belongs is determined; each functional block corresponds to one final linked list.

[0014] More preferably, In step 2, generating a corresponding error correction code array based on each protected data includes: When the memory space occupied by a protected data is less than or equal to the preset memory space size threshold, the verification mode corresponding to the protected data is direct storage mode, and the protected data is backed up as an error correction code array to the corresponding verification structure. When the memory space occupied by a protected data exceeds the memory space size threshold, the verification mode corresponding to the protected data is a 32-bit unsigned integer error correction code mode. An error correction code array is calculated based on the protected data and stored in the corresponding verification structure.

[0015] More preferably, When the verification mode corresponding to a certain requested data is a 32-bit unsigned integer error correction code mode, the number of data protection verification structures to be used is determined based on the memory space occupied by the requested data and the memory space that a structure can verify and correct errors.

[0016] More preferably, When the verification mode of a certain verification structure is 32-bit unsigned integer error correction code mode, check whether the start and end addresses of the protected data corresponding to the verification structure are four-byte aligned. If there is unaligned data, extract the unaligned data and align the extracted unaligned data to four-byte aligned data. Divide the unextracted part of the protected data according to the four-byte aligned data format. Perform bitwise XOR processing on the divided four-byte aligned data and the four-byte aligned data obtained by aligning the unaligned data according to the preset error correction code array generation rules to generate the error correction code array of the verification structure. The preset error correction code array generation rule is to sort the four-byte aligned data obtained by dividing and aligning the unaligned data to obtain four-byte aligned data, encode each number into binary, and for each bit in the binary encoding, perform bitwise XOR on all the four-byte aligned data corresponding to the number with a value of 1 in that bit, as the error correction code in the error correction code array corresponding to that bit.

[0017] More preferably, In step 3, the preset error correction code verification method is used in real time within the interrupted thread of the program. A final linked list is used to verify whether the protected data or the data of the verification structure corresponding to the interrupted thread has become abnormal. When an abnormality occurs, an error flag is marked, including: The system iterates through each data protection verification structure in the final linked list corresponding to the currently interrupted thread to verify whether the corresponding requested data protection has been abnormal. Before verifying whether the corresponding requested data protection has been abnormal based on each data protection verification structure, the system determines whether the verification status of the data protection verification structure is normally enabled. If the system is started normally, the self-checking cyclic redundancy check (CRUD) code of the data protection check structure is recalculated. If the recalculated CRUD code is not equal to the original CRUD code, the data protection check structure itself is considered to have an anomaly, and the check status of the data protection check structure is set to paused and requires error correction. If the recalculated CRUD code is equal to the original CRUD code, the data protection check structure is used to check whether the corresponding requested protection data has an anomaly. If it is not enabled normally, then continue to check whether the verification status of the next data protection verification structure corresponding to the interrupted thread is enabled normally.

[0018] More preferably, Based on each data protection verification structure, verify whether the corresponding requested protection data has an anomaly, including: When the verification mode in the data protection verification structure is 32-bit unsigned integer error correction code mode, the verification status in the data protection verification structure is set to require recalculation of the error correction code. Then, based on the protected data corresponding to the data protection verification structure, the error correction code array is recalculated. It is then determined whether the recalculated error correction code array is equal to the original error correction code array in the data protection verification structure. If they are equal, the verification status of the data protection verification structure is set to normal enabled, and the verification status of the next data protection verification structure corresponding to the interrupted thread is further determined to be normal enabled. If they are not equal, it is determined that the protected data has an anomaly, and the verification status of the data protection verification structure is set to paused and requires error correction. When the verification mode in the data protection verification structure is direct storage mode, it is determined whether the protected data corresponding to the data protection verification structure is consistent with the protected data in the error correction code array of the data protection verification structure. If they are consistent, the verification status of the data protection verification structure is set to normal enabled, and it continues to determine whether the verification status of the next data protection verification structure corresponding to the interrupted thread is normal enabled. If they are inconsistent, it is determined that the protected data corresponding to the data protection verification structure has an anomaly, and the verification status of the data protection verification structure is set to paused and requires error correction.

[0019] More preferably, In step 3, the step of using a preset CRC check method in the main loop thread of the program to check the data based on the final linked list and correct the protected data marked with error flags includes: Using a preset CRC check method, based on each data protection check structure in the final linked list corresponding to the main loop thread, it checks whether the corresponding request protection data is abnormal, and corrects the abnormal request protection data. Using a preset CRC check method, based on each data protection check structure in the final linked list corresponding to each interrupted thread whose check status is normally enabled, the system checks whether the corresponding request protection data has become abnormal, and corrects any abnormal request protection data. When the verification status of a certain data protection verification structure corresponding to a certain interrupted thread is paused and requires error correction, the error correction code array in the data protection verification structure is used to correct the requested protection data that has an exception.

[0020] More preferably, In each data protection verification structure in the final linked list corresponding to the main loop thread and / or a certain interrupted thread, the system verifies whether the corresponding requested protection data is abnormal, and before correcting the abnormal requested protection data, and / or before correcting the abnormal requested protection data by using the error correction code array in the data protection verification structure whose verification status is paused, the system also includes: Recalculate the self-checking cyclic redundancy check (CRC) code of the data protection check structure; determine whether the recalculated CRC code is equal to the original CRC code in the data protection check structure. If so, check whether the corresponding request protection data is abnormal based on the data protection check structure, and correct the abnormal request protection data, or correct the abnormal request protection data based on the error correction code array in the data protection check structure. If not, recalculate the self-checking CRC code of the self-checking structure corresponding to the data protection check structure. Determine whether the recalculated cyclic redundancy check code of the self-checking structure is equal to the original cyclic redundancy check code; if not, return that a restart is required; if yes, recalculate the cyclic redundancy check code of the protected data of the self-checking structure. The system checks if the cyclic redundancy check (CRC) code of the protected data in the recalculated self-checking structure is equal to the CRC code of the original protected data. If so, it checks whether the corresponding requested protection data is abnormal based on the data protection check structure and corrects any abnormal requests, or corrects the abnormal requests based on the error correction code array in the data protection check structure. If not, it recalculates the error correction code array of the self-checking structure, XORs the recalculated error correction code array with the original error correction code array. If the XOR result is 0, it returns that a restart is required; if the XOR result is not 0, it returns that a restart is required. The XOR result determines the abnormal position in the data protection verification structure, and the value at that position is flipped. Then, the cyclic redundancy check code of the protected data in the self-verification structure is recalculated. It is then determined whether the cyclic redundancy check code of the protected data in the recalculated self-verification structure is equal to the cyclic redundancy check code of the original protected data. If not, a restart is required. If yes, based on the data protection verification structure, the corresponding request protection data is checked for abnormality, and the abnormal request protection data is corrected, or the abnormal request protection data is corrected based on the error correction code array in the data protection verification structure.

[0021] More preferably, Using a preset CRC checksum method based on the data protection checksum structure, the system checks whether the corresponding request protection data is abnormal, and corrects any abnormal request protection data, including: Recalculate the cyclic redundancy check (CRQ) code of the protected data in the data protection check structure, and determine whether the recalculated CRQ code of the protected data is equal to the original CRQ code of the protected data. If yes, it is determined that no error correction is needed; if no, the check status of the data protection check structure is set to paused and error correction is required. The error correction code array in the data protection check structure is recalculated, and the recalculated error correction code array is XORed with the original error correction code array. If the XOR result is 0, it is returned that a restart is needed; if the XOR result is not 0, the abnormal position in the data protection check structure is determined based on the XOR result, and the value at that position is flipped. After flipping the value at the abnormal position, the cyclic redundancy check (CR) code of the protected data in the data protection check structure is recalculated. It is then determined whether the CR code of the recalculated protected data is equal to the CR code of the original protected data. If yes, the error correction is considered successful, and the check status in the data protection check structure is set to normal enabled. If no, the error correction is considered unsuccessful, and a restart is required.

[0022] More preferably, When the verification status of a data protection verification structure corresponding to a certain interrupted thread is paused and requires error correction, error correction is performed on the request protection data that has an anomaly based on the error correction code array in the data protection verification structure, including: When the verification mode in the data protection verification structure is direct storage mode, the protected data with abnormality is compared and restored byte by byte with the protected data backed up in the error correction code array of the data protection verification structure. When the verification mode in the data protection verification structure is 32-bit unsigned integer error correction code mode, the error correction code array of the data protection verification structure is recalculated. The recalculated error correction code array is XORed with the original error correction code array. If the XOR result is 0, it returns that a restart is required; if the XOR result is not 0, the abnormal position in the protected data corresponding to the data protection verification structure is determined based on the XOR result, and the value at that position is flipped. After correcting the abnormal request protection data based on the error correction code array in the data protection verification structure, the process also includes recalculating the cyclic redundancy check (CR) code of the protected data in the data protection verification structure, and determining whether the recalculated CR code of the protected data is equal to the original CR code of the protected data. If yes, the error correction is considered successful, and the verification status in the data protection verification structure is set to normal enabled. If no, the error correction is considered unsuccessful, and a restart is required.

[0023] Another aspect of this invention discloses a memory dynamic error correction system supporting a hybrid verification mode based on a memory dynamic error correction method, comprising an initial linked list generation module, a memory registration module, and a memory verification and error correction module: The initial linked list generation module is used to allocate a predefined number of verification structures to form an initial linked list; The memory registration module is used to generate a corresponding error correction code array, a cyclic redundancy check (CRC) code for the protected data, and a self-checking CRC code based on each protected data; and to write the memory start address, data length, error correction code array, CRC code, self-checking CRC code, and a linked list pointer pointing to the next check structure in the same functional block of each protected data into the initial linked list to obtain the final linked list. The memory verification and error correction module is used to verify the protected data or the data of the verification structure itself corresponding to the interrupted thread in real time using a preset error correction code verification method and a final linked list. When an error occurs, an error flag is marked. In the main loop thread of the program, a preset CRC verification method is used to verify the data based on the final linked list and to correct the protected data that has been marked with an error flag.

[0024] Another aspect of this application discloses an electronic device, including a processor and a storage medium; characterized in that: The storage medium is used to store instructions; The processor is configured to operate according to the instructions to execute the aforementioned memory dynamic error correction method supporting mixed verification mode.

[0025] This application also discloses a computer-readable storage medium having a computer program stored thereon, characterized in that the program, when executed by a processor, implements the memory dynamic error correction method supporting mixed verification mode.

[0026] The beneficial effects of this invention are compared with those of the prior art: This invention combines linked list management, multi-level verification, and multi-threaded management mechanisms to correct a single-bit error in a user-specified portion of memory and detect multiple-bit errors, achieving flexible and efficient memory protection.

[0027] This invention provides a dynamic memory error correction method that supports direct storage mode, 32-bit unsigned integer error correction code mode, and CRC check hybrid verification mode. It is a hardware-independent software-based memory verification and error correction method that can verify large amounts of data using relatively little memory (e.g., the current design uses 64 bytes to verify and correct 8K of data). It employs dynamic linked list partitioning management, registering memory blocks to independent linked lists according to functional areas (e.g., main loop, interrupt). Each node contains an address, length, error correction code, and CRC. It provides two verification and error correction modes and is compatible with data blocks starting from any address. A dual verification mechanism is implemented: a 32-bit unsigned integer error correction code is used for fast verification within the interrupt to detect most anomalies; CRC is used for comprehensive verification of all data in the main loop and error correction of abnormal data is performed. A self-protection design enables self-correction functionality.

[0028] This invention also has outstanding advantages such as being able to balance cost controllability and resource utilization efficiency, having a wide range of applications, and high safety and stability. Attached Figure Description

[0029] Figure 1 This is a schematic flowchart illustrating a memory-based dynamic error correction method that supports mixed verification modes; Figure 2 This is a detailed flowchart illustrating the verification and error correction process of a memory-based dynamic error correction method that supports mixed verification modes. Figure 3 This is a simplified system diagram of a memory dynamic error correction system that supports mixed verification mode. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0031] This invention discloses a memory dynamic error correction method supporting mixed verification modes, comprising: like Figure 1 The diagram shown is a schematic flowchart of a memory dynamic error correction method supporting hybrid verification mode proposed in this invention. Figure 2 This describes the detailed process of verification and error correction. This method is suitable for correcting single-bit flip errors in memory and detecting multi-bit flip errors.

[0032] Figure 1 and Figure 2 The memory verification and error correction method includes the following steps: Step 1: Allocate a predefined number of verification structures to form an initial linked list; the verification structure includes the memory starting address of the protected data, data length, error correction code array, verification mode, verification status, cyclic redundancy check code of the protected data, self-verifying cyclic redundancy check code, and a linked list pointer pointing to the next verification structure in the same functional block; the verification mode includes direct storage mode and 32-bit unsigned integer error correction code mode. The verification status includes normal operation, paused modification of memory data, paused error correction, and error correction code recalculation required.

[0033] The functional blocks include the main program loop, goose publishing (publishing substation events for general objects), goose receiving (receiving substation events for general objects), and SV receiving (receiving sampled values); those skilled in the art should know how to allocate a predefined number of verification structures in the remaining memory space of the system, which will not be elaborated here; in particular, for self-verification structures, the linked list pointer pointing to the next verification structure in the same functional block should be replaced with a linked list pointer pointing to the next self-verification structure; The verification structure is divided into a data protection verification structure and a self-verification structure; The preset request protection data is used as the protected data corresponding to the data protection verification structure; the data protection verification structure is used to verify and correct the request protection data. The data protection verification structure is used as the protected data corresponding to the self-verification structure; the self-verification structure is used to verify and correct the data protection verification structure. The number of self-checking structures is calculated based on the predefined number of checking structures, the memory space occupied by one structure, and the maximum memory space that one structure can check and correct, as shown in the following formula: ; in, Indicates the number of predefined validation structures; This represents the maximum memory space size that a structure can use for verification and error correction. Indicates the size of the memory space occupied by a structure; This indicates rounding up to the nearest integer.

[0034] After calculating the number of self-checking structures, the memory space occupied by the data protection check structure is divided into data segments equal to the number of self-checking structures. Each data segment is treated as protected data corresponding to a self-checking structure, and the starting address and data length of the memory of each data segment are filled into the starting address field and data length field of the protected memory in the corresponding self-checking structure.

[0035] In the initial linked list, the linked list pointers pointing to the next verification structure in the same functional block are set to null.

[0036] Step 2: Generate the corresponding error correction code array, cyclic redundancy check (CRC) code of the protected data, and self-checking CRC code based on each protected data; write the memory start address, data length, error correction code array, CRC code, self-checking CRC code of each protected data, and the linked list pointer pointing to the next check structure in the same functional block into the initial linked list to obtain the final linked list; Based on the functional block to which the requested protection data belongs, determine the final linked list to which the data protection verification structure corresponding to the requested protection data belongs; each functional block corresponds to one final linked list; each verification structure forms another final linked list.

[0037] Before calculating the self-checking cyclic redundancy check code, it also includes writing the normal enabled status as the check status into each check structure of each final linked list.

[0038] The generation of corresponding error correction code arrays based on each protected data includes: When the memory space occupied by a protected data is less than or equal to the preset memory space size threshold, the verification mode corresponding to the protected data is direct storage mode, and the original protected data is backed up as an error correction code array to the corresponding verification structure. When the memory space occupied by a protected data item exceeds the memory space size threshold, the verification mode corresponding to the protected data is set to 32-bit unsigned integer error correction code mode. An error correction code array is calculated based on the protected data and stored in the corresponding verification structure. Preferably, the preset memory space size threshold is 4 × n 1 byte, of which, n 1 indicates the number of error correction codes used in the pre-set error correction settings.

[0039] When the verification mode corresponding to a certain data request for protection is a 32-bit unsigned integer error correction code mode, the number of data protection verification structures to be used for the data request for protection is determined based on the memory space occupied by the data request for protection and the memory space that a structure can verify and correct. That is, the memory space occupied by the data request for protection is divided by the maximum memory space that each set of error correction codes can verify, and the calculated result is rounded up to be the number of structures to be used.

[0040] When the verification mode of a certain verification structure is 32-bit unsigned integer error correction code mode, check whether the start and end addresses of the protected data corresponding to the verification structure (part of the requested protection data in the original requested protection data obtained from the aforementioned division, or the data segment) are four-byte aligned. If there is unaligned data, use the corresponding mask to extract the unaligned data and align the extracted unaligned data to four-byte aligned data. Divide the unextracted part of the protected data according to the four-byte aligned data format, and perform bitwise XOR processing on the divided four-byte aligned data and the four-byte aligned data obtained by aligning the unaligned data according to the preset error correction code array generation rules to generate the error correction code array of the verification structure. Those skilled in the art should know how to obtain the corresponding mask and should also know how to align the extracted unaligned data to four-byte aligned data, which will not be elaborated here.

[0041] The preset error correction code array generation rule is as follows: sort the four-byte aligned data obtained from the division and the four-byte aligned data obtained by aligning the unaligned data; encode each index into binary; for each bit in the binary encoding, perform a bitwise XOR operation on all the four-byte aligned data corresponding to the index with a value of 1 at that bit, and use this as the error correction code in the error correction code array corresponding to that bit (here, "that bit" is used for convenience of corresponding to "bit" in binary encoding; since the error correction code is an unsigned integer, "number" is used instead of "that bit" in the following description of the error correction code), as shown in the following formula: (1.2) in, This represents the value of the defined i-th error correction code. i =1,2, , n 1; N This represents the total number of four-byte aligned data, including the extracted start and end data. express N The data in the th k Data ( k (starting from 1) express k In the binary representation of the first i The value of the bit is 1; This indicates bitwise XOR.

[0042] Step 3: In the interrupted thread of the program, a preset error correction code verification method is used in real time to verify whether the protected data or the data of the verification structure corresponding to the interrupted thread has an anomaly. When an anomaly occurs, an error flag is marked. In the main loop thread of the program, a preset CRC verification method is used to verify the data based on the final linked list and to correct the protected data marked with an error flag. The interrupted thread includes goose publishing, goose receiving, and SV receiving.

[0043] The method involves real-time verification using a preset error correction code within the interrupted thread of the program. A final linked list is used to verify whether the protected data or the data of the verification structure corresponding to the interrupted thread has encountered any anomalies. When an anomaly occurs, an error flag is displayed, including: The loop iterates through each data protection verification structure in the final linked list corresponding to the currently interrupted thread, checking whether the corresponding requested protected data has encountered an error. This loop iterates through all the verification structures in the linked list, then starts verifying from the beginning again, until the program stops running at the interruption. The purpose of this loop is to ensure that the protected memory remains error-free during program execution. Verification is only performed once; even if no errors are found after verification, subsequent program execution may still lead to memory errors. Before verifying whether the corresponding requested protected data has encountered an error based on each data protection verification structure, it checks whether the verification status of that data protection verification structure is normally enabled. Based on each data protection verification structure, verify whether the corresponding requested protection data has an anomaly, including: When the verification mode in the data protection verification structure is 32-bit unsigned integer error correction code mode, the verification status in the data protection verification structure is set to require recalculation of the error correction code. Then, based on the protected data corresponding to the data protection verification structure, the error correction code array is recalculated. It is then determined whether the recalculated error correction code array is equal to the original error correction code array in the data protection verification structure. If they are equal, it is determined that the data protection verification structure does not need error correction, and the verification status of the data protection verification structure is set to normal enabled. The verification status of the next data protection verification structure corresponding to the interrupted thread is then checked to see if it is normal enabled. If they are not equal, it is determined that the protected data has an anomaly, and the data protection verification structure needs error correction. The data protection verification structure is then closed, and its verification status is set to paused and error correction required. When the verification mode in the data protection verification structure is direct storage mode, it is determined whether the protected data corresponding to the data protection verification structure is consistent with the original protected data in the error correction code array of the data protection verification structure. If they are consistent, it is determined that the data protection verification structure does not need error correction, the verification status of the data protection verification structure is set to normal enabled, and the verification status of the next data protection verification structure corresponding to the interrupted thread is further determined to be normal enabled. If they are inconsistent, it is determined that the protected data corresponding to the data protection verification structure has an anomaly, the data protection verification structure needs error correction, the data protection verification structure is closed, and the verification status of the data protection verification structure is set to paused and error correction is required.

[0044] The methods for checking errors in interrupts and the main loop are different. Interrupts have shorter execution times, so comparing the original text or calculating the checksum can shorten the computation time; however, the checksum may not detect some specific errors. The main loop has a longer execution time, so CRC checks are performed for more accurate judgment.

[0045] If the system is enabled normally, the self-checking cyclic redundancy check (CRC) code of the data protection verification structure is recalculated. If the recalculated CRC code is not equal to the original CRC code in the data protection verification structure, the data protection verification structure itself is considered abnormal, and the data protection verification structure needs error correction. The data protection verification structure is then closed, meaning its verification status is set to paused and error correction is required. If the recalculated CRC code is equal to the original CRC code in the data protection verification structure, the data protection verification structure is used to verify whether the corresponding requested protection data is abnormal. If it is not enabled normally, and the verification status of the data protection verification structure is paused and requires error correction, then continue to determine whether the verification status of the next data protection verification structure corresponding to the interrupted thread is enabled normally.

[0046] The process of using a preset CRC checksum method in the main loop thread of the program, verifying the data based on the final linked list, and correcting errors in the protected data marked with error flags includes: Using a preset CRC check method, based on each data protection check structure in the final linked list corresponding to the main loop thread, it checks whether the corresponding request protection data is abnormal, and corrects the abnormal request protection data. Using a preset CRC check method, based on each data protection check structure in the final linked list corresponding to each interrupted thread whose check status is normally enabled, the system checks whether the corresponding request protection data has become abnormal, and corrects any abnormal request protection data. Using a preset CRC checksum method based on the data protection checksum structure, the system checks whether the corresponding request protection data is abnormal, and corrects any abnormal request protection data, including: Recalculate the cyclic redundancy check (CRC) code of the protected data in the data protection check structure, and determine whether the recalculated CRC code of the protected data is equal to the original CRC code of the protected data in the data protection check structure. If so, it is determined that no error correction is needed. When the protected data corresponding to the data protection check structure belongs to the main loop thread, or the protected data corresponding to the data protection check structure belongs to an interrupted thread and the check status in the next data protection check structure corresponding to the data protection check structure is normally enabled, continue to use the preset CRC check method. Based on the next data protection check structure corresponding to the data protection check structure, check whether the requested protection data corresponding to the next data protection check structure is abnormal, and correct the abnormal requested protection data. If the If the protected data corresponding to the data protection verification structure belongs to a certain interrupted thread, and the verification status of the next data protection verification structure corresponding to this data protection verification structure is paused and requires error correction, then the requested protected data that has an anomaly is corrected based on the error correction code array in the next data protection verification structure. Otherwise, the verification status of the data protection verification structure is set to paused and requires error correction, i.e., the corresponding verification structure is closed. The error correction code array in the data protection verification structure is recalculated, and the recalculated error correction code array is XORed with the original error correction code array. If every error correction code in the bitwise XOR result is 0, then a restart is required. If there is an error correction code that is not 0 in the bitwise XOR result, then the abnormal position in the data protection verification structure is determined based on the bitwise XOR result, and the value at that position is flipped. After flipping the value at the abnormal location, the cyclic redundancy check (CRC) code of the protected data in the data protection check structure is recalculated. It is then determined whether the recalculated CRC code of the protected data is equal to the original CRC code of the protected data in the data protection check structure. If so, the error correction is considered successful, and the check status in the data protection check structure is set to "normal enabled." This is further confirmed when the protected data corresponding to the data protection check structure belongs to the main loop thread, or when the protected data corresponding to the data protection check structure belongs to an interrupted thread and the check status in the next data protection check structure corresponding to the data protection check structure is [not specified]. During normal startup, the preset CRC check method continues to be used. Based on the next data protection check structure corresponding to the current data protection check structure, it checks whether the requested protection data corresponding to the next data protection check structure is abnormal, and corrects the abnormal requested protection data. If the protected data corresponding to the current data protection check structure belongs to an interrupted thread, and the check status in the next data protection check structure corresponding to the current data protection check structure is paused and requires correction, the abnormal requested protection data is corrected based on the error correction code array in the next data protection check structure. Otherwise, the error correction is judged to have failed, and a restart is required.

[0047] When the verification status of a certain data protection verification structure corresponding to a certain interrupted thread is paused and requires error correction, the request protection data that has an error is corrected based on the error correction code array in the data protection verification structure; the protected data marked with the error flag refers to the data whose verification status of the data verification structure corresponding to the protected data is paused and requires error correction.

[0048] When the verification status of a data protection verification structure corresponding to a certain interrupted thread is paused and requires error correction, error correction is performed on the request protection data that has an anomaly based on the error correction code array in the data protection verification structure, including: When the verification mode in the data protection verification structure is direct storage mode, the protected data with anomalies is compared byte by byte with the original protected data backed up in the error correction code array of the data protection verification structure, and the data is restored to be the same as the protected data backed up in the error correction code array of the data protection verification structure, thus completing the error correction. When the verification mode in the data protection verification structure is 32-bit unsigned integer error correction code mode, the verification status in the data protection verification structure is set to require recalculation of the error correction code. Then, the error correction code array of the data protection verification structure is recalculated. The recalculated error correction code array is XORed with the original error correction code array. If every error correction code in the bitwise XOR result is 0, a restart is required. If there is an error correction code that is not 0 in the bitwise XOR result, the abnormal position in the protected data corresponding to the data protection verification structure is determined based on the bitwise XOR result, and the value at that position is flipped to complete the error correction. After correcting the abnormal request protection data based on the error correction code array in the data protection verification structure, the process also includes recalculating the cyclic redundancy check (CRQ) code of the protected data in the data protection verification structure, and determining whether the recalculated CRQ code of the protected data is equal to the original CRQ code of the protected data in the data protection verification structure. If so, the error correction is considered successful, the verification status in the data protection verification structure is set to normal enabled, and the process continues to determine whether the next verification status corresponding to the data protection verification structure is normal enabled or paused and requires error correction. If not, the error correction is considered unsuccessful, and a restart is required.

[0049] In each data protection verification structure in the final linked list corresponding to the main loop thread and / or a certain interrupted thread, the system verifies whether the corresponding requested protection data is abnormal, and before correcting the abnormal requested protection data, and / or before correcting the abnormal requested protection data by using the error correction code array in the data protection verification structure whose verification status is paused, the system also includes: Recalculate the self-checking cyclic redundancy check (CRC) code of the data protection check structure; determine whether the recalculated CRC code is equal to the original CRC code in the data protection check structure. If so, check whether the corresponding request protection data is abnormal based on the data protection check structure, and correct the abnormal request protection data, or correct the abnormal request protection data based on the error correction code array in the data protection check structure. If not, recalculate the self-checking CRC code of the self-checking structure corresponding to the data protection check structure. Determine whether the recalculated cyclic redundancy check code of the self-checking structure is equal to the original cyclic redundancy check code in the self-checking structure; if not, return that a restart is required; if yes, recalculate the cyclic redundancy check code of the protected data of the self-checking structure. The system checks if the cyclic redundancy check (CRC) code of the protected data in the recalculated self-checking structure is equal to the CRC code of the original protected data in the same self-checking structure. If equal, it checks if the corresponding requested protection data is abnormal based on the data protection check structure and corrects any abnormal requests, or corrects the abnormal requests based on the error correction code array in the data protection check structure. If not equal, it recalculates the error correction code array of the self-checking structure, performs a bitwise XOR operation between the recalculated error correction code array and the original error correction code array. If every error correction code in the bitwise XOR result is 0, it returns that a restart is required. If any error correction code in the bitwise XOR result is 0, it returns that a restart is required. If the error correction code is not 0, the abnormal position in the data protection verification structure is determined based on the bitwise XOR result, and the value of that position is flipped: if the value of that position is 1, it is flipped to 0; if the value of that position is 0, it is flipped to 1. Then, the cyclic redundancy check (CRC) code of the protected data in the self-verification structure is recalculated, and it is determined whether the recalculated CRC code of the protected data in the self-verification structure is equal to the CRC code of the original protected data in the self-verification structure. If not, a restart is required; if yes, based on the data protection verification structure, the corresponding requested protection data is checked for abnormalities, and the abnormal requested protection data is processed accordingly. Error correction is performed on the requested protection data that has an anomaly, or based on the error correction code array in the data protection verification structure. The step of determining the anomaly position in the data protection verification structure based on the bitwise XOR result means determining the anomaly position in the data protection verification structure based on the bits that are 1 in the 32 bits of the error correction code that are not 0 in the bitwise XOR result. Those skilled in the art should be able to determine how to determine the anomaly position in the data protection verification structure based on the bits that are 1 in the 32 bits of the error correction code that are not 0 in the bitwise XOR result, according to the calculation formula for generating the final 32-bit unsigned integer error correction code array. For example, in step 2, the total number of four-byte aligned data in the required protection data corresponding to this verification body is... 5. If the third error correction code in the bitwise XOR result is not 0, and all other error correction codes are 0, and the γ-th bit in the 32 bits of the third error correction code is 1, then the abnormal position in the data protection check structure is determined to be the γ-th bit in the 32 bits of the four-byte aligned data with the sorting order 4 obtained in step 2; if the first and third error correction codes in the bitwise XOR result are not 0, and all other error correction codes are 0, and the γ-th bit in the 32 bits of the first and third error correction codes is 1, then the abnormal position in the data protection check structure is determined to be the γ-th bit in the 32 bits of the four-byte aligned data with the sorting order 5 obtained in step 2; where γ is an integer and γ∈[1,32].

[0050] When data in memory needs to be modified during operation, before the memory modification, a shutdown function is called to disable the verification function of the target block (disabling the verification function of the target block means setting the verification status in the corresponding verification structure to pause memory data modification). After the memory modification, an enable function is called (setting the verification status in the corresponding verification structure to normal enable) to recalculate the corresponding error correction code array, the cyclic redundancy check code of the protected data, and the self-checking cyclic redundancy check code in the corresponding verification body, and restore the verification and error correction of the corresponding verification structure. If error correction is not properly disabled or enabled, a security violation log is recorded and a system alarm is triggered.

[0051] This application also discloses a memory dynamic error correction system based on the aforementioned memory dynamic error correction method, including an initial linked list generation module, a memory registration module, and a memory check and error correction module: The initial linked list generation module is used to allocate a predefined number of verification structures to form an initial linked list; The memory registration module is used to generate a corresponding error correction code array, a cyclic redundancy check (CRC) code for the protected data, and a self-checking CRC code based on each protected data; and to write the memory start address, data length, error correction code array, CRC code, self-checking CRC code, and a linked list pointer pointing to the next check structure in the same functional block of each protected data into the initial linked list to obtain the final linked list. The memory verification and error correction module is used to verify the protected data or the data of the verification structure itself corresponding to the interrupted thread in real time using a preset error correction code verification method and a final linked list. When an error occurs, an error flag is marked. In the main loop thread of the program, a preset CRC verification method is used to verify the data based on the final linked list and to correct the protected data that has been marked with an error flag.

[0052] Example 1 A memory-based dynamic error correction method that supports mixed verification modes, such as Figure 1 and Figure 2 As shown, it includes: Step 1: Allocate a predefined number of validation structures to form an initial linked list; The initialization phase of the system's memory error correction function includes allocating a certain amount of memory space in the remaining system memory to store a predefined number of verification structures. These verification structures are required for verification and error correction, and simultaneously possess verification and error correction functions. The verification structures are divided into two types: data protection verification structures and self-verification structures. The data protection verification structures are used to verify and correct the data to be protected, and the self-verification structures are used to verify and correct the data protection verification structures. Based on the predefined number of verification structures, the maximum memory space size that a structure can verify and correct, and the memory space size occupied by a structure, the number of self-verification structures is calculated and allocated, and an initial linked list is formed based on each verification structure. Those skilled in the art should be able to set the predefined number of verification structures according to the planned memory size for protection. This will not be elaborated upon here. Storage The contiguous memory space used by each verification structure is denoted as the first memory space; The defined verification structure includes the memory start address of the protected data being verified, the data length of the protected data, the verification mode of the protected data, the verification status of the protected data, the error correction code array of the protected memory, the cyclic redundancy check (CRC) code of the protected data, and the self-verification CRC code, as well as a linked list pointer pointing to the next verification structure in the same functional block. The verification modes include direct storage mode and 32-bit unsigned integer error correction code mode; the verification status includes four states: normally enabled, paused memory data modification, paused error correction required, and error correction code recalculation required; the error correction code array is composed of unsigned integer data and is used to verify whether the corresponding memory is faulty; the CRC code of the protected data is the CRC code of the protected data corresponding to this verification structure; the self-verification CRC code is the CRC code used for self-verification of this structure; and the linked list pointers link to the next verification structure in the same block. The functional blocks are divided according to software interrupt functions, including the main loop, goose publish, goose receive, and SV receive; where goose publish, goose receive, and SV receive are all different functions of software interrupts. The main loop is the main loop of any running program in the relay protection device. In particular, for self-checking structures, the linked list pointer pointing to the next check structure in the same functional block should be replaced with a linked list pointer pointing to the next self-checking structure; Each functional block corresponds to a linked list, and all linked lists are stored in the first memory space; each linked list is composed of... A check structure is formed by sequentially connecting some check structures within a check structure. The check structures in each linked list are not necessarily consecutive.

[0053] When initializing the allocated structure, the linked list pointers pointing to the next verification structure in the same functional block must be set to null to prevent the linked list from forming before registration, and the remaining parameters are set to 0; based on the predefined number of verification structures and the size of the storage space occupied by a structure, the number of verification structures n required for self-verification and error correction is determined according to formula (1.1). The first n structures out of a predefined number of verification structures are used for self-verification and error correction. Then, based on the maximum memory length that a structure can verify and correct, the next n structures are used for self-verification and error correction. n The memory space occupied by 0 structures is divided. In a preferred embodiment of the invention, starting from the memory address of the (n+1)th structure, each... l The structure is divided into n parts, each with a length of 0. The memory occupied by each part is less than or equal to the maximum memory length required for verification and error correction of a single structure. The first n structures are used for self-checking and error correction, that is, to check and correct errors in these n portions of space, and to... The first n structures are used to write the addresses and lengths of the n spaces, forming a linked list.

[0054] The formula for calculating the number of self-checking structures n required for self-checking and error correction, based on the predefined number of check structures, the memory space occupied by a structure, and the maximum memory space that a structure can use for check and error correction, is as follows: (1.1) in, This indicates the number of predefined validation structures, and is an integer. This represents the maximum memory space (in bytes) that a structure can use for verification and error correction. This indicates the size of the memory space occupied by a structure (in bytes). This indicates rounding up; those skilled in the art should know how to set the memory space occupied by a structure; preferably, the memory space occupied by the structure is 64 bytes.

[0055] The advantage of formula (1.1) is that, compared to direct allocation, it can accurately calculate the number of structures required for self-checking and error correction based on the predefined number of structures, the maximum memory space size that each structure can use for verification and error correction, and the memory space occupied by each structure. This avoids the problem of insufficient allocation, which would prevent self-correction from being completed, or excessive allocation, which would waste memory.

[0056] Step 2: Generate corresponding error correction code arrays, cyclic redundancy check codes for the protected data, and self-checking cyclic redundancy check codes based on each protected data; write the memory start address, data length, error correction code array, cyclic redundancy check code, self-checking cyclic redundancy check code, and linked list pointers pointing to the next check structure in the same functional block into the initial linked list to obtain the final linked list; The protected data includes preset request protection data and various data protection verification structures; the request protection data is used as the protected data corresponding to the data protection verification structure; the data protection verification structure is used as the protected data corresponding to the self-verification structure.

[0057] In the dynamic memory block registration phase, the starting address, data length, and functional block to which the requested protected data belongs are received. Linked list nodes are dynamically allocated, a corresponding error correction code array is generated, and a Cyclic Redundancy Check (CRC) code is calculated for the requested protected data and its self-verification. Dynamic memory block registration refers to the process of filling the relevant information of the protected memory into each verification structure. Each functional block may have multiple pieces of data that need protection; therefore, each piece of data needs to be divided (based on the maximum memory space that a structure can verify and correct) and registered separately. The process of dividing and registering each piece of data that needs protection is the dynamic allocation of linked list nodes. Each node is a verification structure that records detailed data of the protected memory and a linked list pointer. The number of error correction codes used for error correction is preset to n1, and the number of error correction codes is an unsigned integer (unsigned int). In a preferred embodiment of the present invention, its preferred value is 11. In a preferred embodiment of the present invention, an unsigned integer occupies 4 bytes, that is, the memory space occupied by the error correction code array is 4×n1 bytes. When the memory space occupied by the protected data is less than or equal to the preset memory space size threshold (4×n1 bytes), the direct storage mode is adopted. The "direct storage mode" is stored in the "verification mode" field of the corresponding verification structure, and the original text is backed up to the "error correction code array" field of the corresponding verification structure. When it is greater than the memory space size threshold, the 32-bit unsigned integer error correction code mode is used. The "32-bit unsigned integer error correction code mode" is stored in the "verification mode" field of the corresponding verification structure. The 32-bit unsigned integer error correction code of the data to be protected by the verification body is calculated and stored in the "error correction code array" field of the corresponding verification structure.

[0058] When the verification mode corresponding to a certain requested data is a 32-bit unsigned integer error correction code mode, the number of structures to be used is determined based on the memory space occupied by the requested data and the maximum memory space that each set of error correction codes can verify (i.e., the memory space occupied by the requested data is divided by the maximum memory space that each set of error correction codes can verify, and the result is rounded up to obtain the number of structures to be used). A corresponding node is added after the corresponding functional block, and the memory range information verified by each node is recorded. The memory range information verified by each node includes the starting address, data length, verification mode, error correction code, and CRC information of the memory range verified by that node. Adding a corresponding node after the corresponding functional block means adding a data protection verification structure after the last data protection verification structure in the linked list corresponding to that functional block. That is, a linked list pointer pointing to the next verification structure in the same functional block is added to the last data protection verification structure in the linked list corresponding to that functional block, thus adding a data protection verification structure.

[0059] For step 2, when calculating the error correction code using the 32-bit unsigned integer error correction code mode, first check whether the start and end addresses of the data are four-byte aligned. If there is unaligned data, use the corresponding mask to extract the unaligned part, and align the extracted unaligned data to four-byte aligned data in its original position. Then, according to formula (1.2), perform XOR processing on the remaining four-byte aligned data obtained after extracting the start and end unaligned data from the request protection data, and the four-byte aligned data obtained by aligning the start and end unaligned data, to generate the final 32-bit unsigned integer error correction code array, as shown in the following formula: (1.2) in, This represents the value of the defined i-th error correction code. i =1,2, , n 1; N This indicates the total number of four-byte aligned data in the required protected data corresponding to the verification body. Here, the total number of four-byte aligned data includes the four-byte aligned data obtained by aligning the unaligned data. express N The first of the data k Data ( k (starting from 1) express k In the binary representation of the first i The value of the bit is 1; Indicates bitwise XOR, This means that among N data points, k In the binary representation of the first iThe four-byte aligned data with a value of 1 is XORed bitwise. For example, if there are five four-byte aligned data, the binary representations of these five numbers (1-5) are 001 (binary representation of number 1), 010 (binary representation of number 2), 011 (binary representation of number 3), 100 (binary representation of number 4), and 101 (binary representation of number 5). Each binary number has three bits, which are the 1st, 2nd, and 3rd bits from right to left. i (k) = 1 indicates that the i-th bit of the k-th number is checked. For example, if i equals 1, the i-th error correction code is obtained by XORing the first bit of all four-byte aligned data (001, 010, 011, 100, and 101) that is 1. Specifically, the first, third, and fifth four-byte aligned data are XORed to obtain the first error correction code; the second and third four-byte aligned data are XORed to obtain the second error correction code; and the fourth and fifth four-byte aligned data are XORed to obtain the third error correction code. The values ​​of each error correction code are then stored in the error correction code array field of the check body.

[0060] Step 3, the verification and error correction phase, involves periodically checking the registered data, verifying the data in real time within corresponding interruptions, and marking errors when abnormalities occur in the protected data or the data of the verification structure itself. The main loop then verifies the data and attempts to correct the marked errors. Marking an error means setting the verification status of the data protection verification structure to pause and requiring error correction.

[0061] like Figure 2 As shown, the module first checks the running thread. If the program is running in a soft interrupt thread, it performs 32-bit unsigned integer error correction code verification or original text comparison according to the error correction code verification method, shortening the verification time. It then loops through the currently registered interrupt nodes, marking an error flag when an anomaly is found. Marking an error flag means setting the verification status of the data verification structure corresponding to the protected data to pause and requiring error correction. If the program is running in the main loop thread, it performs CRC verification and, while verifying the memory blocks registered by its own thread, schedules local verification tasks of other threads, marking an error flag when an anomaly is found.

[0062] After receiving an exception flag, the main loop performs the following error location methods: When using direct storage mode, after confirming that the backup data is correct, the exception data is compared with the backup data byte by byte to restore it; when using 32-bit unsigned integer error correction code mode, the difference error location and flip bit are determined by comparing the XOR result of the error correction code and the original error correction code, and an error correction is attempted. The error correction result is then combined with the CRC check result to determine whether the error correction result is correct.

[0063] When data in memory needs to be modified during operation, before the memory modification, a shutdown function is called to disable the verification function of the target block (calling the shutdown function to disable the verification function of the target block means setting the verification status in the corresponding verification structure to pause memory data modification). After the memory modification, an enable function is called (calling the enable function means setting the verification status in the corresponding verification structure to normal enable) to recalculate the corresponding error correction code array, the cyclic redundancy check code of the protected data, and the self-checking cyclic redundancy check code in the corresponding verification body, and restore the verification and error correction functions of the corresponding verification structure. If it is detected that the verification status is not set to pause memory data modification properly or that the verification status in the corresponding verification structure is set to normal enable after memory modification fails, a security violation log is recorded and a system alarm is triggered.

[0064] Example 2 A memory-based dynamic error correction system that supports mixed verification modes, such as Figure 3 The simplified system architecture shown includes an initial module for memory error correction, a memory registration module, a memory verification and error correction module, a verification shutdown module, and a verification startup module.

[0065] The initial module of the memory error correction function is used to initialize the allocated memory and linked lists when the system starts up; The memory registration module is used to accept protected memory requests, dynamically allocate linked list nodes, and calculate error correction codes and CRC. The memory verification and error correction module is used to verify data within an interrupt and to perform verification and error correction in the main loop. The closed verification module and the open verification module are used to close verification before modifying memory data and to reopen verification after modifying the data.

[0066] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0067] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0068] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0069] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A memory dynamic error correction method supporting mixed verification mode, characterized in that, include: Step 1: Allocate a predefined number of validation structures to form an initial linked list; The verification structure includes the memory starting address of the protected data, the data length, the error correction code array, the cyclic redundancy check code, the self-checking cyclic redundancy check code, and a linked list pointer pointing to the next verification structure in the same functional block; the functional block includes the program main loop, goose deployment, goose reception, and SV reception; Step 2: Generate the corresponding error correction code array, cyclic redundancy check (CRC) code of the protected data, and self-checking CRC code based on each protected data; write the memory start address, data length, error correction code array, CRC code, self-checking CRC code of each protected data, and the linked list pointer pointing to the next check structure in the same functional block into the initial linked list to obtain the final linked list; Step 3: In the interrupted thread of the program, a preset error correction code verification method is used in real time. The final linked list is used to verify whether the protected data or the data of the verification structure corresponding to the interrupted thread has been abnormal. When an abnormality occurs, an error flag is marked. In the main loop thread of the program, a preset CRC check method is used to check the data based on the final linked list and correct the protected data that has been marked with error flags. The interrupted threads include goose publish, goose receive, and SV receive.

2. The memory dynamic error correction method according to claim 1, characterized in that: In step 1, the verification structure also includes verification mode and verification status; The verification modes include direct storage mode and 32-bit unsigned integer error correction code mode; The verification status includes normal operation, paused operation requiring error correction, and error correction code recalculation required.

3. The memory dynamic error correction method according to claim 1, characterized in that: In step 1, the verification structure is divided into a data protection verification structure and a self-verification structure; The preset request protection data is used as the protected data corresponding to the data protection verification structure; the data protection verification structure is used to verify and correct the request protection data. The data protection verification structure is used as the protected data corresponding to the self-verification structure; the self-verification structure is used to verify and correct the data protection verification structure. The number of self-checking structures is calculated based on the number of predefined checking structures and the maximum memory space size that a structure can verify and correct.

4. The memory dynamic error correction method according to claim 3, characterized in that: After calculating the number of self-checking structures, the memory space occupied by the data protection check structure is divided into segments equal to the number of self-checking structures. Each segment is treated as protected data corresponding to a self-checking structure, and the starting address and data length of each segment are filled into the corresponding self-checking structure.

5. The memory dynamic error correction method according to claim 3, characterized in that: In step 2, based on the functional block to which the requested protection data belongs, the final linked list to which the data protection verification structure corresponding to the requested protection data belongs is determined; Each functional block corresponds to a final linked list.

6. The memory dynamic error correction method according to claim 1, 2, 3, or 4, characterized in that: In step 2, generating a corresponding error correction code array based on each protected data includes: When the memory space occupied by a protected data is less than or equal to the preset memory space size threshold, the verification mode corresponding to the protected data is direct storage mode, and the protected data is backed up as an error correction code array to the corresponding verification structure. When the memory space occupied by a protected data exceeds the memory space size threshold, the verification mode corresponding to the protected data is a 32-bit unsigned integer error correction code mode. An error correction code array is calculated based on the protected data and stored in the corresponding verification structure.

7. The memory dynamic error correction method according to claim 6, characterized in that: When the verification mode corresponding to a certain requested data is a 32-bit unsigned integer error correction code mode, the number of data protection verification structures to be used is determined based on the memory space occupied by the requested data and the memory space that a structure can verify and correct errors.

8. The memory dynamic error correction method according to claim 2 or 7, characterized in that: When the verification mode of a certain verification structure is 32-bit unsigned integer error correction code mode, check whether the start and end addresses of the protected data corresponding to the verification structure are four-byte aligned. If there is unaligned data, extract the unaligned data and align the extracted unaligned data into four-byte aligned data. The unextracted portion of the protected data is divided into four-byte aligned data format. The four-byte aligned data obtained from the division and the four-byte aligned data obtained by aligning the unaligned data are then subjected to bitwise XOR processing according to the preset error correction code array generation rules to generate the error correction code array of the verification structure. The preset error correction code array generation rule is to sort the four-byte aligned data obtained by dividing and aligning the unaligned data to obtain four-byte aligned data, encode each number into binary, and for each bit in the binary encoding, perform bitwise XOR on all the four-byte aligned data corresponding to the number with a value of 1 in that bit, as the error correction code in the error correction code array corresponding to that bit.

9. The memory dynamic error correction method according to claim 1, 2, or 5, characterized in that: In step 3, the preset error correction code verification method is used in real time within the interrupted thread of the program. A final linked list is used to verify whether the protected data or the data of the verification structure corresponding to the interrupted thread has become abnormal. When an abnormality occurs, an error flag is marked, including: The system iterates through each data protection verification structure in the final linked list corresponding to the currently interrupted thread to verify whether the corresponding requested data protection has been abnormal. Before verifying whether the corresponding requested data protection has been abnormal based on each data protection verification structure, the system determines whether the verification status of the data protection verification structure is normally enabled. If the system is started normally, the self-checking cyclic redundancy check (CRUD) code of the data protection check structure is recalculated. If the recalculated CRUD code is not equal to the original CRUD code, the data protection check structure itself is considered to have an anomaly, and the check status of the data protection check structure is set to paused and requires error correction. If the recalculated CRUD code is equal to the original CRUD code, the data protection check structure is used to check whether the corresponding requested protection data has an anomaly. If it is not enabled normally, then continue to check whether the verification status of the next data protection verification structure corresponding to the interrupted thread is enabled normally.

10. The memory dynamic error correction method according to claim 9, characterized in that: Based on each data protection verification structure, verify whether the corresponding requested protection data has an anomaly, including: When the verification mode in the data protection verification structure is 32-bit unsigned integer error correction code mode, the verification status in the data protection verification structure is set to require recalculation of the error correction code. Then, based on the protected data corresponding to the data protection verification structure, the error correction code array is recalculated. It is then determined whether the recalculated error correction code array is equal to the original error correction code array in the data protection verification structure. If they are equal, the verification status of the data protection verification structure is set to normal enabled, and the verification status of the next data protection verification structure corresponding to the interrupted thread is further determined to be normal enabled. If they are not equal, it is determined that the protected data has an anomaly, and the verification status of the data protection verification structure is set to paused and requires error correction. When the verification mode in the data protection verification structure is direct storage mode, it is determined whether the protected data corresponding to the data protection verification structure is consistent with the protected data in the error correction code array of the data protection verification structure. If they are consistent, the verification status of the data protection verification structure is set to normal enabled, and it continues to determine whether the verification status of the next data protection verification structure corresponding to the interrupted thread is normal enabled. If they are inconsistent, it is determined that the protected data corresponding to the data protection verification structure has an anomaly, and the verification status of the data protection verification structure is set to paused and requires error correction.

11. The memory dynamic error correction method according to claim 1, 2, 5, or 10, characterized in that: In step 3, the step of using a preset CRC check method in the main loop thread of the program to check the data based on the final linked list and correct the protected data marked with error flags includes: Using a preset CRC check method, based on each data protection check structure in the final linked list corresponding to the main loop thread, it checks whether the corresponding request protection data is abnormal, and corrects the abnormal request protection data. Using a preset CRC check method, based on each data protection check structure in the final linked list corresponding to each interrupted thread whose check status is normally enabled, the system checks whether the corresponding request protection data has become abnormal, and corrects any abnormal request protection data. When the verification status of a certain data protection verification structure corresponding to a certain interrupted thread is paused and requires error correction, the error correction code array in the data protection verification structure is used to correct the requested protection data that has an exception.

12. The memory dynamic error correction method according to claim 11, characterized in that: In each data protection verification structure in the final linked list corresponding to the main loop thread and / or a certain interrupted thread, the system verifies whether the corresponding requested protection data is abnormal, and before correcting the abnormal requested protection data, and / or before correcting the abnormal requested protection data by using the error correction code array in the data protection verification structure whose verification status is paused, the system also includes: Recalculate the self-checking cyclic redundancy check (CRC) code of the data protection check structure; determine whether the recalculated CRC code is equal to the original CRC code in the data protection check structure. If so, check whether the corresponding request protection data is abnormal based on the data protection check structure, and correct the abnormal request protection data, or correct the abnormal request protection data based on the error correction code array in the data protection check structure. If not, recalculate the self-checking CRC code of the self-checking structure corresponding to the data protection check structure. Determine whether the recalculated cyclic redundancy check code of the self-checking structure is equal to the original cyclic redundancy check code; if not, return that a restart is required; if yes, recalculate the cyclic redundancy check code of the protected data of the self-checking structure. The system checks if the cyclic redundancy check (CRC) code of the protected data in the recalculated self-checking structure is equal to the CRC code of the original protected data. If so, it checks whether the corresponding requested protection data is abnormal based on the data protection check structure and corrects any abnormal requests, or corrects the abnormal requests based on the error correction code array in the data protection check structure. If not, it recalculates the error correction code array of the self-checking structure, XORs the recalculated error correction code array with the original error correction code array. If the XOR result is 0, it returns that a restart is required; if the XOR result is not 0, it returns that a restart is required. The XOR result determines the abnormal position in the data protection verification structure, and the value at that position is flipped. Then, the cyclic redundancy check code of the protected data in the self-verification structure is recalculated. It is then determined whether the cyclic redundancy check code of the protected data in the recalculated self-verification structure is equal to the cyclic redundancy check code of the original protected data. If not, a restart is required. If yes, based on the data protection verification structure, the corresponding request protection data is checked for abnormality, and the abnormal request protection data is corrected, or the abnormal request protection data is corrected based on the error correction code array in the data protection verification structure.

13. The memory dynamic error correction method according to claim 11, characterized in that: Using a preset CRC checksum method based on the data protection checksum structure, the system checks whether the corresponding request protection data is abnormal, and corrects any abnormal request protection data, including: Recalculate the cyclic redundancy check (CRQ) code of the protected data in the data protection check structure, and determine whether the recalculated CRQ code of the protected data is equal to the original CRQ code of the protected data. If yes, it is determined that no error correction is needed; if no, the check status of the data protection check structure is set to paused and error correction is required. The error correction code array in the data protection check structure is recalculated, and the recalculated error correction code array is XORed with the original error correction code array. If the XOR result is 0, it is returned that a restart is needed; if the XOR result is not 0, the abnormal position in the data protection check structure is determined based on the XOR result, and the value at that position is flipped. After flipping the value at the abnormal position, the cyclic redundancy check (CR) code of the protected data in the data protection check structure is recalculated. It is then determined whether the CR code of the recalculated protected data is equal to the CR code of the original protected data. If yes, the error correction is considered successful, and the check status in the data protection check structure is set to normal enabled. If no, the error correction is considered unsuccessful, and a restart is required.

14. The memory dynamic error correction method according to claim 11, characterized in that: When the verification status of a data protection verification structure corresponding to a certain interrupted thread is paused and requires error correction, error correction is performed on the request protection data that has an anomaly based on the error correction code array in the data protection verification structure, including: When the verification mode in the data protection verification structure is direct storage mode, the protected data with abnormality is compared and restored byte by byte with the protected data backed up in the error correction code array of the data protection verification structure. When the verification mode in the data protection verification structure is 32-bit unsigned integer error correction code mode, the error correction code array of the data protection verification structure is recalculated. The recalculated error correction code array is XORed with the original error correction code array. If the XOR result is 0, it returns that a restart is required; if the XOR result is not 0, the abnormal position in the protected data corresponding to the data protection verification structure is determined based on the XOR result, and the value at that position is flipped. After correcting the abnormal request protection data based on the error correction code array in the data protection verification structure, the process also includes recalculating the cyclic redundancy check (CR) code of the protected data in the data protection verification structure, and determining whether the recalculated CR code of the protected data is equal to the original CR code of the protected data. If yes, the error correction is considered successful, and the verification status in the data protection verification structure is set to normal enabled. If no, the error correction is considered unsuccessful, and a restart is required.

15. A memory dynamic error correction system utilizing the memory dynamic error correction method according to any one of claims 1-14, characterized in that, It includes an initial linked list generation module, a memory registration module, and a memory verification and error correction module: The initial linked list generation module is used to allocate a predefined number of verification structures to form an initial linked list; The memory registration module is used to generate a corresponding error correction code array, a cyclic redundancy check (CRC) code for the protected data, and a self-checking CRC code based on each protected data; and to write the memory start address, data length, error correction code array, CRC code, self-checking CRC code, and a linked list pointer pointing to the next check structure in the same functional block of each protected data into the initial linked list to obtain the final linked list. The memory verification and error correction module is used to verify the protected data or the data of the verification structure itself corresponding to the interrupted thread in real time using a preset error correction code verification method and a final linked list to verify whether any abnormality has occurred. When an abnormality occurs, an error flag is marked. The program's main loop thread uses a preset CRC check method to verify the data based on the final linked list and correct the protected data that has been marked with error flags.

16. A terminal, comprising a processor and a storage medium; characterized in that: The storage medium is used to store instructions; The processor is configured to operate according to the instructions to perform the steps of the memory dynamic error correction method according to any one of claims 1-14.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the memory dynamic error correction method according to any one of claims 1-14.

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