Bioelectric signal recognition model and reconfigurable hardware accelerator thereof

Abstract

The invention discloses a bio-electricity signal recognition model and a reconfigurable hardware accelerator thereof, which adopt a multi-view learning method to comprehensively extract feature information from a plurality of feature views of bio-electricity signal data, can more comprehensively capture various characteristics of signals, and improve the recognition accuracy of the bio-electricity signals. The method comprises the following steps: firstly, learning initial features of three views by adopting a deep neural network to extract deep features; secondly, the depth features of all the views are fused to form a unified multi-view feature representation; and finally, inputting the fused multi-view features into a multi-layer perceptron for further feature learning to obtain a classification result, and finally completing the classification decision of the bio-electricity signals. A reconfigurable computing array is integrated in the reconfigurable hardware accelerator, dynamic multiplexing of hardware resources can be achieved through a time division multiplexing mechanism, a fast Fourier transform computing mode or a neural network reasoning computing mode is dynamically configured according to needs at different computing stages, and extra computing resources do not need to be introduced. Through the reconfigurable design, the overall area of the accelerator is reduced, and the utilization rate of computing resources is improved; data interaction is carried out among the modules through the data interfaces, instruction transmission is completed through the instruction interfaces, flexible reconstruction can be achieved, and it is ensured that in a bio-electricity signal processing task, different calculation stages are efficiently executed.

Description

[0001] This application claims priority to Chinese Patent Application No. 202511718543.1, filed on November 21, 2025, entitled "A Bioelectric Signal Recognition Model and Its Reconfigurable Hardware Accelerator", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of bioelectric signal detection technology, and in particular to a bioelectric signal recognition model and its reconfigurable hardware accelerator. Background Technology

[0003] In the field of bioelectrical signal detection, the classification and recognition of bioelectrical signals mainly involves four key processing stages: data acquisition, signal preprocessing, feature extraction, and classification. In the feature extraction and classification stages, employing machine learning or deep learning methods to analyze and model the extracted features can improve the accuracy of bioelectrical signal recognition.

[0004] For bioelectrical signals, feature extraction mainly includes three types: time-domain features, frequency-domain features, and time-frequency-domain features. These three types of features reflect the statistical properties, spectral characteristics, and dynamic features of bioelectrical signals over time from different perspectives. When only one type of feature is extracted to build a recognition model, important information from other feature types may be overlooked, thus limiting the model's discriminative ability. Therefore, effectively fusing different types of features is a key challenge for improving model performance.

[0005] Among related solutions, multi-view fusion methods can be used to construct models. One approach is pixel-level fusion, which directly concatenates or weights the initial features of different views during the data input stage to form a new fused feature. Although this method can preserve the original information to the greatest extent, it significantly increases computational complexity and may introduce redundant data, leading to a substantial increase in the overhead of pattern training and inference. Another approach is decision-level fusion, which merges decisions at the output stage of multiple independent models or classifiers. The initial features of each view are first extracted and classified through independent sub-networks, and the classification result is finally obtained through voting, weighted averaging, or other methods. While this approach offers some flexibility, the final decision result is limited by the independent decision-making ability of each sub-network. If the decision result of a certain view is unreliable, the overall recognition performance will be affected. Therefore, a new fusion strategy is needed to construct a bioelectrical signal recognition model. Summary of the Invention

[0006] This invention provides a bioelectric signal recognition model and its reconfigurable hardware accelerator to address the problem of low recognition performance in existing technologies.

[0007] In a first aspect, this application provides a bioelectrical signal recognition model, including: A deep temporal feature extraction module is used to extract deep temporal features from the temporal features extracted from the original bioelectrical signals; the original bioelectrical signals include electroencephalogram (EEG) signals and / or electromyogram (EMG) signals. The depth frequency domain feature extraction module is used to extract depth frequency domain features from the frequency domain features extracted from the original bioelectric signals. The deep time-frequency domain feature extraction module is used to extract deep time-frequency domain features from the time-frequency domain features extracted from the original bioelectrical signals. The feature fusion module is used to adaptively weight and fuse the depth temporal features, depth frequency features, and depth temporal frequency features to obtain multi-view depth features. The multi-layer perception decision module is used to classify the multi-view depth features to obtain the recognition result.

[0008] In some embodiments, the feature fusion module is further configured to: Based on the importance weights of the time-domain features, frequency-domain features, and time-frequency-domain features, the depth time-domain features, depth frequency-domain features, and depth time-frequency-domain features are adaptively weighted and fused to obtain multi-view depth features.

[0009] In some embodiments, the model further includes: The model startup module is used to obtain the recognition results of the single-view recognition model on the original bioelectrical signal; If the recognition result is the first result, the depth time-domain feature extraction module, the depth frequency-domain feature extraction module, and the depth time-frequency-domain feature extraction module are invoked to obtain the depth time-domain features, the depth frequency-domain features, and the depth time-frequency-domain features.

[0010] Secondly, this application provides a reconfigurable hardware accelerator, which deploys the bioelectrical signal recognition model described in the first aspect, the reconfigurable hardware accelerator comprising: The calculation module is used to perform calculations on the input data of the bioelectric signal recognition model and obtain the calculation results; The storage module is used to store the input data, intermediate result data, result data, and weight data of the bioelectric signal recognition model. The control module includes a main controller, a data transmission controller, and multiple algorithm controllers; the algorithm controllers include a convolution controller, a fully connected controller, a pooling controller, a vector controller, and a fast Fourier transform controller. The main controller is used to generate control instructions for controlling the computing module and / or storage module based on the input instruction configuration information; The data transmission controller is used to store input data to the storage module and to transmit data stored in the storage module to different storage areas; The algorithm controller is used to respond to the control commands of the main controller, perform corresponding calculations, and output the calculation results to the storage module.

[0011] In some embodiments, the computing module includes: A reconfigurable computing array is used to implement corresponding computational functions under specified computing modes and configuration information; the computing modes include real number multiplication-addition mode, fast Fourier transform mode, and multiply-accumulate tree operation mode; The computing resource controller includes: The decoder is used to receive and decode instruction information, and extract the specified computing mode and configuration information; A reconfiguration controller is used to reconfigure the data paths of the reconfigurable computing array based on computing modes and configuration information; A finite state machine is used to coordinate and control the reconfiguration controller to perform reconfiguration. An input buffer is used to receive the input data; An output buffer is used to output the calculation results.

[0012] In some embodiments, the reconfigurable computing array includes a comparator array and four computing units; each computing unit includes eight multipliers and eight adders; the comparator array includes 16 comparators; The reconfiguration controller is further configured to: The computing unit is reconfigured into a 2-way 4-parallel real number multiplication and accumulation tree operation or a 1-way 8-parallel real number multiplication and accumulation tree operation for convolution calculation; And / or, interconnect the two computing units to reconstruct a 1-way 16-parallel real number multiply-accumulate tree operation for fully connected computation; And / or, refactor the computational unit into a radix-2 fast Fourier transform operation for use in fast Fourier transform calculations.

[0013] Compared with the prior art, the beneficial effects of the present invention are: Compared to traditional machine learning methods, deep neural networks do not rely on complex manual feature extraction processes. They can automatically learn and acquire more discriminative feature representations from input data, which helps improve classification accuracy and significantly reduces the workload of feature engineering, simplifying the entire model design process.

[0014] The reconfigurable hardware accelerator integrates a reconfigurable computing array, enabling dynamic reuse of hardware resources through time-division multiplexing. It can be dynamically configured to either Fast Fourier Transform (FFT) or neural network inference modes as needed at different computational stages, without introducing additional computing resources. This reconfigurable design reduces the overall accelerator area and improves computing resource utilization. Furthermore, based on a programmable configuration interface, RHA-BP supports multifunctional bioelectrical signal processing tasks, including epilepsy detection and gesture recognition. It also allows for flexible deployment of single-view and multi-view inference models. The single-view inference model can be designed in the time domain, frequency domain, or time-frequency domain, making it widely applicable in the field of bioelectrical signal recognition. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of the bioelectric signal recognition model in the embodiments of this application.

[0017] Figure 2 An architecture diagram of a reconfigurable hardware accelerator provided in an embodiment of this application; Figure 3 An architecture diagram of the computing module in a reconfigurable hardware accelerator provided in this application embodiment; Figure 4 An architecture diagram of a single PE provided in an embodiment of this application; Figure 5 This is a data flow diagram of two interconnected real number multiplication and accumulation tree operations provided in an embodiment of this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application.

[0019] First, the concepts involved in the embodiments of this application will be explained: EEG signal: Electroencephalogram (EEG) signal recorded by an EEG acquisition system; EMG signal, an electromyographic signal recorded by a surface electromyography acquisition system; FFT: Fast Fourier Transform; The Multi-view Learning-based Bioelectrical Signal Recognition Model (MVB-Net) is used to perform bioelectrical signal recognition tasks.

[0020] The network consists of a Deep Temporal Feature Extraction Subnetwork (DTS), a Deep Frequency Feature Extraction Subnetwork (DFS), and a Deep Time-Frequency Feature Extraction Subnetwork (DTFS).

[0021] For bioelectrical signals, feature extraction mainly includes three types: time-domain features, frequency-domain features, and time-frequency-domain features. These three types of features each reflect the statistical properties, spectral characteristics, and dynamic features of bioelectrical signals over time from different perspectives. When only one type of feature is extracted to build a recognition model, important information from other feature types may be overlooked, thus limiting the model's discriminative ability.

[0022] In bioelectrical signal recognition tasks, while pixel-level fusion can preserve complete original information, directly splicing initial features from multiple views may lead to information redundancy and make it difficult to fully explore the complex patterns of bioelectrical signals, thus affecting classification performance. Decision-level fusion constructs three sub-networks to learn the initial features of three views respectively, and then merges their respective classification results. Although it has a certain degree of flexibility, the final decision result is limited by the independent decision-making ability of each sub-network. If the decision result of a certain view is unreliable, the overall recognition performance will be affected.

[0023] It should be noted that, in the solutions provided in this application, the bioelectric signal recognition task can have a variety of different recognition tasks depending on the scenario. For example, when used for epilepsy detection, the corresponding bioelectric signal can be an electroencephalogram (EEG) signal, and when used for gesture recognition, the corresponding bioelectric signal can be an electromyogram (EMG) signal. This application uses these two scenarios as examples for explanation and illustration, and does not represent a limitation on specific application scenarios.

[0024] To address the aforementioned issues, this application provides a bioelectrical signal recognition model based on multi-view learning. By employing a feature-level fusion strategy, the model's dependence on a single view can be effectively reduced, thereby improving the accuracy and robustness of the recognition.

[0025] like Figure 1 As shown, a bioelectrical signal recognition model based on multi-view learning includes: a deep temporal feature extraction module, a deep frequency domain feature extraction module, a deep time-frequency domain feature extraction module, a feature fusion module, and a multilayer perception decision module. The deep temporal, deep frequency, and deep time-frequency domain feature extraction modules primarily use a convolutional neural network (CNN) as the backbone network for feature extraction. Through forward propagation, the CNN calculates the output and evaluates the error based on the loss function. Backpropagation is used to optimize the network parameters, gradually improving model performance. Finally, the output of the last layer of the CNN is selected as the deep feature for subsequent fusion and classification tasks. Compared to the initial features, the deep features extracted by the CNN have lower dimensionality, effectively reducing redundant data while retaining key information, thus reducing computational complexity. Furthermore, since bioelectrical signals typically exhibit complex nonlinear and time-varying characteristics, the deep features extracted by the CNN can effectively capture these complex patterns and dynamic changes, providing rich and meaningful multi-view feature information for subsequent feature-level fusion. This information complementarity not only enhances the synergy between views in the multi-view learning framework, but also significantly improves the model's discrimination ability in complex tasks, thereby improving the model's accuracy and robustness.

[0026] Specifically, the deep temporal feature extraction module is used to extract deep temporal features from the temporal features extracted from the original bioelectrical signals; the original bioelectrical signals include electroencephalogram (EEG) signals and / or electromyogram (EMG) signals. The feature fusion module is used to adaptively weight and fuse depth time-domain features, depth frequency-domain features, and depth time-frequency-domain features to obtain multi-view depth features. In the embodiments of this application, different features reveal the dynamic changes and discrimination information of bioelectric signals from different perspectives. For example, time-domain features reflect the fluctuation patterns of bioelectric signals over time, such as amplitude changes, peaks, and waveform morphology, which are suitable for capturing epileptic seizures or changes between different hand gestures; frequency-domain features reveal the energy distribution of the signal at different frequency components, which are suitable for mining rhythmic activities in bioelectric signals; and time-frequency-domain features integrate time and frequency information, enabling the location of spectral changes within a specific time period and improving the ability to distinguish non-stationary signals.

[0027] The multi-view feature decision module is used to classify multi-view depth features to obtain recognition results. By stacking multiple nonlinear transformation layers, the multi-view feature decision module has strong feature transformation and decision-making capabilities. It can further refine the fused features, enhance feature components that are highly correlated with the target category, and suppress redundant and noise information, thereby improving the model's recognition performance for complex epileptic EEG and EMG signals.

[0028] For example, in an epilepsy detection task, adaptive weighted fusion of time-domain, frequency-domain, and time-frequency-domain depth features learned from three views yields a multi-view depth feature comprehensively representing EEG signal information. This feature is then classified using a multilayer perceptron, resulting in a binary classification to complete the epilepsy EEG signal recognition task. Similarly, in a gesture recognition task, adaptive weighted fusion of three single-view depth features produces a multi-view depth feature representing electromyographic (EMG) signal information. This feature is then classified using a multilayer perceptron to complete the gesture recognition task.

[0029] Through this adaptive weighted fusion mechanism, MVB-Net can dynamically adjust the contribution of each view according to the characteristics of the sample features, suppress redundant or irrelevant information interference, enhance the discriminativeness and generalization ability of the final fused features, and thus effectively improve the flexibility and robustness of the overall feature representation.

[0030] In some embodiments, when designing the feature fusion module, an adaptive weighted fusion strategy can be adopted to automatically learn and assign importance weights to different views, dynamically highlighting more discriminative feature views. For example, in some epileptic seizure patterns, frequency domain features may carry more significant representational information, while in other cases, time domain or time-frequency domain features may be more representative. Therefore, the feature fusion module is also used for: Based on the importance weights of time-domain features, frequency-domain features, and time-frequency-domain features, an adaptive weighted fusion of depth time-domain features, depth frequency-domain features, and depth time-frequency-domain features is performed to obtain multi-view depth features. In this way, the weighted fusion result can be adjusted based on different weight values ​​to meet the needs of different scenarios.

[0031] In some embodiments, while deep neural networks can improve classification accuracy compared to traditional machine learning methods, this performance improvement comes at the cost of increased computational complexity. This leads to higher power consumption during hardware design and deployment, especially in applications such as embedded or resource-constrained medical devices, where the hardware overhead is even more pronounced.

[0032] Because bioelectrical signals remain stable for most of the time, they only exhibit specific patterns with diagnostic value for short periods; for example, seizures in epileptic patients account for only 0.01% of the total time. In most bioelectrical signal processing tasks, there are far fewer difficult-to-classify samples than easy-to-classify samples. Continuously activating a computationally complex multi-view deep neural network model to process all samples is not optimal. A more targeted classification strategy should be adopted, optimizing for low power consumption while ensuring classification performance. In some embodiments, the model provided in this application also includes: The model startup module is used to obtain the recognition results of the single-view recognition model on the original bioelectrical signals; If the recognition result is the first result, the depth time domain feature extraction module, the depth frequency domain feature extraction module, and the depth time-frequency domain feature extraction module are invoked to obtain depth time domain features, depth frequency domain features, and depth time-frequency domain features.

[0033] In this embodiment of the application, a low-power optimization strategy is constructed by deploying a model startup module to reduce the computational complexity and power consumption of deep neural networks in the task of bioelectrical signal recognition.

[0034] Specifically, taking epilepsy recognition as an example, optimization strategies may include: In the first stage, a lightweight single-view recognition model is used to extract features and make classification decisions on the input bioelectrical signals. Since this model relies only on features from the time-domain view, it avoids the additional computational overhead of frequency-domain and time-frequency-domain transformations, significantly reducing the number of model parameters and overall computational complexity. To ensure high overall classification performance across the two stages, this stage employs a conservative decision-making strategy, introducing a weighted cross-entropy loss function. By assigning a higher loss weight to the epileptic seizure category, the model enhances its focus on epileptic seizure samples during training, making the model more inclined to identify input samples as epileptic seizure fragments. This results in a relatively larger number of suspicious samples being output to the second-stage multi-view recognition model for further classification, thereby reducing the risk of missed detections. Therefore, this model features low parameter count, low computational complexity, and high sensitivity, but lower accuracy and specificity. If a sample is identified as a non-epileptic seizure fragment in this stage, the classification result is directly output to reduce unnecessary computational overhead; if the sample is identified as an epileptic seizure fragment, it is further output to the second stage. The second stage then employs a multi-view recognition model with higher accuracy and computational complexity to ensure the reliability of the final classification decision.

[0035] The primary goal of the first stage is to quickly output high-confidence negative samples with low computational overhead, reducing the risk of false negatives and thus minimizing unnecessary computational burden. Simultaneously, it rapidly identifies all possible positive samples and passes them to the second stage for in-depth decision-making. The main goal of the second stage is to accurately distinguish between true positive samples and potential false positives, ensuring the reliability of the final classification decision and reducing the risk of false positives. Because the classification mechanism in the first stage guarantees the model's high sensitivity, the model in the second stage can perform inference on a smaller subset of data, thereby achieving more accurate classification results while keeping overall computational complexity under control.

[0036] As can be seen from the above technical solution, the bioelectrical signal recognition model based on multi-view learning provided in this application first uses a deep neural network to learn the initial features of three views to extract depth features; secondly, the depth features of these views are fused to form a unified multi-view feature representation; finally, the fused multi-view features are input into a multilayer perceptron for further feature learning to obtain classification results, ultimately completing the classification decision for bioelectrical signals. Compared with traditional machine learning methods, deep neural networks do not rely on complex manual feature extraction processes, and can automatically learn and obtain more discriminative feature representations from input data, which helps to improve classification accuracy, while significantly reducing the workload of feature engineering and simplifying the entire model design process.

[0037] In practical applications, with the development of IoT and smart healthcare technologies, there is a need to deploy the bioelectrical signal recognition model provided in the aforementioned embodiments to edge devices, such as wearable devices or implantable medical devices. Edge devices typically have strict hardware limitations, requiring low power consumption, small size, high classification performance, and real-time capabilities. This application also provides a reconfigurable hardware accelerator to meet these hardware-constrained requirements.

[0038] See Figure 2 In some embodiments, a reconfigurable hardware accelerator with the aforementioned bioelectric signal recognition model may include a computing module, a storage module, and a control module, which work together during operation to meet the needs of different computing tasks.

[0039] Specifically, the computing module is used to perform calculations on the input data of the bioelectrical signal recognition model to obtain the calculation results; the computing module includes a reconfigurable computing array and a computing resource controller, as shown in some embodiments. Figure 3The reconfigurable computing array comprises a comparator array and four computational units (PEs); each computational unit includes eight multipliers and eight adders; the comparator array includes 16 comparators, supporting the INT16 data format. The reconfigurable computing array is used to implement corresponding computational functions under specified computational modes and configuration information; the computational modes include real number multiplication-addition mode, fast Fourier transform mode, and multiply-accumulate tree operation mode.

[0040] The compute resource controller is responsible for receiving configuration information from the main controller and reconfiguring the compute array according to the requirements of different algorithms. See also: [link to relevant documentation] in some embodiments. Figure 3 Computational resource controller, including: The decoder receives instruction information from external modules, decodes it, and extracts the required computation mode and configuration information. The reconfiguration controller receives the decoding results from the decoder and reconfigures the data path of the computation array according to the computation mode and configuration information to achieve specific computational functions, including real number multiply-accumulate mode, FFT mode, and multiply-accumulate tree operation mode. The finite state machine module coordinates and controls the reconfiguration of the entire computation process, ensuring that each computational step is executed in sequence. The input buffer receives input data from external modules and provides necessary input to the computation array. The output buffer transmits the computation results to external modules for subsequent computation.

[0041] In some embodiments, when designing a reconfigurable computing array, different configurations can be made according to different computing needs to support multiple parallel computing modes, see [link to relevant documentation]. Figure 4 In this embodiment, the computational unit (PE) can be configured with 8 parallel real-number multiplication operations and 8 parallel real-number addition operations to perform vector computation tasks. In addition, after performing the FFT, the complex number result needs to be squared modulo-1 to obtain a real-number sum of the real and imaginary parts, which serves as the input to the subsequent neural network model. In this case, a PE unit can be reconfigured into a 4-parallel real-number multiplication-addition operation mode. By transforming the square root operation into a multiplication-addition operation, this design avoids nonlinear square root operations, simplifies the computational complexity in hardware implementation, and thus reduces additional computational resource overhead.

[0042] Building upon this foundation, a single PE unit can be flexibly configured as a 2-way 4-parallel real number multiply-accumulate tree operation or a 1-way 8-parallel real number multiply-accumulate tree operation. This configuration allows the PE unit to achieve both high flexibility and efficient computation when performing convolution calculations. Considering that a nonlinear activation function (ReLU) layer usually follows a convolutional layer, this design further optimizes the computation flow by employing a data path that directly performs a sign bit check on the computation result after the multiply-accumulate tree operation. Specifically, when the sign bit of the computation result is 0, the multiply-accumulate tree operation result can be directly output; if the sign bit is 1, 0 is output. This method avoids repeated reading and writing of intermediate computation results and eliminates the need for additional comparator resources, thus improving computational efficiency. In practical applications, the four PE units can be flexibly reconfigured according to computational needs, configured as 8-way 4-parallel or 4-way 8-parallel real number multiply-accumulate tree operations to adapt to the computational requirements of different levels and tasks. Through this dynamic reconfiguration mechanism, the reconfigurable computing array in this design can achieve efficient resource utilization and computing performance optimization, especially in convolution operations, where it can be flexibly configured according to the computing scale and requirements.

[0043] The two PE units are interconnected to enable 16-way parallel real number multiplication and accumulation operations, which are used to perform fully connected operations. Figure 5 The data flow diagram for a real number multiplication and accumulation tree operation interconnected by two PEs is shown. In actual computation, the four PEs can be reconfigured into a 2-way 16-parallel real number multiplication and accumulation tree operation according to different configurations.

[0044] Since FFT operations involve complex number calculations, a single PE unit can also be configured for radix-2 FFT operations. Specifically, four real multipliers and two real adders can be combined into a complex multiply-add unit, forming a single radix-2 FFT butterfly operation unit. For the radix-2 FFT transform, this design employs a decimation-in-frequency (DIF) implementation. The DIF algorithm recursively decomposes the input signal, transforming the original Fourier transform problem into multiple smaller subproblems, making it suitable for parallel hardware implementation and improving the efficiency of FFT computation.

[0045] The FFT controller mainly consists of core modules such as an index generation module, an address generation module, a data distribution module, a state machine module, and a top-level control module.

[0046] The entire FFT module is controlled via a state machine, which contains five states. These states indicate the current FFT operation step and are responsible for generating control signals for other sub-modules, ensuring their timing coordination. The initial state is IDLE. When the algorithm controller receives a start signal, it enters the start state. The controller parses the received point information and jumps to the R2 state according to the rules. After completing the first-level operation, it jumps to the BREAK state. Simultaneously, the controller analyzes whether all operations are complete. If all operations are complete, it jumps to the COMPLETE state. If not, it analyzes whether the radix-2 butterfly operation for all levels is complete. If all levels are complete, it jumps to the SPLIT state. If not, it continues to jump to the R2 state and continues butterfly calculation. This process repeats until all levels and the split-term operation are calculated. The state machine then jumps to the completion state and unconditionally returns to the IDLE state, waiting for the next calculation to begin.

[0047] The data transfer controller includes on-chip data transfer and off-chip data transfer. The off-chip transfer controller, a DMA controller, is responsible for transferring data from external DDR memory to the internal source data area or weighted data area according to the configured memory mode. The on-chip transfer controller is responsible for transferring data between different data areas within the chip, including transferring data from the source data area to the intermediate result data area, from the result data area to the intermediate result data area, and from the intermediate result data area to the result data area. This design allows for flexible data transfer between the source data area, intermediate result data area, and result data area, adapting to different computing modes. It supports both single-view model deployment and multi-view model deployment requirements, enabling the model to run smoothly on the accelerator.

[0048] As can be seen from the above technical solution, the reconfigurable hardware accelerator provided in this application integrates a reconfigurable computing array, enabling dynamic reuse of hardware resources through a time-division multiplexing mechanism. It can be dynamically configured to either Fast Fourier Transform (FFT) computing mode or neural network inference computing mode as needed at different computing stages, without introducing additional computing resources. Through this reconfigurable design, the overall area of ​​the accelerator is reduced, and the utilization rate of computing resources is improved. Furthermore, based on a programmable configuration interface, RHA-BP can support multifunctional bioelectrical signal processing tasks, including epilepsy detection and gesture recognition. It can also flexibly deploy single-view and multi-view inference models. The single-view inference model can be designed based on the time domain, frequency domain, or time-frequency domain, and is widely used in the field of bioelectrical signal recognition.

[0049] The modules of the reconfigurable hardware accelerator interact with each other through a data interface and transmit instructions through an instruction interface, enabling flexible reconfiguration to ensure efficient execution of different computational stages in bioelectric signal processing tasks.

[0050] The above detailed embodiments further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A bioelectrical signal recognition model, characterized in that, The model includes: A deep temporal feature extraction module is used to extract deep temporal features from the temporal features extracted from the original bioelectrical signals; the original bioelectrical signals include electroencephalogram (EEG) signals and / or electromyogram (EMG) signals. The depth frequency domain feature extraction module is used to extract depth frequency domain features from the frequency domain features extracted from the original bioelectric signals. The deep time-frequency domain feature extraction module is used to extract deep time-frequency domain features from the time-frequency domain features extracted from the original bioelectrical signals. The feature fusion module is used to adaptively weight and fuse the depth temporal features, depth frequency features, and depth temporal frequency features to obtain multi-view depth features. The multi-layer perception decision module is used to classify the multi-view depth features to obtain the recognition result.

2. The bioelectrical signal recognition model according to claim 1, characterized in that, The feature fusion module is also used for: Based on the importance weights of the time-domain features, frequency-domain features, and time-frequency-domain features, the depth time-domain features, depth frequency-domain features, and depth time-frequency-domain features are adaptively weighted and fused to obtain multi-view depth features.

3. The bioelectrical signal recognition model according to claim 1, characterized in that, The model also includes: The model startup module is used to obtain the recognition results of the single-view recognition model on the original bioelectrical signal; If the recognition result is the first result, the depth time-domain feature extraction module, the depth frequency-domain feature extraction module, and the depth time-frequency-domain feature extraction module are invoked to obtain the depth time-domain features, the depth frequency-domain features, and the depth time-frequency-domain features.

4. A reconfigurable hardware accelerator, characterized in that, Deploying the bioelectric signal recognition model according to any one of claims 1-3, the reconfigurable hardware accelerator comprises: The calculation module is used to perform calculations on the input data of the bioelectric signal recognition model and obtain the calculation results; The storage module is used to store the input data, intermediate result data, result data, and weight data of the bioelectric signal recognition model. The control module includes a main controller, a data transmission controller, and multiple algorithm controllers; the algorithm controllers include a convolution controller, a fully connected controller, a pooling controller, a vector controller, and a fast Fourier transform controller. The main controller is used to generate control instructions for controlling the computing module and / or storage module based on the input instruction configuration information; The data transmission controller is used to store input data to the storage module and to transmit data stored in the storage module to different storage areas; The algorithm controller is used to respond to the control commands of the main controller, perform corresponding calculations, and output the calculation results to the storage module.

5. The reconfigurable hardware accelerator according to claim 4, characterized in that, The computing module includes: A reconfigurable computing array is used to implement corresponding computational functions under specified computing modes and configuration information; the computing modes include real number multiplication-addition mode, fast Fourier transform mode, and multiply-accumulate tree operation mode; The computing resource controller includes: The decoder is used to receive and decode instruction information, and extract the specified computing mode and configuration information; A reconfiguration controller is used to reconfigure the data paths of the reconfigurable computing array based on computing modes and configuration information; A finite state machine is used to coordinate and control the reconfiguration controller to perform reconfiguration. An input buffer is used to receive the input data; An output buffer is used to output the calculation results.

6. The reconfigurable hardware accelerator according to claim 5, characterized in that, The reconfigurable computing array includes a comparator array and four computing units; each computing unit includes eight multipliers and eight adders; the comparator array includes 16 comparators; The reconfiguration controller is further configured to: The computing unit is reconfigured into a 2-way 4-parallel real number multiplication and accumulation tree operation or a 1-way 8-parallel real number multiplication and accumulation tree operation for convolution calculation; And / or, interconnect the two computing units to reconstruct a 1-way 16-parallel real number multiply-accumulate tree operation for fully connected computation; And / or, refactor the computational unit into a radix-2 fast Fourier transform operation for use in fast Fourier transform calculations.

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