Protected hardware processing device

Abstract

There is provided a hardware processing device comprising (i) a plurality of MAC units arranged to be operable in a secure mode, performing at least one addition of a first value and a second value, where the first value is represented by a number of shares and the second value is represented by the same number of shares; and performing at least one multiplication of the first value and the second value based on the share of the first value, the share of the second value and a random number; and (ii) a multiplexer for switching between a secure mode and a normal mode wherein the plurality of MAC units are arranged to operate on the first value and the second value in the normal mode, rather than on a share of the first value and a share of the second value.

Description

Technical Field

[0001] This disclosure generally relates to the field of artificial intelligence (AI), and in particular to protected hardware processing devices. Background Technology

[0002] Artificial intelligence (AI) accelerators, deep learning processors, or neural processing units (NPUs) are a class of dedicated hardware accelerators or computer systems designed to accelerate artificial intelligence and machine learning applications, including artificial neural networks and computer vision. Exemplary AI integrated circuit chips contain tens of billions of MOSFETs (see, for example, https: / / en.wikipedia.org / wiki / AI_accelerator). This type of dedicated hardware is a specific example of a hardware processing device, also referred to herein as an accelerator. Such accelerators are typically used to speed up computations in neural networks during training or inference.

[0003] The accelerator is vulnerable to attacks such as side-channel analysis (SCA). For example, timing analysis (TA) and simple power analysis (SPA) may reveal at least part of the neural network's topology. Differential power analysis (DPA) or differential fault analysis (DFA) may reveal the neural network's weights, bias constants, and / or activation functions. Furthermore, SCA can be used to extract or modify data processed by the accelerator during training or inference.

[0004] Existing methods do not provide effective protection against any attacks based on SCA, TA, SPA, DPA, or DFA, or provide insufficient protection. Such attacks can also be referred to as side-channel attacks.

[0005] Therefore, the goal is to protect or enhance hardware processing devices, particularly the accelerators, in a cost-effective manner to defend against any such attacks. Summary of the Invention

[0006] The above-mentioned problems are solved by the features of the embodiments disclosed in this disclosure. Further embodiments are obtained based on this disclosure.

[0007] The examples presented in this paper can be based on at least one of the following solutions. In particular, the following features can be combined to achieve the desired results.

[0008] A hardware processing device is proposed, the hardware processing device comprising: Multiple MAC units are arranged to operate in safe mode. Perform at least one addition of a first value and a second value, wherein the first value is represented by a certain number of shares and the second value is represented by the same number of shares; Based on the share of the first value, the share of the second value, and a random number, perform at least one multiplication of the first value and the second value; A multiplexer for switching between a safe mode and a normal mode, wherein the plurality of MAC units are arranged to operate on the first value and the second value in the normal mode, rather than on a share of the first value and a share of the second value.

[0009] It should be noted that, in the context of this application, “random” or “randomization” may specifically refer to true randomness, pseudo-randomness, or even certain deterministic methods that may introduce sufficient entropy levels.

[0010] Switching between safe mode and normal mode introduces the flexibility to perform only those operations that require obfuscation due to potential side-channel attacks in safe mode. This allows the efficiency of the hardware processing device to be adjusted according to predetermined needs or requirements.

[0011] According to one implementation method The number of shares is two; The first value is x, and the length is n, denoted by shares x0 and x1, such that... The second value is y, and the length is n, represented by shares y0 and y1, such that... Addition is performed according to the following formula , Multiplication is performed according to the following formula Where r is a random number.

[0012] According to an embodiment, the hardware processing device further includes a random number generator for determining the random number.

[0013] The random number generator mentioned in this article can specifically provide a predefined level of entropy.

[0014] According to an embodiment, the hardware processing device is a hardware accelerator for neural networks. Attached Figure Description

[0015] Embodiments are shown and described with reference to the accompanying drawings. The drawings are for illustrative purposes only and therefore only show aspects necessary for understanding the basic principles. The drawings are not drawn to scale. In the drawings, the same reference numerals denote similar features.

[0016] Figure 1 A block diagram is shown that visualizes how multiplication can be implemented safely.

[0017] Figure 2 An exemplary implementation of an accelerator utilizing a pipeline is shown.

[0018] Figure 3 A schematic diagram of an alternative accelerator that does not employ a pipeline is shown. Detailed Implementation

[0019] The examples presented in this paper specifically enable randomized masking of the data processed by the accelerator, which can be used to quantify neural network inference.

[0020] An exemplary accelerator for inference is a peripheral that supports DMA (Direct Memory Access) for autonomous evaluation of a quantized neural network. It can include a Single Instruction Multiple Data (SIMD) architecture. Multiple multiply-accumulate (MAC) units can process integer data and fixed-point or floating-point data in parallel. The length of the integer data can be 2 bits, 4 bits, 8 bits, 16 bits, or 32 bits, and the length of the fixed-point or floating-point data can be 8 bits, 16 bits, or 32 bits.

[0021] The examples introduced in this paper include a hardware-level 2-share additive masking scheme. A value x of length n bits is replaced with two shares (x0, x1), each of length n bits, such that: (1)

[0022] Then, a homomorphic approach for addition and multiplication can be applied.

[0023] For example, the addition of two values ​​x and y can be calculated component-wise as follows, where each value is represented by two shares: (2)

[0024] Furthermore, based on the respective shares of values ​​x and y, the multiplication of values ​​x and y corresponds to: (3)

[0025] Here, r is a random value of length n bits. The examples proposed in this paper can effectively utilize existing hardware, particularly SIMD hardware, with only minor modifications. In the exemplary implementation, two MAC units can be used together. Multiplication of shares can be performed in a pipelined manner. Multiplexers can be used to group the MAC units and / or to switch between standard mode (without utilizing any shares and additional data masking) and secure mode (masked addition and multiplication of shares as described above).

[0026] Figure 1 A block diagram is shown illustrating how multiplication can be implemented in the aforementioned safe mode.

[0027] In step 1, multiplication is performed on the shares of values ​​x and y. , Then, the summation is performed: , Where r is a random value.

[0028] In the subsequent step 2, multiplication is performed immediately after accumulation: , Thus, the result is: This corresponds to equation (3) mentioned above.

[0029] Multiplexers can be used to select appropriate inputs for the different multiplications performed in steps 1 and 2. Random sources, such as true random number generators or pseudo random number generators, can be used to generate random values ​​r to refresh the randomization sharing of the computation results.

[0030] Figure 2 An example implementation of equation (3) is shown in an accelerator utilizing a pipeline.

[0031] Instead of values ​​x and y, shared values ​​(x0, x1) and (y0, y1) are provided via memory or register 201. Multiplier (MUL) 202 multiplies value x0 with value y0, multiplier 203 multiplies value x0 with value y1, multiplier 204 multiplies value x1 with value y1, and multiplier 205 multiplies value x1 with value y0.

[0032] Adder (ADD) 206 adds the output of multiplier 202 to the value r to obtain the result. Adder 207 adds the output of multiplier 204 to the negative value r (provided via the inversion processing unit (NEG) 212) to obtain the result. .

[0033] In subsequent clock cycles (indicated by flip-flops 208 to 211, which store partial results and delay them by one clock cycle), Adder 213 adds the output of adder 206 and the output of multiplier 203 to obtain... ,and Adder 214 adds the output of adder 207 and the output of multiplier 205 to obtain... .

[0034] Multiplexers (MUX) 215 and 216 are used to switch between safe mode and normal mode. In safe mode, multiplexer 215 connects the output of adder 213 to register 217 to store the obfuscated value. .

[0035] Accordingly—also in safe mode—multiplexer 216 connects the output of adder 214 to register 217 to store the masked value: .

[0036] However, in normal mode, the output of multiplier 202 is directly connected to register 217 without delay via a flip-flop, thus storing the result of the multiplication. .

[0037] Accordingly, in normal mode, the output of multiplier 204 is connected to register 217 to store the result of the multiplication: .

[0038] In normal mode, x0 and y0 can represent two independent actual values ​​(rather than shares). The same applies to the values ​​x1 and y1.

[0039] For specific operations that require strong protection against side-channel attacks, the switching between normal and secure modes provides high flexibility: secure mode can be used for such operations, while less critical operations that do not require any additive sharing can be executed more quickly.

[0040] Figure 3 A schematic diagram of an alternative implementation that does not employ pipelined methods is shown. The overall functionality of this accelerator is similar to... Figure 2 The accelerator shown is similar.

[0041] Memory or register 301 provides shared values ​​(x0, x1) and shared values ​​(y0, y1). Exchange module 302 is used to exchange values ​​y0 and y1, that is, to provide values ​​y0 and y1 or values ​​y1 and y0 at its two outputs.

[0042] Multiplier 303 multiplies value x0 by value y0, where value y0 is selected via switching module 302. Then, adder 310 adds the output of multiplier 303 to value r to obtain... The value r is selected via multiplexer 305. This result is temporarily stored in a register (indicated by flip-flop 307). In the next clock cycle, multiplexer 305 selects the value stored in flip-flop 307, and multiplier 303 multiplies value x0 with value y1 (which, in the subsequent clock cycle, switching module 302 selects the corresponding other value y1). Therefore, after the second clock cycle, the output of adder 310 is: , It can then be stored in register 314 as z0 via multiplexer 312.

[0043] Accordingly, multiplier 304 multiplies value x1 by value y1, where value y1 is selected via swap module 302. Then, adder 311 adds the output of multiplier 304 to the negative value r (determined via inversion processing unit 309) to obtain... The negative value r is selected via multiplexer 306. This result is temporarily stored in a register (indicated by flip-flop 308). In the next clock cycle, multiplexer 306 selects the value stored in flip-flop 308, and multiplier 304 multiplies value x1 by value y0 (in the subsequent clock cycle, switching module 302 selects the corresponding other value y0). Therefore, after the second clock cycle, the output of adder 311 is: It can then be stored in register 314 as z1 via multiplexer 313.

[0044] This scenario refers to a safe mode in which multiplexers 312 and 313 are switched to store the outputs of adders 310 and 311 (based on the shares described above) in register 314.

[0045] It is important to note that the above example can be supplemented with additional hardware measures to avoid Hamming distance leakage, as is seen in non-pipelined implementations—since the relevant data in steps 1 and 2 are calculated by the same hardware. For example, the data in SIMD register 301 can be swapped in step 2, and multiplexers 305 and 306 can be modified to select equivalent / correct triggers 307 and 308 in step 2. Furthermore, the output values ​​can be swapped to ensure the result in SIMD register 314 is correct. This can be achieved by correspondingly changing the inputs of multiplexers 312 and 313.

[0046] However, in normal mode, multiplexers 312 and 313 can be switched to their other input, which allows the output of multiplier 303 to be directly stored as the value z0 and the output of multiplier 304 to be directly stored as the value z1 without delay via flip-flops. Therefore, in normal mode, multiplication of shared addition data is not performed; only the input values ​​are multiplied directly.

[0047] It's important to note that in normal mode, the values ​​x0, x1, y0, and y1 are independent values ​​being multiplied, not shares. This also applies to... Figure 2 .

Claims

1. A hardware processing device, comprising: Multiple multiply-accumulate MAC units are arranged to operate in safe mode. Perform at least one addition of a first value and a second value, wherein the first value is represented by a certain number of shares, and the second value is represented by the same number of shares; and Based on the share of the first value, the share of the second value, and a random number, perform at least one multiplication of the first value and the second value; as well as A multiplexer for switching between the security mode and the normal mode, wherein the plurality of MAC units are arranged to operate on the first value and the second value in the normal mode, rather than on a share of the first value and a share of the second value.

2. The hardware processing device according to claim 1, in, The number of shares is two; Wherein, the first value is x, the length is n, and it is represented by shares x0 and x1, such that... Wherein, the second value is y, and the length is n, denoted by shares y0 and y1, such that The addition is performed according to the following formula. ， The multiplication is performed according to the following formula. Where r is the random number.

3. The hardware processing device according to any one of the preceding claims, comprising a random number generator for determining the random number.

4. The hardware processing device according to any one of the preceding claims, wherein the hardware processing device is a hardware accelerator for a neural network.

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