A chip driving parameter configuration method and a chip driving parameter configuration device

Abstract

The application relates to the chip technical field and provides a chip driving parameter configuration method and a chip driving parameter configuration device, which can determine initial timing parameters and initial electrical parameters of a target chip for driving an external device to be driven based on working state information of the external device to be driven from a preset correlation relationship, determine a total time delay based on physical topology information between the external device to be driven and the target chip, adjust the initial timing parameters based on the total time delay, and adjust the initial electrical parameters based on electrical constraint information of the external device to be driven, so as to drive the external device to be driven based on the adjusted parameters, avoid the problem of long time consumption of manual configuration, improve the efficiency of chip driving parameter configuration, and make the adjusted parameters more suitable for the current actual deployment scene by adjusting the target initial parameters based on the physical topology information and the electrical constraint information, thereby improving the accuracy and adaptability of chip driving parameter configuration.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip driver parameter configuration method and a chip driver parameter configuration device. Background Technology

[0002] As chip application scenarios become increasingly complex, the collaborative deployment of various external devices (such as sensors and memory) with chips is becoming more and more widespread.

[0003] Currently, technicians typically manually analyze the relevant documentation of external devices, clarify the physical connection between the chip and the external device, and configure the chip driver parameters so that the chip can drive the external device according to the configured parameters, thus enabling normal communication between the chip and the external device.

[0004] However, when configuring chip driver parameters manually as described above, the diverse types of external devices and complex physical connections result in low configuration efficiency and difficulty in ensuring the accuracy of driver parameter configuration. Summary of the Invention

[0005] This application provides a chip driver parameter configuration method and a chip driver parameter configuration device, which can improve the efficiency and accuracy of chip driver parameter configuration.

[0006] According to a first aspect of the embodiments of this application, a chip driver parameter configuration method is provided, wherein the target chip is communicatively connected to an external device to be driven, including: Obtain the working status information of the external device to be driven; Based on the preset association relationship, the target initial parameters corresponding to the working status information of the external device to be driven are determined. The target initial parameters include the initial timing parameters and initial electrical parameters of the target chip driving the external device to be driven. The association relationship is the relationship between the working status information of the external device and the initial parameters. The total latency is determined based on the physical topology information between the external device to be driven and the target chip. Based on the total delay, the initial timing parameters are adjusted to obtain the target timing parameters; Based on the electrical constraint information of the external device to be driven, the initial electrical parameters are adjusted to obtain the target electrical parameters. The electrical constraint information is used to characterize the electrical operating restrictions of the external device to be driven. Based on the target timing parameters and target electrical parameters, configure the parameters of the target chip to drive the external device to be driven.

[0007] In some embodiments of this application, the total latency is determined based on the physical topology information between the external device to be driven and the target chip, including: Based on the physical topology information between the external device to be driven and the target chip, the hierarchical depth of the external device to be driven is determined. The hierarchical depth is used to characterize the number of devices on the signal transmission path between the external device to be driven and the target chip. The total layer delay is determined based on the layer depth and the preset unit layer delay. The total latency is determined by the sum of the total hierarchical latency and the inherent latency.

[0008] In some embodiments of this application, the initial timing parameters are adjusted based on the total delay to obtain the target timing parameters, including: The total delay is quantized to generate a delay compensation vector; Based on the time delay compensation vector, the initial timing parameters are superimposed and corrected to obtain the target timing parameters.

[0009] In some embodiments of this application, the initial timing parameters include the initial clock offset of the target chip driving the external device to be driven, the initial signal establishment time, and the initial signal hold time. The delay compensation vector includes the delay compensation vector corresponding to the initial clock offset, the delay compensation vector corresponding to the initial signal establishment time, and the delay compensation vector corresponding to the initial signal hold time. The total delay is quantized to generate a delay compensation vector, including: Determine the ratio of the total latency to the reference clock cycle of the target chip; Based on the scaling factor and the clock phase subdivision bit of the target chip, the delay compensation vector corresponding to the initial clock offset is determined. The clock phase subdivision bit is used to characterize the fineness of timing adjustment of the target chip. The product of the preset first compensation coefficient and the total time delay is used as the time delay compensation vector corresponding to the initial signal establishment time. The product of the preset second compensation coefficient and the total time delay is used as the time delay compensation vector corresponding to the initial signal holding time.

[0010] In some embodiments of this application, the initial electrical parameters include the initial voltage of the target chip driving the external device to be driven, and the electrical constraint information includes the voltage constraint range of the external device to be driven; Based on the electrical constraint information of the external device to be driven, the initial electrical parameters are adjusted to obtain the target electrical parameters, including: Determine the adjustment step size based on the voltage constraint range of the external device to be driven; According to the adjustment step size, the initial voltage is adjusted to the midpoint of the voltage constraint range, and the midpoint is used as the target electrical parameter.

[0011] In some embodiments of this application, the initial electrical parameters include the initial drive current and initial signal slew rate of the target chip driving the external device to be driven, and the electrical constraint information includes the upper limit of the drive capability of the interface between the external device to be driven and the target chip. Based on the electrical constraint information of the external device to be driven, the initial electrical parameters are adjusted to obtain the target electrical parameters, including: Based on the preset level correlation, determine the target level corresponding to the upper limit of the driving capability, and determine the driving current range and the signal slew rate range corresponding to the target level. The initial drive current is adjusted to the midpoint of the drive current range, so that the midpoint of the drive current range is used as the target electrical parameter; The initial signal slew rate is adjusted to the midpoint of the signal slew rate range, and the midpoint of the signal slew rate range is used as the target electrical parameter.

[0012] In some embodiments of this application, the parameters for the target chip to drive the external device to be driven are configured based on target timing parameters and target electrical parameters, including: Pre-configure the parameters of the target chip to drive the external device according to the target timing parameters and target electrical parameters; Start the external device to be driven to perform a self-test; Acquire device operating status signals and communication performance signals; Based on the preset evaluation strategy, determine the first evaluation value corresponding to the operating status signal and the second evaluation value corresponding to the communication performance signal; A weighted summation operation is performed on the first and second evaluation values ​​to obtain the comprehensive evaluation value; If the comprehensive evaluation value is not less than the preset threshold, the target timing parameters and target electrical parameters are configured as the parameters for the target chip to drive the external device to be driven.

[0013] In some embodiments of this application, the method further includes: If the comprehensive evaluation value is not less than the preset threshold, the initial timing parameters of the external device to be driven in the association relationship are replaced with the target timing parameters, and the initial electrical parameters of the external device to be driven in the association relationship are replaced with the target electrical parameters; the association relationship between the working status information, physical topology information and electrical constraint information of the external device to be driven is constructed in the association relationship.

[0014] According to a second aspect of the embodiments of this application, a chip driver parameter configuration device is provided, wherein a target chip is communicatively connected to an external device to be driven, and the device includes: The acquisition module is used to acquire the working status information of the external device to be driven. The determination module is used to determine the target initial parameters corresponding to the working status information of the external device to be driven according to the preset association relationship. The target initial parameters include the initial timing parameters and initial electrical parameters of the target chip driving the external device to be driven. The association relationship is the relationship between the working status information of the external device and the initial parameters. The determination module is also used to determine the total latency based on the physical topology information between the external device to be driven and the target chip; The adjustment module is used to adjust the initial timing parameters based on the total delay to obtain the target timing parameters; The adjustment module is also used to adjust the initial electrical parameters according to the electrical constraint information of the external device to be driven, so as to obtain the target electrical parameters. The electrical constraint information is used to characterize the electrical operating restrictions of the external device to be driven. The configuration module is used to configure the parameters of the target chip to drive the external device based on the target timing parameters and the target electrical parameters.

[0015] According to a third aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory being used to store at least one program, the at least one program being loaded by the processor and executed by any of the above-described chip driver parameter configuration methods.

[0016] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein at least one program is stored in the computer-readable storage medium, and the at least one program is loaded and executed by a processor to implement any of the above-described chip driver parameter configuration methods.

[0017] Therefore, in the above chip driver parameter configuration method, the target chip can determine the initial timing parameters and initial electrical parameters of the target chip driving the external device from the preset association relationship based on the working status information of the external device to be driven. Then, based on the physical topology information between the external device to be driven and the target chip, the total delay is determined, and the initial timing parameters are adjusted based on the total delay. Furthermore, the initial electrical parameters can also be adjusted based on the electrical constraint information of the external device to be driven, so that the external device to be driven can be driven based on the adjusted parameters in the future.

[0018] In other words, the above-described chip driver parameter configuration method eliminates the need for manual configuration, effectively avoiding the tedious and time-consuming nature of manual configuration and thus significantly improving the efficiency of chip driver parameter configuration. Furthermore, the initial parameters can be adjusted based on physical topology and electrical constraint information, ensuring that the adjusted parameters better suit the current deployment scenario. This significantly improves the accuracy and adaptability of chip driver parameter configuration, guaranteeing stable communication between the target chip and the external device to be driven. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating a chip driver parameter configuration method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a chip driver parameter configuration device provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a server provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0023] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various objects, these objects should not be limited by the terms.

[0024] These terms are simply used to distinguish one object from another. For example, without departing from the various examples, a first action can be called a second action, and similarly, a second action can be called a first action. Both the first and second actions can be actions, and in some cases, they can be separate and distinct actions.

[0025] "At least one" refers to one or more actions. For example, at least one action can be one action, two actions, three actions, or any integer number of actions greater than or equal to one. "Multiple" refers to two or more actions. For example, multiple actions can be two actions, three actions, or any integer number of actions greater than or equal to two.

[0026] As chip applications become increasingly complex, the collaborative deployment of various external devices (such as sensors and memory) with chips is becoming more widespread. Currently, technicians typically manually analyze the relevant documentation of external devices, clarify the physical connection relationships between the chip and the external device, and configure the chip driver parameters so that the chip can drive the external device according to the configured parameters and achieve normal communication between the chip and the external device. However, when configuring chip driver parameters manually, the diverse types of external devices and the complex physical connection relationships result in low configuration efficiency and make it difficult to guarantee the accuracy of the driver parameter configuration.

[0027] To address the aforementioned technical issues, this application provides a chip driver parameter configuration method that can adjust the target initial parameters based on physical topology information and electrical constraint information, making the adjusted parameters more suitable for the current actual deployment scenario and improving the efficiency and accuracy of chip driver parameter configuration.

[0028] Figure 1 This is a flowchart illustrating a chip driver parameter configuration method provided in an embodiment of this application. The following is a summary of the process. Figure 1 The chip driver parameter configuration method is described in detail below. The target chip in the embodiments of this application is not limited to MCU, embedded processor, SOC, etc. The execution subject of the chip driver parameter configuration method can be the target chip itself or the master control device that communicates with the target chip. The above chip driver parameter configuration method is described below with the target chip as the execution subject. The chip driver parameter configuration method can include: S101 to S106, as follows.

[0029] In this embodiment, the target chip is communicatively connected to an external device to be driven, which may be a sensor, memory, actuator (motor, camera, display screen, etc.).

[0030] S101, Obtain the working status information of the external device to be driven.

[0031] The operating status information of the external device to be driven indicates its working / operating mode. For example, if the external device to be driven is a sensor, its operating status information could indicate whether the sensor is in high-speed or low-speed acquisition mode. As another example, if the external device to be driven is a memory, its operating status information could indicate whether the memory is in normal read / write mode or low-power standby mode. Yet another example, if the external device to be driven is a camera, its operating status information could indicate whether the camera is in high-definition or standard-definition acquisition mode.

[0032] The target chip can first send an external device probe signal via the bus, and then identify the external device to be driven by monitoring the response signal of the external device. After identifying the external device to be driven, the target chip can obtain the corresponding working status information by reading the configuration space data of the external device to be driven. The configuration space data records information such as the current working mode of the external device to be driven.

[0033] S102, based on the preset association relationship, determine the target initial parameters corresponding to the working status information of the external device to be driven. The target initial parameters include the initial timing parameters and initial electrical parameters of the target chip driving the external device to be driven. The association relationship is the relationship between the working status information of the external device and the initial parameters.

[0034] The above-mentioned relationships can be constructed based on the original technical documents related to the target chip. These documents contain the device identifiers of each external device, the operating status information of each external device, and the initial parameters required for the target chip to drive each external device in each operating state. These initial parameters are the basic parameters required for the target chip to drive the corresponding external device.

[0035] The initial parameters include two types of parameters: timing parameters and electrical parameters. Timing parameters are used to standardize the timing relationship between the target chip and external devices during signal interaction, ensuring the synchronization and correctness of signal transmission. Electrical parameters are used to set the electrical operating conditions between the target chip and external devices, ensuring the stability and reliability of signal transmission.

[0036] Specifically, the target chip can perform OCR format conversion on the original technical document, extract the device identifier and working status information of the external device, concatenate the device identifier and working status information of the external device into an index, and then extract the corresponding initial parameters to build a relationship.

[0037] Then, the target chip can determine the target initial parameters corresponding to the working status information of the external device to be driven based on the above correlation. The target initial parameters include the initial timing parameters and initial electrical parameters of the target chip driving the external device to be driven.

[0038] S103, determine the total latency based on the physical topology information between the external device to be driven and the target chip.

[0039] S104, based on the total delay, adjust the initial timing parameters to obtain the target timing parameters.

[0040] Physical topology information refers to information such as the hardware connection relationship, bus hierarchy, and transmission path length between the external device to be driven and the target chip.

[0041] The target chip can determine the total latency based on the physical topology information between the external device to be driven and the target chip. The total latency refers to the overall signal propagation delay caused by factors such as physical topology path and peripheral layer depth when the signal is transmitted between the target chip and the external device to be driven.

[0042] Furthermore, the target chip can adjust the initial timing parameters based on the total delay to obtain the target timing parameters, thereby offsetting the delay deviation generated during signal transmission, ensuring reliable signal synchronization between the target chip and external devices, and achieving stable data interaction.

[0043] S105, adjust the initial electrical parameters according to the electrical constraint information of the external device to be driven to obtain the target electrical parameters. The electrical constraint information is used to characterize the electrical operating restrictions of the external device to be driven.

[0044] S106, based on the target timing parameters and target electrical parameters, configure the parameters of the target chip to drive the external device to be driven.

[0045] Electrical constraint information can be used to characterize the electrical operating limitations of the external device to be driven. It can define the electrical adaptation range required for the external device to operate normally and the electrical operating threshold of the interface between the target chip and the external device to be driven.

[0046] The target chip can adjust its initial electrical parameters based on the electrical constraint information of the external device to be driven, thereby obtaining the target electrical parameters. This allows the electrical characteristics between the target chip and the external device to be driven to match, ensuring a safe and stable communication process and avoiding electrical anomalies.

[0047] After determining the target timing parameters and target electrical parameters, the parameters of the target chip driver for the external device to be driven can be configured based on the target timing parameters and target electrical parameters.

[0048] Therefore, the above-described chip driver parameter configuration method eliminates the need for manual configuration, effectively avoiding the tedious and time-consuming nature of manual configuration and significantly improving efficiency. Furthermore, the initial parameters can be adjusted based on physical topology and electrical constraints, ensuring the adjusted parameters better suit the current deployment scenario. This significantly improves the accuracy and adaptability of chip driver parameter configuration, guaranteeing stable communication between the target chip and the external device being driven.

[0049] In some embodiments of this application, S103 is involved. The target chip can determine the total latency based on the physical topology information between the external device to be driven and the target chip. S103 may include S1031 to S1033, as follows.

[0050] S1031, determine the layer depth of the external device to be driven based on the physical topology information between the external device to be driven and the target chip. The layer depth is used to characterize the number of devices on the signal transmission path between the external device to be driven and the target chip.

[0051] The target chip can determine the hierarchy depth of the external device to be driven based on the physical topology information between the external device and the target chip. For example, if the external device to be driven is directly connected to the target chip's bus without any other devices in between, then the hierarchy depth of the external device to be driven is 1. As another example, if the external device to be driven is connected to the target chip through a bus extender, then the hierarchy depth of the external device to be driven is 2.

[0052] S1032, determine the total layer delay based on the layer depth and the preset unit layer delay.

[0053] S1033, the sum of the total hierarchical delay and the inherent delay is determined as the total delay.

[0054] After determining the layer depth of the external device to be driven, the target chip can multiply this layer depth by a preset unit layer delay, and use this product as the total layer delay. The unit layer delay refers to the signal propagation delay introduced by each additional layer of device between the target chip and the external device, characterizing the impact of a single layer of device on signal transmission delay. The unit layer delay can be obtained by measuring and statistically fitting the signal transmission delay between the target chip and the external device at different layer depths.

[0055] When determining the total latency, the inherent latency can also be referenced. The inherent latency is the inherent signal delay generated by the target chip's circuitry and the transmission lines between the target chip and the external device to be driven. The inherent latency can be pre-calibrated based on the target chip's hardware design parameters, interface circuit parameters, and the electrical characteristics of the transmission medium through circuit simulation and actual circuit testing. After determining the inherent latency, the sum of the aforementioned total hierarchical latency and the inherent latency can be used to determine the total latency.

[0056] In some embodiments of this application, S104 is involved, in which the target chip can adjust the initial timing parameters based on the total delay to obtain the target timing parameters. S104 may include S1041 and S1042, as follows.

[0057] S1041, quantize the total delay and generate a delay compensation vector; S1042, Based on the time delay compensation vector, the initial timing parameters are superimposed and corrected to obtain the target timing parameters.

[0058] The target chip can quantize the total delay mentioned above to generate a delay compensation vector. This delay compensation vector is a standardized value that the target chip can directly use in timing operations. After determining the delay compensation vector, the target chip can use it to superimpose and correct the initial timing parameters to obtain the target timing parameters. Specifically, the delay compensation vector can be superimposed with the initial timing parameters to compensate for timing deviations caused by signal transmission.

[0059] In some embodiments of this application, the initial timing parameters may include the initial clock offset, initial signal setup time, and initial signal hold time for the target chip driving the external device to be driven. The initial clock offset refers to a preset initial time deviation between the target chip's output clock and a reference clock. The initial signal setup time refers to a preset minimum time for the signal to remain stable before the arrival of the clock's effective edge. The initial signal hold time refers to a preset minimum time for the signal to remain stable after the arrival of the clock's effective edge. The delay compensation vector is composed of the delay compensation vector corresponding to the initial clock offset, the delay compensation vector corresponding to the initial signal setup time, and the delay compensation vector corresponding to the initial signal hold time.

[0060] Regarding S1041, the target chip can quantize the total delay and generate a delay compensation vector. S1041 can include S10411 to S10414, as follows.

[0061] S10411 determines the ratio of the total delay to the reference clock cycle of the target chip.

[0062] S10412 determines the delay compensation vector corresponding to the initial clock offset based on the scaling factor and the clock phase subdivision bit of the target chip. The clock phase subdivision bit is used to characterize the fineness of the timing adjustment of the target chip.

[0063] When determining the delay compensation vector corresponding to the initial clock offset, it can be based on the timing adjustment parameters of the target chip. Specifically, the proportion of the total delay to the reference clock cycle of the target chip can be determined first. Since the target chip performs timing adjustment according to the clock phase subdivision bits, the product of the aforementioned proportion and the clock phase subdivision bits of the target chip can be calculated. The clock phase subdivision bits are the total number of smallest adjustable phase units that divide a reference clock cycle equally. This number can be obtained from the target chip's design manual and can be used to characterize the minimum adjustment step size of the clock phase adjustment by the target chip, as well as the fineness of the timing adjustment. Then, the product can be rounded down, and the result can be used as the delay compensation vector corresponding to the initial clock offset for subsequent superposition correction of the initial clock offset.

[0064] S10413, the product of the preset first compensation coefficient and the total time delay is used as the time delay compensation vector corresponding to the initial signal establishment time.

[0065] S10414, the product of the preset second compensation coefficient and the total time delay is used as the time delay compensation vector corresponding to the initial signal holding time.

[0066] The first compensation coefficient can represent the weight of the total delay on the initial signal establishment time of the target chip driving the external device to be driven, and the second compensation coefficient can represent the weight of the total delay on the initial signal holding time of the target chip driving the external device to be driven. Both the first and second compensation coefficients can be pre-calibrated. Specifically, actual tests and timing simulations can be performed on the signal establishment time and signal holding time under different delay scenarios, and the test and simulation results can be statistically fitted to obtain the corresponding compensation coefficients.

[0067] Then, the product of the first compensation coefficient and the total delay can be used as the delay compensation vector corresponding to the initial signal establishment time, and the product of the second compensation coefficient and the total delay can be used as the delay compensation vector corresponding to the initial signal holding time, so as to be used for subsequent superposition correction of the initial signal establishment time and the initial signal holding time.

[0068] In some embodiments of this application, the initial electrical parameters may include the initial voltage of the target chip driving the external device to be driven, and the electrical constraint information may include the voltage constraint range of the external device to be driven, wherein the voltage constraint range refers to the range of input voltages that enable the external device to be driven to work normally without causing damage to the device.

[0069] Regarding S105, the target chip can adjust the initial electrical parameters according to the electrical constraint information of the external device to be driven. S105 can include S1051 and S1052, as detailed below.

[0070] S1051 determines the adjustment step size based on the voltage constraint range of the external device to be driven.

[0071] S1052, according to the adjustment step size, adjust the initial voltage to the midpoint of the voltage constraint range, so as to use the midpoint as the target electrical parameter.

[0072] The target chip can adjust the initial voltage according to a predetermined adjustment step size, which can be determined based on the voltage constraint range of the external device to be driven. For example, 1% of the voltage constraint range can be used as the adjustment step size. Alternatively, 5% of the voltage constraint range can be used. In practical applications, the specific adjustment step size can be determined based on the electrical characteristics and driving accuracy requirements of the external device to be driven.

[0073] Specifically, the target chip can gradually adjust the initial voltage according to the above adjustment step size until it is adjusted to the middle value of the voltage constraint range. This middle value is determined as the target electrical parameter so that the voltage output by the target chip to the external device to be driven meets the electrical requirements of the external device to be driven. Sufficient voltage margin is reserved for voltage fluctuations caused by external interference, device parameter deviation, transmission line loss, etc., which improves the stability and reliability of the external device to be driven and reduces the risk of abnormal operation or damage to the external device to be driven.

[0074] In some embodiments of this application, the initial electrical parameters may further include the initial drive current and initial signal slew rate of the target chip driving the external device to be driven. Electrical constraint information may also include the upper limit of the drive capability of the interface between the external device to be driven and the target chip. This upper limit refers to the threshold of the maximum drive capability that the interface between the external device to be driven and the target chip can withstand, and is typically determined by the interface circuit, transmission line, and the electrical characteristics of the external device to be driven itself. The upper limit of the drive capability may be the maximum drive current value, maximum drive power value, etc., that the interface between the external device to be driven and the target chip can withstand. During the process of driving the external device to be driven, the target chip needs to control the actual drive parameters within this upper limit to avoid exceeding the interface's capacity, which could lead to device damage or signal abnormalities.

[0075] Regarding S105, the target chip can adjust the initial electrical parameters according to the electrical constraint information of the external device to be driven. S105 can include S1053 and S1055, as detailed below.

[0076] S1053, based on the preset level association relationship, determines the target level corresponding to the upper limit of the driving capability, and determines the driving current range and the signal slew rate range corresponding to the target level.

[0077] S1054 adjusts the initial drive current to the middle value of the drive current range, so as to use the middle value of the drive current range as the target electrical parameter.

[0078] S1055, adjust the initial signal slew rate to the midpoint of the signal slew rate range, and use the midpoint of the signal slew rate range as the target electrical parameter.

[0079] Before adjusting the initial drive current and initial signal slew rate of the target chip to drive the external device, a hierarchical relationship can be pre-established. The hierarchical relationship can be determined through drive performance testing. The hierarchical relationship can consist of two sub-hierarchical relationships: the relationship between the upper limit of the external device's drive capability and the level, and the one-to-one correspondence between the level and the drive current range and the signal slew rate range.

[0080] Based on this, the target chip can determine the target level corresponding to the upper limit of the driving capability of the interface between the external device to be driven and the target chip according to the hierarchical correlation, and determine the driving current range and the signal slew rate range corresponding to the target level, thereby providing a constraint range for the subsequent adjustment of the initial driving current and the initial signal slew rate.

[0081] Alternatively, the hierarchical relationship can be a one-to-one correspondence between the upper limit of the external device's driving capability, its level, the driving current range, and the signal slew rate range.

[0082] For example, in the hierarchical relationship, the upper limit of the drive capability is 500mA, corresponding to the first level, the corresponding drive current range (300 mA, 400 mA), and the corresponding signal slew rate range (1... ,2 The upper limit of the driving capability is 800mA, corresponding to the second level, the corresponding driving current range (500mA, 650mA), and the corresponding signal slew rate range (2). 3.5 The maximum drive capability is 1200mA, corresponding to the third level, with a corresponding drive current range of 800 mA and 1000 mA, and a corresponding signal slew rate range of 3.5. 5 The target chip can directly determine the upper limit of the driving capability of the interface between the external device to be driven and the target chip, as well as the driving current range and signal slew rate range, based on this hierarchical relationship.

[0083] Then, the target chip can adjust the initial drive current to the middle value of the corresponding drive current range. This allows for sufficient current margin to accommodate current fluctuations without exceeding the upper limit of the drive capability of the interface between the external device to be driven and the target chip, preventing the drive current from exceeding the interface's tolerance due to external interference and ensuring a stable and reliable drive process. Furthermore, the initial signal slew rate can be synchronously adjusted to the middle value of the corresponding signal slew rate range, thereby improving the interface's operational reliability without exceeding the upper limit of the drive capability of the interface between the external device to be driven and the target chip.

[0084] In other embodiments of this application, the initial drive current and initial signal slew rate can be set to other values ​​within the corresponding range, which can be determined based on actual needs. Taking the initial drive current as an example, if the upper limit of the drive capability of the interface between the external device to be driven and the target chip is 500mA, and its corresponding drive current range is (300 mA, 400 mA), then the initial drive current can be adjusted to 350mA.

[0085] In some embodiments of this application, S106 is involved, whereby the target chip can configure the parameters for driving the external device to be driven based on target timing parameters and target electrical parameters, so that the target chip outputs a drive signal to the external device to be driven according to the configured parameters, thereby stably driving the external device to be driven to work normally. S106 may include S1061 to S1066, as follows.

[0086] S1061, according to the target timing parameters and target electrical parameters, pre-configure the parameters of the target chip driving the external device to be driven.

[0087] S1062, Start the external device to be driven to perform a self-test.

[0088] S1063, acquire device operating status signals and communication performance signals.

[0089] Before configuring the parameters for driving the external device, the target chip can be pre-configured. Specifically, according to the previously determined target timing parameters and target electrical parameters, and following the bus communication protocol corresponding to the external device, these two types of parameters can be encapsulated into a data packet conforming to the protocol specification. This data packet can then be sent to the external device. Furthermore, the external device can be controlled to write the parameter information from the data packet into its corresponding configuration register, completing the pre-configuration of the operating environment, including runtime timing and electrical drive conditions, for the external device.

[0090] After pre-configuration, the target chip can send a self-test command to the external device to be driven, causing the external device to activate its internal self-test state machine and enter the self-test process. Specifically, after receiving the self-test command, the external device to be driven can perform a step-by-step test on its own functional modules, interface connection status, and communication link integrity. During the self-test, the operating status of each module, whether any abnormalities occur, and the type of abnormality are recorded in real time. A device operating status signal containing status flags and error codes is generated and sent to the target chip. The device operating status signal can be used to reflect the real-time working status of the external device to be driven, to determine whether the external device to be driven is being driven normally and whether there is stable communication with the target chip, and to provide a basis for subsequent parameter evaluation.

[0091] The target chip can also enable its own bus monitoring module to capture bus transaction frames related to the external device to be driven, extract data such as the amount of data transmitted, timestamp, and response results from the transaction frames, and calculate indicators such as average data transmission rate, instruction execution success rate, and maximum transmission delay, thereby generating a communication performance signal. The communication performance signal can be used to reflect the communication quality and efficiency between the target chip and the external device to be driven.

[0092] S1064, according to the preset evaluation strategy, determine the first evaluation value corresponding to the operating status signal and the second evaluation value corresponding to the communication performance signal.

[0093] S1065, perform a weighted summation operation on the first evaluation value and the second evaluation value to obtain the comprehensive evaluation value.

[0094] S1066, if the comprehensive evaluation value is not less than the preset threshold, configure the target timing parameters and target electrical parameters as the parameters for the target chip to drive the external device to be driven.

[0095] After acquiring the device operating status signal and communication performance signal, the target chip can parse the operating status, abnormal triggering identifier, and other data of each functional module of the external device to be driven from the device operating status signal, and parse the average data transmission rate, instruction execution success rate, maximum transmission delay, and other data from the communication performance signal, so as to evaluate the operating reliability and communication performance of the external device to be driven based on the parsed data and the preset evaluation strategy.

[0096] The evaluation strategy can evaluate the data obtained from analyzing the equipment's operating status signals and communication performance signals, and finally calculate a comprehensive evaluation value by combining the corresponding weights.

[0097] Specifically, when evaluating the data obtained from parsing the device's operating status signals, evaluation criteria can be set for data such as the operating status of each functional module and abnormal trigger indicators. For example, 25 points are added for normal module operation and 25 points are added for no abnormal triggers. The target chip can compare the actual data parsed from the device's operating status signals with the evaluation criteria set in this evaluation strategy to obtain a first evaluation value.

[0098] When evaluating the data obtained from parsing the communication performance signal, a corresponding evaluation standard can also be set. The target chip calculates the corresponding score based on the ratio of the actual data obtained from parsing the communication performance signal to the corresponding benchmark value, thereby obtaining the second evaluation value.

[0099] For example, if the benchmark for average data transfer rate is 100Mbps, and the maximum score for this item is 30 points, then if the actual average data transfer rate is 90Mbps, and the ratio of the actual average data transfer rate to the benchmark is 90%, then the score for the actual average data transfer rate is 27 points. Similarly, if the benchmark for instruction execution success rate is 99%, and the maximum score for this item is 40 points, then the score for the actual instruction execution success rate is 40 points. Likewise, if the benchmark for maximum transmission delay is 50ms, and the maximum score for this item is 30 points, then if the actual maximum transmission delay is 40ms, and the ratio of the actual maximum transmission delay to the benchmark is 80%, then the score for the actual maximum transmission delay is 24 points. The sum of the scores for the actual average data transfer rate, the actual instruction execution success rate, and the actual maximum transmission delay is used as the second evaluation value.

[0100] The target chip can then perform a weighted summation operation on the first and second evaluation values ​​to obtain a comprehensive evaluation value. For example, the weight corresponding to the first evaluation value can be set to 0.4, and the weight corresponding to the second evaluation value can be set to 0.6.

[0101] Continuing with the previous example, if all functions of the external device to be driven are normal and the anomaly indicator is none, the first evaluation value is 100 points. If the actual transmission rate reaches 90Mbps and the success rate reaches 99%, the second evaluation value is 99 points. Then, a weighted sum is performed according to the preset weights to obtain a comprehensive evaluation value of 99.4 points.

[0102] If the overall evaluation value is not less than a preset threshold, the target timing parameters and target electrical parameters are configured as the parameters for the target chip to drive the external device. That is, when the overall evaluation value is not less than the preset threshold, it is determined that the current target timing parameters and target electrical parameters can adapt to the electrical constraints and operating characteristics of the external device to be driven, so that the external device to be driven can work in a stable and high-performance state, meeting the system driving and communication performance requirements.

[0103] In other embodiments of this application, if the aforementioned comprehensive evaluation value is less than a preset threshold, that is, the currently pre-configured target timing parameters and target electrical parameters cannot meet the normal operation requirements of the external device to be driven, and the driving configuration effect does not meet the preset standard. Therefore, the target chip can readjust the initial timing parameters and initial electrical parameters, and complete the evaluation again according to the aforementioned process until the obtained comprehensive evaluation value is not less than the preset threshold, thereby determining the final parameters adapted to the external device to be driven, ensuring that the external device to be driven can work stably and reliably and achieve better communication performance.

[0104] In some embodiments of this application, the association can also be updated. Specifically, when the comprehensive evaluation value is not less than a preset threshold, that is, when the current target timing parameters and target electrical parameters can be adapted to the working requirements of the external device to be driven, they can be used as effective parameters.

[0105] Therefore, the target chip can replace the initial timing parameters of the external device to be driven in the association with the target timing parameters, and replace the initial electrical parameters of the external device to be driven in the association with the target electrical parameters, thereby completing the corresponding parameter update. At the same time, it can also construct the association between the working status information, physical topology information, and electrical constraint information of the external device to be driven in the association.

[0106] For example, the target chip can combine the device identifier of the external hardware device to be driven with the current working status information to form an index, encapsulate the corresponding physical topology information, electrical constraint information, target timing parameters and target electrical parameters to form a data block, and replace the original data in the association relationship with the data block.

[0107] In other embodiments of this application, if the preset association does not include information about the external device to be driven, the timing and electrical parameters currently loaded by the external device to be driven can be used as target initial parameters to facilitate subsequent adjustments. Alternatively, the original technical documents related to the target chip can be input into the target chip so that the target chip can retrieve the target initial parameters of the corresponding device from the original technical documents to facilitate subsequent adjustments. Alternatively, the factory default timing and electrical parameters of the external device to be driven can be used as target initial parameters to facilitate subsequent adjustments. Furthermore, if the comprehensive evaluation value is not less than a preset threshold, the device identifier of the external hardware device to be driven can be combined with the current working status information to form an index. The corresponding physical topology information, electrical constraint information, target timing parameters, and target electrical parameters are then encapsulated to form a data block, and this data block is added to the association.

[0108] Therefore, the above-described chip driver parameter configuration method eliminates the need for manual configuration, effectively avoiding the tedious and time-consuming nature of manual configuration and significantly improving efficiency. Furthermore, the initial parameters can be adjusted based on physical topology and electrical constraints, ensuring the adjusted parameters better suit the current deployment scenario. This significantly improves the accuracy and adaptability of chip driver parameter configuration, guaranteeing stable communication between the target chip and the external device being driven.

[0109] In addition, in some embodiments of this application, the association relationship can be updated. Specifically, if the comprehensive evaluation value is not less than a preset threshold, an association relationship can be constructed between the working status information of the external device to be driven and the physical topology information and electrical constraint information, and added to the preset association relationship. The target initial parameters in the association relationship are replaced with target timing parameters and target electrical parameters. Based on this, if the target chip drives the same external device in the future, the adjusted target electrical parameters and target timing parameters can be directly queried from the updated association relationship without repeating the parameter adjustment operation, which greatly improves the efficiency of chip driver parameter configuration.

[0110] In addition, if the preset association relationship does not include the relevant information of the external device to be driven, and the comprehensive evaluation value is not less than the preset threshold, the device identifier of the external hardware device to be driven can be combined with the current working status information to form an index. The corresponding physical topology information, electrical constraint information, target timing parameters and target electrical parameters are encapsulated to form a data block, and the data block is added to the association relationship, thereby enriching and improving the preset association relationship and providing a reference for the configuration of driving parameters of the same external device in the future.

[0111] Embodiments of this application also provide a chip driver parameter configuration device, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of a chip driver parameter configuration device provided in an embodiment of this application. The chip driver parameter configuration device 200 can be deployed on a target chip such as an MCU, embedded processor, or SOC, where the target chip communicates with an external device to be driven. Alternatively, it can be deployed on a main control device that communicates with these target chips. The chip driver parameter configuration device 200 includes: The acquisition module 201 is used to acquire the working status information of the external device to be driven. The determining module 202 is used to determine the target initial parameters corresponding to the working status information of the external device to be driven according to the preset association relationship. The target initial parameters include the initial timing parameters and initial electrical parameters of the target chip driving the external device to be driven. The association relationship is the association relationship between the working status information of the external device and the initial parameters. The determining module 202 is also used to determine the total latency based on the physical topology information between the external device to be driven and the target chip; The adjustment module 203 is used to adjust the initial timing parameters based on the total delay to obtain the target timing parameters; The adjustment module 203 is also used to adjust the initial electrical parameters according to the electrical constraint information of the external device to be driven, so as to obtain the target electrical parameters. The electrical constraint information is used to characterize the electrical operating restrictions of the external device to be driven. Configuration module 204 is used to configure the parameters of the target chip to drive the external device based on the target timing parameters and the target electrical parameters.

[0112] In some embodiments of this application, the determining module 202 is further configured to: determine the layer depth of the external device to be driven based on the physical topology information between the external device to be driven and the target chip, wherein the layer depth is used to characterize the number of devices on the signal transmission path between the external device to be driven and the target chip; determine the total layer delay based on the layer depth and a preset unit layer delay; and determine the sum of the total layer delay and the inherent delay as the total delay.

[0113] In some embodiments of this application, the adjustment module 203 is further configured to quantize the total delay and generate a delay compensation vector; and to superimpose and correct the initial timing parameters according to the delay compensation vector to obtain the target timing parameters.

[0114] In some embodiments of this application, the initial timing parameters include the initial clock offset of the target chip driving the external device to be driven, the initial signal establishment time, and the initial signal hold time. The delay compensation vector includes the delay compensation vector corresponding to the initial clock offset, the delay compensation vector corresponding to the initial signal establishment time, and the delay compensation vector corresponding to the initial signal hold time. The adjustment module 203 is further configured to: determine the proportion coefficient of the total delay to the reference clock cycle of the target chip; determine the delay compensation vector corresponding to the initial clock offset based on the proportion coefficient and the clock phase subdivision bit of the target chip, wherein the clock phase subdivision bit is used to characterize the fineness of the timing adjustment of the target chip; use the product of the preset first compensation coefficient and the total delay as the delay compensation vector corresponding to the initial signal establishment time; and use the product of the preset second compensation coefficient and the total delay as the delay compensation vector corresponding to the initial signal hold time.

[0115] In some embodiments of this application, the initial electrical parameters include the initial voltage of the target chip driving the external device to be driven, and the electrical constraint information includes the voltage constraint range of the external device to be driven; The adjustment module 203 is also used to determine the adjustment step size according to the voltage constraint range of the external device to be driven; and adjust the initial voltage to the middle value of the voltage constraint range according to the adjustment step size, so as to use the middle value as the target electrical parameter.

[0116] In some embodiments of this application, the initial electrical parameters include the initial drive current and initial signal slew rate of the target chip driving the external device to be driven, and the electrical constraint information includes the upper limit of the drive capability of the interface between the external device to be driven and the target chip. The adjustment module 203 is further configured to: determine the target level corresponding to the upper limit of the driving capability according to the preset level association relationship; determine the driving current range and the signal slew rate range corresponding to the target level; adjust the initial driving current to the middle value of the driving current range, so as to use the middle value of the driving current range as the target electrical parameter; and adjust the initial signal slew rate to the middle value of the signal slew rate range, so as to use the middle value of the signal slew rate range as the target electrical parameter.

[0117] In some embodiments of this application, the configuration module 204 is further configured to: pre-configure the parameters of the target chip driving the external device to be driven according to the target timing parameters and the target electrical parameters; start the external device to be driven to perform a self-test; acquire the device operating status signal and the communication performance signal; determine the first evaluation value corresponding to the operating status signal and the second evaluation value corresponding to the communication performance signal according to the preset evaluation strategy; perform a weighted summation operation on the first evaluation value and the second evaluation value to obtain a comprehensive evaluation value; and configure the target timing parameters and the target electrical parameters as the parameters of the target chip driving the external device to be driven if the comprehensive evaluation value is not less than a preset threshold.

[0118] In some embodiments of this application, the chip driver parameter configuration device 200 further includes: replacing the initial timing parameters of the external device to be driven in the association relationship with the target timing parameters when the comprehensive evaluation value is not less than a preset threshold; replacing the initial electrical parameters of the external device to be driven in the association relationship with the target electrical parameters; and constructing an association relationship between the working status information, physical topology information, and electrical constraint information of the external device to be driven in the association relationship.

[0119] Embodiments of this application also provide a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement any of the above-described methods for configuring chip driver parameters.

[0120] Taking computer devices as terminals as an example, Figure 3 A schematic diagram of the structure of a terminal provided in an embodiment of this application is shown below. Figure 3 In some embodiments of this application, terminal 300 may be: a smartphone, tablet computer, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop computer, or desktop computer. Terminal 300 may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other names.

[0121] Typically, terminal 300 includes a processor 301 and a memory 302.

[0122] In some embodiments of this application, processor 301 may include one or more processing cores, such as a quad-core processor, a penta-core processor, etc. Processor 301 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 301 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 301 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 301 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0123] In some embodiments of this application, memory 302 may include one or more computer-readable storage media, which may be non-transitory. Memory 302 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in memory 302 is used to store at least one program code, which is executed by processor 301 to implement the process of terminal execution in the method embodiments of this application.

[0124] In some embodiments, the terminal 300 may also optionally include a peripheral device interface 303 and at least one peripheral device. The processor 301, memory 302, and peripheral device interface 303 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 303 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of a display screen 304, a camera assembly 305, an audio circuit 306, and a power supply 307.

[0125] The peripheral device interface 303 can be used to connect at least one I / O (Input / Output) related peripheral device to the processor 301 and the memory 302. In some embodiments, the processor 301, memory 302, and peripheral device interface 303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 301, memory 302, and peripheral device interface 303 can be implemented on separate chips or circuit boards, and this application embodiment does not limit this.

[0126] Display screen 304 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 304 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 301 for processing. In this case, display screen 304 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 304, disposed on the front panel of terminal 300; in other embodiments, there may be at least two display screens, disposed on different surfaces of terminal 300 or in a folded design; in other embodiments, display screen 304 may be a flexible display screen, disposed on a curved or folded surface of terminal 300. Furthermore, display screen 304 may be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. Display screen 304 may be made of materials such as LCD (Liquid Crystal Display) or OLED (Organic Light-Emitting Diode).

[0127] The camera assembly 305 is used to acquire images or videos. In some embodiments, the camera assembly 305 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the terminal, and the rear-facing camera is located on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 305 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash is a combination of a warm-light flash and a cool-light flash, which can be used for light compensation at different color temperatures.

[0128] The audio circuit 306 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals which are then input to the processor 301 for processing. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each positioned at a different location on the terminal 300. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert the electrical signals from the processor 301 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 306 may also include a headphone jack.

[0129] Power supply 307 is used to power the various components in terminal 300. Power supply 307 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 307 includes a rechargeable battery, the rechargeable battery can support wired or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0130] Understandable. Figure 3 The structure shown does not constitute a limitation on terminal 300, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0131] Taking computer equipment as a server as an example, Figure 4 This is a schematic diagram of a server structure provided in an embodiment of this application. The server 400 can vary significantly due to different configurations or performance. It may include one or more processors 401 (Central Processing Units, CPUs) and one or more memories 402. Each memory 402 stores at least one computer program, which is loaded and executed by the processors 401 to implement the aforementioned chip driver parameter configuration method. Of course, the server 400 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input / output. The server 400 may also include other components for implementing device functions, which will not be elaborated upon here.

[0132] Embodiments of this application also provide a computer-readable storage medium, which includes a stored computer program, wherein the computer program, when running, controls the device where the computer-readable storage medium is located to perform the method described above. Optionally, the computer-readable storage medium may be read-only memory (ROM), random access memory (RAM), compact-disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0133] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0134] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for configuring chip driver parameters, characterized in that, The method for establishing a communication connection between the target chip and the external device to be driven includes: Obtain the working status information of the external device to be driven, wherein the working status information is information related to the working / operating mode of the external device to be driven; Based on a preset association relationship, target initial parameters corresponding to the working status information of the external device to be driven are determined. The target initial parameters include the initial timing parameters and initial electrical parameters of the target chip driving the external device to be driven. The association relationship is the relationship between the working status information of the external device and the initial parameters. The initial electrical parameters include the initial voltage, initial drive current and initial signal slew rate of the target chip driving the external device to be driven. The total latency is determined based on the physical topology information between the external device to be driven and the target chip; Based on the total delay, the initial timing parameters are adjusted to obtain the target timing parameters; Based on the electrical constraint information of the external device to be driven, the initial electrical parameters are adjusted to obtain the target electrical parameters. The electrical constraint information is used to characterize the electrical operating limitations of the external device to be driven, and the electrical constraint information includes the upper limit of the driving capability of the interface between the external device to be driven and the target chip. Based on the target timing parameters and the target electrical parameters, configure the parameters for the target chip to drive the external device to be driven; Based on the electrical constraint information of the external device to be driven, the initial electrical parameters are adjusted to obtain target electrical parameters, including: determining a target level corresponding to the upper limit of the driving capability according to a preset level association relationship, and determining a driving current range and a signal slew rate range corresponding to the target level; adjusting the initial driving current to the middle value of the driving current range, so as to use the middle value of the driving current range as the target electrical parameter; adjusting the initial signal slew rate to the middle value of the signal slew rate range, so as to use the middle value of the signal slew rate range as the target electrical parameter.

2. The method according to claim 1, characterized in that, Based on the physical topology information between the external device to be driven and the target chip, the total latency is determined, including: Based on the physical topology information between the external device to be driven and the target chip, the layer depth of the external device to be driven is determined, and the layer depth is used to characterize the number of devices on the signal transmission path between the external device to be driven and the target chip; The total level delay is determined based on the level depth and the preset unit level delay. The sum of the total hierarchical delay and the inherent delay is determined as the total delay.

3. The method according to claim 1, characterized in that, Based on the total delay, the initial timing parameters are adjusted to obtain the target timing parameters, including: The total delay is quantized to generate a delay compensation vector; The initial timing parameters are superimposed and corrected based on the delay compensation vector to obtain the target timing parameters.

4. The method according to claim 3, characterized in that, The initial timing parameters include the initial clock offset, initial signal establishment time, and initial signal hold time of the target chip driving the external device to be driven. The delay compensation vector includes the delay compensation vector corresponding to the initial clock offset, the delay compensation vector corresponding to the initial signal establishment time, and the delay compensation vector corresponding to the initial signal hold time. The total delay is quantized to generate a delay compensation vector, including: Determine the ratio of the total delay to the reference clock cycle of the target chip; Based on the scaling factor and the clock phase subdivision bit of the target chip, the delay compensation vector corresponding to the initial clock offset is determined, and the clock phase subdivision bit is used to characterize the fineness of the timing adjustment of the target chip. The product of the preset first compensation coefficient and the total time delay is used as the time delay compensation vector corresponding to the initial signal establishment time. The product of the preset second compensation coefficient and the total delay is used as the delay compensation vector corresponding to the initial signal holding time.

5. The method according to claim 1, characterized in that, The electrical constraint information includes the voltage constraint range of the external device to be driven; Based on the electrical constraint information of the external device to be driven, the initial electrical parameters are adjusted to obtain the target electrical parameters, including: The adjustment step size is determined based on the voltage constraint range of the external device to be driven; According to the adjustment step size, the initial voltage is adjusted to the midpoint of the voltage constraint range, and the midpoint is used as the target electrical parameter.

6. The method according to claim 1, characterized in that, Based on the target timing parameters and the target electrical parameters, configure the parameters for the target chip to drive the external device to be driven, including: According to the target timing parameters and the target electrical parameters, the parameters for the target chip to drive the external device to be driven are pre-configured. Start the external device to be driven to perform a self-test; Acquire device operating status signals and communication performance signals; Based on a preset evaluation strategy, a first evaluation value corresponding to the operating status signal and a second evaluation value corresponding to the communication performance signal are determined. A weighted summation operation is performed on the first evaluation value and the second evaluation value to obtain a comprehensive evaluation value; If the comprehensive evaluation value is not less than a preset threshold, the target timing parameters and the target electrical parameters are configured as parameters for the target chip to drive the external device to be driven.

7. The method according to claim 6, characterized in that, The method further includes: If the comprehensive evaluation value is not less than a preset threshold, the initial timing parameters of the external device to be driven in the association relationship are replaced with the target timing parameters, and the initial electrical parameters of the external device to be driven in the association relationship are replaced with the target electrical parameters; and an association relationship is constructed between the working status information of the external device to be driven and the physical topology information and the electrical constraint information in the association relationship.

8. A chip driver parameter configuration device, characterized in that, The target chip communicates with the external device to be driven, and the device includes: The acquisition module is used to acquire the working status information of the external device to be driven, wherein the working status information is information related to the working / operating mode of the external device to be driven. The determination module is used to determine the target initial parameters corresponding to the working status information of the external device to be driven according to a preset association relationship. The target initial parameters include the initial timing parameters and initial electrical parameters of the target chip driving the external device to be driven. The association relationship is the relationship between the working status information of the external device and the initial parameters. The initial electrical parameters include the initial voltage, initial drive current and initial signal slew rate of the target chip driving the external device to be driven. The determining module is further configured to determine the total latency based on the physical topology information between the external device to be driven and the target chip; An adjustment module is used to adjust the initial timing parameters based on the total delay to obtain the target timing parameters; The adjustment module is further configured to adjust the initial electrical parameters according to the electrical constraint information of the external device to be driven, so as to obtain the target electrical parameters. The electrical constraint information is used to characterize the electrical operating limitations of the external device to be driven, and the electrical constraint information includes the upper limit of the driving capability of the interface between the external device to be driven and the target chip. A configuration module is used to configure the parameters for the target chip to drive the external device to be driven based on the target timing parameters and the target electrical parameters; The adjustment module is specifically used to: determine a target level corresponding to the upper limit of the driving capability based on a preset level association relationship; determine a driving current range corresponding to the target level and a signal slew rate range corresponding to the target level; adjust the initial driving current to the middle value of the driving current range, so as to use the middle value of the driving current range as the target electrical parameter; and adjust the initial signal slew rate to the middle value of the signal slew rate range, so as to use the middle value of the signal slew rate range as the target electrical parameter.

9. A computer device, characterized in that, The computer device includes a processor and a memory, the memory being used to store at least one program, the at least one program being loaded by the processor and executed as the chip driver parameter configuration method as described in any one of claims 1 to 7.

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