Pixel circuit, display panel and display device

Abstract

The invention provides a pixel circuit, a display panel and a display device, and relates to the technical field of display, the pixel circuit comprises a driving transistor, a first transistor, a second transistor, a third transistor, a first capacitor and a second capacitor, a grid electrode, a first pole and a second pole of the driving transistor are respectively connected with a first node, a second node and a third node, the first transistor is connected between a first power supply signal end and a second node, the second transistor is connected between a data signal end and a first node, and the third transistor is connected between a third node and a reset signal end. The first capacitor is connected between the first power supply signal end and the second node, and the second capacitor is connected between the first node and the second node. In the four transistors included in the pixel circuit, the body end of at least one transistor is connected with a third power supply signal end, and the third power supply signal end is different from the first power supply signal end, so that the display effect of a display product is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, display panel, and display device. Background Technology

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] In existing display products, the light emission of the light-emitting element is controlled by the pixel circuit. How to improve the accuracy of the driving signal provided by the pixel circuit to the light-emitting element and improve the display effect has become one of the technical problems that urgently need to be solved at this stage. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a pixel circuit, a display panel, and a display device, aiming to improve the accuracy of the driving signals provided by the pixel circuit to the light-emitting elements and enhance the display effect of the display product.

[0005] In a first aspect, this disclosure provides a pixel circuit, including a driving transistor, a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a light-emitting element; the gate of the driving transistor is connected to a first node, a first electrode is connected to a second node, and a second electrode is connected to a third node; the first electrode of the first transistor is connected to a first power supply signal terminal, the second electrode is connected to the second node, and the gate is connected to a first control signal terminal; the first electrode of the second transistor is connected to a data signal terminal, the second electrode is connected to the first node, and the gate is connected to a second control signal terminal; the first electrode of the third transistor is connected to a reset signal terminal, the second electrode is connected to the third node, and the gate is connected to a third control signal terminal; the first plate of the first capacitor is connected to the first power supply signal terminal, and the second plate is connected to the second node; the first plate of the second capacitor is connected to the second node, and the second plate is connected to the first node; the first electrode of the light-emitting element is connected to the third node, and the second electrode is connected to a second power supply signal terminal; at least one of the driving transistor, the first transistor, the second transistor, and the third transistor has its body terminal connected to the third power supply signal terminal, and the first power supply signal terminal, the second power supply signal terminal, and the third power supply signal terminal are respectively connected to different power supply signal lines.

[0006] Secondly, based on the same inventive concept, this disclosure provides a display panel including the pixel circuit provided in the first aspect of this disclosure.

[0007] Thirdly, based on the same inventive concept, this disclosure provides a display device, including the display panel provided in the second aspect of this disclosure.

[0008] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0009] In the pixel circuit, display panel, and display device provided in this disclosure, at least one of the driving transistor, first transistor, second transistor, and third transistor has its body terminal connected to a third power supply signal terminal, instead of the first power supply signal terminal connected to the first capacitor. In this case, the capacitance between the first node and the second node and the first power supply signal terminal is simply increased, while the capacitance between the first node and the third power supply signal terminal and the second node and the third power supply signal terminal remain unchanged. Therefore, the original proportional relationship and capacitance value of the first capacitor and the second capacitor are not affected, meaning the relationship between the first capacitor and the second capacitor is fixed. Consequently, the compensation effect of the first capacitor and the second capacitor on the threshold voltage of the driving transistor in the pixel circuit is not affected. This is beneficial for improving the accuracy of the driving current output to the light-emitting element, thus improving the brightness uniformity of the light-emitting element and enhancing the display effect. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 The diagram shown is a schematic representation of a pixel circuit provided in an embodiment of this disclosure.

[0013] Figure 2 The image shown is a schematic diagram of a pixel circuit structure in related technologies;

[0014] Figure 3 The diagram shown is another structural schematic of the pixel circuit provided in an embodiment of this disclosure;

[0015] Figure 4 The diagram shown is a schematic diagram of another structure of the pixel circuit provided in an embodiment of this disclosure;

[0016] Figure 5The diagram shown is a schematic diagram of a connection between a pixel circuit and a power signal line provided in an embodiment of this disclosure;

[0017] Figure 6 The diagram shown is a wiring schematic of the first power signal line and the third power signal line;

[0018] Figure 7 The diagram shown is a schematic of a film layer of the pixel circuit provided in this disclosure;

[0019] Figure 8 The diagram shown is another film layer schematic of the pixel circuit provided in this disclosure;

[0020] Figure 9 The diagram shown is a wiring schematic of the first power signal line;

[0021] Figure 10 The diagram shows a possible connection between the first power signal line and the third power signal line and the signal input terminal.

[0022] Figure 11 The image shown is a plan view of a display panel provided in an embodiment of this disclosure;

[0023] Figure 12 The figure shown is a plan view of a display device provided in an embodiment of this disclosure.

[0024] Wherein, 00 is the pixel circuit; M0 is the driving transistor; M1 is the first transistor; M2 is the second transistor; M3 is the third transistor; C1 is the first capacitor; C2 is the second capacitor; D0 is the light-emitting element; VDD is the first power signal terminal; VSS is the second power signal terminal; VDD* is the third power signal terminal; L1 is the first power signal line; L2 is the second power signal line; L3 is the third power signal line; K is the first node; A is the second node; Q is the third node; S1 is the first control signal terminal; S2 is the second control signal terminal; S3 is the third control signal terminal; Vdt is the data signal terminal; Vref is the reset signal terminal; m01 is the first metal layer; m02 is the second metal layer; P0 is the signal input terminal; 100 is the display panel; 200 is the display device. Detailed Implementation

[0025] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0026] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0027] Figure 1 The diagram shown is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure. The pixel circuit 00 is applied in a display panel and is used to provide a driving signal to the light-emitting element D0 to drive the light-emitting element to emit light.

[0028] The pixel circuit 00 includes a driving transistor M0, a first transistor M1, a second transistor M2, a third transistor M3, a first capacitor C1, a second capacitor C2, and a light-emitting element D0; it should be noted that... Figure 1 The diagram only illustrates the connection relationships of the transistors, capacitors, and light-emitting elements D0 in the pixel circuit 00, and does not limit the actual layout of the transistors, capacitors, and light-emitting elements D0.

[0029] Specifically, in the pixel circuit 00, the gate of the driving transistor M0 is connected to the first node K, the first electrode is connected to the second node A, and the second electrode is connected to the third node Q. The driving transistor M0 is used to generate a driving signal to drive the light-emitting element D0 to emit light. It should be noted that the first electrode of the driving transistor M0 mentioned in this embodiment can be, for example, the source of the driving transistor M0, and the second electrode can be, for example, the drain of the driving transistor M0. Similar descriptions are used for other transistors, and the similarities will not be repeated. In the pixel circuit 00, the first electrode and the second electrode of the first transistor M1 are connected between the first power supply signal terminal VDD and the second node A. Specifically, the first electrode of the first transistor M1 is connected to the first power supply signal terminal VDD, the second electrode of the first transistor M1 is connected to the second node A, and the gate of the first transistor M1 is connected to the first control signal terminal S1. When the signal from the first control signal terminal S1 controls the first transistor M1 to be turned on, the power signal of the first power supply signal terminal VDD can be transmitted to the second node A, which is the first electrode of the driving transistor M0, through the first transistor M1. The first and second terminals of the second transistor M2 are connected between the data signal terminal Vdt and the first node K. Specifically, the first terminal of the second transistor M2 is connected to the data signal terminal Vdt, and the second terminal of the second transistor M2 is connected to the first node K. The gate of the second transistor M2 is connected to the second control signal terminal S2. When the signal from the second control signal terminal S2 controls the second transistor M2 to conduct, the data signal at the data signal terminal Vdt can be transmitted to the first node K, which is the gate of the driving transistor M0, through the second transistor M2. The first and second terminals of the third transistor M3 are connected between the reset signal terminal Vref and the third node Q. Specifically, the first terminal of the third transistor M3 is connected to the reset signal terminal Vref, and the second terminal of the third transistor M3 is connected to the third node Q. The gate of the third transistor M3 is connected to the third control signal terminal S3. When the signal from the third control signal terminal S3 controls the third transistor M3 to conduct, the reset signal from the reset signal terminal Vref is transmitted to the third node Q, which is the anode of the light-emitting element D0, through the third transistor M3 to reset it. The first plate of the first capacitor C1 is connected to the first power supply signal terminal VDD, and the second plate is connected to the second node A. The first plate of the second capacitor C2 is connected to the second node A, and the second plate is connected to the first node K. The first electrode of the light-emitting element D0 is connected to the third node Q, and the second electrode is connected to the second power supply signal terminal VSS. Optionally, the first electrode of the light-emitting element D0 is the anode, and the second electrode is the cathode. Optionally, the reset signal terminal Vref can be multiplexed with the second power supply signal terminal VSS, and both receive the same signal.

[0030] In this disclosure, among the driving transistor M0, the first transistor M1, the second transistor M2, and the third transistor M3, at least one transistor's body terminal is connected to a third power supply signal terminal VDD*. The first power supply signal terminal VDD, the second power supply signal terminal VSS, and the third power supply signal terminal VDD* are respectively connected to different power supply signal lines. Specifically, the first power supply signal terminal VDD can provide the pixel circuit 00 with a positive voltage signal required for the light-emitting element D0 to emit light; the second power supply signal terminal VSS can provide a negative voltage signal to the cathode of the light-emitting element D0; and the third power supply signal terminal VDD* is used to provide a constant voltage signal to the body terminal of the corresponding transistor. Figure 1 The illustrated embodiment uses the example of connecting the body terminals of the first transistor M1 and the second transistor M2 to the third power signal terminal VDD*, but does not limit the number or type of transistors in the pixel circuit 00 whose body terminals are connected to the third power signal terminal VDD*.

[0031] In one optional embodiment of this disclosure, the driving transistor M0, the first transistor M1, the second transistor M2 and the third transistor M3 are all PMOS transistors, and the light-emitting element D0 is an OLED (Organic Light-Emitting Diode) display device.

[0032] Figure 1 The operation of the pixel circuit 00 shown includes:

[0033] During the initialization phase, the signal from the first control signal terminal S1 controls the first transistor M1 to conduct, and the voltage signal VDD from the first power supply signal terminal VDD (the same character is used to represent the signal terminal and the signal provided by the signal terminal) is transmitted through the first transistor M1 to the second node A, which is the source of the driving transistor M0, and also the first plate of the second capacitor C2. The signal from the second control signal terminal S2 controls the second transistor M2 to conduct, and the signal V01 from the data signal terminal Vdt is transmitted through the second transistor M2 to the first node K, which is the gate of the driving transistor M0, and also the second plate of the second capacitor C2. The signal from the third control signal terminal S3 controls the third transistor M3 to conduct, and the reset signal Vref from the reset signal terminal is transmitted through the third transistor M3 to the anode of the light-emitting element D0, resetting the anode of the light-emitting element D0. At this time, the voltage difference between the first node K and the second node A satisfies |V01-VDD|>Vth, where Vth is the preset threshold voltage of the driving transistor M0.

[0034] During the threshold voltage detection phase, the signal from the third control signal terminal S3 controls the third transistor M3 to turn on, the signal from the first control signal terminal S1 controls the first transistor M1 to turn off, and the signal from the second control signal terminal S2 controls the second transistor M2 to turn off. At this time, the potentials of the first node K and the second node A are floating, driving the transistor M0 to start self-discharge operation.

[0035] During the data writing phase, the first transistor M1 is turned off, and the second transistor M2 is turned on. The data signal Vdata at the data signal terminal Vdt is transmitted to the first node K. That is, the potential of the first node K changes from V01 to Vdata. Due to the coupling effect of the first capacitor C1 and the second capacitor C2, the potential of the source of the driving transistor M0, i.e., the second node A, also changes. At this time, the potential change of the first node K and the potential change of the second node A are related to C1 / (C1+C2). In other words, the threshold voltage of the driving transistor M0 is related to C1 / (C1+C2).

[0036] During the light-emitting stage, the first transistor M1 is turned on, while the second transistor M2 and the third transistor M3 are turned off. A path is formed between the first power signal terminal VDD and the cathode of the light-emitting element D0, and the light-emitting element D0 begins to emit light.

[0037] During the light-emitting stage, the first capacitor C1 and the second capacitor C2 need to be in a certain ratio to effectively maintain the potential of the first node K and the second node A, so as to effectively compensate the pixel circuit 00 and improve the brightness uniformity of the light-emitting element D0. Figure 2 The diagram shown illustrates a pixel circuit in related technologies. This pixel circuit is connected to a first power supply signal terminal VDD', a second power supply signal terminal VSS', a data signal terminal Vdt', and a reset signal terminal Vref'. For specific connection details, please refer to [reference needed]. Figure 2In this circuit, the body terminals of the driving transistor M0', the first transistor M1', the second transistor M2', and the third transistor M3' are all connected to the first power supply signal terminal VDD'. That is, the body terminals of all four transistors are connected to the positive power supply signal terminal that provides power to the light-emitting element D0'. At this time, the pixel circuit only has the first power supply signal terminal VDD' and the second power supply signal terminal VSS' connected to the cathode of the light-emitting element D0'. One terminal of the first capacitor C1' is connected to the first power supply signal terminal VDD', and the other terminal is connected to one terminal of the second capacitor C2'. The body terminal of the transistor is also connected to the first power supply signal terminal VDD'. When the voltage of the gate and source of the transistor changes, the voltage of its body terminal also changes accordingly. Since the body terminal of the transistor is connected to the first power supply signal terminal VDD', the change in the voltage of the body terminal will be coupled to the first power supply signal terminal VDD'. There will be a large number of coupling capacitances between the body terminal of the transistor and the first node K', and between the body terminal and the second node A'. This will change the capacitance relationship between the first node K' and the second node A', between the second node A' and the first power supply signal terminal VDD', and between the first node K' and the first power supply signal terminal VDD'. This will cause the capacitance values ​​and proportional relationship of the first capacitor C1' and the second capacitor C2' to change, resulting in exceeding the compensation range. This will prevent the transistor M0' from effectively compensating for the threshold voltage, affecting the magnitude of the driving current output to the light-emitting element D0', and thus affecting the display effect of the light-emitting element D0'. It may even cause the pixel circuit to fail.

[0038] Therefore, in the pixel circuit 00 provided in this disclosure, please continue to refer to... Figure 1The body terminal of at least one of the driving transistors M0, M1, M2, and M3 is connected to the third power supply signal terminal VDD*. Since one terminal of the first capacitor C1 is connected to the first power supply signal terminal VDD, the signal at the third power supply signal terminal VDD* connected to the body terminal of the transistor is unrelated to the signal at the first power supply signal terminal VDD connected to the first capacitor C1. Even if the voltage at the body terminal of the transistor changes, the capacitance between the first node K and the second node A and the first power supply signal terminal VDD becomes simply an increase in the capacitance between the first node K and the third power supply signal terminal VDD*, and the capacitance between the second node A and the third power supply signal terminal VDD*. The capacitance between the power signal terminals VDD* will not change the capacitance between the first node K and the second node A, between the second node A and the first power signal terminal VDD, or between the first node K and the first power signal terminal VDD. Therefore, it will not affect the original ratio between the first capacitor C1 and the second capacitor C2. That is, the relationship between the first capacitor C1 and the second capacitor C2 is fixed. Thus, it will not affect the compensation effect of the first capacitor C1 and the second capacitor C2 on the threshold voltage of the driving transistor M0 in the pixel circuit 00. This is beneficial to improving the accuracy of the driving current output to the light-emitting element D0, thereby improving the brightness uniformity of the light-emitting element D0 and enhancing the display effect.

[0039] Figure 3 The diagram shown is another structural schematic of the pixel circuit 00 provided in this embodiment of the present disclosure, and the basic connection relationship of the transistor, capacitor and light-emitting element is as follows: Figure 1 The embodiments are the same, and the repeated parts will not be described again. This embodiment is the same as... Figure 1 The difference in the embodiments lies in the number of transistors connected to the third power signal terminal VDD* at the body end. Please refer to [link / reference]. Figure 3In one optional embodiment of this disclosure, the body terminals of the first transistor M1, the second transistor M2, and the driving transistor M0 are all electrically connected to the third power supply signal terminal VDD*. In the pixel circuit 00 provided by this disclosure, the second terminal of the first transistor M1 is connected to the second node A, the second terminal of the second transistor M2 is connected to the first node K, and the gate and first terminal of the driving transistor M0 are respectively connected to the first node K and the second node A. That is, the first transistor M1, the second transistor M2, and the driving transistor M0 are all connected to either the first capacitor C1 or the second capacitor C2. In this case, when the body terminals of the first transistor M1, the second transistor M2, and the driving transistor M0 are connected to the third power supply signal terminal VDD*, the change in the coupling capacitance of the body terminals of the first transistor M1, the second transistor M2, and the third transistor M0 will not affect the connection between the first power supply signal terminal VDD and the first node A. The voltage between node K and the second node A, and the capacitance between the first node K and the second node A and the first power signal terminal VDD, are changed by only increasing the capacitance between the first node K and the third power signal terminal VDD*, and the capacitance between the second node A and the third power signal terminal VDD*. Similarly, the capacitance between the first node K and the second node A, between the second node A and the first power signal terminal VDD, and between the first node K and the first power signal terminal VDD are not changed. Therefore, the original ratio and capacitance value of the first capacitor C1 and the second capacitor C2 will not be affected. This is also beneficial to ensuring the compensation effect of the first capacitor C1 and the second capacitor C2 on the threshold voltage of the driving transistor M0.

[0040] Figure 4 The diagram shown is another structural schematic of the pixel circuit 00 provided in this embodiment of the present disclosure, illustrating the basic connection relationships of the transistors, capacitors, and light-emitting elements. Figure 1 The implementation methods are the same, and the repeated parts will not be described again. Figure 1 and Figure 3 The difference in the embodiments lies in the number of transistors connected to the third power signal terminal VDD* at the body end. Please refer to [link / reference]. Figure 4In one optional embodiment of this disclosure, the body terminals of driving transistor M0, first transistor M1, second transistor M2, and third transistor M3 are all electrically connected to the third power supply signal terminal VDD*. This embodiment illustrates a scheme in which the body terminals of each transistor in the pixel circuit 00 are connected to the third power supply signal terminal VDD*. This design ensures that voltage changes at the body terminals of each transistor do not affect the capacitance between the first power supply signal terminal VDD and the first node K and the second node A. The capacitance between the first node K and the second node A and the first power supply signal terminal VDD is simply increased by adding the capacitance between the first node K and the third power supply signal terminal VDD*, and the capacitance between the second node A and the third power supply signal terminal VDD*. This ensures that the proportional relationship and voltage value of the first capacitor C1 and the second capacitor C2 are not affected, thus helping to guarantee the compensation effect of the first capacitor C1 and the second capacitor C2 on the pixel circuit 00 and improving the display effect. Furthermore, in actual manufacturing processes, the same process can be used to connect the body terminals of each transistor to the third power supply signal terminal VDD*, eliminating the need to introduce different connection processes for different transistors, which also helps to improve production efficiency.

[0041] Please refer to Figure 1 , Figure 3 and Figure 4 In one optional embodiment of this disclosure, the first power signal terminal VDD is configured to transmit a first constant voltage signal with a voltage value of V1 to the pixel circuit 00, and the third power signal terminal VDD* is configured to transmit a second constant voltage signal with a voltage value of V2 to the body terminal of the corresponding transistor, wherein V1 = V2. In the pixel circuit, the first transistor M1 is the transistor that transmits the signal of the first power signal terminal VDD to the driving transistor during the light-emitting stage. When the first transistor M1 is turned on, the source of the driving transistor M0 is also connected to the voltage of the first power signal terminal VDD. Therefore, the threshold voltages of the first transistor M1 and the driving transistor M0 will affect the driving current provided to the light-emitting element D0. In this embodiment, when the voltage value of the third power signal terminal VDD* connected to the body terminal of the transistor is set to be the same as the voltage value of the first power signal terminal VDD, the voltages of the source and body terminals of the first transistor M1 and the driving transistor M0 will be the same during the light-emitting stage. It should be noted that when the source and body voltages of the first transistor M1 and the driving transistor M0 are inconsistent, the body terminal of the transistor has a bias voltage, which changes the threshold voltage of the transistor and affects the current output to the light-emitting element D0. In this embodiment, setting the source and body voltages of the transistors to be the same avoids the threshold voltage variation caused by the difference between the source and body voltages. This helps reduce the variation of the threshold voltage of the transistors during the operation of the pixel circuit 00, thereby improving the accuracy and stability of the driving current provided by the pixel circuit 00 to the light-emitting element D0, and ultimately improving the uniformity of display brightness.

[0042] Figure 5 The diagram shows a connection schematic of a pixel circuit 00 and a power signal line provided in an embodiment of this disclosure. The pixel circuit 00 further includes a first power signal line L1, a second power signal line L2, and a third power signal line L3. The first power signal terminal VDD in the pixel circuit 00 is connected to the first power signal line L1, and a corresponding power voltage signal is transmitted to the first power signal terminal VDD through the first power signal line L1. This power voltage signal is the power signal that drives the light-emitting element D0 to emit light. The second power signal terminal VSS is connected to the second power signal line L2, and a corresponding power voltage signal is transmitted to the second power signal terminal VSS through the second power signal line L2. This power voltage signal is the voltage signal connected to the negative terminal of the light-emitting element D0. The third power signal terminal VDD* is connected to the third power signal line L3, and a corresponding power voltage signal is transmitted to the third power signal terminal VDD* through the third power signal line L3. This power voltage signal is a constant voltage signal provided to the body terminal of the transistor.

[0043] Figure 6 The diagram shows a possible wiring diagram for a first power signal line L1 and a third power signal line L3. Only a portion of the first power signal lines L1 and third power signal lines L3 are shown, and this does not represent the actual number of first power signal lines L1 and third power signal lines L3. The area percentage of the first power signal line L1 is greater than the area percentage of the third power signal line L3. When the total area of ​​the first power signal line L1 and the third power signal line L3 is used as a reference, the area percentage of the first power signal line L1 refers to the ratio of the area of ​​the first power signal line L1 to the total area, and the area percentage of the third power signal line L3 refers to the ratio of the area of ​​the third power signal line L3 to the total area. For example, the number of first power signal lines L1 may be greater than the number of third power signal lines L3, or, if the number of both is the same, the width of the first power signal line L1 may be greater, etc. Considering that the voltage signal provided by the first power signal line L1 is used to drive the light-emitting element D0 to emit light, and a driving current is generated based on this voltage signal to drive the light-emitting element D0 to emit light, while the function of the third power signal line L3 is to provide a constant power supply voltage signal to the body terminal of the transistor, which does not need to generate current or generates very little current, in this embodiment, the area ratio of the first power signal line L1 is set to be relatively large, which is beneficial to ensure the reliability of the driving current output to the light-emitting element D0.

[0044] Figure 7 The diagram shown is a schematic of a film layer for a pixel circuit provided in this disclosure. This diagram only illustrates a portion of the transistors and the first power signal line L1 and the third power signal line L3. Structures located on the same metal layer use the same pattern filling. Please refer to... Figure 6 and Figure 7Optionally, in this embodiment, the first power signal line L1 and the third power signal line L3 are disposed on the same metal layer. This eliminates the need to introduce different film layer structures for the first power signal line L1 and the third power signal line L3, and the fabrication of the first power signal line L1 and the third power signal line L3 can be completed in the same process, which is beneficial to improving production efficiency.

[0045] Please continue to refer to this. Figure 6 When the first power signal line L1 and the third power signal line L3 are disposed on the same metal layer, in order to achieve that the area ratio of the first power signal line L1 is greater than or equal to the area ratio of the third power signal line L3, when the area ratio of the first power signal line L1 is greater than the area ratio of the third power signal line L3, one optional implementation is to set the line width of the first power signal line L1 to be greater than the line width of the third power signal line L3. This is equivalent to reducing the impedance of the first power signal line L1, which is beneficial to improving the transmission rate of the first power voltage signal transmitted on the first power signal line L1, reducing the difference in the first power voltage signal received by the pixel circuits in different areas, and thus improving the uniformity of the display brightness of the light-emitting elements D0 corresponding to different pixel circuits.

[0046] Figure 8 The diagram shown is another film layer schematic of the pixel circuit 00 provided in this disclosure. Figure 9 The diagram shown is a wiring schematic for the first power signal line L1. Please refer to it. Figure 8 and Figure 9 In one optional embodiment of this disclosure, the first power signal line L1 is located in the first metal layer m01, and the third power signal line L3 is located in the second metal layer m02. An insulating layer separates the first metal layer m01 from the second metal layer m02. In the first metal layer m01, the first power signal line L1 is positioned as follows: Figure 9 The mesh wiring structure shown.

[0047] This embodiment illustrates a scheme where the first power signal line L1 and the third power signal line L3 are disposed on different metal layers. The power signal transmitted by the first power signal line L1 is transmitted to the pixel circuit through the first metal layer, and the power signal transmitted by the third power signal line L3 is transmitted to the pixel circuit through the second metal layer. The voltage signal provided by the first power signal line L1 is used to drive the light-emitting element to emit light. Based on this voltage signal, a driving current is generated to drive the light-emitting element to emit light. The magnitude of the driving current is closely related to the magnitude of the voltage transmitted on the first power signal line L1. Considering that there is a voltage drop during the transmission of the voltage signal, in this embodiment, setting the first power signal line L1 as a mesh wiring structure is beneficial to reducing the overall impedance of the first power signal line L1 and reducing the voltage transmission voltage drop. This helps to reduce the difference in the power signal received by the pixel circuits 00 in different areas, thus improving the uniformity of the display brightness of the light-emitting elements D0 connected to different pixel circuits and improving the overall display effect.

[0048] Alternatively, the third power signal line L3 located on the second metal layer can also be manifested as follows: Figure 9 The mesh wiring structure shown is used to reduce signal transmission voltage drop. Of course, in some other embodiments of this disclosure, the third power signal line L3 can also be disposed in other metal film layers in the pixel circuit and employ a method such as... Figure 6 The wiring method shown is not specifically limited in this disclosure. Furthermore, when the first power signal line L1 and the third power signal line L3 are arranged on different layers, the first power signal line L1 and the third power signal line L3 can also adopt the following... Figure 6 The strip wiring structure shown.

[0049] It should be noted that, Figure 7 and Figure 8 The illustrated embodiment shows a scheme in which the film layer containing the first power signal line L1 and the third power signal line L3 is set separately from the film layer containing the transistor. However, this disclosure is not limited thereto. In some other feasible embodiments, at least one of the first power signal line L1 and the third power signal line L3 may also be set in the metal film layer structure where the transistor is located, for example, set in the same layer as the gate of the transistor, or set in the same layer as the source and drain of the transistor, etc. This disclosure does not specifically limit this.

[0050] Figure 10 The diagram illustrates one possible connection between the first power signal line L1 and the third power signal line L3 and the signal input terminal P0. It is illustrated using an example where the first power signal line L1 and the third power signal line L3 are located on the same film layer, and the line width of the first power signal line L1 is greater than the line width of the third power signal line L3. Please refer to [reference needed]. Figure 10In one optional embodiment of this disclosure, a signal input terminal P0 is further included. The signal input terminal P0 is used to transmit power signals; the first power signal line L1 and the third power signal line L3 are connected to the same signal input terminal P0. When the first power signal line L1 and the third power signal line L3 are connected to the same signal input terminal P0, the same power signal is transmitted on the first power signal line L1 and the third power signal line L3. At this time, it is equivalent to making the voltage of the body terminal and the source terminal of the transistor in the pixel circuit the same. This avoids the change of threshold voltage caused by the difference between the source terminal and the body terminal voltage, which helps to reduce the change of the threshold voltage of the transistor during the operation of the pixel circuit, thereby improving the accuracy and stability of the driving current provided by the pixel circuit to the light-emitting element, and thus helping to improve the uniformity of display brightness. In addition, when the first power signal line L1 and the third power signal line L3 are connected to the same signal input terminal P0, it is not necessary to set different signal input terminals for the first power signal line L1 and the third power signal line L3, which also helps to reduce the total number of signal input terminals P0, thus simplifying the overall design structure.

[0051] It should be noted that although the first power signal line L1 and the third power signal line L3 are connected to the same signal input terminal P0 and receive the same voltage signal, since the first power signal line L1 and the third power signal line L3 are two independent signal lines in the array formed by the pixel circuit, the third power signal line L3 is not connected to the first capacitor C1, but only to the body terminal of the transistor. Therefore, the voltage change at the body terminal of the transistor will not affect the capacitance between the first power signal terminal VDD connected to the first power signal line L1 and the first node K and the second node A.

[0052] Understandable, Figure 10 The following explanation is based on the example of the first power signal line L1 and the third power signal line L3 being set on the same layer and connected to the same signal input terminal P0. It can be understood that when the first power signal line L1 and the third power signal line L3 are located on different metal layers, they can also be connected to the same signal input terminal.

[0053] Of course, in some other optional embodiments of this disclosure, the first power signal line L1 and the third power signal line L3 may also be connected to different signal input terminals P0 respectively. The two different signal input terminals P0 can also provide the same power signal to the first power signal line L1 and the third power signal line L3, which is also beneficial to reduce the threshold variation of the transistor.

[0054] Based on the same inventive concept, this disclosure also provides a display panel. Figure 11The diagram shown is a plan view of a display panel 100 provided in an embodiment of this disclosure. The display panel includes the pixel circuit 00 provided in the above embodiments of this disclosure. Optionally, the display panel provided in this disclosure is a silicon-based organic light-emitting display panel. The silicon-based organic light-emitting display panel is an organic light-emitting display panel based on a single-crystal silicon chip with CMOS driving transistor circuitry, which can provide high resolution and high refresh rate.

[0055] The display panel provided in this disclosure includes a plurality of pixel circuits 00 as mentioned in the foregoing embodiments, wherein, Figure 11 This illustration only shows a portion of the pixel circuits 00 in the display panel and does not limit the actual number or arrangement of the pixel circuits 00.

[0056] Please refer to Figure 11 and combined Figure 1 , Figure 3 and Figure 4 Since the display panel provided in this disclosure includes the pixel circuit 00 in the above embodiments, that is, the body terminal of at least one transistor in the pixel circuit 00 is connected to the third voltage signal terminal instead of the first voltage signal terminal, it is advantageous to avoid the problem of affecting the ratio and capacitance value of the first capacitor C1 and the second capacitor C2 due to connecting the body terminal of the transistor to the first voltage signal terminal. It is advantageous to ensure the compensation effect of the first capacitor C1 and the second capacitor C2 on the pixel circuit 00, thus improving the overall display brightness uniformity of the display panel.

[0057] The display panel 100 provided in this embodiment has the beneficial effects of the pixel circuit 00 provided in the above embodiments of this disclosure. For details, please refer to the specific description of the pixel circuit 00 in the above embodiments. This embodiment will not repeat the description here.

[0058] Based on the same inventive concept, this disclosure also provides a display device. Figure 12 The diagram shown is a plan view of a display device 200 provided in an embodiment of this disclosure. The display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in this disclosure can be any electronic device with display function, such as a virtual display device, a tablet computer with touch and display functions, a television, or an in-vehicle display device.

[0059] The display device 200 provided in this embodiment has the beneficial effects of the display panel 100 provided in this embodiment. For details, please refer to the specific description of the display panel 100 in the above embodiments. This embodiment will not repeat the description here.

[0060] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0061] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pixel circuit, characterized in that, The system includes a driving transistor, a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a light-emitting element. The gate of the driving transistor is connected to a first node, its first electrode is connected to a second node, and its second electrode is connected to a third node. The first electrode of the first transistor is connected to a first power signal terminal, its second electrode is connected to the second node, and its gate is connected to a first control signal terminal. The first electrode of the second transistor is connected to a data signal terminal, its second electrode is connected to the first node, and its gate is connected to a second control signal terminal. The first electrode of the third transistor is connected to a reset signal terminal, its second electrode is connected to the third node, and its gate is connected to a third control signal terminal. The first plate of the first capacitor is connected to the first power signal terminal, and its second plate is connected to the second node. The first plate of the second capacitor is connected to the second node, and the second plate is connected to the first node; The first electrode of the light-emitting element is connected to the third node, and the second electrode is connected to the second power signal terminal. In the driving transistor, the first transistor, the second transistor, and the third transistor, at least one transistor's body terminal is connected to a third power signal terminal, and the first power signal terminal, the second power signal terminal, and the third power signal terminal are respectively connected to different power signal lines.

2. The pixel circuit according to claim 1, characterized in that, The body terminals of the first transistor, the second transistor, and the driving transistor are all electrically connected to the third power signal terminal.

3. The pixel circuit according to claim 1, characterized in that, The body terminals of the driving transistor, the first transistor, the second transistor, and the third transistor are all electrically connected to the third power supply signal terminal.

4. The pixel circuit according to claim 1, characterized in that, The driving transistor, the first transistor, the second transistor, and the third transistor are all PMOS transistors.

5. The pixel circuit according to claim 1, characterized in that, The first power signal terminal is configured to transmit a first constant voltage signal with a voltage value of V1 to the pixel circuit, and the third power signal terminal is configured to transmit a second constant voltage signal with a voltage value of V2 to the body terminal of the corresponding transistor, wherein V1 = V2.

6. The pixel circuit according to claim 5, characterized in that, It also includes a signal input terminal for transmitting power signals; the first power signal line and the third power signal line are connected to the same signal input terminal.

7. The pixel circuit according to claim 1, characterized in that, It includes a first power signal line, a second power signal line, and a third power signal line. The first power signal terminal is connected to the first power signal line, the second power signal terminal is connected to the second power signal line, and the third power signal terminal is connected to the third power signal line. The area ratio of the first power signal line is greater than or equal to the area ratio of the third power signal line.

8. The pixel circuit according to claim 7, characterized in that, The first power signal line and the third power signal line are disposed on the same metal layer.

9. The pixel circuit according to claim 8, characterized in that, The width of the first power signal line is greater than the width of the third power signal line.

10. The pixel circuit according to claim 7, characterized in that, The first power signal line is located on the first metal layer, the third power signal line is located on the second metal layer, and the first metal layer and the second metal layer are isolated by an insulating layer. In the first metal layer, the first power signal line has a mesh wiring structure.

11. A display panel, characterized in that, Includes the pixel circuit described in any one of claims 1 to 10.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

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