A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, which comprise N cascaded gate driving units, each of which comprises: a pull-up module configured to pre-charge a driving control node according to an nth-i stage transmission signal output by an nth-i stage output module; an output module configured to output a stage transmission signal of a current stage and at least two gate driving signals under the action of a driving voltage on the driving control node and at least two clock signals; and a charge compensation module configured to be pre-charged to an initial compensation voltage under the action of the nth-i stage transmission signal, and to maintain the driving control node at a target driving voltage under the action of the initial compensation voltage and an external compensation signal within at least two driving signal output periods of the output module when the driving voltage of the driving control node is located in a preset voltage threshold range. The application can improve the stability of the gate driving voltage.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] With the development of high-resolution and high-refresh-rate display panels, gate driver on left (GDL) circuits are widely used in display devices such as active-matrix organic light-emitting diodes (AMOLEDs) and electronic paper. To achieve narrow bezel designs, multiple gate drive signal outputs are often controlled by a single drive control node to simplify wiring and reduce load.

[0003] However, this wiring method will cause leakage current in the drive control node, making the output gate drive voltage unstable. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the problem of unstable gate driving voltage.

[0005] In a first aspect, this application provides a gate driving circuit, including N cascaded gate driving units. Each gate driving unit includes: a pull-up module connected to a driving control node, configured to pre-charge the driving control node according to the ni-th stage transmission signal output by the ni-th stage output module; an output module connected to the driving control node and at least two clock signal lines corresponding to the current stage, configured to output the current stage transmission signal and at least two gate driving signals under the action of the driving voltage on the driving control node and at least two clock signals; and a charge compensation module connected to the driving control node and an external control device, configured to pre-charge to an initial compensation voltage under the action of the ni-th stage transmission signal, and when the driving voltage of the driving control node is within a preset voltage threshold range, maintain the driving control node at a target driving voltage under the action of the initial compensation voltage and the external compensation signal during at least two driving signal output cycles of the output module.

[0006] Optionally, the charge compensation module includes: a pre-charge submodule connected to the drive control node, configured to pre-charge to the initial compensation voltage under the action of the nith stage transmission signal output by the nith stage output module; and a maintenance submodule connected to the pre-charge submodule, the external control device, and the drive output terminal of the output module, configured to maintain the drive control node at the target drive voltage during at least two drive signal output cycles of the output module when the drive voltage of the drive control node is within the preset voltage threshold range, under the action of the initial compensation voltage, the gate drive signal output by the output module, and the external compensation signal.

[0007] Optionally, the pre-charge submodule includes: a first transistor, a first capacitor, a second transistor, and a third transistor; the control terminal of the first transistor and the first terminal of the first transistor are connected to the drive control node; the second terminal of the first transistor is connected to the first terminal of the first capacitor; the control terminal of the second transistor is connected to the first terminal of the second transistor; the second terminal of the first capacitor is connected to the first terminal of the third transistor and the sustaining submodule; the second terminal of the second transistor is connected to the drive control node; the control terminal of the third transistor is connected to the stage output terminal of the nth stage output module; and the second terminal of the third transistor is connected to a low-level terminal.

[0008] Optionally, the sustaining submodule includes: a fourth transistor; the control terminal of the fourth transistor is connected to the drive output terminal of the output module, and the first terminal of the fourth transistor is connected to the external control device.

[0009] Optionally, the pre-charge submodule includes: a first transistor, a second transistor, a first capacitor, and a third transistor; the control terminal of the first transistor is connected to a first terminal of the first transistor, a second terminal of the second transistor, and a first terminal of the first capacitor, respectively, and the second terminal of the first transistor is connected to the drive control node; the control terminal of the second transistor is connected to the stage output terminal of the ni-th stage output module, and the first terminal of the second transistor is connected to a high-level terminal; the second terminal of the first capacitor and the first terminal of the third transistor are connected to the sustaining submodule; the control terminal of the third transistor is connected to the stage output terminal of the ni-th stage output module, and the second terminal of the third transistor is connected to a low-level terminal.

[0010] Optionally, the sustaining submodule includes: a fourth transistor, a second capacitor, a fifth transistor, and a sixth transistor; the control terminal of the fourth transistor is connected to the drive output terminal of the output module, the first terminal of the fourth transistor is connected to a high-level terminal, and the second terminal of the fourth transistor is connected to the pre-charge submodule and the first terminal of the second capacitor; the second terminal of the second capacitor is connected to the first terminal of the fifth transistor and the second terminal of the sixth transistor; the first control terminal of the fifth transistor is connected to the drive output terminal of the output module, the second control terminal of the fifth transistor is connected to the output terminal of the noise reduction control signal, and the second terminal of the fifth transistor is connected to a low-level terminal; the control terminal of the sixth transistor is connected to the drive output terminal of the output module, and the first terminal of the sixth transistor is connected to the external control device.

[0011] Optionally, the gate driving unit further includes a noise reduction module, which is connected to the second control terminal of the driving control node and the fifth transistor respectively, and is configured to generate the noise reduction control signal according to the driving voltage of the driving control node.

[0012] Optionally, the output module includes: a seventh transistor, at least two eighth transistors, a third capacitor, and at least two fourth capacitors; the control terminal of the seventh transistor, the first terminal of the third capacitor, the control terminal of each of the eighth transistors, and the first terminal of each of the fourth capacitors are connected to the drive control node; the first terminal of the seventh transistor is connected to a clock signal line, and the second terminal of the seventh transistor is connected to the second terminal of the third capacitor; the first terminal of each of the eighth transistors is connected to a clock signal line, and the second terminal of each of the eighth transistors is connected to the second terminal of the corresponding fourth capacitor.

[0013] Optionally, the gate driving unit further includes a detection module, which is connected to the driving control node and the external control device respectively, and is configured to detect the driving voltage of the driving control node and output it to the external control device so that the external controller generates the external compensation signal according to the driving voltage of the driving control node.

[0014] In a second aspect, this application provides a display panel including a display area and a non-display area, wherein the display area includes a plurality of scan lines, and the non-display area includes a gate driving circuit as described in any one of the first aspects, and the output module of the gate driving circuit is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] While the drive control node is pre-charged by the pull-up module, the voltage compensation module can also be charged, pre-charging the charge compensation module with the initial compensation voltage. When the drive voltage of the drive control node is within the preset voltage threshold range, it indicates that the drive control node has leakage. Under the action of the external compensation signal and the initial compensation voltage, the drive control node is maintained at the target drive voltage, and each gate drive signal corresponds to one drive signal output cycle. Maintaining the target drive voltage within at least two drive signal output cycles ensures that the drive voltage of the drive control node can control the output module to stably output at least two gate drive signals, thereby ensuring the stability of the display effect. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A structural diagram of a gate driving circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0020] Figure 3 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0021] Figure 4 A circuit diagram of a noise reduction module provided in an embodiment of this application is shown.

[0022] Figure 5 The diagram shows a waveform of a gate drive circuit provided in an embodiment of this application.

[0023] Explanation of reference numerals in the attached figures:

[0024] 100. Gate drive unit; 110. Pull-up module; 120. Output module; 130. Charge compensation module; 131. Precharge submodule; 132. Sustain submodule; 140. Detection module; 200. External control device; T1. First transistor; T2. Second transistor; T3. Third transistor; T4. Fourth transistor; T5. Fifth transistor; T6. Sixth transistor; T7. Seventh transistor; T8. Eighth transistor; T9. Ninth transistor; T10. Tenth transistor; T11. Eleventh transistor; T12. Twelfth transistor; T13. Thirteenth transistor; T14. Fourteenth transistor; T15. Fifteenth transistor; C1. First capacitor; C2. Second capacitor; C3. Third capacitor; 300. Reset module; 400. Pull-down module; 500. Noise reduction module. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0026] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0027] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0028] Figure 1 A structural diagram of a gate driving circuit provided in an embodiment of this application is shown below. Please refer to [link / reference]. Figure 1As shown, the gate drive circuit includes N cascaded gate drive units 100. Each gate drive unit 100 includes: a pull-up module 110, an output module 120, and a charge compensation module 130. The pull-up module 110 is connected to the drive control node Q, the output module 120 is connected to the drive control node Q and at least two clock signal lines corresponding to the current stage, and the charge compensation module 130 is connected to the drive control node Q and the external control device 200.

[0029] In some embodiments, the pull-up module 110 is configured to precharge the drive control node Q according to the nith stage transmission signal output by the nith stage output module 120.

[0030] For example, when the gate driving unit 100 is the nth stage, the driving control node Q is charged in advance by the i-th stage to ensure that the output module 120 can output the gate driving signal on time when it receives the corresponding clock signal.

[0031] In some embodiments, the output module 120 is configured to output the current stage transmission signal and at least two gate drive signals under the action of the drive voltage on the drive control node Q and at least two clock signals.

[0032] For example, this application uses multiple drive signal output terminals sharing a drive control node Q. The output module 120 has at least two drive output terminals. That is, under the action of at least two clock signals, the drive voltage generated by one drive control node Q will support the output module 120 to output at least two gate drive signals. One clock signal generates one gate drive signal to achieve scanning of at least two rows of pixels. The figure shows an example of the output module 120 having four gate output terminals, meaning that the drive voltage generated by one drive control node Q will support the output module 120 to output at least four gate drive signals.

[0033] Wherein, G(m), G(m+1), G(m+2), G(m+3), and G(m+4) represent the output terminals of the four gate drive signals, G(m+j) represents the output terminal of one of the at least two gate drive signals (e.g., j can be 1, 2, 3, etc.), F(n) represents the output terminal of the stage transmission signal of this stage, and F(ni) represents the output terminal of the stage transmission signal of the ni-th stage (i can be 2). ckx, ckx+1, ckx+2, and ckx+3 represent the clock signal lines acting on the gate drive signals, and CKy represents the clock signal line acting on the stage transmission signals.

[0034] In some embodiments, the charge compensation module 130 is configured to: precharge to the initial compensation voltage under the action of the nith stage transmission signal, and when the driving voltage of the driving control node Q is within a preset voltage threshold range, maintain the driving control node Q at the target driving voltage Vmax under the action of the initial compensation voltage and the external compensation signal during at least two driving signal output cycles of the output module 120.

[0035] For example, the charge compensation module 130 is connected to the drive control node Q. While the drive control node Q is pre-charged by the pull-up module 110, the voltage compensation module can also be charged to pre-charge the charge compensation module 130 with the initial compensation voltage. When the drive voltage of the drive control node Q is within the preset voltage threshold range, it indicates that the drive control node Q has leakage. Under the action of the initial compensation voltage and the external compensation signal, the drive control node Q is maintained at the target drive voltage Vmax. Each gate drive signal corresponds to one drive signal output cycle. By maintaining the target drive voltage Vmax within at least two drive signal output cycles, it can be ensured that the drive voltage of the drive control node Q can be controlled by the output module 120 to stably output at least two gate drive signals.

[0036] For example, the target drive voltage Vmax of the drive control node Q is 60V. When the drive voltage is between 30V and 60V, it indicates that the voltage of the drive control node Q is less than 60V during operation, and the drive control node Q is leaking current. The charge compensation module 130 compensates for the drive control node Q so that the voltage of the drive control node Q is maintained at 60V.

[0037] In some embodiments, please refer to Figure 1 As shown, the charge compensation module 130 includes: a pre-charge submodule 131, connected to the drive control node Q, configured to pre-charge to the initial compensation voltage under the action of the nith stage transmission signal output by the nith stage output module 120; and a maintenance submodule 132, connected to the pre-charge submodule 131, the external control device 200, and the drive output terminal of the output module 120, configured to maintain the drive control node Q at the target drive voltage Vmax under the action of the initial compensation voltage, the gate drive signal output by the output module 120, and the external compensation signal during at least two drive signal output cycles of the output module 120 when the drive voltage of the drive control node Q is within a preset voltage threshold range.

[0038] For example, the precharge submodule 131 is precharged to the initial compensation voltage; the maintenance submodule 132 receives an external compensation signal from the external control device 200 to control the initial compensation voltage of the precharge submodule 131 to be applied to the drive control node Q, and receives a gate drive signal to determine the duration of each gate drive signal of the output module 120, so as to maintain the drive control node Q at the target drive voltage Vmax for the duration of each gate drive signal. The external control device 200 can be a timing controller.

[0039] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the precharge submodule 131 includes: a first transistor T1, a first capacitor C1, a second transistor T2, and a third transistor T3; the control terminal of the first transistor T1 and the first terminal of the first transistor T1 are connected to the drive control node Q, the second terminal of the first transistor T1 is connected to the first terminal of the first capacitor C1, and the control terminal of the second transistor T2 is connected to the first terminal of the second transistor T2; the second terminal of the first capacitor C1 is connected to the first terminal of the third transistor T3 and the sustaining submodule 132 respectively; the second terminal of the second transistor T2 is connected to the drive control node Q; the control terminal of the third transistor T3 is connected to the stage transmission output terminal of the ni-th stage output module, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS.

[0040] Please see Figure 2 As shown, the maintenance submodule 132 includes: a fourth transistor T4; the control terminal of the fourth transistor T4 is connected to the drive output terminal of the output module 120, and the first terminal of the fourth transistor T4 is connected to the external control device 200.

[0041] Please see Figure 2 As shown, the pull-up module 110 includes: a ninth transistor T9, the control terminal of the ninth transistor T9 is connected to the stage transmission output terminal of the ni-th stage output module 120, the first terminal of the ninth transistor T9 is connected to the high-level terminal VDD, and the second terminal of the ninth transistor T9 is connected to the drive control node Q.

[0042] Please see Figure 2As shown, the output module 120 includes: a seventh transistor T7, at least two eighth transistors T8, a third capacitor C3, and at least two fourth capacitors C4; the control terminal of the seventh transistor T7, the first terminal of the third capacitor C3, the control terminal of each eighth transistor T8, and the first terminal of each fourth capacitor C4 are connected to the drive control node Q; the first terminal of the seventh transistor T7 is connected to a clock signal line, and the second terminal of the seventh transistor T7 is connected to the second terminal of the third capacitor C3; the first terminal of each eighth transistor T8 is connected to a clock signal line, and the second terminal of each eighth transistor T8 is connected to the second terminal of the corresponding fourth capacitor C4.

[0043] For example, when the pull-up module 110 receives the ni-th stage transmission signal, the pull-up module 110 is turned on. For instance, when the pull-up module 110 includes the ninth transistor T9, the ninth transistor T9 is turned on and will charge the drive control node Q. At the same time, the control terminal of the third transistor T3 receives the ni-th stage transmission signal and will be turned on. The third transistor T3 pulls down the second terminal of the first capacitor C1 to the low level VSS. While the pull-up module 110 is charging the drive control node Q, it will also charge the first terminal of the first capacitor C1 through the first transistor T1, that is, the first compensation node A is pre-charged to the initial compensation voltage. When the output module 120 receives a clock signal, such as when the first terminal of the eighth transistor T8 receives the clock signal CKm, the eighth transistor T8 is turned on. The voltage of the drive control node Q is bootstrapped to the target drive voltage Vmax through the fourth capacitor C4. Then, the voltage of the first compensation node A is boosted to the target drive voltage Vmax through the first transistor T1. The signal is then returned to the drive control node Q via the second transistor T2. Due to leakage at the drive control node Q, its voltage will drop to the initial drive voltage during subsequent drive signal output cycles. When the voltage of the drive control node Q is within a preset voltage threshold range, the external control device 200 will generate an external compensation signal. When the first terminal of the fourth transistor T4 receives the gate drive signals output by the drive output terminals G(m+1) and G(m+3) of the output module 120, the fourth transistor T4 will remain on for the next three drive signal output cycles. The voltage of the external compensation signal will be input to the second compensation node B, thereby bootslinging the voltage of the first capacitor C1, i.e., the voltage of the first compensation node A, to the sum of the initial drive voltage and the voltage of the external compensation signal, i.e., the target drive voltage Vmax. The voltage of the external compensation signal can be obtained from the difference between the actual drive voltage of the drive control node Q of the previous frame scan signal and the target drive voltage Vmax.

[0044] For example, the voltage of VDD is 30V, the target driving voltage Vmax is 60V, and the preset voltage threshold range is between 30V and 60V. When the voltage of the driving control node Q is detected to be between 30V and 60V in the previous frame scan signal, an external compensation signal is written to the first terminal of the fourth transistor T4 in the current frame scan signal. The voltage of the external compensation signal is CVGH.

[0045] In some embodiments, the clock signal line between the last output terminal of at least two drive output terminals in the output module 120 and the stage transmission output terminal is a synchronous clock signal. The stage transmission signal is output at the same time as the last gate drive signal is output, that is, CK(m+3) and CK(n) are synchronous clock signals.

[0046] Figure 3 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 As shown, the pre-charge submodule 131 includes: a first transistor T1, a second transistor T2, a first capacitor C1, and a third transistor T3; the control terminal of the first transistor T1 is connected to the first terminal of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the first capacitor C1, respectively, and the second terminal of the first transistor T1 is connected to the drive control node Q; the control terminal of the second transistor T2 is connected to the stage transmission output terminal of the ni-th stage output module 120, and the first terminal of the second transistor T2 is connected to the high-level terminal VDD; the second terminal of the first capacitor C1 and the first terminal of the third transistor T3 are connected to the sustain submodule 132; the control terminal of the third transistor T3 is connected to the stage transmission output terminal of the ni-th stage output module 120, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS.

[0047] Please see Figure 3 As shown, the sustaining submodule 132 includes: a fourth transistor T4, a second capacitor C2, a fifth transistor T5, and a sixth transistor T6; the control terminal of the fourth transistor T4 is connected to the drive output terminal of the output module 120, the first terminal of the fourth transistor T4 is connected to the high-level terminal VDD, and the second terminal of the fourth transistor T4 is connected to the precharge submodule 131 and the first terminal of the second capacitor C2; the second terminal of the second capacitor C2 is connected to the first terminal of the fifth transistor T5 and the second terminal of the sixth transistor T6; the first control terminal of the fifth transistor T5 is connected to the drive output terminal of the output module 120, the second control terminal of the fifth transistor T5 is connected to the output terminal of the discharge signal, and the second terminal of the fifth transistor T5 is connected to the low-level terminal VSS; the control terminal of the sixth transistor T6 is connected to the drive output terminal of the output module 120, and the first terminal of the sixth transistor T6 is connected to the external control device 200.

[0048] Please see Figure 3 As shown, Figure 3The embodiments include Figure 2 The pull-up module 110 and the output module 120 have the same structure and working principle, which will not be described in detail here.

[0049] For example, when the pull-up module 110 receives the ni-th stage drive signal, the pull-up module 110 is turned on. For instance, when the pull-up module 110 includes the ninth transistor T9, the ninth transistor T9 is turned on, charging the drive control node Q. At the same time, the control terminals of the second transistor T2 and the third transistor T3 will receive the ni-th stage drive signal and be turned on. The first capacitor C1 will be connected to the high-level terminal VDD, that is, the first compensation node A is pre-charged to the initial compensation voltage. When the first control terminal of the fifth transistor T5 receives the (m-1)-th stage gate drive signal, it pulls down the second terminal of the first capacitor C1, that is, the third compensation node C, to the low-level terminal VSS. When the control terminal of the fourth transistor T4 receives the m-th stage gate drive signal and is turned on, it connects the second compensation node B to the high-level terminal VDD. The first compensation node A is bootstrapping to the target drive voltage Vmax through the first capacitor C1, while charging the second capacitor C2. The second compensation node B is also charged to the initial compensation voltage. When leakage occurs at the drive control node Q, the voltage of the drive control node Q will drop to the initial drive voltage during subsequent drive signal output cycles. When the voltage of the drive control node Q is within the preset voltage threshold range, the external control device 200 will generate an external compensation signal. When the first terminal of the sixth transistor T6 receives the gate drive signals of the drive output terminals G(m+1) and G(m+3), the fourth transistor T4 will remain on for the next 3 drive signal output cycles. The voltage of the external compensation signal will be input to the second compensation node B, thereby bootstiming the voltage of the first compensation node A to the sum of the initial drive voltage and the voltage of the external compensation signal CVGH, i.e., the target drive voltage Vmax. This voltage is then transmitted to the drive control node Q through the first transistor T1, thus maintaining the voltage of the drive control node Q at the target drive voltage Vmax. The voltage of the external compensation signal CVGH can be obtained based on the difference between the actual drive voltage of the drive control node Q in the previous frame scan signal and the target drive voltage.

[0050] After the nth-stage output module 120 outputs the gate drive signal, the voltage of the drive control node Q will be pulled low. The second terminal of the fifth transistor T5 is connected to the noise reduction control node P to receive the noise reduction control signal. When the drive control node Q is pulled low, the control terminal of the fifth transistor T5 receives the noise reduction signal and turns on, pulling the third compensation node C low to the low level VSS, thereby preventing the external compensation signal from continuously charging the third compensation node C.

[0051] In some embodiments of this application, the gate driving unit 100 further includes a noise reduction module 500, which is connected to the second control terminal of the driving control node Q and the fifth transistor T5, respectively, and is configured to generate a noise reduction control signal according to the driving voltage of the driving control node Q.

[0052] Figure 4 A circuit diagram of a noise reduction module provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 4 As shown, the noise reduction module 500 includes: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14; the first terminal of the tenth transistor T10 is connected to the low-frequency control signal LC1 terminal, the second terminal of the tenth transistor T10, and the first terminal of the eleventh transistor T11, respectively; the second terminal of the tenth transistor T10 is connected to the control terminal of the eleventh transistor T11 and the first terminal of the twelfth transistor T12, respectively; the second terminal of the eleventh transistor T11, the first terminal of the thirteenth transistor T13, and the control terminal of the fourteenth transistor T14 are connected to the noise reduction control node P; the control terminal of the twelfth transistor T12 is connected to the drive control node Q and the control terminal of the thirteenth transistor T13; the second terminals of the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are connected to the low-level terminal VSS; and the first terminal of the fourteenth transistor T14 is connected to the drive control node Q.

[0053] For example, after the nth-stage output module 120 outputs a drive signal, the drive control node Q is at a low level, the tenth transistor T10 and the eleventh transistor T11 are in the on state, and the noise reduction control signal of the noise reduction control node P is a high-level signal. When the second control terminal of the fifth transistor T5 receives the noise reduction control signal, it pulls the third compensation node C down to the low-level terminal VSS. At the same time, the noise reduction signal will control the fourteenth transistor T14 to turn on, pulling the drive control node Q down to the low-level terminal VSS, thus performing noise reduction on the drive control node Q. When the drive control node Q outputs a high-level drive control voltage signal, the thirteenth transistor T13 turns on, the noise reduction control node P will output a low-level signal, and the second control terminal of the fifth transistor T5 will not turn on, thus preventing the third compensation node C from being pulled down to the low-level terminal VSS.

[0054] In some embodiments, please refer to Figure 2 and Figure 3 As shown, the gate drive unit 100 further includes a detection module 140, which is connected to the drive control node Q and the external control device 200 respectively, and is configured to detect the drive voltage of the drive control node Q and output it to the external control device 200 so that the external controller generates an external compensation signal according to the drive voltage of the drive control node Q.

[0055] For example, the detection module 140 can be a fifteenth transistor T15. The control terminal and the first terminal of the fifteenth transistor T15 are connected to the drive control node Q, and the second terminal of the fifteenth transistor T15 is connected to the external control device 200. The external control device 200 can detect the drive voltage Vsense of the drive control node Q through the fifteenth transistor T15, so that the external controller generates an external compensation signal according to the drive voltage of the drive control node Q.

[0056] In some embodiments, the gate drive unit 100 further includes a pull-down module 400 and a reset module 300. The pull-down module 400 is configured to pull down the drive control node Q to a low level VSS according to the (n+i)th stage transmission signal after the output module 120 outputs at least two gate drive signals. The reset module 300 is configured to reset the drive control node Q according to the reset signal Reset.

[0057] Figure 5 A waveform diagram of a gate driving circuit provided in an embodiment of this application is shown below. Please refer to [link / reference]. Figure 5 As shown in the figure, the voltage CVGH of the drive control node Q, the first compensation node A, and the external compensation signal changes with the clock signal. Without compensation for the drive control node Q, when leakage occurs, the voltage cannot be maintained at the target drive voltage Vmax during the transmission cycles of the four drive signals, such as during the action of signals ck9~ck12. After compensation for the drive control node Q, the voltage will remain at the target drive voltage Vmax during the action of signals ck9~ck12.

[0058] In some embodiments, a display panel includes a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes a gate driving circuit of any of the above embodiments. The output module of the gate driving circuit is connected to at least one scan line.

[0059] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0060] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0061] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, It includes N cascaded gate drive units, each gate drive unit including: The pull-up module, connected to the drive control node, is configured to precharge the drive control node according to the nith stage transmission signal output by the nith stage output module. The output module, connected to the drive control node and at least two clock signal lines corresponding to the current stage, is configured to output the stage transmission signal and at least two gate drive signals of the current stage under the action of the drive voltage and at least two clock signals on the drive control node. The charge compensation module includes: a pre-charge submodule and a sustaining submodule; The pre-charge submodule, connected to the drive control node, is configured to pre-charge to the initial compensation voltage under the action of the nith stage transmission signal output by the nith stage output module. The sustaining submodule, connected to the precharge submodule, the external control device, and the drive output terminal of the output module, is configured to: when the drive voltage of the drive control node is within a preset voltage threshold range, maintain the target drive voltage of the drive control node during at least two gate drive signal output cycles of the output module under the action of the initial compensation voltage, the gate drive signal output by the output module, and the external compensation signal. The pre-charge submodule includes: a first transistor, a first capacitor, a second transistor, and a third transistor; The control terminal of the first transistor and the first terminal of the first transistor are connected to the drive control node, and the second terminal of the first transistor is connected to the first terminal of the first capacitor, and the control terminal of the second transistor is connected to the first terminal of the second transistor. The second terminal of the first capacitor is connected to the first terminal of the third transistor and the sustaining submodule, respectively. The second terminal of the second transistor is connected to the drive control node; The control terminal of the third transistor is connected to the stage output terminal of the ni-th stage output module, and the second terminal of the third transistor is connected to the low-level terminal.

2. The gate driving circuit according to claim 1, characterized in that, The sustaining submodule includes: a fourth transistor; The control terminal of the fourth transistor is connected to the drive output terminal of the output module, and the first terminal of the fourth transistor is connected to the external control device.

3. A gate driving circuit, characterized in that, It includes N cascaded gate drive units, each gate drive unit including: The pull-up module, connected to the drive control node, is configured to precharge the drive control node according to the nith stage transmission signal output by the nith stage output module. The output module, connected to the drive control node and at least two clock signal lines corresponding to the current stage, is configured to output the stage transmission signal and at least two gate drive signals of the current stage under the action of the gate drive voltage and at least two clock signals on the drive control node. The charge compensation module includes: a pre-charge submodule and a sustaining submodule; The pre-charge submodule, connected to the drive control node, is configured to pre-charge to the initial compensation voltage under the action of the nith stage transmission signal output by the nith stage output module. The sustaining submodule, connected to the precharge submodule, the external control device, and the drive output terminal of the output module, is configured to: when the drive voltage of the drive control node is within a preset voltage threshold range, maintain the target drive voltage of the drive control node during at least two gate drive signal output cycles of the output module under the action of the initial compensation voltage, the gate drive signal output by the output module, and the external compensation signal. The pre-charge submodule includes: a first transistor, a second transistor, a first capacitor, and a third transistor; The control terminal of the first transistor is connected to the first terminal of the first transistor, the second terminal of the second transistor, and the first terminal of the first capacitor, respectively; the second terminal of the first transistor is connected to the drive control node. The control terminal of the second transistor is connected to the stage output terminal of the ni-th stage output module, and the first terminal of the second transistor is connected to the high-level terminal. The second terminal of the first capacitor and the first terminal of the third transistor are connected to the sustaining submodule; The control terminal of the third transistor is connected to the stage output terminal of the ni-th stage output module, and the second terminal of the third transistor is connected to the low-level terminal.

4. The gate driving circuit according to claim 3, characterized in that, The sustaining submodule includes: a fourth transistor, a second capacitor, a fifth transistor, and a sixth transistor; The control terminal of the fourth transistor is connected to the drive output terminal of the output module, the first terminal of the fourth transistor is connected to the high-level terminal, and the second terminal of the fourth transistor is connected to the pre-charge submodule and the first terminal of the second capacitor. The second terminal of the second capacitor is connected to the first terminal of the fifth transistor and the second terminal of the sixth transistor; The first control terminal of the fifth transistor is connected to the drive output terminal of the output module, the second control terminal of the fifth transistor is connected to the output terminal of the noise reduction control signal, and the second terminal of the fifth transistor is connected to the low-level terminal. The control terminal of the sixth transistor is connected to the drive output terminal of the output module, and the first terminal of the sixth transistor is connected to the external control device.

5. The gate driving circuit according to claim 4, characterized in that, The gate driving unit further includes: A noise reduction module, which is connected to the second control terminal of the drive control node and the fifth transistor respectively, is configured to generate the noise reduction control signal according to the drive voltage of the drive control node.

6. The gate driving circuit according to claim 1 or 3, characterized in that, The output module includes: a seventh transistor, at least two eighth transistors, a third capacitor, and at least two fourth capacitors; The control terminal of the seventh transistor, the first terminal of the third capacitor, the control terminal of each of the eighth transistors, and the first terminal of each of the fourth capacitors are connected to the drive control node. The first terminal of the seventh transistor is connected to a clock signal line, and the second terminal of the seventh transistor is connected to the second terminal of the third capacitor. The first terminal of each of the eighth transistors is connected to a clock signal line, and the second terminal of each of the eighth transistors is connected to the second terminal of the corresponding fourth capacitor.

7. The gate driving circuit according to claim 1 or 3, characterized in that, The gate driving unit further includes: The detection module, connected to both the drive control node and the external control device, is configured to detect the drive voltage of the drive control node and output it to the external control device, so that the external controller generates the external compensation signal based on the drive voltage of the drive control node.

8. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-7, wherein the output module of the gate driving circuit is connected to at least one of the scan lines.

Images