Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises: a substrate; the grid driving circuit is arranged in the peripheral area of the substrate and comprises a plurality of shifting register units arranged in the first direction, each shifting register unit comprises an input circuit, a control circuit, an output circuit and an output noise reduction circuit, the input circuit is connected with the input end, and the control circuit is connected with the output end. The control module is configured to control the level of the first node in response to an input signal input by the input end; the control circuit is connected with the first node, the second node and the third node. The output circuit is connected with the third node and the output end. The output noise reduction circuit is respectively connected with the second node and the output end; the control circuit comprises a first transistor and a first capacitor, a first electrode of the first transistor is connected with the second node and is configured to control the level of the second node, and the first transistor is located on the side, away from the first clock signal line, of the first capacitor on the substrate.

Description

[0001] Cross-reference to related applications

[0002] This application is a divisional application of patent application No. 202280000279.6, filed on February 24, 2022. Patent application No. 202280000279.6 claims priority to PCT International Application No. PCT / CN2021 / 097512, filed on May 31, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0004] In the field of display technology, pixel arrays in display panels, such as liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays, typically include multiple rows of gate lines and multiple columns of data lines intersecting the gate lines. Driving the gate lines can be achieved through integrated, bonded driver circuitry. In recent years, with the continuous improvement of amorphous silicon thin-film transistor (TFT) or oxide TFT fabrication processes, it is also possible to directly integrate the gate line driving circuit onto the TFT array substrate to form a GOA (Gate driver on Array) for driving the gate lines. For example, a GOA comprising multiple cascaded shift register units can be used to provide switching voltage signals (scan signals) to the multiple rows of gate lines in the pixel array, thereby controlling the multiple rows of gate lines to turn on sequentially. Simultaneously, data signals are provided from the data lines to the corresponding pixel units in the pixel array, forming the grayscale voltages required for each grayscale level of the displayed image in each pixel unit, thus displaying a frame of image. Summary of the Invention

[0005] At least one embodiment of this disclosure provides a display substrate, including: a substrate; and a gate driving circuit disposed in a peripheral region of the substrate. The gate driving circuit includes a plurality of shift register units arranged in a first direction. Each shift register unit includes: an input circuit, a control circuit, an output circuit, and an output noise reduction circuit. The input circuit is connected to an input terminal and configured to control the level of a first node in response to an input signal input to the input terminal. The control circuit is connected to the first node, a second node, and a third node. The output circuit is connected to the third node and the output terminal respectively and configured to provide an output signal to the output terminal. The output noise reduction circuit is connected to the second node and the output terminal respectively and configured to reduce noise at the output terminal. The control circuit includes a first transistor and a first capacitor. The first electrode of the first transistor is connected to the second node and configured to control the level of the second node. The first transistor is located on the side of the first capacitor on the substrate away from the first clock signal line.

[0006] For example, in a display substrate provided in one embodiment of this disclosure, the control circuit further includes a second transistor and a third transistor; the first electrode of the second transistor is connected to the third node, the second electrode of the second transistor is connected to the first power line to receive the first voltage, the gate of the second transistor is connected to the first node, the second transistor is configured to control the level of the third node in response to the level of the first node, and the first electrode of the third transistor is connected to the third node and configured to control the level of the third node.

[0007] For example, in a display substrate provided in one embodiment of this disclosure, the control circuit further includes: a fifth transistor, the first electrode of the fifth transistor being connected to a first power supply line to receive a first voltage, the second electrode of the fifth transistor being connected to a second node, the gate of the fifth transistor being connected to a reset signal line, and the fifth transistor being configured to reset the second node; in a first direction, the active layer of the fifth transistor is located between the active layer of the first transistor and the active layer of the third transistor.

[0008] For example, in a display substrate provided in one embodiment of this disclosure, the control circuit further includes a fourth transistor, the first electrode of the fourth transistor is connected to a first power line to receive a first voltage, and the active layer of the fourth transistor and the active layer of the second transistor are integrally disposed.

[0009] For example, in a display substrate provided in an embodiment of this disclosure, the control circuit further includes a seventh transistor, the input circuit includes an eighth transistor, the first electrode of the seventh transistor is connected to a second power line to receive a second voltage, the second electrode of the seventh transistor is connected to a fourth node, and the active layer of the seventh transistor and the active layer of the eighth transistor are arranged sequentially in a first direction and extend along the first direction.

[0010] For example, in a display substrate provided in one embodiment of this disclosure, the control circuit further includes a sixth transistor; the gate of the sixth transistor is connected to a first node, the first electrode of the sixth transistor is connected to a first clock signal line to receive a first clock signal, and the second electrode of the sixth transistor is connected to a fourth node; the active layer of the sixth transistor is located on the side of the active layer of the eighth transistor away from the first clock signal line, and the two channel regions of the sixth transistor extend along a first direction.

[0011] For example, in a display substrate provided in one embodiment of this disclosure, the control circuit further includes: a ninth transistor and a tenth transistor, the gate of the ninth transistor being connected to a second power supply line, the first electrode of the ninth transistor being connected to a first node, and the second electrode of the ninth transistor being connected to a second control node; the gate of the tenth transistor being connected to the second control node, the first electrode of the tenth transistor being connected to a third clock signal line to receive a third clock signal, and the second electrode of the tenth transistor being connected to the first electrode of a first capacitor; the second electrode of the first capacitor being connected to the second control node; the second control node being connected to the gate of the first transistor, and the gate of the first transistor being connected to the second electrode of the first transistor, wherein the active layer of the ninth transistor extends along a first direction.

[0012] For example, in a display substrate provided in one embodiment of this disclosure, the ninth transistor is arranged sequentially with the eighth transistor in a first direction.

[0013] For example, in a display substrate provided in one embodiment of this disclosure, the ninth transistor and the eighth transistor are closer to the first clock signal line than the other transistors.

[0014] At least one embodiment of this disclosure provides another display device, including: a substrate; and a gate driving circuit disposed in a peripheral region of the substrate, wherein the gate driving circuit includes a plurality of shift register units arranged in a first direction, wherein each shift register unit includes: an input circuit, a control circuit, an output circuit, and an output noise reduction circuit, the input circuit is connected to an input terminal and configured to control the level of a first node in response to an input signal input to the input terminal, the control circuit is connected to the first node, a second node, and a third node, the output circuit is connected to the third node and an output terminal respectively and configured to provide an output signal to the output terminal, and the output noise reduction circuit is connected to the second node and the output terminal respectively and configured to reduce noise at the output terminal, wherein the control circuit includes a first transistor, a ninth transistor, and an eleventh transistor. A transistor and a first capacitor; the first terminal of the first transistor is connected to a second node and configured to control the level of the second node; the first terminal of the ninth transistor is connected to the first node, and the second terminal of the ninth transistor is connected to a second control node; the gate of the eleventh transistor is connected to a second power line, the first terminal of the eleventh transistor is connected to a fourth node, and the second terminal of the eleventh transistor is connected to a third control node; the second terminal of the first capacitor is connected to the second control node; the second control node is connected to the gate of the first transistor, and the gate of the first transistor and the second terminal of the first transistor are connected; the first capacitor includes an extension near a first clock signal line, and in a first direction, the orthographic projection of the extension on the substrate is located on one side of the orthographic projection of the eleventh transistor on the substrate and the orthographic projection of the ninth transistor on the substrate.

[0015] For example, in a display substrate provided in one embodiment of this disclosure, the first transistor is located on the side of the first capacitor on the substrate away from the first clock signal line.

[0016] For example, in a display substrate provided in one embodiment of this disclosure, the control circuit further includes a tenth transistor, wherein the gate of the tenth transistor is connected to a second control node, the first terminal of the tenth transistor is connected to a third clock signal line to receive a third clock signal, the second terminal of the tenth transistor is connected to the first terminal of a first capacitor, the tenth transistor is connected to the first terminal of the first capacitor through a first via, and the orthographic projection of the first via on the substrate is located within the orthographic projection of the first capacitor on the substrate.

[0017] For example, in a display substrate provided in one embodiment of this disclosure, the active layer of the eleventh transistor extends along a first direction, and the active layers of the ninth transistor and the eleventh transistor are arranged sequentially in a second direction.

[0018] For example, in a display substrate provided in one embodiment of this disclosure, the control circuit further includes a sixth transistor and a twelfth transistor. The gate of the sixth transistor is connected to a first node, the first electrode of the sixth transistor is connected to a first clock signal line to receive a first clock signal, and the second electrode of the sixth transistor is connected to a fourth node. The gate of the twelfth transistor is connected to a third control node, the first electrode of the twelfth transistor is connected to a fourth clock signal line to receive a fourth clock signal, and the orthographic projection of the active layer of the twelfth transistor on the substrate and the orthographic projection of the active layer of the sixth transistor on the substrate are located on one side of the orthographic projection of the first capacitor on the substrate.

[0019] For example, in a display substrate provided in one embodiment of this disclosure, the active layer of the first transistor is connected to the first electrode of the first transistor through a third via, and the orthographic projection of the channel of the first transistor on the substrate does not overlap with the orthographic projection of the third via on the substrate.

[0020] For example, in a display substrate provided in an embodiment of this disclosure, the control circuit further includes a seventh transistor, and the input circuit includes an eighth transistor, wherein the first electrode of the seventh transistor and the second power line are connected to receive a second voltage, the second electrode of the seventh transistor and the fourth node are connected, and the orthographic projection of the active layer of the eighth transistor on the substrate and the orthographic projection of the active layer of the seventh transistor on the substrate are located on the first side of the orthographic projection of the first capacitor on the substrate.

[0021] For example, in a display substrate provided in an embodiment of this disclosure, the orthographic projection of the active layer of the first transistor on the substrate is located on the second side of the first capacitor on the substrate. The first side of the first capacitor on the substrate is the side of the first capacitor on the substrate that is close to the first clock signal line, and the second side of the first capacitor on the substrate is the side of the first capacitor on the substrate that is far away from the first clock signal line.

[0022] At least one embodiment of this disclosure provides a display device, including a display substrate provided in any embodiment of this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0024] Figure 1A This is a schematic diagram of the overall circuit architecture of a display panel;

[0025] Figure 1B A schematic diagram of a shift register unit provided in at least one embodiment of the present disclosure is shown;

[0026] Figure 1C A circuit diagram of a shift register unit provided in at least one embodiment of the present disclosure is shown;

[0027] Figure 2A At least one embodiment of the present disclosure is shown. Figure 1C A schematic diagram of one layout of the shift register unit in the display substrate;

[0028] Figure 2B At least one embodiment of the present disclosure is shown. Figure 2A A plan view of the active layer of the display substrate;

[0029] Figure 2C At least one embodiment of the present disclosure is shown. Figure 2A A plan view of the first conductive layer of the display substrate;

[0030] Figure 2D At least one embodiment of the present disclosure is shown. Figure 2A A plan view of the second conductive layer of the display substrate;

[0031] Figure 2E At least one embodiment of the present disclosure is shown. Figure 2A Via distribution diagram of the second insulating layer of the display substrate;

[0032] Figure 2F At least one embodiment of the present disclosure is shown. Figure 2A A plan view of the third conductive layer of the display substrate;

[0033] Figure 3A At least one embodiment of the present disclosure is shown. Figure 1C The diagram shows another layout of the shift register unit in the display substrate;

[0034] Figure 3B At least one embodiment of the present disclosure is shown. Figure 3A A plan view of the active layer of the display substrate;

[0035] Figure 3C At least one embodiment of the present disclosure is shown. Figure 3A The plane of the first conductive layer of the display substrate;

[0036] Figure 3D At least one embodiment of the present disclosure is shown. Figure 3A A plan view of the second conductive layer of the display substrate;

[0037] Figure 3E At least one embodiment of the present disclosure is shown. Figure 3A Via distribution diagram of the second insulating layer of the display substrate;

[0038] Figure 3F At least one embodiment of the present disclosure is shown. Figure 3A A plan view of the third conductive layer of the display substrate;

[0039] Figure 4A It shows Figure 1C The signal timing diagram shown is shown when the shift register unit is working;

[0040] Figure 4B This diagram illustrates the driving timing between a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal provided in at least one embodiment of this disclosure.

[0041] Figure 5A A schematic diagram of the multi-step phenomenon in the gate drive circuit is shown;

[0042] Figure 5B This diagram illustrates how the output signal of a shift register provided in at least one embodiment of the present disclosure changes in accordance with the width of the tenth transistor;

[0043] Figure 5C This diagram illustrates how the output signal of a shift register provided in at least one embodiment of the present disclosure changes in accordance with the width of a first transistor;

[0044] Figure 5D A schematic diagram illustrating how the output signal of a shift register provided in at least one embodiment of this disclosure changes in accordance with the length of a first transistor; and

[0045] Figure 6 A schematic block diagram of a display device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0048] Figure 1A This is a schematic diagram of the overall circuit architecture of a display panel. For example, as shown... Figure 1A As shown, the rectangle pointed to by reference numeral 101 represents the overall outer frame of the display panel; the display panel 101 includes a display area (i.e., a pixel array area) 102 and a peripheral area 106 located around the display area 102. The display area 102 includes an array of pixel units 103; the peripheral area 106 includes a plurality of shift register units 104, which together form a gate drive circuit (GateGOA) for providing, for example, row-by-row shifting gate scan signals to the array of pixel units 103 in the display area 102 of the display panel 101. The plurality of shift register units of the gate drive circuit are in a first direction (e.g., Figure 1A The peripheral area 106 also includes a light emission control register unit 105, and multiple cascaded light emission control register units 105 form a light emission control drive circuit array (EMGOA) for providing light emission control signals, such as line-by-line shifting, to the arrayed pixel units 103 in the display area 102 of the display panel 101.

[0049] In some embodiments, the output signal output by the output circuit of a shift register unit 104 is output to two rows of pixel units 103, and embodiments of this disclosure include, but are not limited to, this.

[0050] like Figure 1AAs shown, data lines DL1-DLN (N being an integer greater than 1) connected to the data driver chip IC vertically pass through the display area 102 to provide data signals for the arrayed pixel units 103; gate lines GL1-GLM (M being an integer greater than 1) connected to the shift register unit 104 and the light emission control register unit 105 horizontally pass through the display area 102 to provide gate scan signals and light emission control signals for the arrayed pixel units 103. For example, each pixel unit 103 may include pixel circuits and light-emitting elements with circuit structures such as 7T1C, 8T2C, or 4T1C, as described in the art. The pixel circuits operate under the control of data signals transmitted through the data lines and gate scan signals and light emission control signals transmitted through the gate lines to drive the light-emitting elements to emit light, thereby realizing operations such as display. The light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).

[0051] like Figure 1A As shown, the gate driving circuit and the light-emitting control driving circuit array have a significant impact on the size of the peripheral area of ​​the display panel. If the layout and wiring of the gate driving circuit or the light-emitting control driving circuit are unreasonable, the peripheral area of ​​the display panel will be large, making it difficult to achieve a narrow bezel.

[0052] At least one embodiment of this disclosure provides a display substrate and a display device. The display substrate includes: a substrate; and a gate driving circuit disposed in a peripheral region of the substrate. The gate driving circuit includes a plurality of shift register units arranged in a first direction. Each shift register unit includes: an input circuit, a control circuit, an output circuit, and an output noise reduction circuit. The input circuit is connected to an input terminal and configured to control the level of a first node in response to an input signal input to the input terminal. The control circuit is connected to the first node, a second node, and a third node. The output circuit is connected to the third node and the output terminal respectively and configured to provide an output signal to the output terminal. The output noise reduction circuit is connected to the second node and the output terminal respectively and configured to reduce noise at the output terminal. The control circuit includes a first transistor, a second transistor, and a third transistor. The first transistor's first terminal is connected to a second node and configured to control the voltage level of the second node. The second transistor's first terminal is connected to a third node, and its second terminal is connected to a first voltage line to receive a first voltage. The second transistor's gate is connected to the first node and configured to control the voltage level of the third node in response to the voltage level of the first node. The third transistor's first terminal is connected to the third node and configured to control the voltage level of the third node. At least two of the active layers of the first, second, and third transistors extend in a first direction and are arranged sequentially in that direction. This display substrate can increase the density of the gate drive circuit layout, thereby reducing the size of the peripheral area and facilitating the achievement of a narrow bezel.

[0053] Figure 1B A schematic diagram of a shift register unit provided in at least one embodiment of the present disclosure is shown.

[0054] like Figure 1B As shown, the shift register unit 200 includes an input circuit 201, a control circuit 202, an output circuit 203, and an output noise reduction circuit 204. (The above text is incomplete and requires further context.) Figure 1A The circuit structure of the shift register unit 104 described may be the same as that of the shift register unit 200.

[0055] The input circuit 201 is connected to the input terminal IN and is configured to control the level of the first node P1 in response to the input signal input to the input terminal IN.

[0056] The control circuit 202 is connected to the first node P1, the second node P2, and the third node P3.

[0057] The output circuit 203 is connected to the third node P3 and the output terminal OUT respectively, and the output circuit 203 is configured to provide an output signal to the output terminal OUT.

[0058] The output noise reduction circuit 204 is connected to the second node P2 and the output terminal OUT respectively, and the output noise reduction circuit 204 is configured to reduce noise at the output terminal OUT.

[0059] The control circuit includes a first transistor T5, a second transistor T8, and a third transistor T7. The first terminal of the first transistor T5 is connected to the second node P2 and configured to control the voltage level of the second node P2. The first terminal of the second transistor T8 is connected to the third node P3, and the second terminal of the second transistor T8 is connected to the first voltage line VGH to receive a first voltage. The gate of the second transistor T8 is connected to the first node P1, and the second transistor T8 is configured to control the voltage level of the third node P3 in response to the voltage level of the first node P1.

[0060] The first terminal of the third transistor T7 is connected to the third node P3 and is configured to control the level of the third node P3.

[0061] At least two of the active layers of the first transistor T5, the second transistor T8, and the third transistor T7 extend in a first direction and are arranged sequentially in the first direction.

[0062] In some embodiments of this disclosure, the active layers of the first transistor T5, the second transistor T8, and the third transistor T7 all extend in a first direction and are arranged sequentially in the first direction.

[0063] At least two of the active layers of the first transistor T5, the second transistor T8, and the third transistor T7 extend in the first direction and are arranged sequentially in the first direction, which enables multiple transistors to be arranged in a regular manner, increases the density of the gate drive circuit layout, thereby reducing the size of the peripheral area and facilitating the realization of a narrow bezel.

[0064] Figure 1C A circuit diagram of a shift register unit provided in at least one embodiment of the present disclosure is shown.

[0065] like Figure 1C As shown, the control circuit includes a first transistor T5, a second transistor T8, and a third transistor T7. The connection relationship between the first transistor T5, the second transistor T8, and the third transistor T7 is as described above and will not be repeated here.

[0066] like Figure 1C As shown, the input circuit 201 may include an eighth transistor T1, the output circuit 203 may include a thirteenth transistor T9, and the output noise reduction circuit 204 may include a fourteenth transistor T10.

[0067] The gate of the eighth transistor T1 is connected to a first clock signal line to receive a first clock signal, such as clock signal line CK', and the first clock signal is, for example, the clock signal CK' provided by clock signal line CK'. The first terminal of the eighth transistor T1 is connected to the input terminal IN, and the second terminal of the eighth transistor T1 is connected to the first node P1. It should be understood that in this disclosure, the clock signal line and the clock signal are represented by the same symbol; for example, CK' represents both the first clock signal and the first clock signal line.

[0068] The gate of the thirteenth transistor T9 is connected to the third node P3, the first terminal of the thirteenth transistor T9 is connected to the output terminal OUT, and the second terminal of the thirteenth transistor T9 is connected to the first power supply line VGH.

[0069] The gate of the fourteenth transistor T10 is connected to the second node P2, the first terminal of the fourteenth transistor T10 is connected to the output terminal OUT, and the second terminal of the fourteenth transistor T10 is connected to the second power supply line VGL.

[0070] like Figure 1C As shown, the gate of the seventh transistor T3 is connected to the second clock signal line, and clock signal line CK is an example of the second clock signal line. The first terminal of the tenth transistor T4 is connected to the third clock signal line, and clock signal line CB' is an example of the third clock signal line. The first terminal of T6 is connected to the fourth clock signal line, and clock signal line CB is an example of the fourth clock signal line.

[0071] The second clock signal line can be the same as the first clock signal line or different from it; similarly, the third clock signal line can be the same as the fourth clock signal line or different from it. (Next) Figure 2A This is an example where the first and second clock signal lines are different signal lines, and the third and fourth clock signal lines are also different signal lines. Specifically, clock signal line CK' is an example of the first clock signal line, clock signal line CK is an example of the second clock signal line, clock signal line CB' is an example of the third clock signal line, and clock signal line CB is an example of the fourth clock signal line. (The following is a continuation of the previous sentence.) Figure 3A Examples of clock signal lines where the second clock signal line is the same as the first clock signal line, and the third clock signal line and the fourth clock signal line are the same, i.e., clock signal line NCK is an example of the first clock signal line and the second clock signal line, and clock signal line NCB is an example of the third clock signal line and the fourth clock signal line.

[0072] The following is combined with Figure 2A , Figure 2B The active layer of the first transistor T5, the active layer of the second transistor T8, the active layer of the third transistor T7, and several embodiments provided in this disclosure will be described.

[0073] Figure 2A At least one embodiment of the present disclosure is shown. Figure 1C The diagram shows a layout of the shift register unit in a display substrate.

[0074] Figure 2B At least one embodiment of the present disclosure is shown. Figure 2A A plan view of the active layer of the display substrate. Figure 2C At least one embodiment of the present disclosure is shown. Figure 2A A plan view of the first conductive layer of the display substrate. Figure 2D At least one embodiment of the present disclosure is shown. Figure 2A The image shows a plan view of the second conductive layer of the display substrate. Figure 2E At least one embodiment of the present disclosure is shown. Figure 2A The via distribution diagram of the second insulating layer of the display substrate. Figure 2F At least one embodiment of the present disclosure is shown. Figure 2A A plan view of the third conductive layer of the display substrate.

[0075] like Figure 2A As shown, the display substrate includes a substrate 10 and a shift register unit 200, a first power supply line VGH, a second power supply line VGL, and multiple clock signal lines disposed on the substrate 10. For example, the multiple clock signal lines include... Figure 1CThe clock signal lines CK', CK', CB', and CB shown may also include trigger signal lines (not shown in the figure).

[0076] like Figure 2A and Figure 2B As shown, the orthographic projections of the active layer of the first transistor T5, the second transistor T8, and the third transistor T7 onto the substrate all extend in the first direction Y and are arranged sequentially in the first direction Y. This first direction Y is the direction in which the multiple shift register units are arranged sequentially on the substrate.

[0077] For example, the central axes of the active layers of the first transistor T5, the second transistor T8, and the third transistor T7 in the extension direction are located on the same straight line or approximately on the same straight line.

[0078] like Figure 1C As shown, in some embodiments of this disclosure, the control circuit 202 includes a first transistor T5, a second transistor T8, and a third transistor T7, as well as a fourth transistor T11 and a fifth transistor T12.

[0079] The first terminal of the fourth transistor T11 is connected to the first power supply line VGH to receive the first voltage VGH. The second terminal of the fourth transistor T11 is connected to the second node. The gate of the fourth transistor T11 is connected to the first control node P21. The fourth transistor T11 is configured to control the level of the second node P2 in response to the level of the first control node P21.

[0080] The first terminal of the fifth transistor T12 is connected to the first power supply line VGH to receive the first voltage VGH, the second terminal of the fifth transistor T12 is connected to the second node P2, the gate of the fifth transistor T12 is connected to the reset signal line Reset, and the fifth transistor T12 is configured to reset the second node P2.

[0081] In some embodiments of this disclosure, the active layer of the fourth transistor T11 and the active layer of the fifth transistor T12 extend in the first direction Y and are arranged along the second direction X, wherein the second direction X intersects the first direction Y.

[0082] For example, such as Figure 2A and Figure 2B As shown, the second direction X is perpendicular to the first direction Y. The active layers of the fourth transistor T11 and the fifth transistor T12 extend along the first direction Y, and the active layers of the fourth transistor T11 and the fifth transistor T12 are arranged along the second direction X.

[0083] In some embodiments of this disclosure, such as Figure 2A and Figure 2B As shown, the active layer of the fifth transistor T12 and the active layer of the second transistor T8 are integrated into one unit.

[0084] In some other embodiments of this disclosure, the active layer of the fourth transistor T11, the active layer of the fifth transistor T12, and the active layer of the second transistor T8 are integrally formed.

[0085] In some embodiments of this disclosure, such as Figure 2A and Figure 2B As shown, in the first direction Y, the active layers of the fourth transistor T11 and the fifth transistor T12 are located between the active layers of the first transistor T5 and the second transistor T8.

[0086] In some embodiments of this disclosure, the active layer of each transistor includes a conductive layer on the side of the active layer of each transistor away from the substrate 10. For example, as Figure 2A As shown, the conductive layer 404 of the fourth transistor T11 and the conductive layer 405 of the fifth transistor T12 are disposed opposite each other, for example, the conductive layer 404 of the fourth transistor T11 and the conductive layer 405 of the fifth transistor T12 are mirror-symmetrical. The overlapping portion of the conductive layer 404 of the fourth transistor T11 and the active layer of the fourth transistor T11 forms the channel of the fourth transistor T11. The overlapping portion of the conductive layer 405 of the fifth transistor T12 and the active layer of the fifth transistor T12 forms the channel of the fifth transistor T12.

[0087] like Figure 1C As shown, the control circuit 202 may further include a sixth transistor T2 and a seventh transistor T3. The gate of the sixth transistor T2 is connected to the first node P1, the first terminal of the sixth transistor T2 is connected to the clock signal line CK' to receive the clock signal CK', and the second terminal of the sixth transistor T2 is connected to the fourth node P4.

[0088] The gate of the seventh transistor T3 is connected to the clock signal line CK to receive the clock signal CK. The first terminal of the seventh transistor T3 is connected to the second power supply line VGL to receive the second voltage VGL. The second terminal of the seventh transistor T3 is connected to the fourth node P4. The active layer of the seventh transistor T3 and the active layer of the eighth transistor T1 are arranged sequentially in the first direction Y and extend along the first direction Y.

[0089] like Figure 2A and Figure 2B As shown, the active layer of the seventh transistor T3 and the active layer of the eighth transistor T1 are arranged sequentially in the first direction Y and extend along the first direction Y.

[0090] In some embodiments of this disclosure, the active layer of the sixth transistor T2 is located on the side of the active layers of the seventh transistor T3 and the eighth transistor T1 away from the clock signal line CK', and the active layer of the sixth transistor T2 extends along the first direction Y. Having the active layer of the sixth transistor T2 located on the side of the active layers of the seventh transistor T3 and the eighth transistor T1 away from the clock signal line CK' facilitates the connection of the sixth transistor T2 to the seventh transistor T3 and the eighth transistor T1 respectively, avoiding excessive wiring. For example, as... Figure 2A and Figure 2B As shown, the first electrode of the sixth transistor T2 is positioned close to the eighth transistor T1, and the second electrode of the sixth transistor T2 is positioned close to the seventh transistor T3. This reduces the wiring between the first electrode of the sixth transistor T2 and the eighth transistor T1, as well as between the second electrode of the sixth transistor T2 and the seventh transistor T3, which helps to save wiring space and improve the compactness of the display substrate.

[0091] like Figure 1C As shown, the control circuit 202 may also include a ninth transistor T13, a tenth transistor T4, and a first capacitor C4.

[0092] The gate of the ninth transistor T13 is connected to the second power supply line VGL, the first terminal of the ninth transistor T13 is connected to the first node P1, and the second terminal of the ninth transistor T13 is connected to the second control node P22.

[0093] The gate of the tenth transistor T4 is connected to the second control node P22. The first terminal of the tenth transistor T4 is connected to the clock signal line CB' to receive the clock signal CB'. The second terminal of the tenth transistor T4 is connected to the first terminal of the first capacitor C4. The second terminal of the first capacitor C4 is connected to the second control node P22. The second control node P22 is connected to the gate of the first transistor T5, and the gate and second terminal of the first transistor T5 are connected. The active layer of the ninth transistor T13 extends along the first direction Y, and is arranged sequentially with the seventh transistor T3 and the eighth transistor T1 in the first direction Y. The active layer of the tenth transistor T4 extends along the second direction X.

[0094] For example, such as Figure 2A and Figure 2B As shown, the ninth transistor T13, the seventh transistor T3, and the eighth transistor T1 are arranged sequentially along the first direction Y, and the ninth transistor T13, the seventh transistor T3, and the eighth transistor T1 are closer to multiple clock signal lines than the other transistors.

[0095] In some embodiments of this disclosure, such as Figure 2A and Figure 2BAs shown, the first capacitor C4 includes an extension 501 near the clock signal line CK'. In the first direction Y, the orthographic projection of the extension 501 onto the substrate lies between the orthographic projections of the tenth transistor T4 and the ninth transistor T13 onto the substrate. The first transistor T5 is located on the side of the first capacitor C4 on the substrate away from the clock signal line CK'. This arrangement increases the area of ​​the first capacitor C4 while improving the compactness of the display substrate layout, thereby reducing output noise.

[0096] For example, the tenth transistor T4 is connected to the first plate C41 of the first capacitor C4 through the first via 601 and the second via 602. The orthographic projections of the first via 601 and the second via 602 on the substrate 10 are located within the orthographic projection of the first capacitor on the substrate. This saves layout space on the display substrate and is more conducive to the realization of narrow bezels. For example, the height of the first via 601 and the second via 602 is perpendicular to the direction of the display substrate 10. For example, the second via 602 is closer to the substrate 10 than the first via 601, and the orthographic projection of the second via 602 on the substrate 10 does not overlap with the orthographic projection of the first via 601 on the substrate 10.

[0097] like Figure 1C As shown, the control circuit 202 also includes an eleventh transistor T14, a twelfth transistor T6, and a second capacitor C1.

[0098] The gate of the eleventh transistor T14 is connected to the second power supply line VGL. The first terminal of the eleventh transistor T14 is connected to the fourth node, and the second terminal of the eleventh transistor T14 is connected to the third control node P23. The gate of the twelfth transistor T6 is connected to the third control node P23. The first terminal of the twelfth transistor T6 is connected to the clock signal line CB to receive the clock signal CB. The second terminal of the twelfth transistor T6 is connected to the first terminal of the second capacitor C1. The second terminal of the second capacitor C1 is connected to the first control node P21.

[0099] like Figure 2A and Figure 2B As shown, the active layer of the eleventh transistor T14 extends along the first direction Y and is arranged sequentially with the active layer of the sixth transistor T2 in the first direction. The active layers of the ninth transistor and the eleventh transistor are arranged sequentially in the second direction X. The orthographic projections of the tenth transistor T4 and the eleventh transistor T14 on the substrate are located on opposite sides of the orthographic projection of the extension 501 on the substrate.

[0100] In some embodiments of this disclosure, the active layer of the eleventh transistor T14 and the active layer of the sixth transistor T2 are arranged sequentially in a first direction, including: the active layers of the eleventh transistor T14 and the sixth transistor T2 are arranged along a straight line in the first direction. For example, the active layers of the eleventh transistor T14 and the sixth transistor T2 are rectangular patterns, and the center line of the rectangular pattern of the active layer of the eleventh transistor T14 overlaps with the center line of the rectangular pattern of the active layer of the sixth transistor T2.

[0101] In some embodiments of this disclosure, the active layer of the twelfth transistor T6 extends along the second direction X, and the orthographic projection of the active layer of the twelfth transistor T6 onto the substrate and the orthographic projection of the active layer of the sixth transistor T2 onto the substrate are located on the side where the orthographic projection of the second capacitor C1 onto the substrate is close to the orthographic projection of the first capacitor C4 onto the substrate. That is, the orthographic projections of the active layer of the twelfth transistor T6 and the active layer of the sixth transistor T2 onto the substrate are located between the orthographic projections of the second capacitor C1 and the first capacitor C4 onto the substrate.

[0102] In some embodiments of this disclosure, the active layer of the first transistor T5 is connected to the first electrode of the first transistor T5 through the third via 603, and the orthographic projection of the channel of the first transistor T5 on the substrate does not overlap with the orthographic projection of the third via 603 on the substrate.

[0103] like Figure 2A As shown, the overlapping portion of the active and conductive layers of the eighth transistor forms its channel, and the overlapping portion of the active and conductive layers of the eighth transistor is its gate. The gate of the eighth transistor is connected to the clock signal line CK'. The second terminal T1-1 of the eighth transistor is connected to the input terminal, and the second terminal T1-2 of the eighth transistor is connected to the gate of the sixth transistor T2 through the fourth via 604. The overlapping portion of the active and conductive layers of the sixth transistor T2 serves as its gate, and the first terminal of the sixth transistor T2 is connected to the clock signal line CK'. Figure 2A As shown, the second terminals of the sixth transistor T2 and the seventh transistor T3 are connected together to the first terminal of the eleventh transistor T14. For example, the second terminals of the sixth transistor T2, the seventh transistor T3 (T3-2), and the first terminal of the eleventh transistor T14 are all connected to P4. The overlapping portion of the active and conductive layers of the seventh transistor T3 serves as its gate, and the gate of the seventh transistor T3 is connected to the clock signal line CK'. The first terminal of the seventh transistor T3, along with T3-1, is connected to the second power supply line VGL.

[0104] like Figure 2AAs shown, the overlapping portion of the active and conductive layers of the eleventh transistor T14 serves as the gate of the eleventh transistor T14, and the overlapping portion of the active and conductive layers of the ninth transistor T13 serves as the gate of the ninth transistor T13. The gates of the eleventh transistor T14 and the ninth transistor T13 are both connected to the second power supply line VGL. The second terminal T14-2 of the eleventh transistor T14 is connected to the second capacitor C1 via wire 701. Figure 2A As shown, the orthographic projection of wire 701 on the substrate 10 and the orthographic projection of the first capacitor C4 on the substrate partially overlap, and wire 701 and the first capacitor C4 are located at different heights in the direction perpendicular to the substrate. The second terminal T7-2 of the third transistor T7 is connected to the first plate of the second capacitor C1, and the gate of the third transistor T7 is connected to the clock signal line CB through wire 702. The first terminal T7-1 of the third transistor T7 is connected to the first terminal of the second transistor T8 through the fifth via 605. The second terminal of the second transistor T8 is connected through the sixth via 606.

[0105] like Figure 2A As shown, the first power supply line VGH and the reset signal line Reset are arranged adjacent to each other and extend along the first direction. The reset signal line Reset is located close to multiple clock signal lines. The active layers of the first transistor T5, the second transistor T8, the third transistor T7, the fourth transistor T11, the fifth transistor T12, the sixth transistor T2, the seventh transistor T3, the eighth transistor T1, the ninth transistor T13, the tenth transistor T4, the eleventh transistor T14, and the twelfth transistor T6 are located on the side of the substrate where the orthogonal projection of the reset signal line Reset is close to the side of the multiple clock signal lines on the substrate. The orthogonal projections of the active layers of the thirteenth transistor T9 and the fourteenth transistor T10 are located on the side of the substrate where the first power supply line VGH is away from the multiple clock signal lines.

[0106] like Figure 2A As shown, the orthographic projection of the second capacitor on the substrate 10 lies within the orthographic projection of the first power line VGH on the substrate 10.

[0107] In some embodiments of this disclosure, Figure 2C The first conductive layer Gate1 shown can be disposed on the first insulating layer, thereby interacting with... Figure 2BThe active layer shown is insulated. For example, the first conductive layer Gate1 may include the first plates C4a, C1a, and C2a of the first capacitor C4, the second capacitor C1, and the third capacitor C2, as well as the gates G1-G14 of transistors T1 to T14, various connection traces (e.g., connection traces L1-L3), and wires (e.g., wires M1, M2, and M3) for connection to signal lines or transition electrodes in the third conductive layer. Wires M1, M2, and M3 are all independent patterns. Figure 2C As shown, the gates G1-G14 of transistors T1 to T14 are the portions enclosed by circular or elliptical dashed lines, i.e. Figure 2B The portion of the active layer structure of each transistor shown overlaps with the electrodes or traces in the first conductive layer Gate1.

[0108] Figure 2D The second conductive layer Gate2 of the display substrate is shown. Gate2 includes second plates C4b, C1b, and C2b of a first capacitor C4, a second capacitor C1, and a third capacitor C2, as well as multiple connecting lines. For example, the multiple connecting lines include an output terminal OUT.

[0109] It should be noted that, in the embodiments of this disclosure, the output terminal OUT located in the second conductive layer Gate 2 can be used to provide an output signal to the pixel unit of the display area. In other embodiments of this disclosure, the output signal of the shift register unit's output terminal OUT can also be provided by an electrode located in another layer. That is, the output terminal OUT can also be located in a layer other than the second conductive layer Gate 2, for example, it can be located in the first conductive layer Gate 1. The embodiments of this disclosure do not limit this.

[0110] like Figure 2E As shown, Figure 2E The vias shown are those that penetrate the third insulating layer, the second insulating layer, the first insulating layer, and those that penetrate the third insulating layer and the second insulating layer.

[0111] The first insulating layer is located at Figure 2B The active layer shown and Figure 2C The first conductive layer Gate1 is shown between the active layer and the first conductive layer Gate1. A second insulating layer is located between the first conductive layer Gate1 and the second conductive layer Gate2 to insulate the first conductive layer Gate1 and the second conductive layer Gate2. A third insulating layer is located between the second conductive layer Gate2 and the third conductive layer to insulate the second conductive layer Gate2 and the third conductive layer.

[0112] Figure 2FThe third conductive layer SD of the display substrate is shown. The third conductive layer SD includes multiple signal lines (e.g., clock signal line CK', clock signal line CK, clock signal line CB', and clock signal line CB), a second power supply line VGL, a first power supply line VGH, and a reset signal line Reset. It should be noted that the third conductive layer SD also includes transition electrodes ET1-ET15 connecting the various transistors, capacitors, and signal lines.

[0113] Figure 3A At least one embodiment of the present disclosure is shown. Figure 1C The diagram shows another layout of the shift register unit in the display substrate. Figure 3B At least one embodiment of the present disclosure is shown. Figure 3A A plan view of the active layer of the display substrate. Figure 3C At least one embodiment of the present disclosure is shown. Figure 3A A plan view of the first conductive layer of the display substrate. Figure 3D At least one embodiment of the present disclosure is shown. Figure 3A The image shows a plan view of the second conductive layer of the display substrate. Figure 3E At least one embodiment of the present disclosure is shown. Figure 3A The via distribution diagram of the second insulating layer of the display substrate. Figure 3F At least one embodiment of the present disclosure is shown. Figure 3A A plan view of the third conductive layer of the display substrate.

[0114] like Figure 3B As shown, a plan view of the active layer of the display substrate and Figure 2B Similar. About Figure 3A For the active layer of the display substrate, please refer to the above text. Figure 2B The description will not be repeated here. Figure 3A The layout of the display substrate and Figure 2A The layout of the display substrate is mainly reflected in the difference between the first capacitor C4 and the second capacitor C1.

[0115] like Figure 3A As shown, the display substrate includes a substrate 20 and a shift register unit 300, a first power supply line VGH_N, a second power supply line VGL_N, and multiple clock signal lines disposed on the substrate 20. For example, the multiple clock signal lines include clock signal lines NCK and NCB, and may also include trigger signal lines (not shown in the figure). Clock signal line NCK is an example of the first and second clock signal lines, and clock signal line NCB is an example of the third and fourth clock signal lines.

[0116] like Figure 3AAs shown, the orthographic projections of the active layer of the ninth transistor T13, the eighth transistor T1, and the seventh transistor T3 on the substrate are located on the first side of the orthographic projection of the first capacitor on the substrate, and are arranged sequentially along the first direction Y. The orthographic projection of the active layer of the first transistor T5 on the substrate is located on the second side of the first capacitor C4 on the substrate. The first side of the first capacitor C4 on the substrate is the side of the first capacitor C4 on the substrate that is closer to the clock signal line NCK, and the second side of the first capacitor C4 on the substrate is the side of the first capacitor C4 on the substrate that is farther away from the clock signal line NCK. The orthographic projection of the first capacitor C4 on the substrate is located between the ninth transistor T13 and the tenth transistor T4 in the first direction Y.

[0117] like Figure 3A As shown, the active layer of the twelfth transistor T6 extends along the second direction X. In the second direction X, the orthographic projection of the active layer of the twelfth transistor T6 on the substrate and the orthographic projection of the second capacitor C1 on the substrate are located between the orthographic projections of the active layer of the sixth transistor T2 and the active layer of the third transistor T7 on the substrate. The orthographic projection of the active layer of the twelfth transistor T6 on the substrate is located on the side of the orthographic projection of the second capacitor C1 on the substrate away from the first capacitor C1. In the second direction X, the active layer of the third transistor T7 is located on the side of the twelfth transistor T6 away from the second capacitor.

[0118] In some embodiments of this disclosure, the aspect ratio of the channel of the tenth transistor T4 is greater than 1.75. For example, Figure 2A or Figure 3A The width-to-length ratio of the channel of the tenth transistor T4 is equal to 2.

[0119] In embodiments of this disclosure, the aspect ratio of the channel of the first transistor T5 is greater than 2. For example, Figure 2A or Figure 3A The width-to-length ratio of the channel of the first transistor T5 is 3.

[0120] By optimizing the width-to-length ratio of the channels of the tenth transistor T4 and the first transistor T5, the output reset capability of the GOA can be enhanced. This at least partially avoids the problem of excessively long reset time and multiple steps caused by transistor decay after a period of driving, thereby extending the lifespan of the GOA.

[0121] In some embodiments of this disclosure, Figure 3C The first conductive layer LY1 shown can be disposed on the first insulating layer, thereby interacting with... Figure 3BThe active layer shown is insulated. For example, the first conductive layer LY1 may include the first plates C4a, C1a, and C2a of the first capacitor C4, the second capacitor C1, and the third capacitor C2, as well as the gates G1-G14 of transistors T1 to T14, various connection traces (e.g., connection traces L1-L3), and wires (e.g., wires M1, M2, and M3) for connection to signal lines or transition electrodes in the third conductive layer. Wires M1, M2, and M3 are all independent patterns. Figure 3C As shown, the gates G1-G14 of transistors T1 to T14 are the portions enclosed by circular or elliptical dashed lines, i.e. Figure 3B The portion of the active layer structure of each transistor shown overlaps with the electrodes or traces in the first conductive layer Gate1.

[0122] Figure 3D The second conductive layer LY2 of the display substrate is shown. The second conductive layer LY2 includes the second plates C4b, C1b, and C2b of the first capacitor C4, the second capacitor C1, and the third capacitor C2, as well as the output terminal OUT.

[0123] It should be noted that, in the embodiments of this disclosure, the output terminal OUT located in the second conductive layer LY2 can be used to provide an output signal to the pixel unit of the display area. In other embodiments of this disclosure, the output signal of the shift register unit's output terminal OUT can also be provided by an electrode located in another layer. That is, the output terminal OUT can also be located in a layer other than the second conductive layer LY2, for example, it can be located in the first conductive layer LY1. The embodiments of this disclosure do not limit this.

[0124] like Figure 3E As shown, Figure 3E The vias shown are those that penetrate the third insulating layer, the second insulating layer, the first insulating layer, and those that penetrate the third insulating layer and the second insulating layer.

[0125] The first insulating layer is located at Figure 3B The active layer shown and Figure 3C The active layer is insulated from the first conductive layer LY1. A second insulating layer is located between the first conductive layer LY1 and the second conductive layer LY2 to insulate the first conductive layer LY1 and the second conductive layer LY2. A third insulating layer is located between the second conductive layer LY2 and the third conductive layer LY3 to insulate the second conductive layer LY2 and the third conductive layer LY3.

[0126] Figure 3FThe third conductive layer LY3 of the display substrate is shown. LY3 includes multiple signal lines (e.g., clock signal line NCK, clock signal line NCB), a second power supply line VGL_N, a first power supply line VGH_N, and a reset signal line RST. It should be noted that LY3 also includes transition electrodes ETC1-ETC5 connecting the various transistors, capacitors, and signal lines.

[0127] At least one embodiment of this disclosure also provides a method for driving a shift register unit. Figure 4A It shows Figure 1C The diagram shows the signal timing of the shift register unit during operation. In this shift register unit, the first and second clock signal lines are the same signal line; the connection point of the first and second clock signal lines will be represented by the clock signal terminal CK. The third and fourth clock signal lines are the same signal line; the connection point of the third and fourth clock signal lines will be represented by the clock signal terminal CB. For example, this driving method is applied to… Figure 3A The display substrate shown.

[0128] For example, such as Figure 1C As shown, the driving method includes a first operation phase S1 and a second operation phase S2; in the first operation phase S1, the driving method includes a first sub-phase t1, a second sub-phase t2, and a third sub-phase t3. A frame includes the first operation phase S1 (i.e., the display phase) and the second operation phase S2 (i.e., the blanking phase). The display phase is used to drive the display panel to display, and the blanking phase is the phase between the display phase of the current frame and the display phase of the next frame. Figure 4A The signal levels shown in the timing diagram are only schematic and do not represent the actual level values.

[0129] In other examples, the driving method also includes a fourth sub-stage t4, a fifth sub-stage t5, and a sixth sub-stage t6.

[0130] For example, the first sub-stage t1 is the input stage t1, the second sub-stage t2 is the output stage t2, and the third sub-stage t3 is the reset stage t3; the fourth sub-stage t4 is the first hold time period t4, the fifth sub-stage t5 is the second hold time period t5, and the sixth sub-stage t6 is the third hold time period t6. In the first operation stage S1, the reset signal line Reset provides a high level, and the fifth transistor T12 is turned off in response to the high level provided by the reset signal line.

[0131] During input phase t1, the clock signal terminal CK provides a low level, the clock signal terminal CB provides a high level, and the input terminal IN provides a high level. The eighth transistor T1 turns on in response to the low level of the clock signal, and the ninth transistor T13 turns on in response to the second voltage provided by the second power supply line VGL. The potential of the first node P1 is high, and the potential of the second control node P22 is high. The tenth transistor T4 and the first transistor T5 are both turned off in response to the high voltage of the second control node P22. The sixth transistor T2 is turned off in response to the high level of the first node P1, the seventh transistor T3 turns on in response to the low level of the clock signal, and the eleventh transistor T14 turns on in response to the second voltage provided by the second power supply line VGL. The potential of the fourth node P4 is low, the potential of the third control node P23 is low, the twelfth transistor T6 turns on in response to the low level of the third control node P23, the potential of the first control node P21 is high, the third transistor T7 turns off in response to the high level of the clock signal, the second transistor T8 turns off in response to the high level of the first node, the fourth transistor T11 turns off in response to the high level of the first control node P21, the potential of the second node P2 remains high, the potential of the third node P3 remains high, the fourteenth transistor T10 turns off in response to the high level of the second node, the thirteenth transistor T9 turns off in response to the low level of the third node P3, and the output terminal OUT outputs a low level.

[0132] During output phase t2, the clock signal terminal CK provides a high level, the clock signal terminal CB provides a low level, and the input terminal IN provides a low level. The eighth transistor T1 is off, the ninth transistor T13 is on, and the potentials of the first node P1 and the second control node P22 remain high. The tenth transistor T4 is off, the first transistor T5 is off, the sixth transistor T2 and the seventh transistor T3 are off, the potential of the fourth node P4 remains low, and the twelfth transistor T6 is on, inputting the low level provided by the second clock signal terminal CB to the first control node P21. The first control node P21 changes from high to low. According to the charge conservation principle of the second capacitor C1, the potential of the third control node P23 is further pulled low by the second capacitor C1. The third transistor T7 is on, the first transistor T8 is off, and the fourth transistor T11 is on in response to the low level of the first control node P21. The potential of the third node P3 is low, and the potential of the second node P2 is still high. Therefore, the thirteenth transistor T9 is on, the fourteenth transistor T10 is off, and the output terminal OUT outputs the high level provided by the first power line VGH.

[0133] During the reset phase t3, the clock signal terminal CK provides a low level, the clock signal terminal CB provides a high level, the input terminal IN provides a low level, the eighth transistor T1 is turned on, the potential of the first node P1 is pulled low, the ninth transistor T13 is turned on, the potential of the second control node P22 is pulled low, the first transistor T5 is turned on, and the potential of the second node P2 is pulled low; the fourteenth transistor T10 responds to the level of the second node P2 and turns on, outputting the second voltage provided by the second power line VGL to the output terminal OUT, and the output terminal OUT outputs a low level, thereby achieving noise reduction of the output terminal OUT; the sixth transistor T2 and the seventh transistor T3 are turned on, the potential of the fourth node P4 is low, the eleventh transistor T14 is turned on, the twelfth transistor T6 is turned on, the first control node P21 becomes high level provided by the clock signal terminal CB, the potential of the third control node P23 is pulled high according to the charge conservation principle of the third control capacitor, and the third transistor T7 is turned off; the second transistor T8 responds to the low level of the first node and turns on, and the potential of the third node P3 is pulled high, and the thirteenth transistor T9 is turned off.

[0134] During the first hold period t4 of the hold phase, the clock signal terminal CK provides a high level, the clock signal terminal CB provides a low level, the input terminal IN provides a low level, the eighth transistor T1 is off, the potential of the first node P1 remains low, the ninth transistor T13 is on, the tenth transistor T4 is on, the clock signal terminal CB pulls down the potential of the second control node P22 through the first capacitor C4, the first transistor T5 is on, thereby keeping the potential of the second node P2 below VGL+Vth, where Vth is the threshold voltage of the fourteenth transistor T10, making the tenth... The four transistors T10 are turned on, thus maintaining the potential of the gate drive signal output at the OUT terminal at the second voltage, that is, maintaining it at a low level, unaffected by noise interference; the seventh transistor T3 is turned off, the sixth transistor T2 is turned on, the potential of the fourth node P4 is the high level provided by the clock signal terminal CK, the eleventh transistor T14 is turned on, the potential of the third control node P23 is high, the potential of the first control node P21 is high, the third transistor T7 is turned on, the second transistor T8 is turned on, the potential of the third node P3 is high, and the thirteenth transistor T9 is turned off.

[0135] During the second hold period t5 of the hold phase, the clock signal terminal CK provides a low level, the clock signal terminal CB provides a high level, the input terminal IN provides a low level, the eighth transistor T1 is turned on, the potential of the first node P1 is low, the ninth transistor T13 is turned on, the second control node P22 is low, the tenth transistor T4 responds to the low level of the second control node P22 and turns on, the potential of the input clock signal provided by the clock signal terminal CB increases, according to the charge conservation principle of the first control capacitor C4, thereby raising the potential of the second control node P22, the first transistor T5 is turned off, and does not affect the potential of the second node P2, so that the potential of the second node P2 is maintained at a low level. The voltage is below VGL+Vth, where Vth is the threshold voltage of the fourteenth transistor T10, causing the fourteenth transistor T10 to turn on. This keeps the potential of the gate drive signal output at the output terminal OUT at the second voltage, i.e., low level, unaffected by noise interference. The seventh transistor T3 is turned on, the potential of the second node P2 is low level, the sixth transistor T2 is turned on, the eleventh transistor T14 is turned on, the potential of the third control node P23 is low level, the twelfth transistor T6 is turned on, the potential of the first control node P21 is high level, the third transistor T7 is turned off, the second transistor T8 is turned off, the potential of the third node P3 remains high level, and the thirteenth transistor T9 is turned off.

[0136] During the third hold period t6 of the hold phase, the clock signal terminal CK provides a high level, the clock signal terminal CB provides a low level, the input terminal IN provides a low level, the input transistor T1 is off, the potential of the first node P1 is maintained at a low level, the tenth transistor T4 is turned on, the clock signal terminal CB pulls down the potential of the second control node P22 through the first capacitor C4, the first transistor T5 is turned on, thereby maintaining the potential of the second node P2 below VGL+Vth, where Vth is the threshold voltage of the fourteenth transistor T10, causing the fourteenth transistor T10 to turn on, thereby maintaining the potential of the gate drive signal output by the output terminal OUT at the second voltage, i.e., a low level, unaffected by noise interference; the seventh transistor T3 is off, the sixth transistor T2 is turned on, the potential of the fourth node P4 is high, the eleventh transistor T14 is turned on, the potential of the third control node P23 is high, the twelfth transistor T6 is off, the potential of the first control node P21 is high, the third transistor T7 is turned on, the second transistor T8 is turned on, the potential of the third node P3 is high, and the thirteenth transistor T9 is off.

[0137] During the holding phase, the potential of the second node P2 can be maintained below VGL+Vth, where Vth is the threshold voltage of the fourteenth transistor T10, causing the fourteenth transistor T10 to turn on. This, in turn, keeps the potential of the gate drive signal output from the output terminal OUT at the second voltage, unaffected by noise interference.

[0138] For example, such as Figure 4A As shown, in the second operation phase S2, the driving method of the shift register unit includes at least one reset phase t7. Figure 4A Only one reset phase t7 is shown in the figure, and the embodiments of this disclosure are not limited thereto.

[0139] For example, during at least one reset phase t7, an active level (e.g., low level) of the reset signal is applied to the reset signal line Reset, and an inactive level (e.g., high level) of the clock signal is applied to the clock signal line CK. The fifth transistor T12 responds to the active level of the reset signal by turning off the fourteenth transistor.

[0140] For example, such as Figure 4A As shown, during the reset phase t7, the clock signal terminals CK and CB provide a high level, the input terminal IN provides a low level, the reset signal line Reset provides a low level, the eighth transistor T1 is cut off, the potential of the first node P1 remains low, the ninth transistor T13 is turned on, the second control node P22 is low, and the tenth transistor T4 turns on in response to the low level of the second control node P22. The potential of the input clock signal provided by the clock signal terminal CB increases, and according to the charge conservation principle of the first capacitor C4, the potential of the second control node P22 is thus pulled up. The first transistor T5 is off. Since the fifth transistor T12 is turned on in response to the low level of the reset signal, the first power line VGH is connected to the second node P2, thereby pulling up the voltage of the second node P2. The fourteenth transistor T10 is off, meaning that the fourteenth transistor T10 is off at least during the reset phase t7 of this second operation phase S2. This prevents the fourteenth transistor T10 from being continuously turned on during the second operation phase S2, thus avoiding affecting the output reset and noise reduction capabilities of the output noise reduction circuit 130. This extends the lifespan of the shift register unit and improves the display quality of the display panel. During this phase, the sixth transistor T2 is on, and the seventh transistor T3 is off, connecting the fourth node P4 to the clock signal line CK. The potential of the fourth node P4 is at a high level compared to the clock signal line CK. The eleventh transistor T14 is on, and the potential of the third control node P23 is high. The twelfth transistor T6 is off, and the potential of the first control node P21 remains high. The third transistor T7 is off, the second transistor T8 is on, and the potential of the third node P3 remains high. The thirteenth transistor T9 is off.

[0141] The signal timing analysis of the shift register unit shows that the tenth transistor T4 and the first transistor T5 have a significant impact on the reset and noise reduction of the shift register unit. Therefore, the tenth transistor T4 and the first transistor T5 can be optimized.

[0142] Figure 4BA schematic diagram illustrating the driving timing between a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal provided in at least one embodiment of this disclosure is shown. This driving timing is, for example, applied to... Figure 2A In the display substrate shown.

[0143] like Figure 4B As shown, in terms of driving timing, during data refresh, CK / CB and CK' / CB' are used as one set of clock signals, and these two sets of signals are identical. During low-frequency hold frames, CK / CB remains high, while CK' / CB' remains low or low for most of the time (e.g., around 10ms). Several (e.g., 8) CK / CB pulses are periodically inserted to ensure that the output level (Out) remains at VGL.

[0144] Figure 5A A schematic diagram of the multi-step phenomenon in the gate drive circuit is shown.

[0145] like Figure 5A As shown, after the shift register unit in the gate drive circuit has been working for a certain period of time, the voltage value of the output signal of the shift register unit exhibits multiple steps. For example... Figure 5A As shown, multiple steps include, for example, a first step, a second step, and a third step.

[0146] To address the issue of multiple steps in the GOA output, the bias voltage of the transistors within the GOA was analyzed, with a focus on the tenth transistor T4 and the first transistor T5.

[0147] For example, with the length of the tenth transistor T4 fixed, the influence of the width of the tenth transistor T4 on the output signal of the shift register is analyzed. For example, the length of the tenth transistor T4 is fixed at 4μm.

[0148] Figure 5B A schematic diagram is shown showing how the output signal of a shift register provided in at least one embodiment of the present disclosure changes in accordance with the width of the tenth transistor T4.

[0149] In the following text, the length or width of a transistor may refer to the length or width of the transistor's channel.

[0150] like Figure 5B As shown, for example, the length of the tenth transistor T4 is 4 μm. When the width of the tenth transistor T4 is 4 μm, the falling edge duration of the output signal is 13 microseconds, and there are two steps in the falling edge. As the width of the tenth transistor T4 increases, the falling edge duration decreases step by step, and the steps gradually disappear. When the width of the tenth transistor T4 is greater than or equal to 7 μm, the falling edge duration is 1.9 microseconds, and the steps have disappeared. Therefore, the width of the tenth transistor T4 can be 8 micrometers.

[0151] For example, the length of the first transistor T5 is fixed, and the influence of the width of the first transistor T5 on the output signal of the shift register is analyzed. For example, the length of the first transistor T5 is fixed at 4μm.

[0152] Figure 5C A schematic diagram is shown illustrating how the output signal of a shift register provided in at least one embodiment of the present disclosure changes in accordance with the width of a first transistor T5.

[0153] like Figure 5C As shown, for example, the length of the first transistor T5 is 4 μm. When the width of the first transistor T5 is 4 μm, the falling edge time of the output signal is 2.3 microseconds, and the shift register has a reset delay. When the width of the first transistor T5 is 8 μm, there are two steps. When the width of the tenth transistor T4 is greater than or equal to 11 μm, the falling edge time is stable at 2.4 microseconds, and the steps have disappeared. Therefore, the width of the first transistor T5 can be 12 micrometers.

[0154] For example, the width of the first transistor T5 is fixed, and the effect of the length of the first transistor T5 on the output signal of the shift register is analyzed. For example, the width of the first transistor T5 is fixed at 8μm.

[0155] Figure 5D A schematic diagram is shown illustrating how the output signal of a shift register provided in at least one embodiment of the present disclosure changes in accordance with the length of a first transistor T5.

[0156] like Figure 5D As shown, for example, the width of the first transistor T5 is 8μm. When the length of the first transistor T5 is 6μm, the falling edge time of the output signal is 2.4 microseconds, at which point the shift register experiences a reset delay. When the length of the first transistor T5 is 5.5μm, there are two steps. When the length of the tenth transistor T4 is equal to 4.5μm, the steps increase. When the length of the tenth transistor T4 is equal to 4μm, the steps disappear. Therefore, the width of the first transistor T5 can be 4μm.

[0157] In some embodiments of this disclosure, for the tenth transistor T4, the multi-step phenomenon gradually disappears as the aspect ratio of the tenth transistor T4 increases. When the aspect ratio of the channel of the tenth transistor T4 is 1.75, the multi-step phenomenon disappears. For example, if the length of the channel of the tenth transistor T4 is 4 μm, the width of the channel of the tenth transistor T4 can be set to 8 μm. For the first transistor T5, the multi-step phenomenon gradually disappears as the aspect ratio of the first transistor T5 increases. When the aspect ratio of the channel of the first transistor T5 is 2, the multi-step phenomenon disappears. For example, the width of the channel of the first transistor T5 can be 12 μm, and the length of the channel of the first transistor T5 can be 4 μm.

[0158] For example, in Figure 2A and Figure 3A In the layout of the display substrate shown, the channel width of the tenth transistor T4 is 8μm and the channel length is 4μm, the channel width of the first transistor T5 is 12μm and the channel length is 4μm.

[0159] Figure 6 A schematic block diagram of a display device provided in at least one embodiment of the present disclosure is shown.

[0160] like Figure 6 As shown, the display device 800 may include a display substrate 810. The display substrate 810 may be the display substrate in any embodiment of this disclosure.

[0161] This display device can increase the density of the gate drive circuit layout, thereby reducing the size of the peripheral area and making it easier to achieve a narrow bezel.

[0162] The following points should be noted regarding this disclosure:

[0163] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0164] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0165] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A display substrate, comprising: Substrate; as well as A gate driving circuit is disposed in the peripheral region of the substrate, wherein the gate driving circuit includes a plurality of shift register units arranged in a first direction, wherein... Each shift register unit includes: input circuitry, control circuitry, output circuitry, and output noise reduction circuitry. The input circuit is connected to the input terminal and configured to control the level of the first node in response to an input signal input to the input terminal. The control circuit is connected to the first node, the second node, and the third node. The output circuit is connected to the third node and the output terminal respectively, and is configured to provide an output signal to the output terminal. The output noise reduction circuit is connected to the second node and the output terminal respectively, and is configured to reduce noise at the output terminal. The control circuit includes a first transistor and a first capacitor. The first terminal of the first transistor is connected to the second node and configured to control the level of the second node. The first transistor is located on the side of the first capacitor on the substrate away from the first clock signal line.

2. The display substrate according to claim 1, wherein, The control circuit also includes a second transistor and a third transistor; The first terminal of the second transistor is connected to the third node, the second terminal of the second transistor is connected to the first power line to receive a first voltage, the gate of the second transistor is connected to the first node, and the second transistor is configured to control the level of the third node in response to the level of the first node. The first electrode of the third transistor is connected to the third node and configured to control the level of the third node.

3. The display substrate according to claim 2, wherein, The control circuit further includes a fifth transistor, wherein: The first terminal of the fifth transistor is connected to the first power line to receive the first voltage, the second terminal of the fifth transistor is connected to the second node, the gate of the fifth transistor is connected to the reset signal line, and the fifth transistor is configured to reset the second node; In the first direction, the active layer of the fifth transistor is located between the active layer of the first transistor and the active layer of the third transistor.

4. The display substrate according to claim 3, wherein, The control circuit further includes a fourth transistor, wherein: The first terminal of the fourth transistor is connected to the first power line to receive the first voltage, and the active layer of the fourth transistor and the active layer of the second transistor are integrally formed.

5. The display substrate according to claim 3, wherein, The control circuit further includes a seventh transistor, and the input circuit includes an eighth transistor, wherein... The first terminal and the second power line of the seventh transistor are connected to receive the second voltage, and the second terminal and the fourth node of the seventh transistor are connected. The active layers of the seventh transistor and the eighth transistor are arranged sequentially in the first direction and extend along the first direction.

6. The display substrate according to claim 5, wherein, The control circuit also includes a sixth transistor; The gate of the sixth transistor is connected to the first node, the first electrode of the sixth transistor is connected to the first clock signal line to receive the first clock signal, and the second electrode of the sixth transistor is connected to the fourth node. The active layer of the sixth transistor is located on the side of the active layer of the eighth transistor away from the first clock signal line, and the two channel regions of the sixth transistor extend along the first direction.

7. The display substrate according to claim 5 or 6, wherein, The control circuit further includes: a ninth transistor and a tenth transistor, wherein, The gate of the ninth transistor is connected to the second power line, the first electrode of the ninth transistor is connected to the first node, and the second electrode of the ninth transistor is connected to the second control node. The gate of the tenth transistor is connected to the second control node, the first terminal of the tenth transistor is connected to the third clock signal line to receive the third clock signal, and the second terminal of the tenth transistor is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the second control node; The second control node is connected to the gate of the first transistor, and the gate of the first transistor is connected to the second terminal of the first transistor. The active layer of the ninth transistor extends along the first direction.

8. The display substrate according to claim 7, wherein, The ninth transistor is arranged sequentially with the eighth transistor in the first direction.

9. The display substrate according to claim 7, wherein, The ninth and eighth transistors are located closer to the first clock signal line than the other transistors.

10. A display substrate, comprising: Substrate; as well as A gate driving circuit is disposed in the peripheral region of the substrate, wherein the gate driving circuit includes a plurality of shift register units arranged in a first direction, wherein... Each shift register unit includes: input circuitry, control circuitry, output circuitry, and output noise reduction circuitry. The input circuit is connected to the input terminal and configured to control the level of the first node in response to an input signal input to the input terminal. The control circuit is connected to the first node, the second node, and the third node. The output circuit is connected to the third node and the output terminal respectively, and is configured to provide an output signal to the output terminal. The output noise reduction circuit is connected to the second node and the output terminal respectively, and is configured to reduce noise at the output terminal. The control circuit includes a first transistor, a ninth transistor, an eleventh transistor, and a first capacitor. The first terminal of the first transistor is connected to the second node and configured to control the level of the second node; The first terminal of the ninth transistor is connected to the first node, and the second terminal of the ninth transistor is connected to the second control node; The gate of the eleventh transistor is connected to the second power line, the first terminal of the eleventh transistor is connected to the fourth node, and the second terminal of the eleventh transistor is connected to the third control node. The second terminal of the first capacitor is connected to the second control node; The second control node is connected to the gate of the first transistor, and the gate of the first transistor is connected to the second terminal of the first transistor; The first capacitor includes an extension near the first clock signal line, and in the first direction, the orthographic projection of the extension on the substrate is located on one side of the orthographic projections of the eleventh transistor on the substrate and the orthographic projections of the ninth transistor on the substrate.

11. The display substrate according to claim 10, wherein, The first transistor is located on the side of the first capacitor on the substrate away from the first clock signal line.

12. The display substrate according to claim 10 or 11, wherein, The control circuit further includes a tenth transistor, wherein... The gate of the tenth transistor is connected to the second control node, the first terminal of the tenth transistor is connected to the third clock signal line to receive the third clock signal, and the second terminal of the tenth transistor is connected to the first terminal of the first capacitor. The tenth transistor is connected to the first terminal of the first capacitor through a first via, and the orthographic projection of the first via on the substrate is located within the orthographic projection of the first capacitor on the substrate.

13. The display substrate according to claim 10, wherein, The active layer of the eleventh transistor extends along the first direction, and the active layers of the ninth transistor and the eleventh transistor are arranged sequentially in the second direction.

14. The display substrate according to claim 13, wherein, The control circuit also includes a sixth transistor and a twelfth transistor; The gate of the sixth transistor is connected to the first node, the first electrode of the sixth transistor is connected to the first clock signal line to receive the first clock signal, and the second electrode of the sixth transistor is connected to the fourth node; The gate of the twelfth transistor is connected to the third control node, and the first terminal of the twelfth transistor is connected to the fourth clock signal line to receive the fourth clock signal; Furthermore, the orthographic projection of the active layer of the twelfth transistor on the substrate and the orthographic projection of the active layer of the sixth transistor on the substrate are located on one side of the orthographic projection of the first capacitor on the substrate.

15. The display substrate according to claim 10, wherein, The active layer of the first transistor is connected to the first electrode of the first transistor through a third via, and the orthographic projection of the channel of the first transistor on the substrate does not overlap with the orthographic projection of the third via on the substrate.

16. The display substrate according to claim 10, wherein, The control circuit further includes a seventh transistor, and the input circuit includes an eighth transistor, wherein... The first terminal and the second power line of the seventh transistor are connected to receive the second voltage, and the second terminal and the fourth node of the seventh transistor are connected. Wherein, the orthographic projection of the active layer of the eighth transistor on the substrate and the orthographic projection of the active layer of the seventh transistor on the substrate are located on the first side of the orthographic projection of the first capacitor on the substrate.

17. The display substrate according to claim 16, wherein, The orthographic projection of the active layer of the first transistor on the substrate is located on the second side of the first capacitor on the substrate. The first side of the first capacitor on the substrate is the side of the first capacitor on the substrate that is closer to the first clock signal line. The second side of the first capacitor on the substrate is the side of the first capacitor on the substrate that is farther away from the first clock signal line.

18. A display device comprising a display substrate according to any one of claims 1-17.

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