Signal generation circuit and switching power supply

Abstract

The invention discloses a signal generation circuit and a switching power supply. The signal generation circuit is applied to the switching power supply. The signal generation circuit comprises an oblique wave generation module, a spread spectrum control module and a signal selection module. The ramp generation module is connected with the signal selection module, and the ramp generation module is used for generating a source current according to the input voltage and outputting a ramp signal to the signal selection module according to the source current. And the spread spectrum control module is connected with the oblique wave generation module and is used for adjusting the source current so as to control the slope of the oblique wave. The signal selection module is used for determining a clock signal according to the ramp signal and the input voltage. Therefore, the intensity of electromagnetic interference can be reduced, the stability of the clock signal is improved, and the influence of electromagnetic interference on the stability of the switching power supply is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a signal generation circuit and a switching power supply. Background Technology

[0002] A switching power supply is a power device that converts electrical energy using high-frequency switching devices. In a switching power supply, the switching transistors generate significant electromagnetic interference (EMI) during the switching process. This EMI can cause fluctuations in the clock signal and affect the operation of surrounding electronic circuits, significantly impacting circuit stability. Summary of the Invention

[0003] This application provides a signal generation circuit and a switching power supply to solve at least one of the aforementioned technical problems.

[0004] The signal generation circuit of this application embodiment is applied to a switching power supply. The signal generation circuit includes a ramp generation module, a spread spectrum control module, and a signal selection module.

[0005] The ramp generation module is connected to the signal selection module. The ramp generation module is used to generate a source current based on the input voltage and output a ramp signal to the signal selection module based on the source current.

[0006] The spread spectrum control module is connected to the ramp generation module. The spread spectrum control module is used to adjust the source current in order to control the slope of the ramp signal.

[0007] The signal selection module is used to determine the clock signal based on the ramp signal and the input voltage.

[0008] In some embodiments, the ramp wave generation module includes a first ramp wave generation module and a second ramp wave generation module;

[0009] The first ramp generation module is used to generate a first source current according to the input power supply voltage, and output a first ramp signal to the signal selection module according to the first source current;

[0010] The second ramp generation module is used to generate a second source current based on the input battery voltage, and output a second ramp signal to the signal selection module based on the second source current.

[0011] In some embodiments, the ramp generation module includes a ramp resistor, a first current mirror unit, a ramp capacitor, and a transistor. The ramp resistor, the first current mirror unit, and the ramp capacitor are connected in sequence, and the transistor is connected between the first current mirror unit and the ramp capacitor. The signal selection module is also used to output the clock signal to the ramp generation module.

[0012] The first current mirror unit is used to mirror the input current according to a preset ratio to obtain the source current, wherein the input current is the current generated by the input voltage through the ramp resistor;

[0013] The ramp capacitor is used to charge based on the source current to generate the ramp signal;

[0014] The transistor is used to switch on / off states according to the clock signal, so that the ramp signal is a sawtooth wave signal.

[0015] In some embodiments, the signal selection module is connected to the spread spectrum control module, and the signal selection module is further used to output the clock signal to the spread spectrum control module. The spread spectrum control module includes a first switching unit, a switch selection unit, a second switching unit, and a second current mirror unit.

[0016] The first switching unit is used to switch the on / off state according to the spread spectrum switching signal to control the working state of the spread spectrum control module, wherein the spread spectrum switching signal is sent to the spread spectrum control module by the main control circuit of the switching power supply;

[0017] The switch selection unit is used to determine the switch selection signal of the second switch unit based on the clock signal and the spread spectrum switch signal;

[0018] The second switching unit is used to switch the on / off state according to the switch selection signal;

[0019] The second current mirror unit is used to generate and output at least one spread spectrum current according to the on / off state of the second switching unit, so as to regulate the source current.

[0020] In some embodiments, the signal selection module includes a first signal selection module, a second signal selection module, and a third signal selection module;

[0021] The first signal selection module is used to determine the operating mode signal of the switching power supply based on the power supply voltage, the battery voltage and the charging and discharging signal, wherein the charging and discharging signal is sent to the signal selection module by the main control circuit of the switching power supply;

[0022] The second signal selection module is used to determine the clock signal based on the power supply voltage, the battery voltage, the first ramp signal, the second ramp signal, and the charge / discharge signal;

[0023] The third signal selection module is used to determine the buck ramp signal and the boost ramp signal based on the first ramp signal, the second ramp signal and the charge / discharge signal.

[0024] In some implementations, the first signal selection module includes a first comparator and a logic gate unit interconnected with each other;

[0025] The first comparator is used to compare the power supply voltage and the battery voltage;

[0026] The logic gate unit is used to output the operating mode signal of the switching power supply based on the comparison result of the first comparator and the charging / discharging signal.

[0027] In some embodiments, the second signal selection module includes a second comparator, a third switching unit, and a fourth switching unit, wherein the third switching unit and the fourth switching unit are respectively connected to the second comparator;

[0028] The third switching unit is used to connect to different input terminals according to the charging and discharging signal, and select the first ramp signal or the second ramp signal to be input to the second comparator;

[0029] The fourth switching unit is used to connect to different input terminals according to the charging and discharging signal, and select the power supply voltage or the battery voltage to input to the second comparator;

[0030] The second comparator is used to output the clock signal based on the selection result of the third and fourth switching units.

[0031] In some embodiments, the charge / discharge signal includes a first charge / discharge signal and a second charge / discharge signal. When the charge / discharge signal is the first charge / discharge signal, the third switching unit is used to select the first ramp signal, the fourth switching unit is used to select the power supply voltage, and the second comparator is used to determine the clock signal based on the relationship between the first ramp signal and the power supply voltage and output it.

[0032] When the charge / discharge signal is the second charge / discharge signal, the third switching unit is used to select the second ramp signal, the fourth switching unit is used to select the battery voltage, and the second comparator is used to determine the clock signal based on the relationship between the second ramp signal and the battery voltage and output it.

[0033] In some implementations, the third signal selection module includes a fifth switching unit and a sixth switching unit;

[0034] The fifth switching unit is used to connect to different input terminals according to the charging and discharging signal, and select the first ramp signal or the second ramp signal as the buck ramp signal output;

[0035] The sixth switching unit is used to connect to different input terminals according to the charging and discharging signal, and select the first ramp signal or the second ramp signal as the boost ramp signal output.

[0036] The switching power supply according to the embodiments of this application includes:

[0037] The signal generation circuit of any of the above embodiments;

[0038] The main control circuit is used to output the spread spectrum switching signal and the charge / discharge signal to the signal generation circuit;

[0039] A PWM control circuit, wherein the PWM control circuit is connected to the signal generation circuit;

[0040] A buck-boost circuit is provided, which is connected to the PWM control circuit.

[0041] In the signal generation circuit and switching power supply of this application embodiment, the ramp generation module generates a source current based on the input voltage and outputs a ramp signal to the signal selection module based on the source current. The spread spectrum control module adjusts the source current to control the slope of the ramp signal. The signal selection module determines the clock signal based on the ramp signal and the input voltage. This reduces the intensity of electromagnetic interference, improves the stability of the clock signal, and reduces the impact of electromagnetic interference on the stability of the switching power supply.

[0042] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort. Among them:

[0044] Figure 1 This is a schematic diagram of a switching power supply module according to certain embodiments of this application;

[0045] Figure 2This is a schematic diagram of the signal generation circuit in some embodiments of this application;

[0046] Figure 3 This is a waveform diagram of the first ramp signal in some embodiments of this application;

[0047] Figure 4 This is a schematic diagram of the spread spectrum control module according to certain embodiments of this application;

[0048] Figure 5 This is a schematic diagram of the structure of a switch selection unit according to certain embodiments of this application;

[0049] Figure 6 This is a schematic diagram of the switch selection signal over 32 clock cycles in some embodiments of this application;

[0050] Figure 7 This is a schematic diagram of the waveform changes of the first ramp signal in some embodiments of this application;

[0051] Figure 8 This is a schematic diagram of the structure of the signal selection module in some embodiments of this application;

[0052] Figure 9 This is a schematic diagram of the buck-boost circuit of some embodiments of this application.

[0053] Explanation of reference numerals in the attached figures:

[0054] The circuit includes a signal generation circuit 100, a ramp generation module 10, a first ramp generation module 11, a first current mirror unit 111, a first ramp resistor R1, a first current mirror 1111, a second current mirror 1112, a first ramp capacitor C1, a first transistor MN1, a second ramp generation module 12, a second ramp resistor R2, a third current mirror 1113, a fourth current mirror 1114, a second ramp capacitor C2, a second transistor MN2, a spread spectrum control module 20, a first switching unit 21, a second switching unit 22, a second current mirror unit 23, a switch selection unit 24, a frequency divider subunit 241, a first trigger 2411, and a second trigger 2412. Third flip-flop 2413, fourth flip-flop 2414, fifth flip-flop 2415, first AND gate 2416, second AND gate 2417, reset subunit 242, selection subunit 243, output subunit 244, signal selection module 30, first signal selection module 31, first comparator 311, logic gate unit 312, second signal selection module 32, second comparator 321, third switch unit 322, fourth switch unit 323, third signal selection module 33, fifth switch unit 331, sixth switch unit 332, main control circuit 200, PWM control circuit 300, buck-boost circuit 400, switching power supply 1000. Detailed Implementation

[0055] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0056] Please see Figure 1 and Figure 2 This application provides a signal generation circuit 100, applied to a switching power supply 1000. The signal generation circuit 100 includes a ramp generation module 10, a spread spectrum control module 20, and a signal selection module 30. The ramp generation module 10 is connected to the signal selection module 30, and is used to generate a source current based on the input voltage, and output a ramp signal to the signal selection module 30 based on the source current. The spread spectrum control module 20 is connected to the ramp generation module 10, and is used to adjust the source current to control the slope of the ramp signal. The signal selection module 30 is used to determine a clock signal based on the ramp signal and the input voltage.

[0057] In the signal generation circuit 100 of this embodiment, the ramp generation module 10 generates a source current based on the input voltage and outputs a ramp signal to the signal selection module 30 based on the source current. The spread spectrum control module 20 adjusts the source current to control the slope of the ramp signal. The signal selection module 30 determines the clock signal based on the ramp signal and the input voltage. This reduces the intensity of electromagnetic interference, improves the stability of the clock signal, and reduces the impact of electromagnetic interference on the stability of the switching power supply 1000.

[0058] Specifically, a voltage input ramp generation module 10 generates a source current based on the input voltage, and a ramp signal is generated based on the source current. The ramp generation module 10 is also connected to a spread spectrum control module 20. After the ramp generation module 10 generates the source current, the spread spectrum control module 20 can adjust the source current. The ramp signal is a signal that varies with the source current; the slope of the ramp signal is related to the magnitude of the source current. Therefore, when the source current changes, the slope of the ramp signal will change. The ramp generation module 10 is connected to a signal selection module 30 to output the changing ramp signal to the signal selection module 30.

[0059] The signal selection module 30 determines the clock signal based on the ramp signal and the output voltage. The slope of the clock signal is related to the slope of the ramp signal. Therefore, when the slope of the ramp signal changes, the frequency of the clock signal changes. By adjusting the source current through the spread spectrum control module 20, the slope of the ramp signal can be controlled, thereby controlling the frequency of the clock signal.

[0060] The switching power supply 1000 can be a DC-DC power supply. In the switching power supply 1000, the switching transistors generate a large amount of electromagnetic interference during the switching process, which affects the stability of the circuit. In this embodiment, the clock signal is frequency modulated by the spread spectrum control module 20, thereby reducing the intensity of electromagnetic interference, improving the stability of the clock signal, and reducing the impact of electromagnetic interference on the stability of the switching power supply 1000.

[0061] Please see Figure 1 and Figure 2 In some embodiments, the ramp generation module 10 includes a first ramp generation module 11 and a second ramp generation module 12. The first ramp generation module 11 is used to generate a first source current based on the input power supply voltage, and output a first ramp signal to the signal selection module 30 based on the first source current. The second ramp generation module 12 is used to generate a second source current based on the input battery voltage, and output a second ramp signal to the signal selection module 30 based on the second source current.

[0062] Specifically, the ramp generation module 10 includes a first ramp generation module 11 and a second ramp generation module 12. The power supply voltage VBUS is input to the first ramp generation module 11, which can generate a first source current Isource1 based on the power supply voltage VBUS, and generate a first ramp signal based on the first source current Isource1.

[0063] The battery voltage VBAT is input to the second ramp generation module 12. The first ramp generation module 11 can generate a second source current Isource2 based on the battery voltage VBAT, and generate a second ramp signal based on the second source current Isource2. The first ramp generation module 11 and the second ramp generation module 12 respectively output the generated first ramp signal and second ramp signal to the signal selection module 30.

[0064] In related technologies, DC-DC power conversion chips use a fixed circuit to generate a working clock signal and then modulate the clock signal at a frequency. The clock generation circuit cannot be switched according to the specific application scenario. The generated clock signal is difficult to maintain a stable frequency and phase when facing different loads, input voltage changes or external environmental interference, resulting in poor clock signal stability.

[0065] In this embodiment, when the switching power supply 1000 is in a charging state, the first ramp generation module 11 receives the power supply voltage VBUS to generate a first source current Isource1, which can then be used to determine the clock signal. When the switching power supply 1000 is in a discharging state, the second ramp generation module receives the battery voltage VBAT to generate a second source current Isource2, which can then be used to determine the clock signal. Thus, the clock generation circuit can be switched according to different application scenarios. The generated clock signal can maintain a stable frequency and phase when facing different loads, input voltage changes, or external environmental interference, resulting in good clock signal stability and further ensuring the stability of the switching power supply 1000.

[0066] Please see Figure 2 In some embodiments, the ramp generation module 10 includes a ramp resistor, a first current mirror unit 111, and a ramp capacitor connected in sequence. The first current mirror unit 111 is used to mirror the input current according to a preset ratio to obtain the source current. The input current is the current generated by the input voltage passing through the ramp resistor. The ramp capacitor is used to charge based on the source current to generate a ramp signal.

[0067] Specifically, the ramp generation module 10 includes a ramp resistor, a first current mirror unit 111, and a ramp capacitor connected in sequence. The ramp resistor includes a first ramp resistor R1 and a second ramp resistor R2, and the ramp capacitor includes a first ramp capacitor C1 and a second ramp capacitor C2.

[0068] The first ramp generation module 11 includes a first ramp resistor R1, a first current mirror unit 111, and a first ramp capacitor C1 connected in sequence. The first current mirror unit 111 includes a first current mirror 1111 and a second current mirror 1112. The first ramp resistor R1, the first current mirror 1111, the second current mirror 1112, and the first ramp capacitor C1 are connected in sequence. The first current mirror 1111 is a P-type current mirror, composed of four P-type field-effect transistors, such as... Figure 2 As shown in M1, M2, M3, and M4. The second current mirror 1112 is an N-type current mirror, composed of four N-type field-effect transistors, as shown in... Figure 2 As shown in M5, M6, M7 and M8.

[0069] In the first ramp generation module 11, the input power supply voltage VBUS passes through the first ramp resistor R1 to generate a first input current. The first current mirror unit 111 mirrors the first input current according to a preset ratio to obtain the first source current Isource1. The preset ratio can be set according to the actual situation. In one example, the mirror ratio of the first current mirror 1111 is 1:1, the mirror ratio of the second current mirror 1112 is 1:1, and the preset ratio corresponding to the first current mirror unit 111 is 1:1. After obtaining the first source current Isource1, the first ramp capacitor C1 can be charged based on the first source current Isource1 to generate the first ramp signal.

[0070] The first ramp generation module 11 also includes a third resistor R3, which is connected between the field-effect transistors M2 and M4. The third resistor R3 is used to adjust the magnitude of the current generated by the first current mirror 1111, so that I1 = VBUS / R1, where I1 is the current generated by the first current mirror 1111.

[0071] The second ramp generation module 12 includes a second ramp resistor R2, a first current mirror unit 111, and a second ramp capacitor C2 connected in sequence. The first current mirror unit 111 includes a third current mirror 1113 and a fourth current mirror 1114. The second ramp resistor R2, the third current mirror 1113, the fourth current mirror 1114, and the second ramp capacitor C2 are connected in sequence. The third current mirror 1113 is a P-type current mirror, composed of four P-type field-effect transistors, such as... Figure 2 As shown in M9, M10, M11, and M12. The fourth current mirror 1114 is an N-type current mirror, composed of four N-type field-effect transistors, as shown in... Figure 2 As shown in M13, M14, M15 and M16.

[0072] In the second ramp generation module 12, the input battery voltage VBAT passes through the second ramp resistor R2 to generate a second input current. The first current mirror unit 111 mirrors the second input current according to a preset ratio to obtain a second source current Isource2. The preset ratio can be set according to actual conditions. After obtaining the second source current Isource2, the second ramp capacitor C2 can be charged based on the second source current Isource2 to generate a second ramp signal.

[0073] The first ramp generation module 11 also includes a fourth resistor R4, which is connected between the field-effect transistors M9 and M11. The fourth resistor R4 is used to adjust the magnitude of the current generated by the third current mirror 1113, so that I2 = VBAT / R2, where I2 is the current generated by the third current mirror 1113.

[0074] Please see Figure 2In some embodiments, the ramp generation module 10 further includes a transistor connected between the first current mirror unit 111 and the ramp capacitor. The signal selection module 30 is also used to output a clock signal to the ramp generation module 10, and the transistor is used to switch on / off states according to the clock signal so that the ramp signal is a sawtooth wave signal.

[0075] Specifically, the transistor can be a P-type field-effect transistor. The first ramp generation module 11 includes a first transistor MN1. The drain of the first transistor MN1 is connected between the first current mirror unit 111 and the first ramp capacitor C1, the source is grounded, and the gate is used to receive the clock signal sent by the signal selection module 30. The clock signal controls the gate of the first transistor MN1 to switch the on and off state of the first transistor MN1, so that the first ramp signal generated based on the first ramp capacitor C1 is a sawtooth wave signal.

[0076] The second ramp generation module 12 includes a second transistor MN2. The drain of the second transistor MN2 is connected between the first current mirror unit 111 and the second ramp capacitor C2, the source is grounded, and the gate is used to receive a clock signal sent by the signal selection module 30. The clock signal controls the gate of the second transistor MN2 to switch the on / off state of the second transistor MN2, so that the second ramp signal generated based on the second ramp capacitor C2 is a sawtooth wave signal, such as... Figure 3 As shown, the sawtooth wave signal has linear characteristics and a stable waveform, making it less susceptible to external interference and exhibiting high stability. This can further improve the stability of the switching power supply 1000.

[0077] Frequency modulation based on the spread spectrum control module 20 includes four methods: sinusoidal modulation, triangular modulation, exponential modulation, and random signal modulation. Among them, sinusoidal modulation is easy to analyze and implement, but it cannot produce the optimal spectral distribution; exponential modulation can produce a flat spectrum, but it is difficult to implement in practice; random signal modulation modulates the system with an irregular signal, and its effect in suppressing electromagnetic interference is better than the other three periodic signal modulations, but it is difficult to implement; triangular modulation achieves a trade-off between the effects of circuit implementation and spectral distribution, that is, it can suppress electromagnetic interference and save circuit resources.

[0078] Therefore, the embodiment of this application employs triangular wave modulation. The ramp generation module 10 uses transistors to make the generated ramp signal sawtooth-shaped, so that the spread spectrum control module 20 can control the slope of the ramp signal to achieve triangular wave modulation of the clock signal frequency. In this way, while suppressing electromagnetic interference, the circuit structure of the switching power supply 1000 can be simplified.

[0079] Please see Figure 2 , Figure 4 and Figure 5In some embodiments, the signal selection module 30 is connected to the spread spectrum control module 20, and the signal selection module 30 is also used to output a clock signal to the spread spectrum control module 20. The spread spectrum control module 20 includes a first switching unit 21, a second switching unit 22, a second current mirror unit 23, and a switch selection unit 24. The first switching unit 21 is used to switch the on / off state according to the spread spectrum switching signal to control the working state of the spread spectrum control module 20. The switch selection unit 24 is used to determine the switch selection signal of the second switching unit 22 according to the clock signal and the spread spectrum switching signal. The second switching unit 22 is used to switch the on / off state according to the switch selection signal, and the second current mirror unit 23 generates at least one spread spectrum current according to the on / off state of the second switching unit 22 and outputs it to regulate the source current. The spread spectrum switching signal is sent to the spread spectrum control module 20 by the main control circuit 200 of the switching power supply 1000.

[0080] Specifically, the switching power supply 1000 includes a main control circuit 200, which sends a spread spectrum switching signal EN_DITHER to the spread spectrum control module 20 to control the operating state of the spread spectrum control module 20. A signal selection module 30 is connected to the spread spectrum control module 20 and, after generating a clock signal, also outputs the clock signal to the spread spectrum control module 20. There can be two spread spectrum control modules 20: one connected to the first ramp generation module 11 and the other connected to the second ramp generation module 12.

[0081] Each spread spectrum control module 20 includes a first switching unit 21, a second switching unit 22, a second current mirror unit 23, and a switch selection unit 24. When the spread spectrum control module 20 receives the spread spectrum switching signal EN_DITHER, the first switching unit 21 can switch its on / off state according to the spread spectrum switching signal EN_DITHER to control the working state of the spread spectrum control module 20. For example, when the spread spectrum switching signal EN_DITHER = 0, the first switching unit 21 is turned on, turning off the spread spectrum function of the spread spectrum control module 20; when the spread spectrum switching signal EN_DITHER = 1, the first switching unit 21 is turned off, turning on the spread spectrum function of the spread spectrum control module 20.

[0082] The second current mirror unit 23 is used to generate at least two proportional spread-frequency currents. For example... Figure 4As shown, taking the charging of the switching power supply 1000 as an example, during charging, the first ramp generation module 11 receives the power supply voltage VBUS and generates a first source current Isource1 based on the power supply voltage VBUS. The product control module adjusts the first source current Isource1 to achieve the spreading frequency function of the charging direction. The spreading frequency control module 20 also includes a third current mirror unit composed of transistors M29, M30, M35, and M36, and a fourth current mirror unit composed of transistors M31, M32, M33, and M34. The third current mirror unit mirrors the first source current Isource1 to the spreading frequency control module 20. The switch selection unit 24 receives the clock signal sent by the signal selection module 30 and the spreading frequency switch signal EN_DITHER sent by the main control circuit 200. Based on the clock signal and the spreading frequency switch signal EN_DITHER, it determines the switch selection signal CONT_<5:1> of the second switch unit 22, so that the second current mirror unit 23 can generate at least one spreading frequency current according to the on / off state of the second switch unit 22.

[0083] The second switching unit 22 includes multiple sub-switches, the number of which is the same as the maximum number of spread spectrum currents that the second current mirror unit 23 can generate. Each sub-switch controls the on / off state of the corresponding flow path that generates the spread spectrum current. The second switching unit 22 switches the on / off states of the multiple sub-switches according to the switch selection signal CONT_<5:1>, controlling at least one flow path that generates the spread spectrum current to control the output spread spectrum current and adjust the source current. The at least one spread spectrum current output by the second switching unit 22 is the total spread spectrum current.

[0084] This application's implementation takes the second current mirror unit 23 generating a maximum of 5 spread spectrum currents as an example. The number of sub-switches is 5, namely Sn1, Sn2, Sn3, Sn4, and Sn5. When all 5 sub-switches are turned on, the current mirrored by the third current mirror unit is mirrored through transistors M19 and M20 to obtain the first spread spectrum current In1, through transistors M21 and M22 to obtain the second spread spectrum current In2, through transistors M23 and M24 to obtain the third spread spectrum current In3, through transistors M25 and M26 to obtain the fourth spread spectrum current In4, and through transistors M27 and M28 to obtain the fifth spread spectrum current In5. The ratio of the 5 spread spectrum currents is In1:In2:In3:In4:In5 = 1:2:4:8:16.

[0085] The five spread spectrum currents are added together to form the total spread spectrum current. The total spread spectrum current is mirrored to the first ramp generation module 11 through the fourth current mirror unit and added to the first source current Isource1, causing the first source current Isource1 to change, thereby changing the slope of the first ramp signal, and thus changing the frequency of the clock signal.

[0086] The following is combined Figure 5 The switch selection unit 24 is described in detail below. It includes a frequency divider subunit 241, a reset subunit 242, a selection subunit 243, and an output subunit 244. The frequency divider subunit 241 includes multiple flip-flops and two AND gates. The flip-flops can be D flip-flops. The number of flip-flops is related to the spread spectrum period achievable by the spread spectrum control module 20. In one example, the number of flip-flops is 5, and the achievable spread spectrum period is 2... 5 = 32 cycles.

[0087] Five flip-flops are connected sequentially. The CLK input of the first flip-flop 2411 is connected to the first AND gate 2416, and the CLR inputs of multiple flip-flops are all connected to the second AND gate 2417. The D input of each flip-flop is connected to itself... The output is connected to each flip-flop. The output is also connected to the CLK input of the next flip-flop. The input signals of the first AND gate 2416 are the clock signal and the spread spectrum switching signal EN_DITHER, and the input signals of the second AND gate 2417 are the pulse reset signal RESET_i and the spread spectrum switching signal EN_DITHER.

[0088] The output signal at the Q output terminal of the first flip-flop 2411 is A1. The output signal at the output terminal is B1, and the output signal at the Q output terminal of the second flip-flop 2412 is A2. The output signal at the output terminal is B2, and the output signal at the Q output terminal of the third flip-flop 2413 is A3. The output signal at the output terminal is B3, and the output signal at the Q output terminal of the fourth flip-flop 2414 is A4. The output signal at the output terminal is B4, and the output signal at the Q output terminal of the fifth flip-flop 2415 is A5. The output signal at the output terminal is B5.

[0089] The reset subunit 242 includes multiple logic gates. In one example, the reset subunit 242 includes four NOT gates, three NOR gates, and one AND gate. The inputs of the reset subunit 242 are the output signal A5 of the Q output terminal of the fifth flip-flop 2415 and the spread spectrum switching signal EN_DITHER. The output signals are the reset signal RESET and the pulse reset signal RESET_i.

[0090] The selection subunit 243 includes a flip-flop and three NOT gates. The input signals of the selection subunit 243 are the reset signal RESET and the spread spectrum switch signal EN_DITHER, and the output signals are the first selection signal HALF_A and the second selection signal HALF_B.

[0091] The output subunit 244 includes a first output subunit 244, a second output subunit 244, a third output subunit 244, a fourth output subunit 244, and a fifth output subunit 244. Each output subunit 244 includes two AND gates, one NOR gate, and one NOT gate.

[0092] In the first output subunit 244, the input signals of the first AND gate are the output signal A1 of the first flip-flop 2411 and the first selection signal HALF_A. The input signals of the second AND gate are the output signal B1 of the first flip-flop 2411 and the second selection signal HALF_B. After the input signals of the two AND gates pass through the NOR gate and the NOT gate, the first switch selection signal CONT_<5:1>CONT_1 is output by the NOT gate.

[0093] In the second output subunit 244, the input signals of the first AND gate are the output signal A2 of the second flip-flop 2412 and the first selection signal HALF_A. The input signals of the second AND gate are the output signal B2 of the second flip-flop 2412 and the second selection signal HALF_B. After the input signals of the two AND gates pass through the NOR gate and the NOT gate, the NOT gate outputs the second switch selection signal CONT_<5:1>CONT_2.

[0094] In the third output subunit 244, the input signals of the first AND gate are the output signal A3 of the third flip-flop 2413 and the first selection signal HALF_A. The input signals of the second AND gate are the output signal B3 of the third flip-flop 2413 and the second selection signal HALF_B. After the input signals of the two AND gates pass through the NOR gate and the NOT gate, the NOT gate outputs the third switch selection signal CONT_<5:1>CONT_3.

[0095] In the fourth output subunit 244, the input signals of the first AND gate are the output signal A4 of the fourth flip-flop 2414 and the first selection signal HALF_A. The input signals of the second AND gate are the output signal B4 of the fourth flip-flop 2414 and the second selection signal HALF_B. After the input signals of the two AND gates pass through the NOR gate and the NOT gate, the fourth switch selection signal CONT_<5:1>CONT_4 is output by the NOT gate.

[0096] In the fifth output subunit 244, the input signals of the first AND gate are the output signal A5 of the fifth flip-flop 2415 and the first selection signal HALF_A. The input signals of the second AND gate are the output signal B5 of the fifth flip-flop 2415 and the second selection signal HALF_B. After the input signals of the two AND gates pass through the NOR gate and the NOT gate, the fifth switch selection signal CONT_<5:1>CONT_5 is output by the NOT gate.

[0097] Timing begins when the spread spectrum switch signal EN_DITHER changes from 0 to 1. Multiple flip-flops in the frequency divider subunit 241 are used to generate the clock signal for frequency division timing. When the output signal A5 of the fifth flip-flop 2415 generates a rising or falling edge, the reset subunit 242 generates a pulse signal RESET_i to reset the multiple flip-flops in the frequency divider subunit 241. Simultaneously, the falling edge of the reset signal RESET from the reset subunit 242 generates the first selection signal HALF_A and the second selection signal HALF_B through the flip-flops in the selection subunit 243.

[0098] like Figure 6 As shown, when the second selection signal HALF_B is high and the first selection signal HALF_A is low, the output sub-unit 244 selects signals A5, A4, A3, A2, and A1, and the output sub-unit 244 generates binary incrementing signals from 00000(0) to 11111(15) to control the five sub-switches of the second switching unit 22.

[0099] When the second selection signal HALF_B is low and the first selection signal HALF_A is high, the output subunit 244 selects signals B5, B4, B3, B2, and B1. That is, the output subunit 244 generates a binary decreasing signal from 11111 (15) to 00000 (0) to control the five sub-switches of the second switching unit 22. For example, when the switch selection signal CONT_<5:1> output by the output subunit 244 is 10101, sub-switches Sn1, Sn3, and Sn5 are turned on, and sub-switches Sn2 and Sn3 are turned off.

[0100] When output subunit 244 selects signals B5, B4, B3, B2, and B1, it outputs a switch selection signal CONT_<5:1> once per spread spectrum cycle, causing the second switch unit 22 to switch its on / off state once, outputting a total spread spectrum current consisting of at least one spread spectrum current. The total spread spectrum current output by the second switch unit 22 gradually increases. This total spread spectrum current is mirrored to the path of the first current source through the fourth current mirror unit, added to the first current source, and thus adjusts the first current source. The gradual increase in the first current source causes the slope and frequency of the first ramp signal to increase, such as... Figure 7As shown, the frequency change of the first ramp signal is Fsw1→Fsw2→Fsw3→…→Fswn.

[0101] When output subunit 244 selects signals A5, A4, A3, A2, and A1, the total spread spectrum current output through the second switching unit 22 gradually decreases. This total spread spectrum current is mirrored back to the path of the first current source through the fourth current mirror unit, and added to the first current source to obtain a new first current source, thus regulating the first current source. The gradual decrease in the first current source causes the slope and frequency of the first ramp signal to decrease, such as... Figure 7 As shown, the frequency change of the first ramp signal is Fswn→…→Fsw3→Fsw2→Fsw1.

[0102] It should be noted that when the switching power supply 1000 is in a discharging state, Figure 4 The first ramp generation module 11 is switched to the second ramp generation module 12. The second current source is adjusted by the spread spectrum total current output by the second switching unit 22, so that the spread spectrum function of the discharge direction can be realized. This will not be elaborated here.

[0103] Please see Figure 8 In some embodiments, the signal selection module 30 includes a first signal selection module 31, a second signal selection module 32, and a third signal selection module 33. The first signal selection module 31 determines the operating mode signal of the switching power supply 1000 based on the power supply voltage, battery voltage, and charge / discharge signals. The second signal selection module 32 determines a clock signal based on the power supply voltage, battery voltage, a first ramp signal, a second ramp signal, and the charge / discharge signals. The third signal selection module 33 determines a buck ramp signal and a boost ramp signal based on the first ramp signal, the second ramp signal, and the charge / discharge signals. The charge / discharge signals are sent to the signal selection module 30 by the main control circuit 200 of the switching power supply 1000.

[0104] Specifically, the switching power supply 1000 includes a main control circuit 200, which is used to send a charge / discharge signal CHG_EN to the signal selection module 30. The first signal selection module 31, the second signal selection module 32, and the third signal selection module 33 respectively receive the charge / discharge signal CHG_EN to determine the operating mode signal, clock signal, buck ramp signal, and boost ramp signal of the switching power supply 1000.

[0105] The input signals of the first signal selection module 31 are the power supply voltage VBUS divider, the battery voltage VBAT divider, and the charge / discharge signal CHG_EN. Based on the power supply voltage VBUS divider, the battery voltage VBAT divider, and the charge / discharge signal CHG_EN, the first signal selection module 31 can output the operating mode signal of the switching power supply 1000. The power supply voltage VBUS divider can be 1 / 2, 1 / 4, or any other arbitrary ratio of the power supply voltage VBUS. Similarly, the battery voltage VBAT divider can be 1 / 2, 1 / 4, or any other arbitrary ratio of the battery voltage VBAT.

[0106] The input signals of the second signal selection module 32 are the power supply voltage VBUS divider, the battery voltage VBAT divider, the first ramp signal, the second ramp signal, and the charge / discharge signal CHG_EN. Based on the power supply voltage VBUS divider, the battery voltage VBAT divider, the first ramp signal, the second ramp signal, and the charge / discharge signal CHG_EN, the second signal selection module 32 can determine the clock signal.

[0107] The input signals of the third signal selection module 33 are the first ramp signal, the second ramp signal, and the charge / discharge signal CHG_EN. Based on the first ramp signal, the second ramp signal, and the charge / discharge signal CHG_EN, the third signal selection module 33 can determine the buck ramp signal and the boost ramp signal.

[0108] Please see Figure 8 In some embodiments, the first signal selection module 31 includes a first comparator 311 and a logic gate unit 312 interconnected. The first comparator 311 is used to compare the power supply voltage and the battery voltage. The logic gate unit 312 is used to output an operating mode signal of the switching power supply 1000 based on the comparison result of the first comparator 311 and the charge / discharge signal.

[0109] Specifically, the first signal selection module 31 includes a first comparator 311 and a logic gate unit 312. The logic gate unit 312 includes an AND gate, a NOR gate, and an OR gate. The input signals of the first comparator 311 are a voltage divider of the power supply voltage VBUS and a voltage divider of the battery voltage VBAT. The output terminal of the first comparator 311 is connected to one input terminal of the AND gate and the NOR gate. The input signals of the other input terminals of the AND gate and the NOR gate are both the charge / discharge signal CHG_EN. The output terminals of the AND gate and the NOR gate are respectively connected to the two input terminals of the OR gate. The output terminal of the OR gate is used to output the operating mode signal of the switching power supply 1000.

[0110] When the charging / discharging signal CHG_EN = 1, it indicates that the switching power supply 1000 is in a charging state. When the power supply voltage VBUS is greater than the battery voltage VBAT, the output switching power supply 1000's operating mode signal is buck mode, represented by 1; when the power supply voltage VBUS is less than the battery voltage VBAT, the output switching power supply 1000's operating mode signal is boost mode, represented by 0.

[0111] When the charge / discharge signal CHG_EN = 0, it indicates that the switching power supply 1000 is in a discharging state. When the power supply voltage VBUS is greater than the battery voltage VBAT, the output operating mode signal of the switching power supply 1000 is in boost mode, represented by 0; when the power supply voltage VBUS is less than the battery voltage VBAT, the output operating mode signal of the switching power supply 1000 is in buck mode, represented by 1. The operating mode signal is used to control the buck-boost circuit 400 of the switching power supply 1000, which will be described in detail later.

[0112] Please see Figure 8 In some embodiments, the second signal selection module 32 includes a second comparator 321, a third switching unit 322, and a fourth switching unit 323, which are respectively connected to the second comparator 321. The third switching unit 322 connects to different input terminals according to the charge / discharge signal, selecting either a first ramp signal or a second ramp signal to be input to the second comparator 321. The fourth switching unit 323 connects to different input terminals according to the charge / discharge signal, selecting either a power supply voltage or a battery voltage to be input to the second comparator 321. The second comparator 321 outputs a clock signal based on the selection result of the third switching unit 322 and the fourth switching unit 323.

[0113] Specifically, the second signal selection module 32 includes a second comparator 321, a third switching unit 322, and a fourth switching unit 323. The third switching unit 322 and the fourth switching unit 323 can be single-pole double-throw switches. The two input terminals of the third switching unit 322 are respectively connected to the first ramp signal and the second ramp signal, and the two input terminals of the fourth switching unit 323 are respectively connected to the power supply voltage VBUS divider and the battery voltage VBAT divider.

[0114] Please see Figure 8In some embodiments, the charge / discharge signal includes a first charge / discharge signal and a second charge / discharge signal. When the charge / discharge signal is the first charge / discharge signal, the third switching unit 322 is used to select the first ramp signal, the fourth switching unit 323 is used to select the power supply voltage, and the second comparator 321 is used to determine and output a clock signal based on the relationship between the first ramp signal and the power supply voltage. When the charge / discharge signal is the second charge / discharge signal, the third switching unit 322 is used to select the second ramp signal, the fourth switching unit 323 is used to select the battery voltage, and the second comparator 321 is used to determine and output a clock signal based on the relationship between the second ramp signal and the battery voltage.

[0115] When the charge / discharge signal CHG_EN = 1, which is the first charge / discharge signal, it indicates that the switching power supply 1000 is in a charging state. The third switching unit 322 is connected to the input terminal corresponding to the first ramp signal, and the fourth switching unit 323 is connected to the input terminal corresponding to the power supply voltage VBUS divider. The second comparator 321 compares the first ramp signal and the power supply voltage to determine and output the clock signal based on the relationship between the first ramp signal and the power supply voltage.

[0116] It is understandable that during charging, the battery voltage VBAT may be low (0V), while the power supply voltage VBUS needs to be higher than a certain voltage to work properly. In this case, connecting the input terminal corresponding to the voltage divider of the power supply voltage VBUS to generate a clock signal can ensure the stability of the generated clock signal.

[0117] When the charge / discharge signal CHG_EN = 0, which is the second charge / discharge signal, it indicates that the switching power supply 1000 is in a discharging state. The third switching unit 322 is connected to the input terminal corresponding to the second ramp signal, and the fourth switching unit 323 is connected to the input terminal corresponding to the battery voltage VBAT voltage divider. The second comparator 321 compares the second ramp signal and the battery voltage to determine and output the clock signal based on the relationship between the second ramp signal and the battery voltage.

[0118] It is understandable that during discharge, the power supply voltage VBUS may experience a short circuit with a voltage of 0V, while the battery voltage VBAT needs to be higher than a certain voltage to operate normally. In this case, selecting the input terminal corresponding to the voltage divider of the battery voltage VBAT to generate a clock signal ensures the stability of the generated clock signal. Thus, when the switching power supply 1000 is in charging or discharging state, the signal selection module 30 can select different ramp signals and input voltages to generate a clock signal, ensuring the stability of the generated clock signal.

[0119] The third switch unit 322 and the fourth switch unit 323 are respectively connected to the second comparator 321 to input the selected signal as the input signal to the second comparator 321. The second comparator 321 outputs a clock signal according to the selection result of the third switch unit 322 and the fourth switch unit 323.

[0120] Please see Figure 8 In some embodiments, the third signal selection module 33 includes a fifth switching unit 331 and a sixth switching unit 332. The fifth switching unit 331 is used to connect different input terminals according to the charging and discharging signal and select a first ramp signal or a second ramp signal as a buck ramp signal output. The sixth switching unit 332 is used to connect different input terminals according to the charging and discharging signal and select a first ramp signal or a second ramp signal as a boost ramp signal output.

[0121] Specifically, the third signal selection module 33 includes a fifth switch unit 331 and a sixth switch unit 332, both of which are single-pole double-throw switches. The two input terminals of the fifth switch unit 331 and the sixth switch unit 332 are respectively connected to the first ramp signal and the second ramp signal.

[0122] When the charge / discharge signal CHG_EN = 1, it indicates that the switching power supply 1000 is in a charging state. The fifth switch unit 331 is connected to the input terminal corresponding to the first ramp signal, and the sixth switch unit 332 is connected to the input terminal corresponding to the second ramp signal. When the charge / discharge signal CHG_EN = 0, it indicates that the switching power supply 1000 is in a discharging state. The fifth switch unit 331 is connected to the input terminal corresponding to the second ramp signal, and the sixth switch unit 332 is connected to the input terminal corresponding to the first ramp signal.

[0123] Please see Figure 1 and Figure 9 This application also provides a switching power supply 1000. The switching power supply 1000 includes a signal generation circuit 100, a main control circuit 200, a PWM control circuit 300, and a buck-boost circuit 400, as described in any of the above embodiments. The main control circuit 200 outputs a spread spectrum switching signal and a charge / discharge signal to the signal generation circuit 100. The PWM control circuit 300 is connected to the signal generation circuit 100. The buck-boost circuit 400 is connected to the PWM control circuit 300.

[0124] Specifically, the main control circuit 200 can be a microcontroller unit (MCU) or a central processing unit (CPU). The main control circuit 200 is used to output the spread spectrum switching signal EN_DITHER to the spread spectrum control module 20 to control the operating state of the spread spectrum control module 20. The main control circuit 200 is also used to output the charge / discharge signal CHG_EN to the signal selection module 30, so that the signal selection module 30 selects different ramp signals and input voltages to generate clock signals when the switching power supply 1000 is in a charging or discharging state.

[0125] The PWM control circuit 300 is connected to the signal generation circuit 100 and receives the boost ramp signal and buck ramp signal output from the signal selection circuit. It determines the boost PWM signal based on the boost ramp signal and the buck PWM signal based on the buck ramp signal, and outputs both the boost and buck PWM signals to the buck-boost circuit 400. The buck-boost circuit 400 is connected to the PWM control circuit 300 to receive the boost and buck PWM signals. Furthermore, the buck-boost circuit 400 also receives the operating mode signal output from the signal selection module 30 to perform buck-boost operations based on the boost PWM signal, the buck PWM signal, and the operating mode signal.

[0126] For example, when the switching power supply 1000 is in a charging state (charge / discharge signal CHG_EN = 1), if the operating mode signal is 1, which is the buck operating mode, the buck-boost circuit 400 performs bucking based on the buck PWM signal through transistors M37 and M38; if the operating mode signal is 0, which is the boost operating mode, the buck-boost circuit 400 performs boosting based on the boost PWM signal through transistors M39 and M40.

[0127] In the signal generation circuit 100 and switching power supply 1000 of this application embodiment, the ramp generation module 10 generates a source current based on the input voltage and outputs a ramp signal to the signal selection module 30 based on the source current. The spread spectrum control module 20 adjusts the source current to control the slope of the ramp signal. The signal selection module 30 determines the clock signal based on the ramp signal and the input voltage. This reduces the intensity of electromagnetic interference, improves the stability of the clock signal, and reduces the impact of electromagnetic interference on the stability of the switching power supply 1000.

[0128] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0129] The foregoing disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0130] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," and "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0131] Although embodiments of this application have been shown and described above, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A signal generation circuit, characterized in that, Applied to switching power supplies, the signal generation circuit includes a ramp generation module, a spread spectrum control module, and a signal selection module; The ramp generation module is connected to the signal selection module. The ramp generation module is used to generate a source current based on the input voltage and output a ramp signal to the signal selection module based on the source current. The spread spectrum control module is connected to the ramp generation module. The spread spectrum control module is used to adjust the source current in order to control the slope of the ramp signal. The signal selection module is used to determine the clock signal based on the ramp signal and the input voltage.

2. The signal generation circuit according to claim 1, characterized in that, The ramp wave generation module includes a first ramp wave generation module and a second ramp wave generation module; The first ramp generation module is used to generate a first source current according to the input power supply voltage, and output a first ramp signal to the signal selection module according to the first source current; The second ramp generation module is used to generate a second source current based on the input battery voltage, and output a second ramp signal to the signal selection module based on the second source current.

3. The signal generation circuit according to claim 1, characterized in that, The ramp generation module includes a ramp resistor, a first current mirror unit, a ramp capacitor, and a transistor. The ramp resistor, the first current mirror unit, and the ramp capacitor are connected in sequence. The transistor is connected between the first current mirror unit and the ramp capacitor. The signal selection module is also used to output the clock signal to the ramp generation module. The first current mirror unit is used to mirror the input current according to a preset ratio to obtain the source current, wherein the input current is the current generated by the input voltage through the ramp resistor; The ramp capacitor is used to charge based on the source current to generate the ramp signal; The transistor is used to switch on / off states according to the clock signal so that the ramp signal is a sawtooth wave signal.

4. The signal generation circuit according to claim 1, characterized in that, The signal selection module is connected to the spread spectrum control module. The signal selection module is also used to output the clock signal to the spread spectrum control module. The spread spectrum control module includes a first switching unit, a switch selection unit, a second switching unit, and a second current mirror unit. The first switching unit is used to switch the on / off state according to the spread spectrum switching signal to control the working state of the spread spectrum control module, wherein the spread spectrum switching signal is sent to the spread spectrum control module by the main control circuit of the switching power supply; The switch selection unit is used to determine the switch selection signal of the second switch unit based on the clock signal and the spread spectrum switch signal; The second switching unit is used to switch the on / off state according to the switch selection signal; The second current mirror unit is used to generate and output at least one spread spectrum current according to the on / off state of the second switching unit, so as to regulate the source current.

5. The signal generation circuit according to claim 2, characterized in that, The signal selection module includes a first signal selection module, a second signal selection module, and a third signal selection module; The first signal selection module is used to determine the operating mode signal of the switching power supply based on the power supply voltage, the battery voltage and the charging and discharging signal, wherein the charging and discharging signal is sent to the signal selection module by the main control circuit of the switching power supply; The second signal selection module is used to determine the clock signal based on the power supply voltage, the battery voltage, the first ramp signal, the second ramp signal, and the charge / discharge signal; The third signal selection module is used to determine the buck ramp signal and the boost ramp signal based on the first ramp signal, the second ramp signal and the charge / discharge signal.

6. The signal generation circuit according to claim 5, characterized in that, The first signal selection module includes a first comparator and logic gate units that are interconnected. The first comparator is used to compare the power supply voltage and the battery voltage; The logic gate unit is used to output the operating mode signal of the switching power supply based on the comparison result of the first comparator and the charging / discharging signal.

7. The signal generation circuit according to claim 5, characterized in that, The second signal selection module includes a second comparator, a third switching unit, and a fourth switching unit, wherein the third switching unit and the fourth switching unit are respectively connected to the second comparator; The third switching unit is used to connect to different input terminals according to the charging and discharging signal, and select the first ramp signal or the second ramp signal to be input to the second comparator; The fourth switching unit is used to connect to different input terminals according to the charging and discharging signal, and select the power supply voltage or the battery voltage to input to the second comparator; The second comparator is used to output the clock signal based on the selection result of the third and fourth switching units.

8. The signal generation circuit according to claim 7, characterized in that, The charging and discharging signal includes a first charging and discharging signal and a second charging and discharging signal. When the charging and discharging signal is the first charging and discharging signal, the third switching unit is used to select the first ramp signal, the fourth switching unit is used to select the power supply voltage, and the second comparator is used to determine the clock signal based on the relationship between the first ramp signal and the power supply voltage and output it. When the charge / discharge signal is the second charge / discharge signal, the third switching unit is used to select the second ramp signal, the fourth switching unit is used to select the battery voltage, and the second comparator is used to determine the clock signal based on the relationship between the second ramp signal and the battery voltage and output it.

9. The signal generation circuit according to claim 5, characterized in that, The third signal selection module includes a fifth switching unit and a sixth switching unit; The fifth switching unit is used to connect to different input terminals according to the charging and discharging signal, and select the first ramp signal or the second ramp signal as the buck ramp signal output; The sixth switching unit is used to connect to different input terminals according to the charging and discharging signal, and select the first ramp signal or the second ramp signal as the boost ramp signal output.

10. A switching power supply, characterized in that, include: The signal generation circuit according to any one of claims 1-9; The main control circuit is used to output the spread spectrum switching signal and the charge / discharge signal to the signal generation circuit; A PWM control circuit, wherein the PWM control circuit is connected to the signal generation circuit; A buck-boost circuit is provided, which is connected to the PWM control circuit.

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