Communication module

Abstract

Provided is a communication module capable of reducing the circuit scale. A communication module (10) is provided with: an amplification control device (101) that is connected to a master device (201) and that receives, from the master device, a master signal that includes a command signal, an address signal that specifies the address of at least one register included in an antenna switch (102) and a band selection switch (103), and a write data signal to be recorded in a register corresponding to the address; the amplification control device (101) interprets the command signal; and an antenna switch (102) and a band selection switch (103) connected to the amplification control device (101) through a first signal line for transmitting a clock signal and a second signal line for transmitting a data signal.

Description

Technical Field

[0001] This invention relates to a communication module. Background Technology

[0002] In semiconductor devices, data is sometimes transmitted and received between multiple devices via serial communication. In serial communication, there is a master device and slave devices connected to the master device. Data is written to the slave device, for example, by the master device sending signals to it. The slave device sometimes interprets the commands contained in the signals from the master device and performs the corresponding processing.

[0003] The circuitry used for command interpretation is large. Therefore, when each sub-device has its own command interpretation circuitry, the overall circuitry size also increases. Furthermore, Patent Document 1 describes a structure where, instead of having command interpretation circuitry in each sub-device, an interface circuit for interpreting signals from the master device is provided separately from the sub-devices.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: U.S. Patent Application Publication No. 2017 / 0192918 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] In the structure described in Patent Document 1, the interface circuit connects to the sub-device, which is the destination for data transmission, via a clock bus, a data bus, and an enable bus for transmitting enable signals. In the structure described in Patent Document 1, the interface circuit selects any one of multiple sub-devices via the enable bus and transmits data. In this case, since an enable bus is set up for each sub-device, a wiring area is required for setting up the enable bus, increasing the overall circuit size.

[0009] The present invention was made in view of the following circumstances, and its object is to provide a communication module that can reduce the size of the circuit.

[0010] Solution for solving the problem

[0011] One aspect of the present invention relates to a communication module comprising: a first sub-device connected to a master device; and at least one second sub-device not connected to the master device, but connected to the first sub-device via a first signal line for transmitting a clock signal and a second signal line for transmitting a data signal.

[0012] The first sub-device receives a master signal from the master device, wherein the master signal includes a command signal, an address signal specifying the address of at least one register of at least one second sub-device, and a write data signal to be recorded into the register corresponding to the address. The address signal follows the command signal, and the write data signal follows the address signal. The first sub-device interprets the command signal. Based on the interpretation result of the command signal, if information based on the data signal needs to be written to any one of the at least one second sub-device, the first sub-device generates a write indication signal after receiving the command signal and during the period of receiving the master signal. Based on the interpretation result of the command signal, the first sub-device generates a data signal based on the address signal and the write data signal to be provided to each of the at least one second sub-device after receiving the command signal and during the period of receiving the master signal. After receiving the command signal and during the period of receiving the master signal, the first sub-device provides the write indication signal to each of the at least one second sub-device via a first signal line or a second signal line, and provides the data signal to each of the at least one second sub-device via a second signal line.

[0013] Each of the at least one second sub-device determines whether the register corresponding to the address represented by the address signal is included in the at least one second sub-device. If the register is included in the at least one second sub-device and a write instruction signal is provided from the first sub-device, each of the at least one second sub-device writes a write data signal to the register.

[0014] Another aspect of the present invention relates to a communication module comprising: a first sub-device connected to a master device, receiving a master signal from the master device, wherein the master signal includes a command signal and a device ID signal representing a device ID for identifying the device, the first sub-device interpreting the command signal and being assigned first device ID information; a second sub-device connected to the first sub-device via a first signal line for transmitting a clock signal and a second signal line for transmitting a data signal, the second sub-device being assigned second device ID information; and a third sub-device connected to the first sub-device via a third signal line for transmitting a clock signal and a fourth signal line for transmitting a data signal, the third sub-device being assigned third device ID information.

[0015] In the communication module, the first sub-device determines whether the device ID signal contained in the main signal is consistent with the first device ID information possessed by the first sub-device, and determines whether the device ID signal contained in the main signal is consistent with the second device ID information or the third device ID information possessed by the first sub-device. If the device ID signal contained in the main signal is consistent with the second device ID information possessed by the first sub-device, the first sub-device generates a first sub-device control signal indicating data writing or reading for the second sub-device based on the interpretation result of the command signal, and provides the first sub-device control signal to the second sub-device. If the device ID signal contained in the main signal is consistent with the third device ID information possessed by the first sub-device, the first sub-device generates a second sub-device control signal indicating data writing or reading for the third sub-device based on the interpretation result of the command signal, and provides the second sub-device control signal to the third sub-device.

[0016] The effects of the invention

[0017] According to the present invention, a communication module capable of reducing circuit size can be provided. Attached Figure Description

[0018] Figure 1 This is a diagram illustrating an example of a circuit including the communication module according to the first embodiment.

[0019] Figure 2 This is a diagram showing the structure of the amplification control device in the communication module according to the first embodiment.

[0020] Figure 3 This is a diagram illustrating the structure of a sub-device in the communication module according to the first embodiment.

[0021] Figure 4 This is an example of the main signal and data signal involved in the first embodiment.

[0022] Figure 5 This is another example of the main signal and data signal involved in the first embodiment.

[0023] Figure 6 This is another example of the main signal and data signal involved in the first embodiment.

[0024] Figure 7 This is another example of the main signal and data signal involved in the first embodiment.

[0025] Figure 8 This is another example of the main signal and data signal involved in the first embodiment.

[0026] Figure 9This is a diagram illustrating another example of the structure of a sub-device in the communication module according to the first embodiment.

[0027] Figure 10 This is a diagram illustrating another example of the structure of a sub-device in the communication module according to the first embodiment.

[0028] Figure 11 This is a diagram illustrating an example of a circuit including the communication module according to the first embodiment.

[0029] Figure 12 This is a diagram showing the structure of the amplification control device in the communication module according to the second embodiment.

[0030] Figure 13 This is a diagram illustrating the structure of a sub-device in the communication module according to the second embodiment.

[0031] Figure 14 This is an example of the signals transmitted and received by the amplification control device and the signals transmitted and received by the sub-devices involved in the second embodiment.

[0032] Figure 15 This is another example of the signals transmitted and received by the amplification control device and the signals transmitted and received by the sub-devices involved in the second embodiment.

[0033] Figure 16 This is a diagram illustrating an example of a circuit including the communication module according to the third embodiment.

[0034] Figure 17 This is a flowchart illustrating the processing of the amplification control device in the communication module according to the third embodiment. Detailed Implementation

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, the same reference numerals will be used to label the same elements, and repeated descriptions will be omitted as much as possible.

[0036] (First Implementation)

[0037] The first embodiment will be described. Figure 1 An example of a circuit including the communication module 10, the main device 201, and the analog circuits 301a, 301b, and 301c involved in this embodiment is shown.

[0038] The communication module 10 is a sub-device whose data communication is controlled by the master device 201.

[0039] The communication module 10 includes an amplification control device 101, an antenna switch 102, and a frequency band selection switch 103. The amplification control device 101 controls the power amplifier circuit; the antenna switch 102 selects the signal amplified by the power amplifier circuit and transmitted / received via the antenna; and the frequency band selection switch 103 selects the wavelength of the signal transmitted / received via the antenna. Furthermore, in... Figure 1 In the example shown, antenna switch 102 and frequency band selection switch 103 are illustrated as sub-devices, but the number of sub-devices can be more than two, or it can be just one. Furthermore, the functions of the devices connected to the main device 201 are not limited to power amplification, antenna control, and wavelength selection; devices with other functions can also be connected.

[0040] The amplification control device 101 is connected to the antenna switch 102 and the frequency band selection switch 103 via two wires: clock signal line 104 and data signal line 105. The amplification control device 101 communicates bidirectionally with the antenna switch 102 and the frequency band selection switch 103 via a two-wire bus. Alternatively, the communication module 10 can follow the I2C protocol or other communication methods.

[0041] In order to rewrite the information stored in the registers of antenna switch 102 or frequency band selection switch 103, master device 201 sends a master signal to amplification control device 101. The master signal includes a command signal, an address signal specifying the address of at least one register of antenna switch 102 or frequency band selection switch 103, and a write data signal to be recorded to the register corresponding to the address. Additionally, master device 201 sends a clock signal to amplification control device 101.

[0042] Command signals indicate the type of write operation based on the master signal. Command signals may indicate, for example, the form of writing to at least one register within a device, writing to a single register within a device, or writing to a register within a device while masking the bit values. Address signals identify the registers of antenna switch 102 or band selection switch 103. Address signals may be, for example, 5-bit or 8-bit data. Write data signals are the data to be written to the register, and their bit length may be, for example, 8 bits.

[0043] Analog circuit 301a is connected to the register of amplification control device 101 and performs control functions such as bias control for power amplification based on information stored in the register of amplification control device 101. Analog circuit 301b is connected to the register of antenna switch 102 and performs switching functions such as switching between transmitting and receiving signals through the antenna based on information stored in the register of antenna switch 102. Analog circuit 301c is connected to the register of frequency band selection switch 103 and selects the wavelength of the signal transmitted and received through the antenna based on information stored in the register of frequency band selection switch 103. In this embodiment, amplification control device 101, antenna switch 102, and frequency band selection switch 103 are described as different devices, but they all share the common function of controlling analog circuits based on information written in their respective registers.

[0044] Reference Figure 2 The various parts of the amplification control device 101 will be described. The amplification control device 101 includes a data receiving unit 1011, a command start determination unit 1012, a data signal generation unit 1013, a clock enable signal generation unit 1014, a data transmission unit 1015, and a register unit 1016.

[0045] The data receiving unit 1011 receives a clock signal and a master signal from the master device 201, and performs processing to interpret the master signal. For example, based on information represented by a command signal contained in the master signal, the data receiving unit 1011 generates command identification information for identifying commands. The data receiving unit 1011 sends the command identification information to the data signal generation unit 1013 and the clock enable signal generation unit 1014, which will be described later.

[0046] The data receiving unit 1011 sends the address signal and write data signal contained in the main signal to the data signal generation unit 1013. Furthermore, the data receiving unit 1011 generates bit position information indicating the location of additional command identification information and sends this bit position information to the data signal generation unit 1013 and the clock enable signal generation unit 1014. In addition to including the location of the additional command identification information, the bit position information may also include information indicating the start and end positions of signals in the data signal, such as the start position of the address signal and the start position of the write data signal.

[0047] The command start determination unit 1012 determines, based on the clock signal and the master signal, whether the transmission of command signals from the master device 201 to the amplification control device 101 has begun. When the provision of command signals begins, the command start determination unit 1012 sends a command detection signal to the data transmission unit 1015. Additionally, the command start determination unit 1012 sends a reset signal to the data signal generation unit 1013.

[0048] The data signal generation unit 1013 generates a data signal to be transmitted to the antenna switch 102 and the frequency band selection switch 103 based on the command identification information, bit position information, address signal, and write data signal received from the data receiving unit 1011. The data signal generation unit 1013 then transmits the data signal to the data transmission unit 1015.

[0049] The clock enable signal generation unit 1014 generates a clock enable signal based on command identification information and bit position information. The clock enable signal is used to start transmitting data signals from the amplification control device 101 to the antenna switch 102. When the timing indicator determined based on the bit position information indicates the time point at which data signals are to be transmitted to the antenna switch 102 and the frequency band selection switch 103, the clock enable signal generation unit 1014 generates the clock enable signal and sends it to the data transmission unit 1015.

[0050] When the data transmission unit 1015 receives an input command detection signal and a clock enable signal from the clock enable signal generation unit 1014, it transmits the data signal from the data signal generation unit 1013 along with the clock signal provided to the data transmission unit 1015 to the antenna switch 102 and the frequency band selection switch 103. The data transmission unit 1015 transmits the clock signal via the clock signal line 104 and the data signal via the data signal line 105.

[0051] Register section 1016 is a rewritable storage area including registers. Furthermore, register section 1016 controls writing to each register based on signals from data receiving section 1011. Register section 1016 is connected to analog circuit 301a.

[0052] The communication module 10 performs parallel operations of signal communication within itself, in parallel with the reception of the main signal. The amplification control device 101, in parallel with the processing of interpreting the main signal from the main device 201, generates and transmits data signals to be sent to the antenna switch 102 and the frequency band selection switch 103. This significantly improves processing efficiency compared to situations where, for example, the signal to be written to the antenna switch 102 and the frequency band selection switch 103 is stored in the amplification control device 101, and then, based on reading the information stored in the amplification control device 101, it is sent to the antenna switch 102 and the frequency band selection switch 103.

[0053] Reference Figure 3 Antenna switch 102 is described below. Other sub-devices, including frequency band selection switch 103, also have the same structure as those used in data communication devices. Antenna switch 102 includes a data receiving unit 1021, a command start determination unit 1022, and a register unit 1023.

[0054] The data receiving unit 1021 receives the address signal and write data signal contained in the data signal.

[0055] The command start determination unit 1022 determines, based on the clock signal and the main signal, whether data signal transmission from the amplification control device 101 to the antenna switch 102 has started. When data signal transmission begins, the command start determination unit 1012 sends a reset signal to the data receiving unit 1021.

[0056] Register section 1023 is a rewritable storage area including registers 10231, 10232, 10233, and 10234. Furthermore, register section 1023 controls writes to each register based on signals from data receiving section 1021. Registers 10231, 10232, 10233, and 10234 each have their own unique address. Additionally, each register of band selection switch 103 has an address that is different from or the same as the addresses of registers 10231, 10232, 10233, and 10234. Register section 1023 is connected to analog circuit 301b.

[0057] Reference Figure 4 This illustrates an example of data signal generation by the amplification control device 101 and data signal interpretation by the antenna switch 102. Figure 4 The diagram illustrates an example of a main signal and a data signal in the case of writing data to a register based on a command to write to at least one register within a device.

[0058] The main signals include, in sequence, the start signal, the command signal, the address signal, the write data signal, and the end signal.

[0059] When the data receiving unit 1011 receives a master signal from the master device 201, the data receiving unit 1011 interprets the command signal. If the command signal indicates a command to write to at least one register within a device, the data signal generation unit 1013 generates information that appends identification information B1 to the beginning of the address signal based on the address signal, command identification information, and bit position information. Identification information B1 is a 1-bit information; a bit value of 0 indicates a 5-bit address length, and a bit value of 1 indicates an 8-bit address length. The data transmitting unit 1015 records the identification information B1 at the position corresponding to the beginning clock of the address signal in the master signal and transmits a data signal that offsets the address signal by one clock cycle.

[0060] Next, the data signal generation unit 1013 generates a follow-up address signal and appends identification information B2 to the beginning of the write data signal. Identification information B2 is a 1-bit information; a bit value of 0 indicates that the following signal is a write data signal, and a bit value of 1 indicates that the following signal is a mask signal specifying bits that will not be written. The data transmission unit 1015 uses the data signal corresponding to the beginning clock of the write data signal in the main signal as identification information B2 and transmits a data signal that offsets the write data signal by one clock cycle. Additionally, the data signal also includes parity bits at the beginning and end, and the bits sandwiched between the parity bits record information indicating the actual write data.

[0061] exist Figure 4 In the example, the main signal includes only one write data signal. Therefore, the data signal generation unit 1013 generates the data signal by appending identification information B3 to the parity bit at the end of the write data signal. Identification information B3 is a 1-bit information; a bit value of 0 indicates that no write to the register based on the write data is performed. In this case, the register in the antenna switch 102 is not modified. Alternatively, when the bit value of identification information B3 is 1, identification information B3 indicates that a write to the register based on the write data is performed. The signal with a bit value of 1 in identification information B3 functions as a write indication signal indicating that information based on the data signal is written to the register of the sub-device. Furthermore, for example, if there is an error in the write data signal, the data signal generation unit 1013 sets the bit value of identification information B3 to 0, so that no write is performed.

[0062] In the communication module 10, each sub-device, such as the antenna switch 102 and the frequency band selection switch 103, receives the address signal contained in the data signal received by the data receiving unit 1021.

[0063] The data receiving unit sends a write enable signal to the register unit 1023 based on the identification information contained in the data signal. The register unit 1023 determines whether the interpreted address information corresponds to the address of register 10231, etc., contained in its own register unit 1023. If the address information corresponds to the address of its own register and the value of the identification information B3 bit is 1, the register unit 1023 writes the write data signal to the corresponding register. If the value of the identification information B3 bit is 1 but the interpreted address information does not correspond to the address of its own register, the register unit 1023 does not perform writing to register 10231, etc., based on the write data signal.

[0064] Therefore, even when a common data signal is sent from the amplification control device 101 to multiple sub-devices, the feasibility of the final write can be determined based on the consistency of the address that is different for each register, thus allowing the registers of each sub-device to be rewritten appropriately.

[0065] Reference Figure 5 This illustrates another example of data signal generation by the amplification control device 101 and data signal interpretation by the antenna switch 102. Figure 5 The diagram illustrates an example of a main signal and a data signal for writing data to two registers, based on a command indicating a write to at least one register within a device.

[0066] The main signals sequentially include the start signal, command signal, address signal, first write data signal, second write data signal, and end signal.

[0067] The data transmission unit 1015 generates information that sets the identification information B1 to 0 and appends it to the beginning of the address signal. The data signal generation unit 1013 generates information that appends the identification information B2 to the beginning of the first written data signal after the address signal.

[0068] Next, the data signal generation unit 1013 generates information that appends the identification information B4 to the end of the first write data signal, following the first write data signal. Figure 5 In the example, identification information B4 is a 1-bit information. Similar to identification information B3, a bit value of 0 indicates that no write to the register is performed based on the data to be written, and a bit value of 1 indicates that a write to the register is performed based on the data to be written.

[0069] Finally, the data signal generation unit 1013 generates a data signal by appending identification information B3 to the end of the written data signal.

[0070] exist Figure 5 In the example, antenna switch 102 interprets the address information contained in the data signal received by data receiving unit 1021. Here, we will take the case where the address signal represents the antenna switch 102's own register as an example.

[0071] The data receiving unit 1021 receives the first write data signal following the identification information B2 and the address signal. Since the bit value of the identification information B2 is 0, it is determined that the subsequent data is write data. Next, the data receiving unit 1021 receives the second write data signal following the identification information B4 and the first data signal. Since the bit value of the identification information B4 is 1, the data receiving unit 1021 determines that the first write data can be written to the register. Finally, the data receiving unit 1021 receives the identification information B3 following the second write data signal. Since the bit value of the identification information B3 is 1, the data receiving unit 1021 determines that the second write data can be written to the register. At this time, the data receiving unit 1021 increments the address represented by the initial address information and writes the second write data to the next register.

[0072] Reference Figure 6 This illustrates another example of data signal generation by the amplification control device 101 and data signal interpretation by the antenna switch 102. Figure 4 The diagram illustrates an example of a main signal and a data signal for writing data to a register, based on a command that indicates writing bit values ​​to a register within a device while masking them.

[0073] The main signals sequentially include the start signal, command signal, address signal, mask signal, write data signal, and end signal.

[0074] The data transmission unit 1015 generates information that sets the identification information B1 to 0 and appends it to the beginning of the address signal. The data signal generation unit 1013 generates information that appends the identification information B2 to the beginning of the first write data signal after the address signal. At this time, since the command indicates that the bit value is being masked and written to a register in a certain device, the data signal generation unit 1013 sets the bit of the identification information B2 to 1.

[0075] Next, the data signal generation unit 1013 generates information that appends identification information B5 to the beginning of the data signal following the mask signal. Figure 5 In the example, identification information B5 is 1 bit information. Similar to identification information B2, a bit value of 0 indicates that the following signal is a data write signal, and a bit value of 1 indicates that the following signal is a mask signal representing the bits of the mask object.

[0076] Finally, the data signal generation unit 1013 generates a data signal by appending identification information B3 to the end of the written data signal.

[0077] exist Figure 6In the example, antenna switch 102 interprets the address information contained in the data signal received by data receiving unit 1021.

[0078] The data receiving unit 1021 receives the mask signal following the identification information B2 and the address signal. Since the bit value of the identification information B2 is 1, it is determined that the subsequent signal is the mask signal.

[0079] Next, the data receiving unit 1021 receives the write data signal following the identification information B5 and the mask signal. Since the bit value of the identification information B5 is 0, the data receiving unit 1021 determines that the signal content is write data. Finally, the data receiving unit 1021 receives the identification information B3 following the write data signal. The bit value of the identification information B3 is 1, therefore the data receiving unit 1021 determines that the write data can be written to the register. At this time, the data receiving unit 1021 does not rewrite the bits represented by the mask signal, but writes the write data to the register corresponding to the address represented by the initial address information.

[0080] exist Figures 4 to 6 In the example, by appending identification information B3 to the end of the data signal by the data signal generation unit 1013, the antenna switch 102 can determine whether writing is permissible. However, the data signal generation unit 1013 does not necessarily need to include the identification information B3 in the data signal. For example, the communication module 10 can also determine whether writing is permissible based on the presence or absence of a clock signal sent by the data transmission unit 1015.

[0081] exist Figure 7 An example of this situation is shown in the image. Figure 7 In the example, the main signal and Figure 4 The situation is the same. However, the data signal generation unit 1013 does not append identification information B3 to the end of the data signal, which is the same as... Figure 4 The examples are different.

[0082] exist Figure 7 In the example, when the amplification control device 101 allows data to be written to the antenna switch 102, the data transmission unit 1015 sends a clock signal C1 to the antenna switch 102 after the write data signal. When the data receiving unit 1011 receives the clock signal C1 after the write data signal, the antenna switch 102 determines that data can be written. The clock signal C1 functions as a write indication signal indicating that information based on the data signal will be written to the register of the sub-device.

[0083] exist Figure 8The example shown illustrates a situation where data writing is not performed due to reasons such as an error in the write data signal. In this case, the data transmitting unit 1015 does not send a clock signal to the antenna switch 102 after the write data signal. Since the data receiving unit 1011 does not receive a clock signal after the write data signal, the antenna switch 102 does not perform data writing.

[0084] Thus, in the communication module 10, based on the clock signal or identification information from the amplification control device 101, it is determined whether data can be written to the antenna switch 102, etc.

[0085] exist Figure 9 Another example of the structure of the antenna switch 102 is shown. The antenna switch 102A with the data receiving unit 1021A can also be made without performing the processing corresponding to the command indicating that bit values ​​are masked while being written.

[0086] exist Figure 10 The diagram shows another example of the structure of the antenna switch 102. The antenna switch 102B, which has a data receiving unit 1021B, may also include a write clock generation unit 1024, which converts a write enable signal based on a data signal to... Figure 7 , Figure 8 As explained, the writing to register section 1023 is controlled based on the clock signal.

[0087] (Second Implementation)

[0088] The second embodiment will be described. In the embodiments following the second embodiment, the differences from the first embodiment will be mainly described, while the similarities with the first embodiment will be omitted. Figure 11 An example of a circuit including the communication module 110, the main device 201, and the analog circuits 301a, 301b, and 301c according to the second embodiment is shown. The communication module 110 according to the second embodiment differs from the communication module 10 according to the first embodiment in that it can be read from the register of the amplification control device 1101A, or the antenna switch 1102 or the frequency band selection switch 1103.

[0089] The communication module 110 is a sub-device whose data communication is controlled by the master device 201.

[0090] The communication module 110 includes an amplification control device 1101, an antenna switch 1102, and a frequency band selection switch 1103. As an example, the amplification control device 1101 is an amplification control device that controls a power amplifier circuit; the antenna switch 1102 is a switch that selects the signal amplified by the power amplifier circuit and transmitted / received through the antenna; and the frequency band selection switch 1103 is a switch that selects the wavelength of the signal transmitted / received through the antenna. Furthermore, in... Figure 11 In the example, two sub-devices are shown as sub-devices, but the number of sub-devices can be more than two, or it can be one. The amplification control device 1101 has an analog circuit 301a, and the antenna switch 1102 and the frequency band selection switch 1103 each have analog circuits 301b and 301c, respectively. The functions of the analog circuits 301a, 301b, and 301c are the same as those of the analog circuits described in the first embodiment.

[0091] The amplification control device 1101 is connected to the antenna switch 1102 and the frequency band selection switch 1103 via two wirings: clock signal line 1104 and data signal line 1105. The amplification control device 1101 communicates bidirectionally with the antenna switch 1102 and the frequency band selection switch 1103 in the same manner as in the first embodiment.

[0092] The amplification control device 1101 has a write mode for writing information to its own register or to the register of the antenna switch 1102 or the frequency band selection switch 1103, and a read mode for reading information from the register of the amplification control device 1101 or the register of the antenna switch 1102 or the frequency band selection switch 1103. The antenna switch 1102 and the frequency band selection switch 1103 also have a write mode for writing information to their own registers and a read mode for reading information from their own registers. The write or read modes of the amplification control device 1101, the antenna switch 1102, and the frequency band selection switch 1103 can be switched based on signals from the master device 201.

[0093] In order to rewrite the information stored in the register of the antenna switch 1102 or the frequency band selection switch 1103, the master device 201 sends a master signal containing a command signal indicating that it needs to be written to the amplification control device 1101. Alternatively, in order to read the information stored in the register of the antenna switch 1102 or the frequency band selection switch 1103, the master device 201 sends a master signal containing a command signal indicating that it needs to be read to the amplification control device 1101.

[0094] The main signal includes a command signal and an address signal that specifies the address of at least one register of antenna switch 1102 and frequency band selection switch 1103, respectively.

[0095] The command signal contains information instructing the writing to the register of antenna switch 1102 or frequency band selection switch 1103, or instructing the reading of information stored in the register of antenna switch 1102 or frequency band selection switch 1103. When the command signal contains information instructing the writing to the register of antenna switch 1102 or frequency band selection switch 1103, the command signal also contains information indicating the type of writing based on the main signal. Similar to the first embodiment, the command signal in the case of writing may indicate, for example, writing to at least one register within a device, writing to one register within a device, or writing to one register within a device while masking bit values, etc.

[0096] When performing a write operation, the master device 201 sends a master signal containing a command signal, an address signal, and a write data signal to be recorded into the register to the amplification control device 1101. The command signal contains information instructing the writing to the register of the antenna switch 1102 or the frequency band selection switch 1103.

[0097] When performing a readout operation, the master device 201 sends a master signal containing a command signal and an address signal to the amplification control device 1101. The command signal includes an instruction to read information stored in the register of the antenna switch 1102 or the frequency band selection switch 1103. Additionally, the master device 201 sends a clock signal to the amplification control device 1101.

[0098] In addition, the master device 201 can write to and read from the registers of the amplification control device 1101, and can also send a master signal indicating a write or read operation to the amplification control device 1101.

[0099] The address signal is information that identifies the registers of antenna switch 1102 or band selection switch 1103. The address signal is, for example, 5-bit or 8-bit data.

[0100] Reference Figure 12 The various parts of the amplification control device 1101 will be described below. In addition to the command start determination unit 1012, data signal generation unit 1013, clock enable signal generation unit 1014, and register unit 1016 described in the first embodiment, the amplification control device 1101 also includes a data transceiver unit 1201, input / output buffer units 1202 and 1203, a mode control unit 1204, an input / output control circuit 1205, and a selection circuit 1206. Figure 12 In the diagram, dashed lines indicate the transmission path of the signal corresponding to the information read from the amplification control device 1101, the antenna switch 1102, or the frequency band selection switch 1103.

[0101] The data transceiver unit 1201 receives a clock signal and a master signal from the master device 201, and performs processing to interpret the master signal. For example, based on the information represented by a command signal contained in the master signal, the data transceiver unit 1201 generates command identification information for recognizing commands. The data transceiver unit 1201 sends the command identification information to the data signal generation unit 1013 and the clock enable signal generation unit 1014. Furthermore, the data transceiver unit 1201 performs the following control: it receives information read from the antenna switch 1102 or the frequency band selection switch 1103 as a readout signal and sends it to the master device 201. Alternatively, the readout signal can also be sent to the master device 201 as a signal that information stored in the register unit 1016 of the amplification control device 1101 has been read.

[0102] The input / output buffer unit 1202 is a circuit that allows signals to pass through during communication between the amplification control device 1101 and the main device 201. The input / output buffer unit 1203 is a circuit that allows signals to pass through during communication between the amplification control device 1101 and the antenna switch 1102 and the frequency band selection switch 1103.

[0103] The mode control unit 1204 is a circuit that controls the write mode or read mode of the amplification control device 1101. The master device 201 sends a signal to the amplification control device 1101 to control the write mode or read mode. Based on the input from the master device 201, the data transceiver unit 1201 sends a mode control signal that sets the write mode or read mode of the amplification control device 1101 to the mode control unit 1204. In addition, the mode control signal includes information for setting the read mode to read information from the antenna switch 1102 or the frequency band selection switch 1103 or to read information stored in the amplification control device 1101 itself.

[0104] The mode control unit 1204 stores information corresponding to the mode control signal. The information stored in the mode control unit 1204 is referenced by the input / output control circuit 1205 and the selection circuit 1206.

[0105] The input / output control circuit 1205 determines whether the amplification control device 1101 is in write mode or read mode by referring to the information stored in the mode control unit 1204. Based on the settings of write mode and read mode, the input / output control circuit 1205 sends the signal controlling the transmission and reception of signals handled by the input / output buffer units 1202 and 1203 to the input / output buffer units 1202 and 1203.

[0106] In write mode, the input / output control circuit 1205 controls the input / output buffer 1202, causing the input / output buffer 1202 to send the write data signal contained in the main signal to the data transceiver 1201. Additionally, in write mode, the input / output control circuit 1205 controls the input / output buffer 1203, causing the input / output buffer 1203 to send a data signal or a readout indication signal to the antenna switch 1102 and the frequency band selection switch 1103.

[0107] In readout mode, the input / output control circuit 1205 controls the input / output buffer 1202, causing it to send readout signals from the antenna switch 1102, the band selection switch 1103, or the amplification control device 1101 to the main device 201 via the amplification control device 101. Also in readout mode, the input / output control circuit 1205 controls the input / output buffer 1203, causing it to send readout signals from the antenna switch 1102 or the band selection switch 1103 to the selection circuit 1206.

[0108] The selection circuit 1206 receives a signal read from the antenna switch 1102 or the band selection switch 1103, or a signal containing information stored in the amplification control device 1101 read from the register section 1016 by the data transceiver section 1201. The selection circuit 1206 determines whether the amplification control device 1101 is in write mode or read mode by referring to information stored in the mode control section 1204. When the amplification control device 1101 is in read mode, the selection circuit 1206 determines whether the read information comes from the antenna switch 1102 or the band selection switch 1103, or is stored within the amplification control device 1101 itself. Based on the determination result, the selection circuit 1206 sends the information from the antenna switch 1102 or the band selection switch 1103, or the information stored in the amplification control device 1101, to the input / output buffer section 1202.

[0109] The operation of the amplification control device 1101 in write mode will be described. The operation of the amplification control device 1101 in write mode is the same as that of the amplification control device 101 in the first embodiment. The data transceiver unit 1201 sends the address signal and write data signal included in the main signal to the data signal generation unit 1013, where the command start determination unit 1012 determines whether the transmission of the command signal has started. The data signal generation unit 1013 generates a data signal based on the command identification information, bit position information, address signal, and write data signal from the data receiving unit 1011, and sends the data signal to the data transmitting unit 1015. The clock enable signal generation unit 1014 generates a clock enable signal based on the command identification information and bit position information, and sends it to the data transmitting unit 1015. When the data transmission unit 1015 receives an input command detection signal and a clock enable signal from the clock enable signal generation unit 1014, it transmits the data signal from the data signal generation unit 1013 along with the clock signal provided to the data transmission unit 1015 to the antenna switch 1102 or the frequency band selection switch 1103. Similar to the communication module 10 in the first embodiment, the communication module 110 performs parallel operations of signal communication within itself, in parallel with the reception of the main signal. The amplification control device 101 performs the generation of data signals to be transmitted to the antenna switch 102 and the frequency band selection switch 103, and the transmission of data signals to the antenna switch 102 and the frequency band selection switch 103, in parallel with the processing of interpreting the main signal from the main device 201.

[0110] The operation of the amplification control device 1101 in readout mode will be explained. Here it is assumed that, in addition to the amplification control device 1101, the antenna switch 1102 and the frequency band selection switch 1103 are also preset to readout mode before the amplification control device 1101 reads out.

[0111] The data transceiver unit 1201 receives a main signal from the master device 201, which includes an address signal and a read command signal indicating that data can be read from the antenna switch 1102 or the frequency band selection switch 1103.

[0112] The data transceiver unit 1201 sends the address signal included in the main signal to the data signal generation unit 1013. Furthermore, the data receiving unit 1011 generates command identification information indicating the readout from the antenna switch 1102 or the frequency band selection switch 1103, and bit position information indicating the position of the additional command identification information, and sends this bit position information to the data signal generation unit 1013 and the clock enable signal generation unit 1014. In addition to the information containing the position of the additional command identification information, the bit position information may also include information indicating the start and end positions of signals in the data signal, such as the start position of the address signal and the start position of the readout signal.

[0113] The data signal generation unit 1013 generates a readout indication signal to be sent to the antenna switch 102 and the frequency band selection switch 103 based on the command identification information, bit position information and address signal from the data receiving unit 1011. The data signal generation unit 1013 then sends the readout indication signal to the data transmitting unit 1015.

[0114] When the data transmission unit 1015 receives an input command detection signal and a clock enable signal from the clock enable signal generation unit 1014, it sends a readout indication signal from the data signal generation unit 1013 along with a clock signal provided to the data transmission unit 1015 to the antenna switch 1102 and the frequency band selection switch 1103. The data transmission unit 1015 transmits the clock signal via the clock signal line 104 and the readout indication signal via the data signal line 105. This instructs the data to be read from the antenna switch 1102 and the frequency band selection switch 1103.

[0115] Reference Figure 13 Antenna switch 1102 is described below. Other sub-devices, including frequency band selection switch 1103, also have the same structure for data communication. In addition to the command start determination unit 1022 and register unit 1023 described in the first embodiment, antenna switch 1102 also includes a data transceiver unit 1301, an input / output buffer unit 1302, a mode control unit 1303, an input / output control circuit 1304, and a register selection circuit 1305.

[0116] In write mode, the data transceiver unit 1301 receives the address signal and write data signal contained in the data signal from the amplification control device 1101. In read mode, the data transceiver unit 1301 receives the read indication signal from the amplification control device 1101.

[0117] The input / output buffer section 1302 is a circuit that allows signals to pass through during communication between the amplification control device 1101 and the antenna switch 1102.

[0118] The mode control unit 1303 is a circuit that controls the write mode or read mode of the antenna switch 1102. The master device 201 sends a signal to the antenna switch 1102 via the amplification control device 1101 to control the write mode or read mode of the antenna switch 1102. Based on the input from the master device 201 via the amplification control device 1101, the data transceiver unit 1301 sends a mode control signal that sets the write mode or read mode of the antenna switch 1102 to the mode control unit 1303.

[0119] The mode control unit 1303 stores information corresponding to the mode control signal. The information stored in the mode control unit 1303 is referenced by the input / output control circuit 1304.

[0120] The input / output control circuit 1304 determines whether the amplification control device 1101 is in write mode or read mode by referring to the information stored in the mode control unit 1303. Based on the settings of write mode and read mode, the input / output control circuit 1304 sends the signal controlling the transmission and reception of the signal handled by the input / output buffer unit 1302 to the input / output buffer unit 1302.

[0121] In write mode, the input / output control circuit 1304 controls the input / output buffer 1302, causing the input / output buffer 1302 to send the write data signal contained in the data signal to the data transceiver 1301.

[0122] In addition, in readout mode, input / output control circuit 1304 controls input / output buffer 1302, causing input / output buffer 1302 to send the readout signal from antenna switch 1102 to amplifier control device 101.

[0123] The register selection circuit 1305 selects the register of the register section 1023 based on the address of each register of the register section 1023 of the antenna switch 1102 contained in the read indication signal. The information read from the selected register is sent as a read signal to the amplification control device 1101 via the data transceiver section 1301.

[0124] The operation of the antenna switch 1102 in write mode will be described. The operation of the antenna switch 1102 in write mode is the same as that of the antenna switch 102 in the first embodiment. The data transceiver unit 1301 receives data signals from the amplification control device 1101. The command start determination unit 1022 determines, based on the clock signal and the data signal, whether data signal transmission from the amplification control device 1101 to the antenna switch 1102 has begun. When data signal transmission begins, the command start determination unit 1022 sends a reset signal to the data transceiver unit 1301. The register unit 1023 controls the writing to each register based on signals from the data transceiver unit 1301.

[0125] The operation of antenna switch 1102 in readout mode will be explained. Here, antenna switch 1102 is assumed to be preset to readout mode. Furthermore, readout mode is used to verify whether the data stored in antenna switch 1102 in write mode has been correctly written; therefore, it can also be called test mode. Test modes are set exclusively for antenna switch 1102 and band selection switch 1103. That is, when antenna switch 1102 is in readout mode, band selection switch 1103 is not set to readout mode. Data transceiver unit 1301 receives a readout indication signal from amplification control device 1101. Data transceiver unit 1301 reads the information stored in antenna switch 1102 based on the address contained in the readout indication signal. Specifically, antenna switch 1102 determines whether the register corresponding to the address represented by the address signal is included in antenna switch 1102. If the register is included in antenna switch 1102 and a readout indication signal is provided from amplification control device 1101, the information stored in the register is read from the register.

[0126] Reference Figure 14 The signals in the amplification control device 1101 and the antenna switch 1102 in readout mode are explained. Figure 14 An example of a signal based on a command read from a register of antenna switch 1102 is shown.

[0127] The main signals received by the amplification control device 1101 include a start signal, a command signal, a byte count signal, and an address signal. Following the main signals, the amplification control device 1101 outputs a read signal to the master device 201, and the read operation is completed based on the end signal. Here, the byte count signal indicates the number of bytes of data read. The byte count signal is a 4-bit signal that sets the number of bytes from 1 byte to 16 bytes. Figure 14 In the example, the byte count signal is set to indicate that 1 byte of data has been read.

[0128] When the data transceiver unit 1201 receives a master signal from the master device 201, the data transceiver unit 1201 interprets the command signal. If the command signal indicates a command to read from at least one register of the antenna switch 1102, the data signal generation unit 1013 generates information that appends the identification information B6 to the beginning of the byte count signal based on the address signal, command identification information, and bit position information.

[0129] Identification information B6 is a 1-bit information; a bit value of 0 indicates an indication to read data. The data transmission unit 1015 records identification information B6 at a position corresponding to the beginning clock of the byte count signal in the main signal, and transmits a data signal that offsets the byte count signal by one clock cycle. When the antenna switch 1102 is set to readout mode (test mode) and identification information B6 indicates that data should be read, the antenna switch 1102 reads out the signal.

[0130] Next, the data signal generation unit 1013 generates information that appends the identification information B1 to the beginning of the address signal. The identification information B1 is a 1-bit information; a bit value of 0 indicates a 5-bit address length, and a bit value of 1 indicates an 8-bit address length. The data transmission unit 1015 records the identification information B1 at the position corresponding to the beginning clock of the address signal in the main signal, and transmits a data signal that offsets the address signal by one clock cycle. Additionally, at this time, the address signal in the main signal includes parity bits P at the beginning and end, and the bits sandwiched between the parity bits P contain information representing the actual address.

[0131] exist Figure 14 In this example, the number of bytes specified by the byte count signal is 1. Therefore, a readout signal of 1 byte is read from the antenna switch 1102. The readout signal is sent from the data transceiver unit 1301 of the antenna switch 1102 to the amplification control device 1101, and then output to the master device 201 through the data transceiver unit 1201 of the amplification control device 1101.

[0132] Reference Figure 15 Another example of the signal in the amplification control device 1101 and the antenna switch 1102 in readout mode will be described. Figure 15 An example of a signal based on a command read from two registers of antenna switch 1102 is shown.

[0133] The main signals received by the amplification control device 1101 include a start signal, a command signal, a byte count signal, and an address signal. Following the main signals, the amplification control device 1101 outputs multiple read signals to the master device 201, and completes the read operation based on the end signal. Figure 15 In the example, the byte count signal is set to indicate that 2 bytes of data have been read.

[0134] When the command signal indicates a command to read from multiple registers of antenna switch 1102, data signal generation unit 1013 generates information that appends identification information B6 to the beginning of the byte count signal based on the address signal, command identification information, and bit position information. When antenna switch 1102 is set to read mode (test mode) and identification information B6 indicates read data, antenna switch 1102 reads the signal. Next, data signal generation unit 1013 generates information that appends identification information B1 to the beginning of the address signal. Figure 15 In this example, the number of bytes specified by the byte count signal is 2. Therefore, a readout signal of 2 bytes is read from antenna switch 1102.

[0135] In the communication module 110 according to the second embodiment, similarly to the communication module 10 described in the first embodiment, the circuitry for command interpretation can be provided only in the amplification control device 1101. The antenna switch 1102 and the frequency band selection switch 1103 only need to have circuitry for address interpretation, thus reducing the circuit size of the antenna switch 1102 and the frequency band selection switch 1103. Therefore, the overall circuit size of the communication module 10 can be reduced.

[0136] Furthermore, in the communication module 110 according to the second embodiment, in addition to writing information to the sub-devices in the communication module 10 as described in the first embodiment, information can also be read directly from the sub-devices. Here, directly reading information means, for example, reading the information itself stored in the register of the antenna switch 1102. Without directly reading information from the antenna switch 1102, the following process is required. First, when writing information to the antenna switch 1102, a copy of the written information is stored in the amplification control device 1101 beforehand. Next, the information stored in the amplification control device 1101 is read as information stored in the antenna switch 1102, thereby replacing the reading of the information from the antenna switch 1102. In such a process, it is impossible to confirm whether the information has actually been correctly written to the antenna switch 1102. For example, it is conceivable that a write error might occur due to the state of the signal path between the amplification control device 1101 and the antenna switch 1102. On the other hand, in the communication module 110, information can be read directly from the sub-devices, thus allowing for proper confirmation of the write status during product evaluation and factory testing.

[0137] (Third Implementation)

[0138] The third embodiment will be described. Figure 16 An example of a circuit including the communication module 160, the master device 201, and the analog circuits 301a, 301b, and 301c according to the third embodiment is shown. The communication module 160 is a sub-device whose data communication is controlled by the master device 201.

[0139] The communication module 160 includes an amplification control device 1601, an antenna switch 1602, and a frequency band selection switch 1603.

[0140] The amplification control device 1601 is connected to the antenna switch 1602 via clock signal line 1604 and data signal line 1605. The amplification control device 1601 is connected to the frequency band selection switch 1103 via clock signal line 1606 and data signal line 16057. The communication module 160 differs from the communication module 10 of the first embodiment in that the amplification control device 1601 is connected to each of the antenna switches 1602 and 1603 via independent paths.

[0141] The amplification control device 1601, antenna switch 1602, and frequency band selection switch 1603 communicate bidirectionally with the communication module 10 described in the first embodiment and the communication module 110 described in the second embodiment to read and write information.

[0142] In the communication module 160, device ID information for identifying each device is assigned as slave device addresses to the amplification control device 1601, the antenna switch 1602, and the frequency band selection switch 1603. Additionally, the amplification control device 1601 stores the device ID information of each sub-device connected to it.

[0143] In the communication module 160, a main signal containing a command signal indicating a write or read operation and a device ID signal indicating a device ID used to identify the device is sent from the master device 201 to the amplification control device 1601. Based on the device ID signal, the amplification control device 1601 performs signal transmission and reception for the antenna switch 1602 and the frequency band selection switch 1603.

[0144] Reference Figure 17 The processing in the amplification control device 1601 is explained. In step S1701, the amplification control device 1601 receives the main signal from the main device 201.

[0145] In step S1702, the amplification control device 1601 determines whether the device ID signal contained in the main signal is consistent with the device ID information of the amplification control device 1601 itself.

[0146] When a positive judgment is made in step S1702, in step S1703, the amplification control device 1601 performs a write or read process on itself.

[0147] When a negative judgment is made in step S1702, in step S1704, the amplification control device 1601 determines whether the device ID signal contained in the main signal is consistent with the device ID information assigned to the antenna switch 1602 or the frequency band selection switch 1603.

[0148] When an affirmative judgment is made in step S1704, in step S1705, the amplification control device 1601 generates a sub-device control signal, which indicates writing or reading from the sub-device identified by the device ID information. Here, the sub-device control signal refers to a signal used to write or read from the information described in the first and second embodiments.

[0149] In step S1706, the amplification control device 1601 sends a clock signal and a sub-device control signal to the sub-device determined by the device ID information.

[0150] When a negative judgment is made in step S1704, in step S1707, the amplification control device 1601 stops receiving the main signal from the main device 201.

[0151] In communication module 160, amplification control device 1601 transmits and receives signals to antenna switch 1602 or frequency band selection switch 1603 based on device identification signals. Therefore, circuits for interpreting the main signals are no longer needed in antenna switch 1602 and frequency band selection switch 1603. Antenna switch 1602 and frequency band selection switch 1603 only need circuits for address interpretation, thus reducing the circuit size of antenna switch 1602 and frequency band selection switch 1603. As a result, the overall circuit size of communication module 10 can be reduced. Furthermore, in communication modules 10 and 110 of the first and second embodiments, amplification control device and each sub-device are identified by a common address, but in communication module 160, amplification control device and each sub-device can be identified by different addresses for writing or reading information.

[0152] The above describes this embodiment. The communication module 10 according to the first embodiment includes: an amplification control device 101 connected to a main device 201; and at least one second sub-device, which is not connected to the main device 201 but is connected to the first sub-device via a first signal line for transmitting a clock signal and a second signal line for transmitting a data signal. The amplification control device 101 receives a main signal from the main device 201, wherein the main signal includes a command signal, an address signal specifying the address of at least one register possessed by the at least one second sub-device, and a write data signal to be recorded into the register corresponding to the address. The address signal follows the command signal, and the write data signal follows the address signal. The amplification control device 101 interprets the command signal. Based on the interpretation result of the command signal, if it is necessary to write information based on the data signal into either the antenna switch 102 or the frequency band selection switch 103, upon receiving the command signal... After receiving the command signal and during the period of receiving the main signal, a write indication signal is generated. Based on the interpretation result of the command signal, the amplification control device 101 generates a data signal based on the address signal and the write data signal to be provided to the antenna switch 102 and the frequency band selection switch 103 respectively after receiving the command signal and during the period of receiving the main signal. After receiving the command signal and during the period of receiving the main signal, the amplification control device 101 provides a write indication signal to the antenna switch 102 and the frequency band selection switch 103 respectively through the first signal line or the second signal line, and provides a data signal to the antenna switch 102 and the frequency band selection switch 103 respectively through the second signal line.

[0153] In the communication module 10, the antenna switch 102 and the frequency band selection switch 103 determine whether the register corresponding to the address represented by the address signal is included in the antenna switch 102 or the frequency band selection switch 103. If the register is included in the antenna switch 102 or the frequency band selection switch 103 and a write instruction signal is provided from the amplification control device 101, a write data signal is written to the register.

[0154] In the communication module 10, the amplification control device 101 performs the following processing in parallel with the reception of the main signal: based on the interpretation result of the command signal, if information based on the data signal needs to be written to either the antenna switch 102 or the frequency band selection switch 103, a write indication signal is generated; based on the interpretation result of the command signal, a data signal based on the address signal and the write data signal is generated to be provided to the antenna switch 102 and the frequency band selection switch 103 respectively; and a write indication signal is provided to the antenna switch 102 and the frequency band selection switch 103 respectively via the clock signal line 104 or the data signal line 105, and a data signal is provided to the antenna switch 102 and the frequency band selection switch 103 respectively via the data signal line 105, wherein the antenna switch 102 and the frequency band selection switch 103 each determine whether the register corresponding to the address represented by the address signal is included in at least one sub-device, and if the register is included in at least one sub-device and a write indication signal is provided from the amplification control device 101, a write data signal is written to the register.

[0155] In the communication module 10, the large-scale circuitry for command interpretation can be housed only in the amplification and control device 101. The antenna switch 102 and the frequency band selection switch 103 only require circuitry for address interpretation, thus reducing their circuit size. This reduces the overall circuit size of the communication module 10. Furthermore, the communication module 10 generates and transmits data signals to the antenna switch 102 and the frequency band selection switch 103 in parallel with the reception of the main signal. This improves communication efficiency.

[0156] In the above-described manner, the amplification control device 101 may generate a data signal containing identification information, which is information about the type of write data signal made to at least one register. A write indication signal is included at the end of the data signal as identification information. The antenna switch 102 and the frequency band selection switch 103 each write the write data signal to the register based on the identification information.

[0157] Therefore, antenna switch 102 and frequency band selection switch 103 do not require circuitry to interpret commands, thus reducing the circuit size of communication module 10. Furthermore, antenna switch 102 and frequency band selection switch 103 do not require circuitry to determine whether data writing is permitted, thus reducing the circuit size of communication module 10.

[0158] In the above methods, the identification information can also be information indicating the data length of the data signal. In the above embodiments, the identification information can also be information indicating the type of data contained in the data signal.

[0159] In the above method, the write category may include a write category that indicates writing a portion of a write data signal to the register without modifying specified bits of the register. Identification information indicates whether the data contained in the data signal is a write data signal or a mask signal, where the mask signal indicates the specified bits that are not modified. The antenna switch 102 and the band selection switch each write a portion of the write data signal to at least one register based on the write data signal and the mask signal. Thus, data can be written while masking specified bits.

[0160] In the above method, the write category may include a write category indicating that a first write data signal is written to the first register of the antenna switch 102 and the band selection switch 103, and a second write data signal is written to the second register of at least one sub-device. Identification information is included at the end of each of the first and second write data signals. Based on the identification information, the antenna switch 102 and the band selection switch 103 each write the first write data signal to the first register and the second write data signal to the second register. This allows for continuous writing of information to multiple registers. Furthermore, it enables the generation of a data signal based on the master signal while maintaining the data width.

[0161] In the communication module 110 of the second embodiment, the main signal includes a command signal indicating that information should be read from at least one register of the antenna switch 102 or the frequency band selection switch 103. Based on the interpretation result of the command signal, the amplification control device 1101 generates a readout indication signal based on the address signal when it is necessary to read the information stored in at least one register of the antenna switch 102 or the frequency band selection switch 103. The amplification control device 1101 provides the readout indication signal to the antenna switch 102 and the frequency band selection switch 103 respectively through the clock signal line 1104 or the data signal line 1105. The amplification control device 1101 receives the readout signal read from the register of the antenna switch 102 or the frequency band selection switch 103 and sends the readout signal to the main device 201.

[0162] In the communication module 110, the antenna switch 102 and the frequency band selection switch 103 determine whether the register corresponding to the address represented by the address signal is included in the antenna switch 102 or the frequency band selection switch 103. If the register is included in the antenna switch 102 or the frequency band selection switch 103 and a readout indication signal is provided from the amplification control device, the information stored in the register is read out from the register.

[0163] Similar to the communication module 10, the antenna switch 1102 and the frequency band selection switch 1103 only require circuitry for address interpretation in the communication module 110. This reduces the circuit size of the antenna switch 1102 and the frequency band selection switch 1103, thus reducing the overall circuit size of the communication module 110. Furthermore, in the communication module 110, information can be directly read from the antenna switch 1102 and the frequency band selection switch 1103, allowing for proper verification of the write status in these switches during product evaluation and factory testing.

[0164] In the above-described manner, the amplification control device 1101 may generate a readout indication signal containing identification information based on the category of readout from at least one register, and the amplification control device 1101 may receive a readout signal read from the antenna switch 102 or the band selection switch 103 based on the identification information. Alternatively, in the above-described manner, the identification information may also be information indicating the data length of the readout signal.

[0165] Thus, for example, the read category can be set to output a signal in the same form as that used by the device for confirming the write status, thereby improving the convenience of confirming the write status.

[0166] In the above-described manner, the main signal may include a command signal indicating that the antenna switch 102 and the frequency band selection switch 103 are set to write mode or read mode. Based on the interpretation of the command signal, the amplification control device 1101 generates a mode setting signal that sets the antenna switch 102 and the frequency band selection switch 103 to write mode or read mode. The amplification control device 1101 provides the mode setting signal to each of the antenna switch 102 and the frequency band selection switch 103 via the clock signal line 1104 or the data signal line 1105. The amplification control device 1101 receives a read signal read from the register of either the antenna switch 102 or the frequency band selection switch 103, which is set to read mode and has been provided with a read indication signal. Thus, writing and reading settings for the sub-devices can be performed.

[0167] In the above method, the write indication signal can also be a clock signal generated after the data signal. Additionally, in the above method, the amplification control devices 101 and 1101 can also determine that the write data signal will not be written to either the antenna switch 102 or the frequency band selection switch 103 if an error exists in the main signal.

[0168] Therefore, error detection is not required by antenna switch 102, etc., which reduces the circuit size of antenna switch 102, etc. This reduces the overall circuit size of communication modules 10 and 110.

[0169] The communication module 160 according to the third embodiment includes: an amplification control device 1601 connected to a master device 201, receiving a master signal from the master device 201, the master signal including a command signal and a device ID signal representing a device ID for identifying the device, the amplification control device 1601 interpreting the command signal, and the amplification control device 1601 being assigned first device ID information; an antenna switch 1602 connected to the amplification control device 1601 via a first signal line for transmitting a clock signal and a second signal line for transmitting a data signal, the antenna switch 1602 being assigned second device ID information; and a frequency band selection switch 1603 connected to the amplification control device 1601 via a third signal line for transmitting a clock signal and a fourth signal line for transmitting a data signal, the frequency band selection switch 1603 being assigned third device ID information.

[0170] In the communication module, the amplification control device 1601 determines whether the device ID signal contained in the main signal is consistent with the first device ID information possessed by the amplification control device 1601, and whether the device ID signal contained in the main signal is consistent with the second or third device ID information possessed by the amplification control device 1601. If the device ID signal contained in the main signal is consistent with the second device ID information possessed by the amplification control device 1601, the amplification control device 1601 generates a first sub-device control signal indicating data writing or reading for the antenna switch 1602 based on the interpretation result of the command signal, and provides the first sub-device control signal to the antenna switch 1602. If the device ID signal contained in the main signal is consistent with the third device ID information possessed by the amplification control device 1601, the amplification control device 1601 generates a second sub-device control signal indicating data writing or reading for the frequency band selection switch 1603 based on the interpretation result of the command signal, and provides the second sub-device control signal to the frequency band selection switch 1603.

[0171] Therefore, circuits for interpreting the main signal are no longer needed in antenna switch 1602 and frequency band selection switch 1603. Antenna switch 1602 and frequency band selection switch 1603 only need circuits for address interpretation, thus reducing the circuit size of antenna switch 1602 and frequency band selection switch 1603, and consequently reducing the overall circuit size of communication module 10. Furthermore, communication module 160 can identify amplification control devices and various sub-devices using different addresses, enabling information writing and reading, thereby improving the convenience of writing and reading.

[0172] Furthermore, the embodiments described above are for the purpose of making the present invention easier to understand, and are not intended to limit the interpretation of the embodiments of the present invention. The present invention can be modified / improved without departing from its spirit, and the present invention also includes its equivalents. That is, any solution obtained by those skilled in the art through appropriate design changes to each embodiment, as long as it possesses the features of the present invention, is also included within the scope of the present invention. For example, the elements, their configurations, conditions, etc., possessed in each embodiment are not limited to the illustrative content and can be appropriately modified. In addition, each embodiment is illustrative, and of course, partial substitutions or combinations of the structures shown in different embodiments are possible; as long as they contain the features of the present invention, these embodiments are also included within the scope of the present invention.

[0173] <1>

[0174] A communication module, comprising:

[0175] The first sub-device, which is connected to the main device; and

[0176] At least one second sub-device, which is not connected to the main device, but is connected to the first sub-device via a first signal line for transmitting clock signals and a second signal line for transmitting data signals.

[0177] The first sub-device receives a master signal from the master device, wherein the master signal includes a command signal, an address signal specifying the address of at least one register possessed by at least one second sub-device, and a write data signal to be recorded into the register corresponding to the address, wherein the address signal follows the command signal, and the write data signal follows the address signal.

[0178] The first sub-device interprets the command signal.

[0179] Based on the interpretation result of the command signal, if the first sub-device needs to write information based on the data signal to any one of the at least one second sub-device, it generates a write indication signal after receiving the command signal and during the receipt of the main signal.

[0180] Based on the interpretation result of the command signal, the first sub-device, after receiving the command signal and during the period of receiving the main signal, generates the data signal based on the address signal and the write data signal to be provided to each of the at least one second sub-device.

[0181] Upon receiving the command signal and while receiving the master signal, the first sub-device provides the write instruction signal to each of the at least one second sub-device via the first signal line or the second signal line, and provides the data signal to each of the at least one second sub-device via the second signal line.

[0182] Each of the at least one second sub-device determines whether the register corresponding to the address represented by the address signal is included in the at least one second sub-device. If the register is included in the at least one second sub-device and the write indication signal is provided from the first sub-device, each of the at least one second sub-device writes the write data signal to the register.

[0183] <2>

[0184] according to <1> The communication module, wherein,

[0185] The first sub-device generates a data signal containing identification information based on the type of write to the at least one register, with a write indication signal included at the end of the data signal as part of the identification information.

[0186] Each of the at least one second sub-device writes the write data signal into the register based on the identification information.

[0187] <3>

[0188] according to <1> The communication module, wherein,

[0189] The identification information is information indicating the data length of the data signal.

[0190] <4>

[0191] according to <2> The communication module, wherein,

[0192] The identification information is information indicating the type of data contained in the data signal.

[0193] <5>

[0194] according to <4> The communication module, wherein,

[0195] The write category includes a write category that indicates writing a portion of the write data signal to the register without modifying specified bits of the register.

[0196] The identification information indicates whether the data contained in the data signal is a written data signal or a mask signal, and the mask signal represents the specified bits that are not modified.

[0197] Each of the at least one second sub-device writes a portion of the write data signal to the at least one register based on the write data signal and the mask signal.

[0198] <6>

[0199] according to <4> or <5> The communication module, wherein,

[0200] The write category includes write categories that indicate writing a first write data signal to a first register of the at least one second sub-device and writing a second write data signal to a second register of the at least one second sub-device.

[0201] The identification information is included at the end of both the first write data signal and the second write data signal.

[0202] Each of the at least one second sub-device writes the first write data signal to the first register and the second write data signal to the second register based on the identification information.

[0203] <7>

[0204] according to <1> to <6> The communication module described in any one of the following, wherein,

[0205] The write indication signal is the clock signal generated after the data signal.

[0206] <8>

[0207] according to <1> to <7> The communication module described in any one of the following, wherein,

[0208] The main signal includes a command signal indicating that information should be read from at least one register of the at least one second sub-device.

[0209] Based on the interpretation result of the command signal, the first sub-device generates a read indication signal based on the address signal when it is necessary to read information stored in the at least one register from the at least one second sub-device.

[0210] The first sub-device provides the readout indication signal to each of the at least one second sub-device via the first signal line or the second signal line.

[0211] The first sub-device receives a read signal from the register of any one of the at least one second sub-device.

[0212] The first sub-device sends the readout signal to the master device.

[0213] <9>

[0214] according to <8> The communication module, wherein,

[0215] The first sub-device generates the readout indication signal containing identification information based on the category of readout from the at least one register.

[0216] The first sub-device receives the readout signal read from the at least one second sub-device based on the identification information.

[0217] <10>

[0218] according to <9> The communication module, wherein,

[0219] The identification information is information indicating the data length of the readout signal.

[0220] <11>

[0221] according to <8> to <10> The communication module described in any one of the following, wherein,

[0222] The master signal includes the command signal indicating that the at least one second sub-device is set to write mode or read mode.

[0223] Based on the interpretation result of the command signal, the first sub-device generates a mode setting signal that sets the at least one second sub-device to write mode or read mode.

[0224] The first sub-device provides the mode setting signal to each of the at least one second sub-device via the first signal line or the second signal line.

[0225] The first sub-device receives a read signal from the register of any one of the at least one second sub-devices that is set to read mode and is provided with the read indication signal.

[0226] <12>

[0227] according to <1> to <11> The communication module described in any one of the following, wherein,

[0228] The first sub-device is an amplification control device that controls the power amplifier circuit.

[0229] The at least one second sub-device is an antenna switch that selects a signal amplified by a power amplifier circuit and transmitted / received through an antenna, or a frequency band selection switch that selects the wavelength of a signal transmitted / received through the antenna.

[0230] <13>

[0231] according to <1> to <12> The communication module described in any one of the following, wherein,

[0232] If the main signal has an error, the first sub-device determines that it will not write the write data signal to any of the at least one second sub-device.

[0233] <14>

[0234] A communication module, comprising:

[0235] A first sub-device is connected to a master device and receives a master signal from the master device, wherein the master signal includes a command signal and a device ID signal representing a device ID for identifying the device, the first sub-device interprets the command signal, and the first sub-device is assigned first device ID information;

[0236] A second sub-device is connected to the first sub-device via a first signal line for transmitting clock signals and a second signal line for transmitting data signals. The second sub-device is assigned a second device ID.

[0237] A third sub-device is connected to the first sub-device via a third signal line for transmitting clock signals and a fourth signal line for transmitting data signals. The third sub-device is assigned a third device ID.

[0238] Specifically, the first sub-device determines whether the device ID signal contained in the main signal is consistent with the first device ID information possessed by the first sub-device.

[0239] The first sub-device determines whether the device ID signal contained in the main signal is consistent with the second device ID information or the third device ID information possessed by the first sub-device.

[0240] If the device ID signal included in the main signal is consistent with the second device ID information possessed by the first sub-device, the first sub-device generates a first sub-device control signal indicating data writing or reading based on the interpretation result of the command signal for the second sub-device.

[0241] The first sub-device provides the second sub-device with its own control signals.

[0242] If the device ID signal included in the main signal is consistent with the third device ID information possessed by the first sub-device, the first sub-device generates a second sub-device control signal indicating data writing or reading based on the interpretation result of the command signal for the third sub-device.

[0243] The first sub-device provides the second sub-device control signal to the third sub-device.

[0244] Explanation of reference numerals in the attached figures

[0245] 10, 110, 160: Communication module; 101, 1101, 1601: Amplification control device; 102, 1102, 1602: Antenna switch; 103, 1103, 1603: Frequency band selection switch; 104, 1104, 1604, 1606: Clock signal line; 105, 1105, 1605, 1607: Data signal line; 201: Master device; 301: Analog circuit; 1011: Data receiving unit; 1012: Command start determination unit; 1013: Data signal generation unit; 1014: Clock enable signal generation unit; 1015: Data transmitting unit; 1021: Data receiving unit; 1022: Command start determination unit; 1023: Register unit.

Claims

1. A communication module, comprising: The first sub-device, which is connected to the main device; and At least one second sub-device, which is not connected to the main device, but is connected to the first sub-device via a first signal line for transmitting clock signals and a second signal line for transmitting data signals. The first sub-device receives a master signal from the master device, wherein, The main signal includes a command signal, an address signal specifying the address of at least one register of at least one second sub-device, and a write data signal to be recorded into the register corresponding to the address. The address signal follows the command signal, and the write data signal follows the address signal. The first sub-device interprets the command signal. Based on the interpretation result of the command signal, if the first sub-device needs to write information based on the data signal to any one of the at least one second sub-device, it generates a write indication signal after receiving the command signal and during the receipt of the main signal. Based on the interpretation result of the command signal, the first sub-device, after receiving the command signal and during the period of receiving the main signal, generates the data signal based on the address signal and the write data signal to be provided to each of the at least one second sub-device. Upon receiving the command signal and while receiving the master signal, the first sub-device provides the write instruction signal to each of the at least one second sub-device via the first signal line or the second signal line, and provides the data signal to each of the at least one second sub-device via the second signal line. Each of the at least one second sub-device determines whether the register corresponding to the address represented by the address signal is included in the at least one second sub-device. If the register is included in the at least one second sub-device and the write indication signal is provided from the first sub-device, each of the at least one second sub-device writes the write data signal to the register.

2. The communication module according to claim 1, wherein, The first sub-device generates a data signal containing identification information based on the type of write to the at least one register, with a write indication signal included at the end of the data signal as part of the identification information. Each of the at least one second sub-device writes the write data signal into the register based on the identification information.

3. The communication module according to claim 2, wherein, The identification information is information indicating the data length of the data signal.

4. The communication module according to claim 2, wherein, The identification information is information indicating the type of data contained in the data signal.

5. The communication module according to claim 4, wherein, The write category includes a write category that indicates writing a portion of the write data signal to the register without modifying specified bits of the register. The identification information indicates whether the data contained in the data signal is a written data signal or a mask signal, and the mask signal represents the specified bits that are not modified. Each of the at least one second sub-device writes a portion of the write data signal to the at least one register based on the write data signal and the mask signal.

6. The communication module according to claim 4 or 5, wherein, The write category includes write categories that indicate writing a first write data signal to a first register of the at least one second sub-device and writing a second write data signal to a second register of the at least one second sub-device. The identification information is included at the end of both the first write data signal and the second write data signal. Each of the at least one second sub-device writes the first write data signal to the first register and the second write data signal to the second register based on the identification information.

7. The communication module according to any one of claims 1 to 6, wherein, The write indication signal is the clock signal generated after the data signal.

8. The communication module according to any one of claims 1 to 7, wherein, The main signal includes a command signal indicating that information should be read from at least one register of the at least one second sub-device. Based on the interpretation result of the command signal, the first sub-device generates a read indication signal based on the address signal when it is necessary to read information stored in the at least one register from the at least one second sub-device. The first sub-device provides the readout indication signal to each of the at least one second sub-device via the first signal line or the second signal line. The first sub-device receives a read signal from the register of any one of the at least one second sub-device. The first sub-device sends the readout signal to the master device.

9. The communication module according to claim 8, wherein, The first sub-device generates the readout indication signal containing identification information based on the category of readout from the at least one register. The first sub-device receives the readout signal read from the at least one second sub-device based on the identification information.

10. The communication module according to claim 9, wherein, The identification information is information indicating the data length of the readout signal.

11. The communication module according to any one of claims 8 to 10, wherein, The master signal includes the command signal indicating that the at least one second sub-device is set to write mode or read mode. Based on the interpretation result of the command signal, the first sub-device generates a mode setting signal that sets the at least one second sub-device to write mode or read mode. The first sub-device provides the mode setting signal to each of the at least one second sub-device via the first signal line or the second signal line. The first sub-device receives a read signal from the register of any one of the at least one second sub-devices that is set to read mode and is provided with the read indication signal.

12. The communication module according to any one of claims 1 to 11, wherein, The first sub-device is an amplification control device that controls the power amplifier circuit. The at least one second sub-device is an antenna switch that selects a signal amplified by a power amplifier circuit and transmitted / received through an antenna, or a frequency band selection switch that selects the wavelength of a signal transmitted / received through the antenna.

13. The communication module according to any one of claims 1 to 12, wherein, If the main signal has an error, the first sub-device determines that it will not write the write data signal to any of the at least one second sub-device.

14. A communication module, comprising: The first sub-device is connected to the main device and receives main signals from the main device, wherein... The main signal includes a command signal and a device ID signal representing a device ID used to identify the device. The first sub-device interprets the command signal and is assigned first device ID information. The second sub-device is connected to the first sub-device via a first signal line for transmitting clock signals and a second signal line for transmitting data signals. The second sub-device is assigned second device ID information. as well as A third sub-device is connected to the first sub-device via a third signal line for transmitting clock signals and a fourth signal line for transmitting data signals. The third sub-device is assigned a third device ID. Specifically, the first sub-device determines whether the device ID signal contained in the main signal is consistent with the first device ID information possessed by the first sub-device. The first sub-device determines whether the device ID signal contained in the main signal is consistent with the second device ID information or the third device ID information possessed by the first sub-device. If the device ID signal included in the main signal is consistent with the second device ID information possessed by the first sub-device, the first sub-device generates a first sub-device control signal indicating data writing or reading based on the interpretation result of the command signal for the second sub-device. The first sub-device provides the second sub-device with its own control signals. If the device ID signal included in the main signal is consistent with the third device ID information possessed by the first sub-device, the first sub-device generates a second sub-device control signal indicating data writing or reading based on the interpretation result of the command signal for the third sub-device. The first sub-device provides the second sub-device control signal to the third sub-device.

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