A pixel circuit and an image sensor

Abstract

The application discloses a pixel circuit and an image sensor, relates to the technical field of pixel circuits, and is used for realizing flexible switching of different gains of the pixel circuit. The pixel circuit comprises: an input end of a feedback subcircuit is adapted to be connected with a photodiode, the feedback subcircuit is configured to: receive and store an exposure current output by the photodiode; an input end of an amplification subcircuit is adapted to be connected with the photodiode, the amplification subcircuit is configured to: amplify the voltage of the input end of the amplification subcircuit based on the exposure current output by the photodiode; and clamp the voltage of the photodiode at a preset potential through the feedback subcircuit; a gain switching subcircuit is connected between the second end of a fourth capacitor and the ground end, and between the second end of the fourth capacitor and the output end of the amplification subcircuit, and the gain switching subcircuit is configured to: control the capacitance value between the input end and the output end of the feedback subcircuit to change, so as to change the gain of the feedback subcircuit to the exposure current.

Description

Technical Field

[0001] This invention relates to the field of pixel circuit technology, and more particularly to a pixel circuit and an image sensor. Background Technology

[0002] In the pixel circuit design of image sensors, the core requirement is to effectively receive, store, and amplify the exposure current output by the photodiode to ensure image quality. Image sensors consist of multiple pixel circuits, and the performance of each circuit collectively determines the sharpness, uniformity, and dynamic range of the final image. The gain of traditional pixel circuits (such as 3T pixel circuits, which include three transistors) is determined by the capacitance value of their internal capacitors. This makes it difficult to flexibly adjust the gain of the exposure current according to light intensity or noise levels, and prevents switching between high-sensitivity and low-noise imaging modes, limiting their applicability in complex lighting conditions. Summary of the Invention

[0003] The purpose of this invention is to provide a pixel circuit and an image sensor, which enables flexible switching of different gains in the pixel circuit to meet the imaging gain requirements in different scenarios.

[0004] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0005] In a first aspect, the present invention provides a pixel circuit comprising: a feedback sub-circuit, an amplification sub-circuit, and a gain switching sub-circuit. The input terminal of the feedback sub-circuit is adapted to be connected to a photodiode, and the feedback sub-circuit is configured to receive and store the exposure current output by the photodiode. The feedback sub-circuit includes: a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. A first terminal of the first capacitor is adapted to be connected to the photodiode; the second terminals of the first, second, third, and fourth capacitors are connected together; the second terminal of the second capacitor is connected to the output terminal of the amplification sub-circuit; the second terminal of the third capacitor is connected to a first voltage terminal; and the second terminal of the fourth capacitor is connected to a ground terminal. The input terminal of the amplification sub-circuit is adapted to be connected to the photodiode, and the amplification sub-circuit is configured to amplify the voltage at its input terminal based on the exposure current output by the photodiode; and clamp the voltage of the photodiode at a preset potential through the feedback sub-circuit. The gain switching sub-circuit is connected between the second terminal of the fourth capacitor and the ground terminal, and between the second terminal of the fourth capacitor and the output terminal of the amplification sub-circuit. The gain switching sub-circuit is configured to change the capacitance value between the input and output terminals of the feedback sub-circuit to change the gain of the feedback sub-circuit on the exposure current.

[0006] This invention introduces a feedback sub-circuit consisting of a first to a fourth capacitor, combined with a gain switching sub-circuit, to effectively control the capacitance value between the input and output terminals of the feedback sub-circuit. Since this gain switching sub-circuit is connected between the second terminal of the fourth capacitor and the ground terminal, and between the second terminal of the fourth capacitor and the output terminal of the amplification sub-circuit, switching its connection state can change the way the fourth capacitor is connected in the circuit, thereby flexibly adjusting the equivalent capacitance of the feedback sub-circuit and thus regulating the exposure current gain, enabling the pixel circuit to adapt to different exposure conditions.

[0007] In some embodiments, the gain switching subcircuit includes a first gain switching switch and a second gain switching switch; a first terminal of the first gain switching switch is connected to a second terminal of a fourth capacitor, and a second terminal of the first gain switching switch is connected to a ground terminal; a first terminal of the second gain switching switch is connected to a second terminal of the fourth capacitor, and a second terminal of the second gain switching switch is connected to the output terminal of the amplification subcircuit. The gain switching subcircuit is configured such that: when the first gain switching switch is closed and the second gain switching switch is open, the pixel circuit operates in a first gain mode; when the second gain switching switch is closed and the first gain switching switch is open, the pixel circuit operates in a second gain mode; wherein, in the first gain mode, the gain of the amplification subcircuit on the exposure current is greater than the gain of the amplification subcircuit on the exposure current in the second gain mode.

[0008] In this embodiment, by setting a first gain switching switch and a second gain switching switch, and controlling their on / off combinations, the pixel circuit can conveniently switch between a first gain mode (hereinafter referred to as a high gain mode) and a second gain mode (hereinafter referred to as a low gain mode). When the first gain switching switch is closed and the second gain switching switch is open, the second terminal of the fourth capacitor is grounded, and the equivalent capacitance in the feedback path is small, thus enabling the circuit to operate in a high gain mode, suitable for signal reading in low-light environments. When the second gain switching switch is closed and the first gain switching switch is open, the second terminal of the fourth capacitor is connected to the output terminal of the amplifier sub-circuit, causing the fourth capacitor to be connected to the feedback loop, increasing the equivalent capacitance of the feedback loop, thereby reducing the gain, suitable for signal reading in strong light environments.

[0009] In some embodiments, in a first gain mode, the voltage provided by the first voltage terminal is a ground voltage before the photodiode is exposed, and increases from the ground voltage to a first preset reference voltage during the exposure of the photodiode; in a second gain mode, the voltage provided by the first voltage terminal is a ground voltage before the photodiode is exposed, and increases from the ground voltage to a second preset reference voltage during the exposure of the photodiode; wherein the first preset reference voltage is less than the second preset reference voltage.

[0010] In this embodiment, the performance of the pixel circuit is further optimized by applying different voltage control strategies to the first voltage terminal under different gain modes. In the first gain mode, the first voltage terminal is increased from ground voltage to a smaller first preset reference voltage during exposure. This voltage jump can achieve a common-mode reduction effect, thereby effectively expanding the dynamic range of the pixel and improving its adaptability to low light without changing the gain of the high-gain mode itself. In the second gain mode, the first voltage terminal is increased from ground voltage to a larger second preset reference voltage during exposure, using the same common-mode reduction mechanism to adapt to the dynamic range requirements in the low-gain state.

[0011] In some embodiments, the capacitance of the first capacitor is a first capacitance value, the capacitance of the second capacitor is a second capacitance value, the capacitance of the third capacitor is a third capacitance value, and the capacitance of the fourth capacitor is a fourth capacitance value; wherein any one of the first capacitance value, the second capacitance value, and the third capacitance value is less than the fourth capacitance value.

[0012] In this embodiment, by configuring the capacitance values ​​of the first, second, and third capacitors to be smaller than that of the fourth capacitor, it is possible to reduce the gain by utilizing the large capacitance of the fourth capacitor to change the equivalent feedback capacitance when it is connected to the feedback loop, while ensuring that the feedback sub-circuit has basic integration and clamping functions. This capacitance differentiation design can achieve a large range of gain variation within a limited chip area, improving the pixel circuit's adaptability to changes in illumination.

[0013] In some embodiments, the first capacitance value, the second capacitance value, and the third capacitance value are the same preset capacitance value, and the fourth capacitance value is N times the preset capacitance value, where N is greater than or equal to 2.

[0014] In this embodiment, the first, second, and third capacitance values ​​are set to the same preset value, and the fourth capacitance value is set to N times this preset value (N≥2). This not only simplifies the capacitor design and manufacturing process and improves circuit consistency, but also ensures that the gain change factor is precisely determined by the connection method and capacitance ratio of the fourth capacitor when switching between high-gain and low-gain modes. This design makes the gain switching accuracy controllable and facilitates flexible adjustment of the dynamic range according to actual application requirements.

[0015] In some embodiments, the pixel circuit further includes: a first switch coupled between the photodiode and the output terminal of the amplifier sub-circuit; the first switch is configured to be in a closed state between a first time point and a second time point to reset the voltage at the output terminal of the amplifier sub-circuit and the voltage of the photodiode, the first time point being the start time of operation of the pixel circuit, and the second time point being after the first time point.

[0016] In this embodiment, by introducing a first switch and closing it between the first and second time points, a rapid reset of the photodiode node and the output of the amplification sub-circuit can be achieved, effectively clearing the residual charge from the previous frame and preparing for a new exposure cycle. This reset mechanism ensures that the pixel circuit has a defined initial state at the start of each operation, thereby improving the accuracy and repeatability of signal readout.

[0017] In some embodiments, the pixel circuit further includes: a reset sampling capacitor, a first terminal of which is coupled to the output of an amplification sub-circuit, and a second terminal of which is coupled to a ground terminal; a second switch coupled between the first terminal of the reset sampling capacitor and the output of the amplification sub-circuit; the second switch is configured to: be closed between a first time point and a third time point to reset the reset sampling capacitor; and be open at the third time point to allow the reset sampling capacitor to store a reset voltage; an exposure sampling capacitor, a first terminal of which is coupled to the output of the amplification sub-circuit, and a second terminal of which is coupled to a ground terminal; and a third switch coupled between the first terminal of the exposure sampling capacitor and the output of the amplification sub-circuit; the third switch is configured to: be closed between a first time point and a fourth time point to reset the exposure sampling capacitor; and be open at the fourth time point to allow the exposure sampling capacitor to store an exposure voltage; wherein the third time point is after the second time point and before the photosensitive diode begins exposure; and the fourth time point is after the photosensitive diode ends exposure.

[0018] In this embodiment, by setting a reset sampling capacitor, an exposure sampling capacitor, and their corresponding second and third switches, time-division sampling and storage of the reset voltage and exposure voltage are achieved. The second switch is opened at the third time point, allowing the reset sampling capacitor to store the reset voltage before the start of exposure; the third switch is opened at the fourth time point, allowing the exposure sampling capacitor to store the exposure voltage after the end of exposure. This correlated dual-sampling structure can effectively eliminate fixed-mode noise and reset noise in the amplification sub-circuit, improving the output image quality of the image sensor.

[0019] In some embodiments, in a first gain mode, after a fourth time point, the voltage provided by the first voltage terminal drops from a first preset reference voltage to ground voltage; in a second gain mode, after a fourth time point, the voltage provided by the first voltage terminal drops from a second preset reference voltage to ground voltage; wherein the first preset reference voltage is less than the second preset reference voltage.

[0020] In this embodiment, in the first gain mode, the voltage at the first voltage terminal is reduced from the first preset reference voltage to the ground voltage after the fourth time point; in the second gain mode, the voltage at the first voltage terminal is reduced from the second preset reference voltage to the ground voltage after the fourth time point. This operation can utilize the voltage change coupled through the third capacitor after exposure to perform additional charge adjustment or reset assistance on the output terminal or related nodes of the amplification sub-circuit, thereby preparing a stable starting state for the acquisition of the next frame image, effectively improving the reset efficiency and signal consistency of the pixel circuit during continuous operation.

[0021] In some embodiments, the pixel circuit further includes: a fourth switch, a first terminal of which is connected to a first terminal of a reset sampling capacitor, and a second terminal of which is connected to a first terminal of an exposure sampling capacitor; the fourth switch is configured to: be in an open state when the row selection signal is enabled and the column selection signal is disabled, so that the first terminal of the reset sampling capacitor is not connected to the first terminal of the exposure sampling capacitor; and be in a closed state when the row selection signal is enabled and the column selection signal is enabled, so that the first terminal of the reset sampling capacitor is connected to the first terminal of the exposure sampling capacitor; a first readout sub-circuit coupled between the first terminal of the reset sampling capacitor and the negative output terminal; the first readout sub-circuit configured to: output a first negative output voltage based on a reset voltage when the fourth switch is in the open state; and output a second negative output voltage based on the reset voltage and the exposure voltage when the fourth switch is in the closed state; a second readout sub-circuit coupled between the first terminal of the exposure sampling capacitor and the positive output terminal; the second readout sub-circuit configured to: output a first positive output voltage based on the exposure voltage when the fourth switch is in the open state; and output a second positive output voltage based on the reset voltage and the exposure voltage when the fourth switch is in the closed state.

[0022] In this embodiment, by setting a fourth switch and a first and a second readout sub-circuit, flexible output of pixel signals under different row and column selection states is achieved. When the row selection signal is enabled but the column selection signal is disabled, the fourth switch is open, and the readout sub-circuit outputs the reset voltage and exposure voltage separately, which can be used for independent signal monitoring or processing. When both the row selection signal and the column selection signal are enabled, the fourth switch is closed, connecting the first terminal of the reset sampling capacitor and the exposure sampling capacitor. At this time, the readout sub-circuit performs differential output based on the difference between the reset voltage and the exposure voltage (i.e., the effective image signal), which can effectively suppress common-mode noise, improve the anti-interference capability of signal transmission, and support column-level or chip-level differential signal processing architecture.

[0023] In a second aspect, the present invention also provides an image sensor, comprising: a pixel array. At least one pixel in the pixel array includes a photodiode and the pixel circuit described in the first aspect.

[0024] The beneficial effects of the aforementioned image sensor can be referenced in the beneficial effects of the pixel circuit provided in the first aspect above, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This invention provides a schematic diagram of the structure of a 3T pixel circuit;

[0027] Figure 2 A schematic diagram of an improved pixel circuit provided by the present invention;

[0028] Figure 3 A schematic diagram of the working timing of an improved pixel circuit provided by the present invention;

[0029] Figure 4 A schematic diagram of a pixel circuit provided by the present invention;

[0030] Figure 5 A schematic diagram of a pixel circuit provided by the present invention;

[0031] Figure 6 A schematic diagram of the equivalent circuit of a pixel circuit in the first gain mode provided by the present invention;

[0032] Figure 7 A schematic diagram of the equivalent circuit of a pixel circuit in the second gain mode provided by the present invention;

[0033] Figure 8 A timing diagram of a pixel circuit operating in different gain modes is provided by the present invention;

[0034] Figure 9 This is a schematic diagram of the composition of an image sensor provided by the present invention.

[0035] Figure label:

[0036] PD1: First photodiode, Cpd1: First parasitic capacitance, MN11: First N-type transistor, MN12: Second N-type transistor, MN13: Third N-type transistor.

[0037] PD2: Second photodiode, Cpd2: Second parasitic capacitance, Cf1: Amplifier feedback capacitor, 201: Amplifier reset switch, 202: Reset sampling switch, 203: Exposure sampling switch, 204: First sampling capacitor, 205: Second sampling capacitor, 206: Sampling connection switch, 207: Amplification module, 208: First output sub-circuit, 209: Second output sub-circuit, MP21: First first P-type transistor, MP22: Second first P-type transistor, MN21: First second N-type transistor, MN22: Second second N-type transistor, MN23: Third second N-type transistor, MN24: Fourth second N-type transistor, MN25: Fifth second N-type transistor, MN26: Sixth second N-type transistor.

[0038] 401: Feedback sub-circuit, 402: Amplification sub-circuit, 403: Gain switching sub-circuit.

[0039] PD: Photodiode, Cpd3: Third parasitic capacitance, 501: First switch, 502: Second switch, 503: Third switch, 504: Reset sampling capacitor, 505: Exposure sampling capacitor, 506: Fourth switch, 507: First readout sub-circuit, 508: Second readout sub-circuit, C1: First capacitor, C2: Second capacitor, C3: Third capacitor, C4: Fourth capacitor, 4031: First gain switching switch, 4032: Second gain switching switch, MP51: First second P-type transistor, MP52: Second second P-type transistor, MN31: First third N-type transistor, MN32: Second third N-type transistor, MN33: Third third N-type transistor, MN34: Fourth third N-type transistor, MN35: Fifth third N-type transistor, MN36: Sixth third N-type transistor.

[0040] 601: First terminal, 602: Second terminal, C12: First equivalent capacitor, C13: Second equivalent capacitor, C23: Third equivalent capacitor, C14: Fourth equivalent capacitor, C24: Fifth equivalent capacitor, C34: Sixth equivalent capacitor.

[0041] 701: First connection terminal, 702: Second connection terminal, CL1: First low-gain equivalent capacitor, CL2: Second low-gain equivalent capacitor, CL3: Third low-gain equivalent capacitor.

[0042] 900: Image sensor, 901: Pixel array, 902: Pixel circuit. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] It should be noted that in the embodiments of the present invention, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0045] In embodiments of the present invention, the terms "first," "second," "third," "fourth," "fifth," and "sixth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," "third," "fourth," "fifth," and "sixth" may explicitly or implicitly include one or more of that feature.

[0046] In embodiments of the invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. For "A and / or B," three combinations are included: A only, B only, and a combination of A and B.

[0047] Image sensors are widely used in photography, video surveillance, medical imaging, industrial inspection, and other fields. An image sensor consists of multiple pixel circuits arranged in an array. Each pixel circuit converts incident light signals into electrical signals through photoelectric conversion to generate image information. Depending on the pixel structure, pixel circuits can be divided into various types, including but not limited to 3T pixel circuits and 4T pixel circuits. A 3T pixel circuit refers to a pixel circuit where each pixel consists of three transistors. It has a simple structure and a high fill factor, but due to the inability to achieve correlated double sampling, it suffers from high reset noise, making it suitable for low-cost applications where noise requirements are not high. A 4T pixel circuit adds one more transistor to the 3T pixel circuit.

[0048] like Figure 1 As shown, the 3T pixel circuit includes: a first photodiode (PD) PD1, a first first N-type transistor MN11, a second first N-type transistor MN12, a third first N-type transistor MN13, and a first parasitic capacitor Cpd1.

[0049] In this configuration, the anode of the first photodiode PD1 is coupled to ground, the cathode of the first photodiode PD1 is coupled to the first terminal of the first parasitic capacitor Cpd1, and the second terminal of the first parasitic capacitor Cpd1 is coupled to ground. The cathode of the first photodiode PD1 is also coupled to the source of the first first N-type transistor MN11, and the cathode of the first photodiode PD1 is also coupled to the gate of the second first N-type transistor MN12. Furthermore, the first terminal of the first parasitic capacitor Cpd1 is also coupled to the source of the first first N-type transistor MN11, and the first terminal of the first parasitic capacitor Cpd1 is also coupled to the gate of the second first N-type transistor MN12. The gate of the first first N-type transistor MN11 is used to receive a reset signal, and the drain of the first first N-type transistor MN11 is coupled to a power supply terminal. The drain of the second first N-type transistor MN12 is coupled to a power supply terminal, and the source of the second first N-type transistor MN12 is coupled to the drain of the third first N-type transistor MN13. The gate of the third first N-type transistor MN13 is used to receive the row selection signal, and the source of the third first N-type transistor MN13 is the output terminal of the pixel circuit.

[0050] exist Figure 1 In the 3T pixel circuit shown, the exposure signal is obtained by discharging the first parasitic capacitance Cpd1 corresponding to the first photodiode PD1. The capacitance value of the first parasitic capacitance Cpd1 is determined by the area and doping of the first photodiode PD1. To ensure photosensitivity, the capacitance value is usually large, reaching more than 50 fF, resulting in a long exposure time, which is not conducive to achieving high-speed image acquisition and high frame rate imaging. At the same time, in large array image sensors, there are process deviations and consistency differences in the first parasitic capacitance Cpd1 between pixels, which causes gain mismatch between pixels of the image sensor and affects the imaging uniformity. In addition, the signal gain of this pixel circuit is determined based on the first parasitic capacitance Cpd1 and cannot be flexibly adjusted according to the light intensity and noise environment, making it difficult to meet the imaging requirements of high sensitivity and low noise, thus limiting the application scenarios.

[0051] In order to solve such Figure 1 To address the problem of excessively long exposure time in the 3T pixel circuit shown, this invention provides a possible implementation method, such as... Figure 2As shown, the improved pixel circuit includes: a second photodiode PD2, a second parasitic capacitance Cpd2, an amplifier feedback capacitor Cf1, an amplifier reset switch 201, a reset sampling switch 202, an exposure sampling switch 203, a first sampling capacitor 204, a second sampling capacitor 205, a sampling connection switch 206, an amplification module 207, a first output sub-circuit 208, and a second output sub-circuit 209.

[0052] The anode of the second photodiode PD2 is coupled to the ground terminal, the cathode of the second photodiode PD2 is coupled to the first terminal of the second parasitic capacitor Cpd2, and the second terminal of the second parasitic capacitor Cpd2 is coupled to the ground terminal; the cathode of the second photodiode PD2 is also coupled to the input terminal of the amplifier module 207 and the first terminal of the amplifier feedback capacitor Cf1.

[0053] The second end of the amplifier feedback capacitor Cf1 is coupled to the output of the amplifier module 207.

[0054] The amplifier reset switch 201 is coupled between the cathode of the second photodiode PD2 and the output terminal of the amplifier module 207. It is used to turn on during the reset phase and clamp the cathode potential of the second photodiode PD2 to the preset reset potential.

[0055] A reset sampling switch 202 is coupled between the output terminal of the amplification module 207 and the first terminal of the first sampling capacitor 204, and the second terminal of the first sampling capacitor 204 is coupled to the ground terminal. The reset sampling switch 202 is used to turn on during the reset phase, so that the first sampling capacitor 204 stores the reset voltage. The reset voltage is the voltage output by the amplification module 207 after the reset phase and voltage stabilization. This reset voltage is determined by the output potential of the amplification module 207 after the pixel reset operation is completed, and is used to characterize the output reference level in the pixel reset state.

[0056] Exposure sampling switch 203 is coupled between the output terminal of amplification module 207 and the first terminal of second sampling capacitor 205, and the second terminal of second sampling capacitor 205 is coupled to ground. Exposure sampling switch 203 is used to conduct during the reset and exposure phases, so that second sampling capacitor 205 stores exposure voltage. Exposure voltage refers to the voltage output by amplification module 207 after the exposure phase ends and the voltage stabilizes. This exposure voltage includes the light signal component generated by the second photodiode PD2 after exposure and is used to characterize the output level of the pixel after exposure.

[0057] The sampling connection switch 206 is coupled between the first end of the first sampling capacitor 204 and the first end of the second sampling capacitor 205. The control end of the sampling connection switch 206 is coupled to the AND logic output of the row selection signal and the column selection signal. It is used to turn on when both row and column selection are valid, so as to connect the reset sampling node and the exposure sampling node to realize differential signal readout.

[0058] The amplification module 207 can be a common-source, common-gate amplifier, comprising: a first first P-type transistor MP21, a second first P-type transistor MP22, a first second N-type transistor MN21, and a second second N-type transistor MN22. The source of the first first P-type transistor MP21 is coupled to a power supply terminal, and its gate is used to receive a bias signal. The source of the second first P-type transistor MP22 is coupled to the drain of the first first P-type transistor MP21, and its gate is used to receive a bias signal. The drain of the first second N-type transistor MN21 is coupled to the drain of the second first P-type transistor MP22, and its gate is used to receive a bias signal. The drain of the second N-type transistor MN22 is coupled to the source of the first N-type transistor MN21, the gate of the second N-type transistor MN22 is coupled to the cathode of the second photodiode PD2 and the first terminal of the second parasitic capacitance Cpd2, and the source of the second N-type transistor MN22 is coupled to the ground terminal.

[0059] The first output sub-circuit 208 includes a third second N-type transistor MN23 and a fourth second N-type transistor MN24. The drain of the third second N-type transistor MN23 is coupled to the power supply terminal, the gate of the third second N-type transistor MN23 is coupled to the first terminal of the first sampling capacitor 204, the source of the third second N-type transistor MN23 is coupled to the drain of the fourth second N-type transistor MN24, the gate of the fourth second N-type transistor MN24 is used to receive the row selection signal, and the source of the fourth second N-type transistor MN24 is coupled to the negative output terminal.

[0060] The second output sub-circuit 209 includes a fifth second N-type transistor MN25 and a sixth second N-type transistor MN26. The drain of the fifth second N-type transistor MN25 is coupled to the power supply terminal, the gate of the fifth second N-type transistor MN25 is coupled to the first terminal of the second sampling capacitor 205, the source of the fifth second N-type transistor MN25 is coupled to the drain of the sixth second N-type transistor MN26, the gate of the sixth second N-type transistor MN26 is used to receive the row selection signal, and the source of the sixth second N-type transistor MN26 is coupled to the positive output terminal.

[0061] It should be understood that, Figure 2The improved pixel circuit shown introduces a multi-stage switching control structure between the photosensitive area where the photodiode (i.e., the second photodiode PD2) is located and the output circuit based on the first output sub-circuit 208 and the second output sub-circuit 209. This structure consists of an amplifier feedback capacitor Cf1, a first sampling capacitor 204, a second sampling capacitor 205, an amplifier reset switch 201, a reset sampling switch 202, an exposure sampling switch 203, and a sampling connection switch 206. The core improvement lies in replacing the charging and discharging process of the amplifier feedback capacitor Cf1 with the traditional method. Figure 1 The first parasitic capacitance Cpd1 in the pixel circuit shown (i.e. Figure 2 The improved pixel circuit shown employs a direct charging and discharging exposure method for the second parasitic capacitor Cpd2. Specifically, the second parasitic capacitor Cpd2 is the inherent parasitic capacitance of the second photodiode PD2, and its capacitance value is determined by the inherent parameters of the second photodiode PD2, such as the photosensitive area and doping concentration. To ensure that the photosensitive performance cannot be arbitrarily reduced, the amplifier feedback capacitor Cf1 is an externally added capacitor that is not limited by the inherent parameters of the photosensitive device. Its capacitance value can be designed to be much smaller than that of the second parasitic capacitor Cpd2 (for example, it can be designed to be a few fF to a dozen fF) according to the requirements of high-speed imaging. This significantly reduces the time required for the photosensitive current to charge and discharge, effectively shortening the exposure time of the pixel circuit.

[0062] based on Figure 2 The improved pixel circuit shown is as follows: Figure 3 As shown, give Figure 2 The specific timing sequence of the improved pixel circuit is as follows: From time t1 to t2, the amplifier reset switch 201, reset sampling switch 202, and exposure sampling switch 203 are all closed, putting the amplification module 207 in a reset state. At time t2, the amplifier reset switch 201 is opened, ending the reset process of the amplification module 207. After the output of the amplification module 207 stabilizes, at time t3, the reset sampling switch 202 is opened, saving the reset voltage of the amplification module 207 to the first sampling capacitor 204. After time t3, the light-emitting diode (LED) is lit to begin exposure. The second photodiode PD2 generates an exposure current and charges and discharges the amplifier feedback capacitor Cf1. After a certain time, the LED ends the exposure. Between the end of exposure and time t4, after the output of the amplification module 207 stabilizes, the exposure sampling switch 203 is opened, saving the voltage signal after exposure (i.e., the exposure voltage) to the second sampling capacitor 205.

[0063] Based on the above description, after all pixel units in the pixel array of the image sensor synchronously complete the above reset, sampling and exposure operations, the reset voltage and exposure voltage of each pixel will be stored in the first sampling capacitor 204 and the second sampling capacitor 205 respectively. Then, the two voltage signals can be read out sequentially or synchronously using the corresponding readout method and differential operation can be performed to obtain the actual exposure value, waiting for subsequent readout circuits to read. During reading, the row selection switches in the first output sub-circuit 208 and the second output sub-circuit 209 are first turned on to read out the reset voltage and exposure voltage respectively. Then, the sampling connection switch 206 is turned on to balance the first sampling capacitor 204 and the second sampling capacitor 205. The balanced reset voltage and the balanced exposure voltage are read out. Based on the voltage conditions read out twice, the final actual exposure result can be obtained.

[0064] However, Figure 2 The improved pixel circuit shown still has certain limitations:

[0065] On the one hand, to achieve sufficiently high pixel gain, the amplifier feedback capacitor Cf1 needs to be designed to be small enough. However, due to the large array layout of image sensors, the distance between pixel units at different positions in the array is relatively large. Influenced by factors such as chip manufacturing process deviations, wiring length differences, and uneven ambient temperature distribution, the actual capacitance value of the amplifier feedback capacitor Cf1 within different pixel units will have a certain deviation. This capacitance difference directly translates into gain mismatch between pixels. Furthermore, the smaller the designed capacitance value of the amplifier feedback capacitor Cf1, the greater the impact of its small capacitance deviation on pixel gain, leading to a greater degree of gain mismatch between pixels, ultimately affecting the imaging uniformity of the image sensor and causing problems such as fixed-pattern noise. Therefore, Figure 2 The improved pixel structure is difficult to apply in large-array, high-sensitivity image sensors.

[0066] On the other hand, the smaller the amplifier feedback capacitor Cf1, the greater the pixel gain, but the greater the noise in the final exposure result. When the noise in the image sensor input signal is high, it is necessary to reduce the pixel gain and appropriately increase the exposure time to improve the final image quality. Figure 1 3T pixel circuit or Figure 2 The improved pixel circuits still cannot achieve free switching between low noise and high sensitivity, making it difficult to adapt to the diverse application scenarios.

[0067] Based on this, embodiments of the present invention provide a pixel circuit, which includes a feedback sub-circuit, an amplification sub-circuit, and a gain switching sub-circuit. The feedback sub-circuit receives and stores the exposure current output by the photodiode; the amplification sub-circuit amplifies the exposure current and clamps the voltage of the photodiode at a preset potential via the feedback sub-circuit; and the gain switching sub-circuit controls the change in the equivalent capacitance of the feedback sub-circuit to adjust the gain of the pixel circuit to the exposure current. By combining a multi-capacitor-based feedback sub-circuit with the gain switching sub-circuit, the present invention allows for flexible adjustment of the equivalent capacitance of the feedback loop, enabling switchable adjustment of the pixel circuit gain. This ensures high sensitivity and fast exposure performance while suppressing gain mismatch and fixed-mode noise, allowing the pixel circuit to simultaneously meet the application requirements of high frame rates, low noise, and large-array image sensors.

[0068] The pixel circuit provided in the embodiments of the present invention will be described below with reference to the accompanying drawings. The pixel circuit provided in the embodiments of the present invention is applicable to pixel arrays within image sensors and can be used to realize the conversion of optical signals to electrical signals, the storage and amplification of exposure current, and the flexible adjustment of pixel gain, thereby improving the imaging quality, frame rate performance, and scene adaptability of the image sensor. In the embodiments of the present invention, the image sensor can be applied to various electronic devices requiring image acquisition, such as high-speed imaging equipment, high-sensitivity imaging scenarios, and large-array image acquisition devices. Specifically, it can be applied to industrial cameras, security monitoring equipment, medical imaging instruments, consumer electronic terminals, etc., and the present invention does not impose specific limitations thereon.

[0069] In this embodiment of the invention, the pixel circuit provided by the invention includes a feedback sub-circuit 401, an amplification sub-circuit 402, and a gain switching sub-circuit 403, such as... Figure 4 As shown. Among them, Figure 4 For specific embodiments of other structures, please refer to Figure 5 The specific wording is not elaborated here.

[0070] In this embodiment of the invention, the input terminal of the feedback sub-circuit 401 is adapted to be connected to the photodiode PD, and the feedback sub-circuit 401 is configured to receive and store the exposure current output by the photodiode PD. Figure 4 As shown, the feedback sub-circuit 401 includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The first end of the first capacitor C1 is adapted to be connected to the photodiode PD. The second ends of the first capacitor C1, the first ends of the second capacitor C2, the first ends of the third capacitor C3, and the first ends of the fourth capacitor C4 are connected together. The second end of the second capacitor C2 is connected to the output terminal of the amplifier sub-circuit 402. The second end of the third capacitor C3 is connected to the first voltage terminal. The second end of the fourth capacitor C4 is connected to the ground terminal.

[0071] Understandably, the feedback sub-circuit 401, through the star-connected structure of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, can both receive and store the exposure current output by the photodiode PD, and work with the amplification sub-circuit 402 to precisely clamp the potential of the photodiode PD at a preset voltage, thereby achieving rapid charging and discharging of the photocurrent to shorten the exposure time. At the same time, this multi-capacitor combination provides a physical basis for subsequent gain adjustment. The equivalent feedback capacitance can be flexibly adjusted by switching the connection mode of the fourth capacitor C4, which not only ensures the advantages of high sensitivity and high-speed exposure, but also improves the gain mismatch problem of large array image sensors and enhances imaging uniformity.

[0072] In this embodiment of the invention, the gain switching sub-circuit 403 is connected between the second end of the fourth capacitor C4 and the ground end, and between the second end of the fourth capacitor C4 and the output end of the amplification sub-circuit 402. The gain switching sub-circuit 403 is configured to control the capacitance value between the input and output ends of the feedback sub-circuit 401 to change the gain of the feedback sub-circuit 401 on the exposure current.

[0073] It is understood that, in this embodiment of the invention, the control of the connection method of the fourth capacitor C4 by the gain switching sub-circuit 403 enables flexible adjustment of the equivalent capacitance value of the feedback sub-circuit 401, thereby changing the gain of the pixel circuit to the exposure current. This method allows the pixel circuit to dynamically adjust its operating mode according to light intensity and noise environment: obtaining high gain under low light conditions to achieve high-sensitivity imaging, and reducing gain under strong light conditions to avoid saturation and suppress noise. This adjustable gain characteristic improves the adaptability and imaging quality of the pixel circuit in different application scenarios.

[0074] A schematic diagram of a pixel circuit provided by the present invention.

[0075] like Figure 5 The diagram shown is a schematic diagram of a pixel circuit provided by the present invention. The pixel circuit includes: a first switch 501, a second switch 502, a third switch 503, a reset sampling capacitor 504, an exposure sampling capacitor 505, a fourth switch 506, a first readout sub-circuit 507, a second readout sub-circuit 508, a feedback sub-circuit 401, an amplification sub-circuit 402, and a gain switching sub-circuit 403.

[0076] It should be noted that the reset sampling capacitor 504 can be Figure 2 The first sampling capacitor 204 and the exposure sampling capacitor 505 can be... Figure 2 The second sampling capacitor 205 and the amplifier sub-circuit 402 can be... Figure 2 The amplification module 207 and the first readout sub-circuit 507 can be... Figure 2The first output sub-circuit 208 and the second readout sub-circuit 508 can be... Figure 2 The second output sub-circuit 209 in the embodiment is only a partial embodiment, and this application does not impose specific limitations on it.

[0077] The image sensor includes a pixel array, where at least one pixel comprises a photodiode (PD) and a... Figure 5 The pixel circuit shown is as follows. The anode of the photodiode PD is grounded, and the cathode of the photodiode PD is connected to the first terminal of the third parasitic capacitor Cpd3, the first terminal of the first capacitor C1 in the feedback sub-circuit 401, and the input terminal of the amplification sub-circuit 402, respectively. The second terminal of the third parasitic capacitor Cpd3 is grounded. The photodiode PD is used to convert the light signal into exposure current, and the third parasitic capacitor Cpd3, as the inherent parasitic capacitance of the photodiode PD, is used to temporarily store the node charge.

[0078] The embodiments of the present invention enable the photodiode (PD) to convert optical signals into electrical signals and output them to the subsequent feedback sub-circuit 401 and amplification sub-circuit 402, providing the necessary photoelectric conversion basis for the present invention to achieve gain adjustment through equivalent capacitance. The circuit structure is simple and conducive to improving the integration of pixel circuits.

[0079] In some embodiments, such as Figure 5 As shown, the gain switching sub-circuit 403 includes a first gain switching switch 4031 and a second gain switching switch 4032; the first end of the first gain switching switch 4031 is connected to the second end of the fourth capacitor C4, and the second end of the first gain switching switch 4031 is connected to the ground terminal; the first end of the second gain switching switch 4032 is connected to the second end of the fourth capacitor C4, and the second end of the second gain switching switch 4032 is connected to the output terminal of the amplification sub-circuit 402.

[0080] The gain switching sub-circuit 403 is configured such that: when the first gain switching switch 4031 is closed and the second gain switching switch 4032 is open, the pixel circuit operates in the first gain mode; when the second gain switching switch 4032 is closed and the first gain switching switch 4031 is open, the pixel circuit operates in the second gain mode; wherein, in the first gain mode, the gain of the amplification sub-circuit 402 on the exposure current is greater than the gain of the amplification sub-circuit 402 on the exposure current in the second gain mode.

[0081] In this embodiment of the invention, the pixel circuit achieves convenient switching between high-gain and low-gain modes through the coordinated control of the first gain switching switch 4031 and the second gain switching switch 4032. When the first gain switching switch 4031 is closed and the second gain switching switch 4032 is open, the fourth capacitor C4 is connected to the ground terminal, resulting in a small equivalent feedback capacitance. The pixel circuit operates in high-gain mode, suitable for high-sensitivity imaging in low-light environments. When the second gain switching switch 4032 is closed and the first gain switching switch 4031 is open, the fourth capacitor C4 is connected to the output terminal of the amplification sub-circuit 402, forming a larger equivalent feedback capacitance in parallel with the second capacitor C2. The pixel circuit operates in low-gain mode, suitable for anti-saturation imaging in strong light environments. This switching control method has a simple structure and reliable switching, enabling the pixel circuit to flexibly adjust its operating state according to lighting conditions, thus balancing the imaging requirements of high sensitivity and low noise.

[0082] exist Figure 5 Based on this, as one implementation, when the first gain switching switch 4031 is closed and the second gain switching switch 4032 is open, and the pixel circuit operates in the first gain mode, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 in the feedback sub-circuit 401 change from a star connection to a terminal connection to achieve a transformation of the equivalent capacitance between the input and output terminals of the feedback sub-circuit 401. Specifically, as follows... Figure 6 As shown. The first terminal 601 is connected to the photodiode PD, and the second terminal 602 is connected to the output terminal of the amplifier sub-circuit 402. The first equivalent capacitor C12 is the equivalent capacitor between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2, corresponding to the coupling effect between the first capacitor C1 and the second capacitor C2 in a star connection; the second equivalent capacitor C13 is the equivalent capacitor between the second terminal of the first capacitor C1 and the first terminal of the third capacitor C3, corresponding to the coupling effect between the first capacitor C1 and the third capacitor C3 in a star connection; the third equivalent capacitor C23 is the equivalent capacitor between the first terminal of the second capacitor C2 and the first terminal of the third capacitor C3, corresponding to the coupling effect between the second capacitor C2 and the third capacitor C3 in a star connection. The fourth equivalent capacitor C14 is the equivalent capacitor between the second terminal of the first capacitor C1 and the first terminal of the fourth capacitor C4, corresponding to the coupling effect between the first capacitor C1 and the fourth capacitor C4 in a star connection; the fifth equivalent capacitor C24 is the equivalent capacitor between the first terminal of the second capacitor C2 and the first terminal of the fourth capacitor C4, corresponding to the coupling effect between the second capacitor C2 and the fourth capacitor C4 in a star connection; the sixth equivalent capacitor C34 is the equivalent capacitor between the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4, corresponding to the coupling effect between the third capacitor C3 and the fourth capacitor C4 in a star connection.

[0083] In this embodiment of the invention, the equivalent capacitance distribution of the feedback sub-circuit 401 in the first gain mode can be intuitively quantified through the equivalent transformation from star to terminal, and the contribution of each capacitor to the feedback gain can be accurately analyzed. This provides theoretical support for the optimization of circuit parameters in the high gain mode, ensuring that the pixel circuit has stable current gain and fast response capability during high-sensitivity imaging. At the same time, it lays the foundation for subsequent comparison of equivalent capacitance with the low gain mode, improving the accuracy and reliability of gain adjustment in both modes.

[0084] exist Figure 5 Based on this, as another implementation, when the first terminal of the second gain switching switch 4032 is connected to the second terminal of the fourth capacitor C4, and the second terminal of the second gain switching switch 4032 is connected to the output terminal of the amplification sub-circuit 402, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 in the feedback sub-circuit 401 change from a star connection to a terminal connection, thereby transforming the equivalent capacitance between the input and output terminals of the feedback sub-circuit 401. Specifically, as follows... Figure 7 As shown. The first connection terminal 701 is connected to the photodiode PD, and the second connection terminal 702 is connected to the output terminal of the amplifier sub-circuit 402. The first low-gain equivalent capacitor CL1 is the equivalent capacitor between the second terminal of the first capacitor C1 and the first terminal of the parallel circuit of the second capacitor C2 and the fourth capacitor C4, corresponding to the coupling effect of the parallel branch of the first capacitor C1 and (second capacitor C2 + fourth capacitor C4) in the star connection; the second low-gain equivalent capacitor CL2 is the equivalent capacitor between the second terminal of the first capacitor C1 and the first terminal of the third capacitor C3, corresponding to the coupling effect of the first capacitor C1 and the third capacitor C3 in the star connection; the third low-gain equivalent capacitor CL3 is the equivalent capacitor between the first terminals of the second capacitor C2 and the fourth capacitor C4 and the first terminal of the third capacitor C3, corresponding to the coupling effect of the parallel branch of (second capacitor C2 + fourth capacitor C4) and the third capacitor C3 in the star connection.

[0085] This invention, through a star-to-terminal equivalent transformation, clearly presents the distribution of the equivalent capacitors in the feedback sub-circuit 401 in the second gain mode. In this mode, since the second terminal of the fourth capacitor C4 is connected to the output terminal of the amplification sub-circuit 402 via the second gain switching switch 4032, the fourth capacitor C4 is connected in parallel with the second capacitor C2, thereby increasing the equivalent feedback capacitance between the input and output terminals of the feedback sub-circuit 401. This achieves the low-gain characteristics of the pixel circuit in the second gain mode, suitable for anti-saturation and low-noise imaging requirements in strong light environments. This equivalent analysis provides a clear theoretical basis for the gain calculation of the pixel circuit in the second gain mode, facilitating precise control of the equivalent feedback capacitance value.

[0086] In some embodiments, the capacitance of the first capacitor C1 is a first capacitance value, the capacitance of the second capacitor C2 is a second capacitance value, the capacitance of the third capacitor C3 is a third capacitance value, and the capacitance of the fourth capacitor C4 is a fourth capacitance value; wherein any one of the first capacitance value, the second capacitance value, and the third capacitance value is less than the fourth capacitance value.

[0087] It is understandable that setting the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 to be smaller than the capacitance value of the fourth capacitor C4 can ensure that the feedback sub-circuit 401 has a sufficiently small basic equivalent capacitance to achieve high gain and high-speed exposure. At the same time, the larger capacitance value of the fourth capacitor C4 is used as the main carrier for gain adjustment, avoiding the aggravation of gain mismatch caused by factors such as process deviation and wiring differences due to excessively small capacitance values. This balances high sensitivity and the uniformity of large array imaging, and improves the overall image quality performance of the image sensor.

[0088] As one possible implementation, when the first gain switching switch 4031 is closed and the second gain switching switch 4032 is open, the pixel circuit operates in the first gain mode, based on... Figure 6 Based on the equivalent relationship shown, determine the capacitance values ​​of each equivalent capacitor. The capacitance value of the first capacitor C1 is... The capacitance of the second capacitor C2 is The capacitance of the third capacitor C3 is The capacitance of the fourth capacitor C4 is At this time, the capacitance of the first equivalent capacitor C12 is The capacitance of the second equivalent capacitor C13 is The capacitance of the third equivalent capacitor C23 is The capacitance of the fourth equivalent capacitor C14 is The capacitance of the fifth equivalent capacitor C24 is The capacitance of the sixth equivalent capacitor C34 is .

[0089] For example, if the fourth capacitance value is greater than or equal to any one of the first, second, and third capacitance values, it can be seen from the above equivalent capacitor capacitance calculation formula that the capacitance value of the fourth capacitor C4 will directly affect the capacitance values ​​of each equivalent capacitor. Among them, the capacitance values ​​of the fourth equivalent capacitor C14, the fifth equivalent capacitor C24, and the sixth equivalent capacitor C34, which are related to the fourth capacitor C4, will remain relatively stable due to the larger capacitance value of the fourth capacitor C4, and are not easily affected by process deviations. This ensures the stability of the equivalent capacitance of the feedback sub-circuit 401. At the same time, relying on the larger capacitance value of the fourth capacitor C4 as the core of gain adjustment, the pixel circuit gain can be accurately and flexibly controlled, further enhancing the balance between high gain, high-speed exposure, and large array imaging uniformity, and ensuring the image quality and frame rate performance of the image sensor.

[0090] As another possible implementation, when the first terminal of the second gain switching switch 4032 is connected to the second terminal of the fourth capacitor C4, and the second terminal of the second gain switching switch 4032 is connected to the output terminal of the amplifier sub-circuit 402, the pixel circuit operates in the second gain mode, based on... Figure 7 Based on the equivalent relationship shown, determine the capacitance values ​​of each equivalent capacitor. The capacitance value of the first capacitor C1 is... The capacitance of the second capacitor C2 is The capacitance of the third capacitor C3 is The capacitance of the fourth capacitor C4 is At this time, the capacitance of the first low-gain equivalent capacitor CL1 is The capacitance of the second low-gain equivalent capacitor CL2 is... The capacitance of the third low-gain equivalent capacitor CL3 is... .

[0091] For example, if the fourth capacitance value is greater than or equal to any one of the first, second, and third capacitance values, combined with the above equivalent capacitor capacitance calculation formula, it can be seen that after the fourth capacitor C4 is connected in parallel with the second capacitor C2, it will increase the capacitance values ​​of the first low-gain equivalent capacitor CL1 and the third low-gain equivalent capacitor CL3. This makes the equivalent feedback capacitance between the input and output terminals of the feedback sub-circuit 401 in the second gain mode much larger than that in the first gain mode, resulting in a decrease in the corresponding circuit gain. At the same time, because the capacitance value of the fourth capacitor C4 is large, the equivalent capacitor capacitance value related to the fourth capacitor C4 also has good process stability, which can avoid gain mismatch caused by process deviations and wiring differences. This ensures the low noise and anti-saturation imaging capability of the pixel circuit in the second gain mode, complementing the first gain mode and further improving the adaptability and imaging uniformity of the image sensor under different lighting scenarios.

[0092] In some embodiments, the first capacitance value, the second capacitance value, and the third capacitance value are the same preset capacitance value, and the fourth capacitance value is N times the preset capacitance value, where N is greater than or equal to 2.

[0093] Understandably, setting the first capacitor C1, the second capacitor C2, and the third capacitor C3 to the same preset capacitance value can simplify the design and manufacturing process of the feedback sub-circuit 401, reduce the difficulty of device matching, and improve the consistency between pixel units. Setting the capacitance value of the fourth capacitor C4 to N times (N≥2) can not only ensure the stability of the basic feedback capacitor, but also achieve gain adjustment by multiples through the connection or switching of the fourth capacitor C4, so that the pixel circuit can smoothly switch between high sensitivity and low noise modes, enhancing the scene adaptability.

[0094] As one possible implementation, when the first gain switching switch 4031 is closed and the second gain switching switch 4032 is open, the pixel circuit operates in the first gain mode, based on... Figure 6 The equivalent relationships shown, and the capacitance values ​​of the equivalent capacitors determined above, are used to determine the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3, all of which are C. The capacitance value of the fourth capacitor C4 is nC (n is a multiple of 2 or greater), and the first voltage terminal is always grounded. In this case, the sixth equivalent capacitor C34 is short-circuited and ineffective due to the grounding of the first voltage terminal. The second equivalent capacitor C13 and the fourth equivalent capacitor C14 are the pixel trap capacitances to ground, and the third equivalent capacitor C23 and the fifth equivalent capacitor C24 are the output capacitances to ground of the amplifier sub-circuit 402. None of these equivalent capacitors affect the current gain of the circuit. Only the first equivalent capacitor C12 remains functional in this circuit, and its capacitance value can be calculated using the formula: If the first equivalent capacitor C12 is made to reach the size of the preset feedback capacitor Cf, then C = (3 + n) × Cf can be derived.

[0095] Therefore, as long as the capacitance of the fourth capacitor C4 is large enough, the corresponding n value will also be large enough. The first capacitor C1 to the fourth capacitor C4 can achieve the feedback effect of a small capacitor with a larger capacitance value. Furthermore, capacitors with larger capacitance values ​​exhibit better consistency between pixels, ensuring... Figure 5 The pixel array formed by the pixel circuit shown has a low pixel gain mismatch, thereby achieving low noise and high sensitivity of the pixel circuit, while taking into account both image quality and scene adaptability.

[0096] As another possible implementation, when the first terminal of the second gain switching switch 4032 is connected to the second terminal of the fourth capacitor C4, and the second terminal of the second gain switching switch 4032 is connected to the output terminal of the amplifier sub-circuit 402, the pixel circuit operates in the second gain mode, based on... Figure 7The equivalent relationships shown, and the equivalent capacitor values ​​determined above, are used to determine the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3, all of which are C. The capacitance value of the fourth capacitor C4 is nC (n is a multiple of 2 or greater), and the first voltage terminal is always grounded. In this case, the second low-gain equivalent capacitor CL2 is the equivalent capacitor of the node containing the photodiode PD to ground, and the third low-gain equivalent capacitor CL3 is the equivalent capacitor of the output terminal of the amplifier sub-circuit 402 to ground. None of these equivalent capacitors affect the current gain of the circuit. Only the first low-gain equivalent capacitor CL1 remains functional in this circuit, and its capacitance value can be calculated using the formula:

[0097] When n is sufficiently large, the first low-gain equivalent capacitor CL1 is approximately equal to C, compared to the first equivalent capacitor in the first gain mode. In the second gain mode, the equivalent capacitance increases, and the corresponding circuit gain decreases to 1 / (3+n) of that in the high gain mode, thereby achieving precise switching between high and low gain modes of the pixel circuit and meeting the imaging requirements under different lighting conditions.

[0098] In some embodiments, in a first gain mode, the voltage provided by the first voltage terminal is a ground voltage before the photodiode (PD) is exposed, and increases from the ground voltage to a first preset reference voltage during the exposure of the PD; in a second gain mode, the voltage provided by the first voltage terminal is a ground voltage before the PD is exposed, and increases from the ground voltage to a second preset reference voltage during the exposure of the PD; wherein the first preset reference voltage is less than the second preset reference voltage.

[0099] In the first gain mode, before the photodiode (PD) is exposed, a ground voltage is provided at the first voltage terminal. This effectively releases the residual charge on the third capacitor C3, preventing residual charge from interfering with the conversion of light signals to electrical signals during exposure and ensuring exposure accuracy and signal purity. During PD exposure, the voltage at the first voltage terminal increases to a first preset reference voltage. A preset amount of charge is injected into the photosensitive node through the third capacitor C3, providing an adjustable potential offset for the photosensitive node. This expands the dynamic range without changing the pixel gain. Combined with the equivalent capacitance characteristics of the feedback sub-circuit 401, this further enhances the sensitivity of the high-gain mode, improves the dynamic range of the pixels, and helps achieve high-speed, high-sensitivity imaging.

[0100] In the second gain mode, before the photodiode (PD) is exposed, the first voltage terminal is also grounded to release the residual charge on the third capacitor C3, ensuring the stability of the initial exposure state. During PD exposure, the voltage at the first voltage terminal increases to the second preset reference voltage, which is greater than the first preset reference voltage. This allows the third capacitor C3 to still achieve common-mode reduction in the second gain mode, but with a smaller amplitude, to meet the dynamic range expansion requirements in low-gain scenarios. Simultaneously, in the second gain mode, the fourth capacitor C4 is connected to the output of the amplifier sub-circuit 402, increasing the equivalent feedback capacitance. Combined with the smaller jump in the second preset reference voltage, this reduces power surges and noise introduction during voltage switching. Combined with the low-noise characteristics of the low-gain mode itself, this further ensures imaging stability and signal fidelity.

[0101] In embodiments of the present invention, such as Figure 4 or Figure 5 As shown, the input terminal of the amplification sub-circuit 402 is adapted to be connected to the photodiode PD. The amplification sub-circuit 402 is configured to: amplify the voltage at the input terminal of the amplification sub-circuit 402 based on the exposure current output by the photodiode PD; and clamp the voltage of the photodiode PD at a preset potential through the feedback sub-circuit 401.

[0102] It is understandable that the amplification sub-circuit 402 amplifies the voltage of the exposure current output by the photodiode PD and, together with the feedback sub-circuit 401, achieves stable clamping of the working potential of the photodiode PD, thereby providing stable signal conversion and potential constraint for the pixel circuit, and thus ensuring the signal linearity and operational stability of the pixel circuit during operation. In one implementation, the weak photocurrent generated by the photodiode PD under illumination flows into the capacitor network of the feedback sub-circuit 401. This current attempts to change the voltage of the cathode (i.e., the photosensitive node) of the photodiode PD. However, since the input terminal of the amplification sub-circuit 402 directly monitors the voltage of the photosensitive node, the output voltage of the amplification sub-circuit 402 will change significantly with the small fluctuations in the voltage of the photosensitive node. This change in the output voltage is coupled back to the photosensitive node through the capacitor in the feedback sub-circuit 401, forming a negative feedback loop. This negative feedback loop continuously adjusts the output voltage of the amplification sub-circuit 402 until the voltage of the photosensitive node is precisely pulled back to the preset potential determined by the bias of the input pair of transistors in the amplification sub-circuit 402, thereby achieving dynamic clamping. At this point, the photocurrent can no longer change the voltage of the photosensitive node and can only flow through the feedback sub-circuit 401 and integrate on the capacitor, ultimately manifesting as a change in the output voltage of the amplification sub-circuit 402.

[0103] As one possible implementation method, such as Figure 5As shown, the amplifier sub-circuit 402 includes a first second P-type transistor MP51, a second second P-type transistor MP52, a first third N-type transistor MN31, and a second third N-type transistor MN32. The source of the first second P-type transistor MP51 is coupled to the power supply terminal, and its gate is used to receive a bias signal. The source of the second second P-type transistor MP52 is coupled to the drain of the first second P-type transistor MP51, and its gate is used to receive a bias signal. The drain of the first third N-type transistor MN31 is coupled to the drain of the second second P-type transistor MP52, and its gate is used to receive a bias signal. The drain of the second third N-type transistor MN32 is coupled to the source of the first third N-type transistor MN31, its gate is coupled to the cathode of the photodiode PD and the first terminal of the third parasitic capacitance Cpd3, and its source is coupled to the ground terminal.

[0104] As another possible implementation, the amplifier sub-circuit 402 includes only one P-type transistor and one N-type transistor. Exemplarily, the source of the P-type transistor is coupled to the power supply terminal, the gate of the P-type transistor is used to receive a bias signal, the drain of the P-type transistor is coupled to the drain of the N-type transistor, the gate of the N-type transistor is coupled to the cathode of the photodiode PD and the first terminal of the third parasitic capacitance Cpd3, and the source of the N-type transistor is coupled to the ground terminal.

[0105] It should be understood that this invention does not impose specific limitations on the number of P-type transistors and N-type transistors in the amplifier sub-circuit 402. This application also does not impose specific limitations on the structure of the amplifier sub-circuit 402; it can employ a common-source, common-gate structure to optimize gain and noise performance, or a simple common-source structure to reduce area and power consumption. In practical applications, the choice can be flexibly made according to performance requirements.

[0106] In some embodiments, the pixel circuit further includes a first switch 501, coupled between the photodiode PD and the output terminal of the amplifier sub-circuit 402. The first switch 501 is configured to be closed between a first time point T1 and a second time point T2 to reset the voltage at the output terminal of the amplifier sub-circuit 402 and the voltage of the photodiode PD. The first time point T1 is the start time of operation of the pixel circuit, and the second time point T2 is after the first time point T1.

[0107] All time points mentioned here and below (including but not limited to the first time point T1, the second time point T2, the third time point T3, the fourth time point T4, the start of exposure, and the end of exposure, etc.) can be found at [reference needed]. Figure 8 The diagram shows the working timing.

[0108] It is understandable that by setting the first switch 501 and controlling it to close from the start time of the pixel circuit operation (i.e., the first time point T1) to the second time point T2, the output terminal of the amplifier sub-circuit 402 can be short-circuited with the photodiode PD, so that the voltage of both can be reset to the known initial potential before the exposure begins, eliminating the influence of residual charge from the previous frame on the current exposure signal; at the same time, this reset operation provides a reference voltage for subsequent correlation double sampling, which helps to suppress fixed pattern noise and reset noise of the pixel circuit, and improve the signal-to-noise ratio and imaging quality of the image sensor.

[0109] In some embodiments, the pixel circuit further includes: a reset sampling capacitor 504, a first end of which is coupled to the output of the amplifier sub-circuit 402, and a second end of which is coupled to a ground terminal; a second switch 502, which is coupled between the first end of the reset sampling capacitor 504 and the output of the amplifier sub-circuit 402; the second switch 502 is configured to: be closed between a first time point T1 and a third time point T3 to reset the reset sampling capacitor 504; and be open at the third time point T3 to allow the reset sampling capacitor 504 to store a reset voltage.

[0110] The reset voltage stored in the reset sampling capacitor 504 is the voltage at the output of the amplification sub-circuit 402 at the third time point T3, which is the voltage output by the amplification sub-circuit 402 before the pixel is reset and exposure begins.

[0111] In this embodiment, by setting a reset sampling capacitor 504 and a second switch 502, the second switch 502 is controlled to close and conduct during the period from the first time point T1 to the third time point T3, so that the circuit is in the reset phase and the potential gradually stabilizes. When the second switch 502 is opened at the third time point T3, the output voltage (i.e., the reset voltage) of the amplification sub-circuit 402 after reset can be sampled and stored in the reset sampling capacitor 504. This reset voltage contains fixed-mode noise components such as the reset noise of the pixel circuit and the effect of switch injection, providing a reference signal for subsequent correlation double sampling readout, which facilitates the elimination of common-mode noise through differential operation during the readout stage, thereby improving the signal-to-noise ratio and imaging quality of the image sensor.

[0112] In some embodiments, an exposure sampling capacitor 505 is provided, with its first end coupled to the output of the amplification sub-circuit 402 and its second end coupled to ground. A third switch 503 is coupled between the first end of the exposure sampling capacitor 505 and the output of the amplification sub-circuit 402. The third switch 503 is configured to: be closed between a first time point T1 and a fourth time point T4 to reset the exposure sampling capacitor 505; and be open at the fourth time point T4 to allow the exposure sampling capacitor 505 to store the exposure voltage. The third time point T3 is after the second time point T2 and before the photodiode PD begins exposure; the fourth time point T4 is after the photodiode PD ends exposure.

[0113] The exposure sampling capacitor 505 stores the exposure voltage, which is the voltage at the output of the amplifier sub-circuit 402 at the fourth time point T4. This exposure voltage is the output voltage of the photodiode PD after it has completed exposure, with the exposure signal superimposed on it.

[0114] In this embodiment, by setting an exposure sampling capacitor 505 and a third switch 503, the circuit remains closed and conductive between the first time point T1 and the fourth time point T4, allowing the circuit voltage to gradually transition from the voltage stabilized after the reset phase (i.e., the reset voltage) to the voltage stabilized after exposure (i.e., the exposure voltage). At the fourth time point T4, the third switch 503 is opened, allowing the voltage at the output of the amplification sub-circuit 402 after exposure (i.e., the exposure voltage) to be sampled and stored in the exposure sampling capacitor 505. This exposure voltage contains information about the photogenerated charge generated by the photodiode PD during exposure. By setting the third time point T3 before the start of exposure and the fourth time point T4 after the end of exposure, the exposure sampling capacitor 505 ensures that it completely records the signal changes throughout the entire exposure cycle. This provides a complete signal pair for subsequent correlation dual sampling readout with the reset voltage stored in the reset sampling capacitor 504, effectively eliminating reset noise and fixed-pattern noise in the pixel circuit and improving the dynamic range and image quality of the image sensor.

[0115] In some embodiments, in the first gain mode, after the fourth time point T4, the voltage provided by the first voltage terminal drops from the first preset reference voltage to the ground voltage; in the second gain mode, after the fourth time point T4, the voltage provided by the first voltage terminal drops from the second preset reference voltage to the ground voltage; wherein the first preset reference voltage is less than the second preset reference voltage.

[0116] In this embodiment, in the first gain mode, the voltage of the first voltage terminal is reduced from the first preset reference voltage to the ground voltage after the fourth time point T4; in the second gain mode, the voltage of the first voltage terminal is reduced from the second preset reference voltage to the ground voltage after the fourth time point T4. This operation can utilize the change in the first voltage terminal after the photodiode (PD) exposure is completed to perform additional charge adjustment or reset assistance on the output terminal or related nodes of the amplification sub-circuit 402, thereby preparing a stable starting state for the acquisition of the next frame image, effectively improving the reset efficiency and signal consistency of the pixel circuit during continuous operation.

[0117] It should be noted that in the first gain mode (i.e., high gain), the equivalent feedback capacitance is extremely small and highly sensitive to voltage changes. Only a small voltage jump (i.e., a small first preset reference voltage) is needed to achieve the charge adjustment effect on the photosensitive node or related circuits. However, in the second gain mode (i.e., low gain), the equivalent feedback capacitance is larger and less sensitive to voltage changes. A larger voltage jump (i.e., a larger second preset reference voltage) is required to achieve the same charge adjustment effect. Therefore, the first preset reference voltage is smaller than the second preset reference voltage precisely to match the circuit's response characteristics to voltage changes in different gain modes. This ensures that the voltage drop operation at the first voltage terminal after exposure can achieve stable and efficient reset assistance and charge adjustment in both gain modes.

[0118] In some embodiments, the pixel circuit further includes: a fourth switch 506, the first end of which is connected to the first end of the reset sampling capacitor 504, and the second end of which is connected to the first end of the exposure sampling capacitor 505; the fourth switch 506 is configured to: be in an open state when the row selection signal is enabled and the column selection signal is disabled, so that the first end of the reset sampling capacitor 504 is not connected to the first end of the exposure sampling capacitor 505; and be in a closed state when the row selection signal is enabled and the column selection signal is enabled, so that the first end of the reset sampling capacitor 504 is connected to the first end of the exposure sampling capacitor 505.

[0119] As one possible implementation, by setting the fourth switch 506 to be controlled by the NAND logic of the row selection signal and the column selection signal, flexible readout control of the pixel circuit during row and column interleaving addressing can be achieved. When only the row selection signal is enabled and the column selection signal is not enabled, the fourth switch 506 is open, and the reset sampling capacitor 504 and the exposure sampling capacitor 505 independently output their respective voltage signals, which are then used by the first readout sub-circuit 507 and the second readout sub-circuit 508 to read the reset voltage and the exposure voltage, respectively, to achieve differential output of correlated double sampling. When both the row selection signal and the column selection signal are enabled, the fourth switch 506 is closed, and the first terminals of the reset sampling capacitor 504 and the exposure sampling capacitor 505 are short-circuited. At this time, the first readout sub-circuit 507 and the second readout sub-circuit 508 can cooperate to achieve a specific readout mode (such as global shutter or shared readout), enhancing the flexibility and scene adaptability of the pixel circuit readout method.

[0120] The first readout sub-circuit 507 is coupled between the first terminal of the reset sampling capacitor 504 and the negative output terminal; the first readout sub-circuit 507 is configured to: output a first negative output voltage based on the reset voltage when the fourth switch 506 is in the open state; and output a second negative output voltage based on the reset voltage and the exposure voltage when the fourth switch 506 is in the closed state.

[0121] As one possible implementation method, such as Figure 5 As shown, the first readout sub-circuit 507 includes a third third N-type transistor MN33 and a fourth third N-type transistor MN34. The drain of the third third N-type transistor MN33 is coupled to the power supply terminal, the gate of the third third N-type transistor MN33 is coupled to the first terminal of the reset sampling capacitor 504, the source of the third third N-type transistor MN33 is coupled to the drain of the fourth third N-type transistor MN34, the gate of the fourth third N-type transistor MN34 is used to receive the row selection signal, and the source of the fourth third N-type transistor MN34 is coupled to the negative output terminal.

[0122] The second readout sub-circuit 508 is coupled between the first terminal of the exposure sampling capacitor 505 and the positive output terminal; the second readout sub-circuit 508 is configured to: output a first positive output voltage based on the exposure voltage when the fourth switch 506 is in the open state; and output a second positive output voltage based on the reset voltage and the exposure voltage when the fourth switch 506 is in the closed state.

[0123] As one possible implementation method, such as Figure 5As shown, the second readout sub-circuit 508 includes a fifth third N-type transistor MN35 and a sixth third N-type transistor MN36. The drain of the fifth third N-type transistor MN35 is coupled to the power supply terminal, the gate of the fifth third N-type transistor MN35 is coupled to the first terminal of the exposure sampling capacitor 505, the source of the fifth third N-type transistor MN35 is coupled to the drain of the sixth third N-type transistor MN36, the gate of the sixth third N-type transistor MN36 is used to receive the row selection signal, and the source of the sixth third N-type transistor MN36 is coupled to the positive output terminal.

[0124] For example, after all pixels in the pixel array of the image sensor synchronously complete the reset and exposure operations, the pixel reset voltage Vrst and exposure voltage Vexp are stored in the reset sampling capacitor 504 and exposure sampling capacitor 505, respectively, waiting for the readout circuit to read the signals. During the readout phase, the row selection signal is enabled, and the readout circuit samples and outputs the reset voltage Vrst and exposure voltage Vexp.

[0125] If the source follower formed by the third N-type transistor MN33 and the fourth N-type transistor MN34 has an input voltage of Vin and an output voltage of Vout, then its transfer relationship can be expressed as Vout = Vin. Vth33, where Vth33 is the threshold voltage of the third N-type transistor MN33; the source follower composed of the fifth and sixth N-type transistors MN35 and MN36 has an input voltage of Vin and an output voltage of Vout, then its transfer relationship can be expressed as Vout = Vin. Vth35, where Vth35 is the threshold voltage of the fifth third N-type transistor MN35. Therefore, the first negative output of the pixel is Vrst. Vth33, the first positive output is Vexp Vth35.

[0126] Among them, the third third N-type transistor MN33 and the fifth third N-type transistor MN35 are source follower input transistors, and their threshold voltages Vth33 and Vth35 will be superimposed on the output voltage, which needs to be eliminated through differential operation; the fourth third N-type transistor MN34 and the sixth third N-type transistor MN36 are row selection switches, which are only used to control the conduction and cutoff of the readout path. When they are on, they are equivalent to a low-impedance path. Their threshold voltages do not participate in the differential operation of the signal voltage, so they are not reflected in the voltage expression.

[0127] Subsequently, the column selection signal is enabled, and the row selection signal and column selection signal are jointly input to the switch controlled by the AND gate, closing the switch. This resets the charge balance across the sampling capacitor 504 and the exposure sampling capacitor 505, clamping the gate voltages of the third N-type transistor MN33 and the fifth N-type transistor MN35 to (Vrst + Vexp) / 2. At this point, the second negative output of the pixel is (Vrst + Vexp) / 2. Vth33, the second positive output is (Vrst+Vexp) / 2 Vth35. Subtracting the two difference outputs yields: [(Vexp Vth35) (Vrst Vth33)] {[(Vrst+Vexp) / 2 Vth35] [(Vrst+Vexp) / 2 After simplification, the output is Vexp. Vrst, the exposure signal of a pixel, effectively eliminates threshold voltage and common-mode noise.

[0128] Among them, the row selection signal is a gating signal that controls the conduction of the row where the current pixel is located, and is used to indicate that the current row enters the readout state; the column selection signal is a gating signal that controls the conduction of the column where the current pixel is located, and is used to indicate that the current column enters the readout state; when the row selection signal and the column selection signal are enabled at the same time, it indicates that the current pixel unit is in the effective readout state.

[0129] The following section explains in more detail how the pixel circuit operates in different gain modes. Based on Figure 5 ,like Figure 8 The diagram shows the timing sequence of a pixel circuit under different gain modes provided by the present invention. These different gain modes include a first gain mode and a second gain mode. The timing sequence diagram illustrates the potential changes of the first switch 501, LED exposure, the second switch 502, the third switch 503, and the first voltage terminal (i.e., from ground potential to the first preset reference voltage Vsub1 in the first gain mode, and from ground potential to the second preset reference voltage Vsub2 in the second gain mode). The horizontal axis represents time, and the vertical axis represents the closed / open state or potential level of each signal. The first preset reference voltage Vsub1 is less than the second preset reference voltage Vsub2.

[0130] As one possible implementation, in the first gain mode, when The voltage of the circuit is adjusted based on the second terminal of the third capacitor C3 being coupled to the first voltage terminal. Figure 8 The illustrated timing sequence provides the voltage signal. Specifically, it includes:

[0131] First, at the first time point T1, the first switch 501 is closed. At this time, the output terminal of the amplification sub-circuit 402 is short-circuited to the cathode of the photodiode PD, the pixel circuit enters a reset state, and the voltage of the photosensitive node and the output terminal of the amplification sub-circuit 402 is reset to the initial potential. Simultaneously, the second switch 502 and the third switch 503 are also closed. The first terminal of the reset sampling capacitor 504 is short-circuited to the output terminal of the amplification sub-circuit 402, and the first terminal of the exposure sampling capacitor 505 is also short-circuited to the output terminal of the amplification sub-circuit 402. Therefore, both the reset sampling capacitor 504 and the exposure sampling capacitor 505 are reset to the output potential of the amplification sub-circuit 402. The first voltage terminal remains at ground potential (0V) at this time.

[0132] Then, from the first time point T1 to the second time point T2, the first switch 501 remains closed, and the pixel circuit remains in the reset state. The output voltage of the amplification sub-circuit 402 stabilizes at the reset potential, and the reset sampling capacitor 504 and the exposure sampling capacitor 505 follow this potential. At the second time point T2, the first switch 501 opens, ending the reset of the amplification sub-circuit 402 and the photodiode PD. At this time, the short-circuit path between the output of the amplification sub-circuit 402 and the cathode of the photodiode PD is broken, and the pixel circuit exits the reset state.

[0133] Subsequently, between the second time point T2 and the third time point T3, the first switch 501 remains open, while the second switch 502 and the third switch 503 remain closed. The output voltage of the amplifier sub-circuit 402 gradually stabilizes, and its output value reflects the noise level after reset. This stabilization period ensures that the output of the amplifier sub-circuit 402 reaches a stable state, preparing for subsequent reset voltage sampling.

[0134] Next, at the third time point T3, the second switch 502 is opened. At this time, the connection between the first terminal of the reset sampling capacitor 504 and the output terminal of the amplification sub-circuit 402 is broken, and the reset sampling capacitor 504 samples and stores the output voltage of the amplification sub-circuit 402 at the moment of disconnection (i.e., the reset voltage). This reset voltage includes fixed-mode noise components such as pixel circuit reset noise and switch injection effects. At this time, the third switch 503 remains closed, and the exposure sampling capacitor 505 continues to follow the output voltage of the amplification sub-circuit 402.

[0135] Next, after the third time point T3, a brief stabilization period ensures that the disturbance caused by the opening of the second switch 502 has subsided, and the output voltage of the amplification sub-circuit 402 stabilizes again. Subsequently, the LED exposure signal begins, and the photodiode PD starts converting the incident light signal into exposure current. Simultaneously, at the same time the LED exposure signal starts, the voltage at the first voltage terminal jumps from ground potential (0V) to the first preset reference voltage Vsub1, i.e., to the reduced common-mode value. This voltage jump is coupled to the common node through the third capacitor C3 in the feedback sub-circuit 401, thereby injecting a certain amount of charge into the cathode of the photodiode PD. This injected charge needs to be neutralized by the photosensitive current during the exposure process, effectively setting an adjustable offset for the exposure signal, thereby effectively preventing high-light saturation and expanding the dynamic range of the pixel circuit.

[0136] It should be noted that, in Figure 6 In the equivalent circuit shown, the capacitance of the second equivalent capacitor C13 is... When the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are all set to a preset capacitance value C, the capacitance value of the fourth capacitor C4 is set to n times the preset capacitance value C (i.e., ...). )hour, The second equivalent capacitor C13 is connected between the first terminal 601 (i.e., connected to the cathode of the photodiode PD) and the first voltage terminal. Therefore, when the first voltage terminal jumps from ground potential (0V) to the first preset reference voltage Vsub1 at the start of exposure, charge is injected into the cathode of the photodiode PD through the second equivalent capacitor C13, and the amount of injected charge is... Since the capacitance values ​​of the second equivalent capacitor C13 and the first equivalent capacitor C12 are equal (C÷(3+n)), the amount of charge that the photosensitive current needs to remove to restore the photosensitive node potential corresponds exactly to the change in output voltage Vsub1 of the amplifier sub-circuit 402. The entire process is equivalent to reducing the exposure value of the pixel circuit by Vsub1 through the operation of the first voltage terminal, thus setting an adjustable offset for the exposure signal. This effectively expands the dynamic range without changing the pixel gain, and the voltage of the first preset reference voltage Vsub1 can be precisely controlled by external circuitry, achieving a significant improvement in dynamic range.

[0137] Next, while the LED exposure signal remains high, the photodiode PD continues photoelectric conversion, and the resulting photocurrent charges and discharges the equivalent feedback capacitor through the feedback sub-circuit 401. The output voltage of the amplification sub-circuit 402 changes linearly with the exposure amount. During this period, the third switch 503 remains closed, and the exposure sampling capacitor 505 continuously follows the output voltage changes of the amplification sub-circuit 402.

[0138] Next, after the preset exposure time, the LED exposure signal is turned off, ending the exposure. The photodiode (PD) stops generating photocurrent, and the output voltage of the amplifier circuit 402 stops changing. From the end of the LED exposure to the fourth time point T4, the output voltage of the amplifier circuit 402 gradually stabilizes, and its final value reflects the exposure voltage after the exposure ends. This stabilization period ensures that the output of the amplifier circuit 402 reaches a stable state after the exposure, preparing for subsequent exposure voltage sampling.

[0139] Next, at the fourth time point T4, the third switch 503 is turned off. At this time, the connection between the first terminal of the exposure sampling capacitor 505 and the output terminal of the amplification sub-circuit 402 is broken, and the exposure sampling capacitor 505 samples and stores the output voltage (i.e., the exposure voltage) of the amplification sub-circuit 402 at the moment of disconnection. Thus, the reset sampling capacitor 504 stores the reset voltage, and the exposure sampling capacitor 505 stores the exposure voltage, providing a complete signal pair for subsequent correlated double sampling readout.

[0140] Finally, at a preset time after the fourth time point T4, the voltage at the first voltage terminal gradually recovers from the first preset reference voltage Vsub1 to the ground potential (0V), preparing for the acquisition of the next frame image. At this time, the entire exposure and sampling cycle ends, and the pixel circuit can enter the readout stage or the reset stage for the next frame image.

[0141] As another possible implementation, the timing of the pixel circuit in the second gain mode is basically the same as that in the first gain mode, and will not be repeated here, but can still be referred to. Figure 8 As shown. The differences between the two include, but are not limited to, the following aspects: In the second gain mode, the second terminal of the fourth capacitor C4 is connected to the output terminal of the amplification sub-circuit 402 through the gain switching sub-circuit 403, rather than being grounded. Figure 8 As shown, in the second gain mode, the voltage at the first voltage terminal changes from ground potential to the second preset reference voltage Vsub2. Furthermore, in the second gain mode, after the fourth time point T4, the voltage at the first voltage terminal gradually recovers from the second preset reference voltage Vsub2 back to ground potential (0V). Specifically, this includes:

[0142] (1) In the second gain mode, after the third time point T3, a short stabilization period is completed to ensure that the disturbance caused by the opening of the second switch 502 has subsided, and the output voltage of the amplification sub-circuit 402 stabilizes again. Subsequently, the LED exposure signal starts, and the photodiode PD begins to convert the incident light signal into exposure current. At the same time as the LED exposure signal starts, the voltage at the first voltage terminal jumps from the ground potential (0V) to the second preset reference voltage (i.e., Vsub2), that is, jumps to the reduced common-mode value. This voltage jump is coupled to the common node through the third capacitor C3 in the feedback sub-circuit 401, thereby injecting a certain amount of charge into the cathode of the photodiode PD. This injected charge needs to be neutralized by the photosensitive current during the exposure process, which is equivalent to setting an adjustable offset for the exposure signal, thereby effectively preventing high light saturation and expanding the dynamic range of the pixel circuit.

[0143] (2) In the second gain mode, after a preset time following the fourth time point T4, the voltage at the first voltage terminal gradually recovers from the second preset reference voltage Vsub2 to the ground potential (0V), preparing for the acquisition of the next frame image. At this time, the entire exposure and sampling cycle ends, and the pixel circuit can enter the readout stage or the reset stage of the next frame image.

[0144] In the second gain mode, the same settings are applied. .based on Figure 7 In the equivalent transformation, only the first low-gain equivalent capacitor CL1 remains active in the second gain mode, and its capacitance is... When n is sufficiently large, the first low-gain equivalent capacitor CL1 approaches C, compared to the capacitance of the first equivalent capacitor in the first gain mode. The gain increases significantly, corresponding to a circuit gain decrease to 1 / (3+n) of the first gain mode. The second low-gain equivalent capacitor CL2 is connected between the cathode of the photodiode PD and the first voltage terminal, with a capacitance of [value missing]. Due to the capacitance value of the second low-gain equivalent capacitor CL2 The capacitance value of the first low-gain equivalent capacitor CL1 Compared to the first gain mode configuration, the selected second preset reference voltage Vsub2 allows for the injection of more charge, thus satisfying the same output voltage change. Both gain modes share the same common-mode reduction mechanism, achieving gain adjustment by switching the connection method of the fourth capacitor C4, thereby meeting the imaging requirements under different lighting conditions.

[0145] The present invention also provides an image sensor 900. For example... Figure 9 As shown, the image sensor 900 includes a pixel array 901, at least one pixel in the pixel array including a photodiode PD and the aforementioned... Figure 4 or Figure 5 The pixel circuit 902 shown.

[0146] Because the image sensor in this embodiment of the invention employs the aforementioned pixel circuit, it can flexibly switch pixel gain to adapt to imaging requirements under different lighting conditions. Simultaneously, voltage modulation at the first voltage terminal effectively expands the dynamic range, improving image quality and scene adaptability. Since the image sensor in this embodiment of the invention includes the aforementioned pixel circuit, the technical effects it achieves can also be referred to in the embodiments of the aforementioned pixel circuit; therefore, the embodiments of the invention will not be described again here.

[0147] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, include: Feedback sub-circuit, amplification sub-circuit, and gain switching sub-circuit; The input terminal of the feedback sub-circuit is adapted to be connected to the photodiode, and the feedback sub-circuit is configured to receive and store the exposure current output by the photodiode. The feedback sub-circuit includes: a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first terminal of the first capacitor is adapted to be connected to the photosensitive diode. The second terminals of the first capacitor, the first terminals of the second capacitor, the first terminals of the third capacitor, and the first terminals of the fourth capacitor are connected together. The second terminal of the second capacitor is connected to the output terminal of the amplification sub-circuit. The second terminal of the third capacitor is connected to the first voltage terminal. The second terminal of the fourth capacitor is connected to the ground terminal. The input terminal of the amplification sub-circuit is adapted to be connected to the photosensitive diode. The amplification sub-circuit is configured to: amplify the voltage at the input terminal of the amplification sub-circuit based on the exposure current output by the photosensitive diode; and clamp the voltage of the photosensitive diode at a preset potential through the feedback sub-circuit. The gain switching subcircuit is connected between the second terminal of the fourth capacitor and the ground terminal, and between the second terminal of the fourth capacitor and the output terminal of the amplification subcircuit. The gain switching subcircuit is configured to control the capacitance value between the input and output terminals of the feedback subcircuit to change the gain of the feedback subcircuit on the exposure current, so that the pixel circuit operates in a first gain mode or a second gain mode; in the first gain mode, the gain of the amplification subcircuit on the exposure current is greater than the gain of the amplification subcircuit on the exposure current in the second gain mode. In the first gain mode, the voltage provided by the first voltage terminal is the ground voltage before the photodiode is exposed, and is increased from the ground voltage to the first preset reference voltage when the photodiode is exposed. In the second gain mode, the voltage provided by the first voltage terminal is the ground voltage before the photodiode is exposed, and is increased from the ground voltage to the second preset reference voltage when the photodiode is exposed. Wherein, the first preset reference voltage is less than the second preset reference voltage.

2. The pixel circuit according to claim 1, characterized in that, The gain switching sub-circuit includes a first gain switching switch and a second gain switching switch; The first terminal of the first gain switching switch is connected to the second terminal of the fourth capacitor, and the second terminal of the first gain switching switch is connected to the ground terminal. The first terminal of the second gain switching switch is connected to the second terminal of the fourth capacitor, and the second terminal of the second gain switching switch is connected to the output terminal of the amplifier sub-circuit. The gain switching sub-circuit is configured as follows: When the first gain switching switch is closed and the second gain switching switch is open, the pixel circuit operates in the first gain mode; When the second gain switch is closed and the first gain switch is open, the pixel circuit operates in the second gain mode.

3. The pixel circuit according to any one of claims 1-2, characterized in that, The capacitance of the first capacitor is a first capacitance value, the capacitance of the second capacitor is a second capacitance value, the capacitance of the third capacitor is a third capacitance value, and the capacitance of the fourth capacitor is a fourth capacitance value. Wherein, any one of the first capacitance value, the second capacitance value, and the third capacitance value is less than the fourth capacitance value.

4. The pixel circuit according to claim 3, characterized in that, The first capacitance value, the second capacitance value, and the third capacitance value are the same preset capacitance value, and the fourth capacitance value is N times the preset capacitance value, where N is greater than or equal to 2.

5. The pixel circuit according to any one of claims 1-2, characterized in that, The pixel circuit also includes: The first switch is coupled between the photosensitive diode and the output terminal of the amplifier sub-circuit; The first switch is configured to be closed between a first time point and a second time point to reset the voltage at the output of the amplification sub-circuit and the voltage of the photosensitive diode. The first time point is the start time of the operation of the pixel circuit, and the second time point is after the first time point.

6. The pixel circuit according to claim 5, characterized in that, The pixel circuit also includes: A reset sampling capacitor, wherein the first end of the reset sampling capacitor is coupled to the output terminal of the amplifier sub-circuit, and the second end of the reset sampling capacitor is coupled to the ground terminal; A second switch is coupled between the first terminal of the reset sampling capacitor and the output terminal of the amplification sub-circuit; the second switch is configured to be closed between the first time point and the third time point to reset the reset sampling capacitor; and open at the third time point to allow the reset sampling capacitor to store a reset voltage. An exposure sampling capacitor, wherein a first end of the exposure sampling capacitor is coupled to the output terminal of the amplification sub-circuit, and a second end of the exposure sampling capacitor is coupled to the ground terminal; A third switch is coupled between the first terminal of the exposure sampling capacitor and the output terminal of the amplification sub-circuit; the third switch is configured to be closed between the first time point and the fourth time point to reset the exposure sampling capacitor; and open at the fourth time point to allow the exposure sampling capacitor to store the exposure voltage. The third time point is after the second time point and before the photosensitive diode begins exposure; the fourth time point is after the photosensitive diode ends exposure.

7. The pixel circuit according to claim 6, characterized in that, In the first gain mode, after the fourth time point, the voltage provided by the first voltage terminal drops from the first preset reference voltage to the ground voltage; In the second gain mode, after the fourth time point, the voltage provided by the first voltage terminal drops from the second preset reference voltage to the ground voltage; wherein the first preset reference voltage is less than the second preset reference voltage.

8. The pixel circuit according to claim 6 or 7, characterized in that, The pixel circuit also includes: A fourth switch, wherein the first terminal of the fourth switch is connected to the first terminal of the reset sampling capacitor, and the second terminal of the fourth switch is connected to the first terminal of the exposure sampling capacitor; the fourth switch is configured to: be in an open state when the row selection signal is enabled and the column selection signal is disabled, so that the first terminal of the reset sampling capacitor is not connected to the first terminal of the exposure sampling capacitor; and be in a closed state when the row selection signal is enabled and the column selection signal is enabled, so that the first terminal of the reset sampling capacitor is connected to the first terminal of the exposure sampling capacitor; A first readout sub-circuit is coupled between a first terminal and a negative output terminal of the reset sampling capacitor; the first readout sub-circuit is configured to: output a first negative output voltage based on the reset voltage when the fourth switch is in the open state; and output a second negative output voltage based on the reset voltage and the exposure voltage when the fourth switch is in the closed state. The second readout sub-circuit is coupled between the first terminal and the positive output terminal of the exposure sampling capacitor; the second readout sub-circuit is configured to: output a first positive output voltage based on the exposure voltage when the fourth switch is in the open state; and output a second positive output voltage based on the reset voltage and the exposure voltage when the fourth switch is in the closed state.

9. An image sensor, characterized in that, It includes a pixel array, at least one pixel in the pixel array including a photodiode, and a pixel circuit as claimed in any one of claims 1-8.

Images