Data readout method and readout circuit of image sensor storage array

Abstract

The invention provides a data read-out method and a read-out circuit for an image sensor storage array, and the method comprises the steps: adjusting the voltage or width or phase of a read-out enable signal of each column according to the distance between each column in the storage array and a read-out control unit, so as to compensate the delay of the read-out enable signal generated in a decoding process, and improve the decoding efficiency. On the premise that the chip area and power consumption are not increased as much as possible, the far-end and near-end difference of the array is reduced, and on the condition that the original reading frequency is kept, the effective reading time of the far-end of the array is prolonged, the discharge voltage difference is increased, and the working frequency is improved.

Description

Technical Field

[0001] This invention relates to a data readout method and readout circuit for an image sensor storage array. Background Technology

[0002] Image sensors typically use memory arrays to store column data. When reading data from the memory array, the address decoder outputs a read enable signal for each column according to the address change pattern. The stored data of the selected column is usually discharged through the bit line and then read out by the sensitive amplifier of the readout control unit. The use of differential structure for readout can effectively reduce the voltage difference that the bit line actually needs to discharge, thereby reducing power consumption and improving readout speed.

[0003] However, the read control unit is usually located on one side of the storage array. The distance between each column of storage cells in the storage array and the read control unit will vary. Since the function or timing of the read control unit is usually fixed, a single function or timing cannot meet the differences caused by the different distances between each column of the storage array and the read control unit.

[0004] For example, Figure 1 This diagram illustrates a conventional data readout circuit structure for an image sensor storage array, including a decoder 102, a storage array 103, and a readout control unit 104, with an input address signal A. <i:0>The signal is transmitted to decoder 102, which generates a read enable signal WL for each column based on the address signal switching. During the read process, the storage array 103 discharges the bit lines BL / BLb, and the result Data is generated in the read control unit 104.

[0005] The readout control unit 104 has the following structure: Figure 2 As shown, the system includes a clock control unit 1041 and a differential amplifier 1042. The clock control unit 1041 receives the input clock signal clk and generates a corresponding enable signal sen for the differential amplifier 1042. After the bit lines BL / BLb discharge, the differential amplifier 1042 operates under the control of the enable signal sen and outputs the final result Data. The BL / BLb discharge process needs to maintain a fixed timing relationship with the enable signal sen, ensuring that the differential amplifier 1042 starts operating when the voltage difference between the bit lines BL / BLb is at its maximum. This helps prevent data readout errors.

[0006] However, as the size of the storage array 103 increases, the difference between the near and far ends of the array also increases. Figure 1 In the illustrated embodiment, the read control unit 104 is located on the left side of the storage array 103. The end closer to the read control unit 104 is the array near end 103a, and the end farther from the read control unit 104 is the array far end 103b. The array far end 103b is affected by address signal A. <i:0>The readout enable signal WL will also be delayed accordingly, so some discharge time will be wasted and the discharge voltage difference will decrease accordingly. As the chip's requirements for readout frequency gradually increase, the effective readout time of data will be further shortened, and the bit line discharge voltage difference during the readout process will decrease, resulting in a limitation on the operating frequency.

[0007] Existing technologies mainly reduce signal delay and increase operating frequency by reducing array length (such as segmented driving and reducing the length of each segment), reducing signal line resistance (widening the traces), and increasing discharge speed (increasing the size of the discharge tube). However, these solutions all have certain drawbacks, such as increasing chip area, increasing power consumption, or leading to complex structural designs.

[0008] Therefore, a method and circuit are needed to improve the data readout performance of image sensor storage arrays, reduce signal delay caused by differences between the near and far ends of the array, increase the effective readout time of the far end of the array, increase the discharge voltage difference, and increase the operating frequency without increasing chip area and power consumption. Summary of the Invention

[0009] The purpose of this invention is to provide a data readout method and readout circuit for an image sensor storage array, which reduces the signal delay caused by the difference between the near and far ends of the array, increases the effective readout time at the far end of the array while maintaining the original readout frequency, increases the discharge voltage difference, and improves the operating frequency.

[0010] To address the aforementioned technical problems, one aspect of the present invention provides a data readout method for an image sensor storage array, comprising: a decoder decoding an address signal provided by an address control unit and providing readout enable signals to each column in the storage array, so that data in each column of the storage array can be read out by the readout control unit; wherein, the voltage, width, or phase of the readout enable signal of each column is adjusted according to the distance between each column in the storage array and the readout control unit to compensate for the readout enable signal delay generated during the decoding process.

[0011] Preferably, in the storage array, the end closer to the read control unit is the near end of the array, and the end farther from the read control unit is the far end of the array. The phase of the read enable signal of each column is adjusted by the address control unit so that the voltage difference of each column is approximately equal.

[0012] Preferably, the address control unit uses sampling clock signals of different phases to sample the original address signal and outputs it to the decoder. The sampling clock signal near the far end of the array is relatively earlier than the sampling clock signal near the near end of the array, thereby adjusting the phase of the readout enable signal of each column.

[0013] Preferably, the address control unit receives raw address signals of different phases and outputs them to the decoder after sampling. The raw address signals near the far end of the array are relatively earlier than the raw address signals near the near end of the array, thereby adjusting the phase of the readout enable signal of each column.

[0014] Preferably, the data reading order of each column in the storage array is sequential reading from the near end of the array to the far end of the array or from the far end of the array to the near end of the array, intermittent reading, or random reading.

[0015] Preferably, the address control unit includes an address sampling unit, an address driving unit, a logic control unit, a gating unit, and at least one delay module; wherein, the address sampling unit samples the original address signal according to the sampling clock signal, the address driving unit drives the sampled address signal, and outputs the driven address signal to the decoder; the logic control unit divides the storage array into at least two segments according to at least one of the original address signal, the sampled address signal, and the driven address signal, and outputs corresponding control signals for each segment; the gating unit selects the original sampling clock signal or the sampling clock signal delayed by the delay module according to the control signal and provides it to the address sampling unit for sampling.

[0016] Preferably, the sampling clock signal near the far end of the array is the original clock signal, and the sampling clock signal near the near end of the array is the clock signal delayed by the delay module. The closer the sampling clock signal is to the near end of the array, the greater the delay.

[0017] Preferably, the readout control unit includes a clock control unit and a differential amplifier. The clock control unit receives an input clock signal and generates an enable signal for the differential amplifier. The effective discharge time of the differential amplifier is controlled by the readout enable signal of the decoder and the enable signal for the differential amplifier.

[0018] Preferably, the input clock signal and the original sampling clock signal are the same clock signal.

[0019] Another aspect of the present invention provides a data readout circuit for an image sensor storage array, including an address control unit, a decoder, a storage array, and a readout control unit; the decoder decodes the address signal provided by the address control unit and provides readout enable signals for each column in the storage array, so that the data in each column of the storage array can be read out by the readout control unit; wherein, the voltage, width, or phase of the readout enable signal of each column is adjusted according to the distance between each column in the storage array and the readout control unit to compensate for the readout enable signal delay generated during the decoding process.

[0020] Preferably, in the storage array, the end closer to the read control unit is the near end of the array, and the end farther from the read control unit is the far end of the array. The phase of the read enable signal of each column is adjusted by the address control unit so that the voltage difference of each column is approximately equal.

[0021] Preferably, the address control unit uses sampling clock signals of different phases to sample the original address signal and outputs it to the decoder. The sampling clock signal near the far end of the array is relatively earlier than the sampling clock signal near the near end of the array, thereby adjusting the phase of the readout enable signal of each column.

[0022] Preferably, the address control unit receives raw address signals of different phases and outputs them to the decoder after sampling. The raw address signals near the far end of the array are relatively earlier than the raw address signals near the near end of the array, thereby adjusting the phase of the readout enable signal of each column.

[0023] Preferably, the data reading order of each column in the storage array is sequential reading from the near end of the array to the far end of the array or from the far end of the array to the near end of the array, intermittent reading, or random reading.

[0024] Preferably, the address control unit includes an address sampling unit, an address driving unit, a logic control unit, a gating unit, and at least one delay module; wherein, the address sampling unit samples the original address signal according to the sampling clock signal, the address driving unit drives the sampled address signal, and outputs the driven address signal to the decoder; the logic control unit divides the storage array into at least two segments according to at least one of the original address signal, the sampled address signal, and the driven address signal, and outputs corresponding control signals for each segment; the gating unit selects the original sampling clock signal or the sampling clock signal delayed by the delay module according to the control signal and provides it to the address sampling unit for sampling.

[0025] Preferably, the sampling clock signal near the far end of the array is the original clock signal, and the sampling clock signal near the near end of the array is the clock signal delayed by the delay module. The closer the sampling clock signal is to the near end of the array, the greater the delay.

[0026] Preferably, the readout control unit includes a clock control unit and a differential amplifier. The clock control unit receives an input clock signal and generates an enable signal for the differential amplifier. The effective discharge time of the differential amplifier is controlled by the readout enable signal of the decoder and the enable signal for the differential amplifier.

[0027] Preferably, the input clock signal and the original sampling clock signal are the same clock signal.

[0028] The image sensor storage array data readout method and readout circuit of the present invention adjust the voltage, width or phase of the readout enable signal of each column according to the distance between each column in the storage array and the readout control unit, so as to compensate for the readout enable signal delay generated during the decoding process, reduce the difference between the near and far ends of the array without increasing the chip area and power consumption, increase the effective readout time of the far end of the array while maintaining the original readout frequency, increase the discharge voltage difference, and improve the operating frequency. Attached Figure Description

[0029] Figure 1 A schematic diagram of the data readout circuit of a prior art image sensor storage array; Figure 2 for Figure 1 A schematic diagram of the readout control unit; Figure 3 This is a schematic diagram of the data readout circuit of the image sensor storage array of the present invention; Figure 4 for Figure 3 A schematic diagram of the structure of one embodiment of the address control unit; Figure 5 According to Figure 4 Signal timing diagram of the address control unit in the embodiment; Figure 6 According to Figure 4 Signal timing diagram of each column of the storage array in the embodiment; Figure 7 for Figure 3 A schematic diagram of another embodiment of the address control unit; Figure 8 According to Figure 7 A signal timing diagram of the address control unit in the embodiment; Figure 9 According to Figure 7 Another signal timing diagram of the address control unit in the embodiment. Detailed Implementation

[0030] Numerous specific details are set forth in the following description to provide a full understanding of the invention. However, the invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0031] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, the schematic diagrams are merely examples for ease of explanation and should not limit the scope of protection of the present invention.

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be described in detail below with reference to the accompanying drawings.

[0033] The data readout method and readout circuit of the image sensor storage array of the present invention mainly compensate for the readout enable signal delay generated during the decoding process by enabling each column of the entire storage array to obtain readout enable signals of different intensities, such as setting different voltages, different widths, and different phase relationships for the readout enable signals of each column. This increases the effective readout time at the far end of the array, increases the discharge voltage difference, and makes the discharge voltage difference of each column approximately equal. Thus, the same readout control unit can be compatible with the entire storage array. Regardless of whether each column in the storage array is far or near the readout control unit, high performance can be achieved at a lower cost.

[0034] Figure 3 This illustration shows an embodiment of the data readout circuit for the image sensor storage array of the present invention, including an address control unit 201, a decoder 202, a storage array 203, and a readout control unit 204, wherein the decoder 202 reads the address signal ADDR provided by the address control unit 201. <i:0>After decoding, a read enable signal WL is provided to each column in the storage array 203. Each column of the storage array 203 discharges BL / BLb, and the resulting Data is generated in the read control unit 204, so that the data in each column of the storage array 203 can be read out through the read control unit 204. Unlike the prior art, the present invention adjusts the voltage, width, or phase of the read enable signal WL of each column according to the distance between each column in the storage array 203 and the read control unit 204, thereby compensating for the read enable signal delay generated during the decoding process and achieving approximately equal discharge voltage differences in each column.

[0035] exist Figure 3 In the embodiment shown, the phase of the read enable signal WL of each column in the memory array 203 can be adjusted by the address control unit 201 so that the voltage difference of each column is approximately equal.

[0036] like Figure 4 As shown, the address control unit 201 includes an address sampling unit 2011 and an address driving unit 2012; wherein, the address sampling unit 2011 processes the original address signal A according to the sampling clock signal clk_a. <i:0>Perform sampling and output the sampled address signal AS. <i:0>The address driving unit 2012 processes the sampled address signal AS <i:0>Perform the drive and output the address signal ADDR after the drive. <i:0>Give decoder 202.

[0037] The address control unit 201 further includes a logic control unit 2013, a gating unit 2014, and a delay module 2015. The delay module 2015 receives the original sampling clock signal clk and generates a delayed sampling clock signal clk_delay. The logic control unit 2013 then selects the original address signal A. <i:0>Sampling address signal AS <i:0>Address signal ADDR after driving <i:0>At least one of the components divides the storage array 203 into at least two segments, each outputting a corresponding control signal SW to control the gating unit 2014. For example, the logic control unit 2013 can change the value of SW when the address is greater than a certain value, thereby dividing the entire address into two segments, each sampled using a different clock. The gating unit 2014 selects the original sampling clock signal clk or the delayed sampling clock signal clk_delay as the sampling clock signal clk_a according to the corresponding control signal SW and provides it to the address sampling unit 2011. The address sampling unit 2011 samples according to the sampling clock signal clk_a. The storage array 203 has its near end 203a, closer to the read control unit 204, designated as the near end, and its far end 203b, designated as the far end. By setting the sampling clock signal clk_a near the far end 203b to be earlier than the sampling clock signal clk_a near the near end 203a—for example, the sampling clock signal clk_a near the far end 203b being the original clock signal clk, and the sampling clock signal clk_a near the near end 203a being the clock signal clk_delay delayed by the delay module 2015—the address signal ADDR driven from the far end 203b can be made more efficient. <i:0>The address signal ADDR after driving is closer to the array near the 203a. <i:0>The phase of the readout enable signal WL of each column is adjusted relatively early to compensate for the delay of the readout enable signal WL near the far end of the array 203b.

[0038] exist Figure 4 In this embodiment, the logic control unit 2013 uses the sampled address signal AS <i:0>The corresponding control signal SW is output to select different sampling clock signals clk_a. In other embodiments not shown, the logic control unit 2013 can also select based on the original address signal A. <i:0>Or the address signal ADDR after the driver <i:0>To select different sampling clock signals clk_a, simply change the original address signal A. <i:0>Or the address signal ADDR after the driver <i:0>Simply connect it to the input terminal of the logic control unit 2013.

[0039] Figure 5 It shows according to Figure 4 The timing relationship between the sampling address signal and the sampling clock signal in the structural design, where A <i:0>The original address signal is clk, the original sampling clock signal is clk_delay, the sampling clock signal is delayed by the delay module 2015, and clk_a is... Figure 4 The sampling clock signal output by the gating module 2014. When the sampled address is less than a certain value (e.g., n), the logic control unit 2013 outputs a SW value. The gating module 2014 selects the sampling clock signal clk_delay, delayed by the delay module 2015, as the sampling clock signal clk_a based on this SW value. When the sampled address reaches n, the SW value is changed, and the sampling clock signal clk_a switches to the original sampling clock signal clk that has not been delayed by the delay module 2014. Thus, the sampled address AS... <i:0>Starting from n+1, the delay time of the delay module is advanced by a certain amount as the sampling clock signal clk_a advances, and the sampling time of the nth address is shortened.

[0040] Figure 6 The timing relationship between decoder 202 and the near-far end differences of memory array 203 is shown. In the conventional mode, due to the large size of memory array 203, the address signal ADDR output by address control unit 201... <i:0>The delay from the near end 203a to the far end 203b increases, and correspondingly, the difference in the read enable signal WL output by the decoder 202 increases. The read control unit typically includes a clock control unit and a differential amplifier. The clock control unit receives the input clock signal and generates the differential amplifier's enable signal sen. The input clock signal of the differential amplifier can be the same clock signal clk as the original sampling clock signal. The effective discharge time of the differential amplifier is controlled by the decoder's read enable signal WL and the differential amplifier's enable signal sen. For example, the effective discharge time of each column in the memory array 203 is from the rising edge of the column's read enable signal WL to the falling edge of the differential amplifier's enable signal sen. Since the differential amplifier is also located on one side of the memory array 203, and its timing does not change due to different addresses, the delay of the far-end read enable signal WL reduces the effective discharge time because the discharge of BL is invalid after the falling edge of the differential amplifier's enable signal sen, i.e., after the differential amplifier has started operating. Figure 4 After the address control unit 201, starting from the nth column, the sampling clock signal clk_a is switched. The effective discharge time of the nth column remains unchanged, but starting from the n+1th column, the read enable signal WL of subsequent columns is advanced due to the address sampling. The reduction in discharge time caused by the address delay can be made up, thereby increasing the effective read time at the far end of the array, increasing the discharge voltage difference, and improving the operating frequency.

[0041] Figure 7 It shows Figure 3 Another embodiment of the address control unit 201 includes an address sampling unit 2011, an address driving unit 2012, a logic control unit 2013, a gating unit 2014, delay modules 2015-1, 2015-2, ..., 2015-k, where k ≥ 2. The delayed sampling clock signals clk_delay generated by the multiple delay modules 2015 are all different. For example, the delay from delay module 2015-1 to delay module 2015-k increases progressively. Of course, it's also possible that the delay of delay module 2015-1 is zero, i.e., the original sampling clock signal clk is output. The logic control unit 2013 receives the sampled address signal AS. <i:0>And generate a multi-bit control signal SW <m:0>Used to control the gating unit 2014 (where,), the gating module 2014 is based on the multi-bit control signal SW <m:0>The original sampling clock signal clk or the sampling clock signal clk_delay after arbitrary delay is selected as the output, i.e., the selected sampling clock signal clk_a, and transmitted to the address sampling unit 2011 for sampling. The address driving unit 2012 receives the sampled address signal AS output by the address sampling unit 2011. <i:0>And output the address signal ADDR after driving. <i:0>Give decoder 202.

[0042] Among them, the logic control unit 2013 can switch the SW when the address is in a certain range. <m:0>By setting a certain value, a specific delay module is selected, thereby dividing the entire address into several segments. Each segment is sampled using a sampling clock signal with a different delay. The sampling clock signal closer to the array's near end 203a has a larger delay, while the sampling clock signal closer to the array's far end 203b has a smaller delay. This ensures that the address signal ADDR after driving the signal closer to the array's far end 203b... <i:0>The address signal ADDR after driving is closer to the array near the 203a. <i:0>The phase of the readout enable signal WL for each column is adjusted relatively early to compensate for the delay of the readout enable signal WL near the far end of the array 203b. Compared to the two-segment method in the previous embodiment, multi-segmentation can improve the adjustment accuracy of the sampling clock signal delay, allowing for a larger effective discharge time in any column, thereby improving readout performance. Those skilled in the art can choose the segmentation method and number according to actual needs, and can even choose one delay module for each column, that is, the phase of the sampling clock signal for each column can be adjusted independently to obtain the highest accuracy, but this increases circuit complexity and chip area accordingly.

[0043] Similarly, in other embodiments not shown, the logic control unit 2013 can also base its logic on the original address signal A. <i:0>Or the address signal ADDR after the driver <i:0>To select different sampling clock signals clk_a, simply change the original address signal A. <i:0>Or the address signal ADDR after the driver <i:0>Simply connect it to the input terminal of the logic control unit 2013.

[0044] Figure 8 It shows according to Figure 7 The timing relationship between the sampling address and the sampling clock in the embodiment is designed as follows: In the storage array 203 of this embodiment, the data reading order is from the near end 203a of the array to the far end 203b of the array, for example, from column 0 to column n and then to column p... Taking the setting of 3 delay modules to divide the entire address into 3 segments as an example, clk_delay1, clk_delay2, and clk_delay3 are the original sampling clock signal clk after being delayed by delay modules 2015-1, 2015-2, and 2015-3, respectively. The delays of clk_delay1, clk_delay2, and clk_delay3 increase sequentially. <i:0>The sampled address signal, clk_a is Figure 7 The sampling clock signal output by the central selection module 2014. When the sampled address signal AS... <i:0>When the value is less than a certain value (e.g., n), the logic control unit 2013 outputs a control signal SW. <m:0>For example, j-1, the gating module 2014 is based on SW. <m:0>The sampling clock signal is selected after being delayed by a certain delay module. For example, the sampling clock signal clk_delay3 after being delayed by delay module 2015-3 is used as the sampling clock signal clk_a; when the sampled address signal AS... <i:0>After n is reached, the logic control unit 2013 outputs the control signal SW. <m:0>The value is changed, for example, switching from j-1 to j. The sampling clock signal clk_a is switched to the output clock of another delay module, for example, the sampling clock signal clk_delay2 after passing through the delay module 2015-2. Therefore, the sampled address SW <m:0>Starting from n+1, the sampling clock signal clk_delay2 is advanced by a certain time, and this time difference is the delay time difference between clk_delay3 and clk_delay2, with the time for the nth address shortened; when the sampled address signal AS... <i:0>Continuing the traversal to, for example, p, SW <m:0>If the value is changed again, for example from j to j+1, the sampling clock signal clk_a will switch to the output clock of the delay module at another level. For example, the sampling clock signal clk_delay1 after delay module 2015-1 will be the sampled address SW. <m:0>Starting from p+1, the sampling clock signal clk_delay1 is advanced again by a certain time. This time difference is the delay time difference between clk_delay2 and clk_delay1, and the time for the p-th address is shortened. If the number of delay modules continues to increase, the control signal SW... <m:0>The sampling clock signal clk_a can also continue to switch accordingly.

[0045] Figure 9 It shows according to Figure 7 Another timing relationship in the embodiment is as follows: In the storage array 203 of this embodiment, the data reading order is from the far end 203b of the array to the near end 203a of the array, for example, from column p to column n and then to column 0... Taking the example of setting 3 delay modules to divide the entire address into 3 segments, the delays of clk_delay1, clk_delay2, and clk_delay3 increase sequentially. When the sampled address signal AS... <i:0>When the value is greater than a certain value (e.g., p), the logic control unit 2013 outputs a control signal SW. <m:0>For example, if it is j+1, the gating module 2014 is based on SW. <m:0>Select clk_delay1 as the sampling clock signal clk_a; when the sampled address signal AS... <i:0>After reaching p, the logic control unit 2013 outputs the control signal SW. <m:0>When a value is changed, for example, from j+1 to j, the sampling clock signal clk_a is changed to clk_delay2. Therefore, the sampled address SW... <m:0>Starting from p-1, the sampling clock signal clk_delay2 is delayed by a certain period of time. This time difference is the delay time difference between clk_delay2 and clk_delay1, and the time for the p-th address is extended; when the sampled address signal AS... <i:0>Continue iterating to, for example, n, SW <m:0>If the value is changed again, for example from j to j-1, the sampling clock signal clk_a is changed to clk_delay3 again, and the sampled address SW... <m:0>Starting from address n-1, the sampling clock signal clk_delay3 is delayed again for a period of time. This time difference is the delay time difference between clk_delay3 and clk_delay2, and the time for the nth address is extended. If the number of delay modules continues to increase, the control signal SW... <m:0>The sampling clock signal clk_a can also continue to switch accordingly.

[0046] It is important to note that, Figure 8 In the embodiment, when the sampling clock signal clk_a switches from a path with a longer delay to a path with a shorter delay, SW <m:0>Switching must be done on the rising edge of the clock; while Figure 9 In the embodiment, when the sampling clock signal clk_a switches from a path with a shorter delay to a path with a longer delay, SW <m:0>Switching must be done on the falling edge of the clock; otherwise, timing errors will occur.

[0047] Besides the above embodiments where the data reading order is sequential from the near end of the array to the far end or from the far end to the near end, in other embodiments not shown, the data can also be read intermittently or randomly from the near end to the far end or from the far end to the near end. Regardless of the reading order, by setting the sampling clock signal clk_a near the far end of the array 203b to be relatively earlier than the sampling clock signal clk_a near the near end of the array 203b, the address signal ADDR after driving the signal near the far end of the array 203b can be made to be earlier. <i:0>The address signal ADDR after driving is closer to the array near the 203a. <i:0>The phase of the readout enable signal WL of each column is adjusted relatively early to compensate for the delay of the readout enable signal WL near the far end of the array 203b.

[0048] In addition to adjusting the phase of the enable signal WL by using sampling clock signals clk_a with different phases in the above embodiments, the phase of the original address signal A can also be adjusted by using original address signals A with different phases. <i:0>The phase of the enable signal WL is adjusted in this way. For example, if the address control unit 201 receives the original address signal A... <i:0>Since the signals already have different phases, the ADDR address signal, after sampling and driving, is output to the decoder. <i:0>Naturally, they also have different phases, so the original address signal A, which is closer to the far end of array 203b, can be set. <i:0>Compared to the original address signal A near the array near end 203a <i:0>The relatively early timing allows the address signal ADDR, driven near the far end of the array 203b, to be driven earlier. <i:0>It is also closer to the address signal ADDR after driving the array near the near end 203a. <i:0>The phase of the readout enable signal WL of each column is adjusted relatively early to compensate for the delay of the readout enable signal WL near the far end of the array 203b.

[0049] In summary, the data readout method and readout circuit of the image sensor storage array of the present invention adjust the voltage, width, or phase of the readout enable signal of each column according to the distance between each column in the storage array and the readout control unit, so as to compensate for the readout enable signal delay generated during the decoding process. Under the premise of minimizing the increase in chip area and power consumption, the difference between the near and far ends of the array is reduced. While maintaining the original readout frequency, the effective readout time of the far end of the array is increased, the discharge voltage difference is increased, and the operating frequency is improved.

[0050] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for reading data from an image sensor storage array, characterized in that, include: After decoding the address signal provided by the address control unit, the decoder provides read enable signals for each column in the storage array, so that the data in each column of the storage array can be read out by the read control unit. Specifically, the voltage, width, or phase of the read enable signal of each column is adjusted according to the distance between each column in the storage array and the read control unit to compensate for the read enable signal delay generated during the decoding process.

2. The data readout method for an image sensor storage array as described in claim 1, characterized in that, In the storage array, the end closer to the read control unit is the array near end, and the end farther from the read control unit is the array far end. The phase of the read enable signal of each column is adjusted by the address control unit so that the voltage difference of each column is approximately equal.

3. The data readout method for an image sensor storage array as described in claim 2, characterized in that, The address control unit uses sampling clock signals of different phases to sample the original address signal and outputs it to the decoder. The sampling clock signal near the far end of the array is relatively earlier than the sampling clock signal near the near end of the array, thereby adjusting the phase of the readout enable signal of each column.

4. The data readout method for an image sensor storage array as described in claim 2, characterized in that, The address control unit receives raw address signals of different phases and outputs them to the decoder after sampling. The raw address signals closer to the far end of the array are relatively earlier than those closer to the near end of the array, thereby adjusting the phase of the readout enable signal of each column.

5. The data readout method for an image sensor storage array as described in claim 2, characterized in that, The data reading order of each column in the storage array is sequential reading from the near end of the array to the far end of the array or from the far end of the array to the near end of the array, intermittent reading, or random reading.

6. The data readout method for an image sensor storage array as described in claim 3, characterized in that, The address control unit includes an address sampling unit, an address driving unit, a logic control unit, a gating unit, and at least one delay module; The address sampling unit samples the original address signal according to the sampling clock signal, the address driving unit drives the sampled address signal, and outputs the driven address signal to the decoder. The logic control unit divides the memory array into at least two segments based on at least one of the original address signal, the sampled address signal, and the driven address signal, and outputs corresponding control signals for each segment. The gating unit selects the original sampling clock signal or the sampling clock signal delayed by the delay module based on the control signal and provides it to the address sampling unit for sampling.

7. The data readout method for an image sensor storage array as described in claim 6, characterized in that, The sampling clock signal near the far end of the array is the original clock signal, while the sampling clock signal near the near end of the array is the clock signal delayed by the delay module. The closer the sampling clock signal is to the near end of the array, the greater the delay.

8. The data readout method for an image sensor storage array as described in claim 6, characterized in that, The readout control unit includes a clock control unit and a differential amplifier. The clock control unit receives an input clock signal and generates an enable signal for the differential amplifier. The effective discharge time of the differential amplifier is controlled by the readout enable signal of the decoder and the enable signal for the differential amplifier.

9. The data readout method for an image sensor storage array as described in claim 8, characterized in that, The input clock signal is the same clock signal as the original sampling clock signal.

10. A data readout circuit for an image sensor storage array, characterized in that, Includes address control unit, decoder, memory array, and readout control unit; The decoder decodes the address signal provided by the address control unit and provides read enable signals for each column in the storage array, so that the data in each column of the storage array can be read out by the read control unit. Specifically, the voltage, width, or phase of the read enable signal of each column is adjusted according to the distance between each column in the storage array and the read control unit to compensate for the read enable signal delay generated during the decoding process.

11. The data readout circuit of the image sensor storage array as described in claim 10, characterized in that, In the storage array, the end closer to the read control unit is the array near end, and the end farther from the read control unit is the array far end. The phase of the read enable signal of each column is adjusted by the address control unit so that the voltage difference of each column is approximately equal.

12. The data readout circuit of the image sensor storage array as described in claim 11, characterized in that, The address control unit uses sampling clock signals of different phases to sample the original address signal and outputs it to the decoder. The sampling clock signal near the far end of the array is relatively earlier than the sampling clock signal near the near end of the array, thereby adjusting the phase of the readout enable signal of each column.

13. The data readout circuit of the image sensor storage array as described in claim 11, characterized in that, The address control unit receives raw address signals of different phases and outputs them to the decoder after sampling. The raw address signals closer to the far end of the array are relatively earlier than those closer to the near end of the array, thereby adjusting the phase of the readout enable signal of each column.

14. The data readout circuit of the image sensor storage array as described in claim 11, characterized in that, The data reading order of each column in the storage array is sequential reading from the near end of the array to the far end of the array or from the far end of the array to the near end of the array, intermittent reading, or random reading.

15. The data readout circuit of the image sensor storage array as described in claim 12, characterized in that, The address control unit includes an address sampling unit, an address driving unit, a logic control unit, a gating unit, and at least one delay module; The address sampling unit samples the original address signal according to the sampling clock signal, the address driving unit drives the sampled address signal, and outputs the driven address signal to the decoder. The logic control unit divides the memory array into at least two segments based on at least one of the original address signal, the sampled address signal, and the driven address signal, and outputs corresponding control signals for each segment. The gating unit selects the original sampling clock signal or the sampling clock signal delayed by the delay module based on the control signal and provides it to the address sampling unit for sampling.

16. The data readout circuit of the image sensor storage array as described in claim 15, characterized in that, The sampling clock signal near the far end of the array is the original clock signal, while the sampling clock signal near the near end of the array is the clock signal delayed by the delay module. The closer the sampling clock signal is to the near end of the array, the greater the delay.

17. The data readout circuit of the image sensor storage array as described in claim 15, characterized in that, The readout control unit includes a clock control unit and a differential amplifier. The clock control unit receives an input clock signal and generates an enable signal for the differential amplifier. The effective discharge time of the differential amplifier is controlled by the readout enable signal of the decoder and the enable signal for the differential amplifier.

18. The data readout circuit of the image sensor storage array as described in claim 17, characterized in that, The input clock signal is the same clock signal as the original sampling clock signal.

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