Process method for integrating multiple application voltage MOSFET devices

Abstract

The invention provides a process method for integrating a plurality of application voltage metal-oxide-semiconductor field effect transistor (MOSFET) devices. The method defines first, second and third voltage device regions on a semiconductor substrate. And when well regions required by the first and second voltage devices are formed, the first and second conduction type devices in the third voltage device region respectively borrow the corresponding well regions of the first or second voltage device. And opening a third voltage device region by using a newly added third application voltage photoetching mask, carrying out one-step threshold voltage regulation ion implantation, and simultaneously regulating threshold voltages of the two conduction type devices. And then forming a third gate dielectric layer and a gate structure. According to the invention, a high-performance medium-voltage device can be integrated with low cost on the basis of the existing double-gate oxide process only by adding a photomask and through ingenious well region borrowing and a single injection step.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a process method for integrating multiple application voltage MOSFET devices. Background Technology

[0002] As integrated circuit chips become increasingly complex, chip designs often require the integration of metal-oxide-semiconductor field-effect transistors (MOSFETs) with different application voltages to meet the needs of various circuit modules. Common process platforms include dual-gate oxide (DTO) technology, which typically integrates high-voltage and low-voltage devices on the same chip, or triple-gate oxide (TTO) technology, used to integrate devices with even more voltage levels.

[0003] In existing semiconductor manufacturing processes, each device for a specific application voltage typically requires specific well regions, threshold voltage regulation injection, gate dielectric layers, and lightly doped source / drain (LDD) structures to ensure its electrical performance. Therefore, integrating an additional device for a different application voltage into a chip usually requires adding 3 to 5 mask layers and corresponding photolithography, injection, and etching processes.

[0004] For example, if a medium-voltage device (e.g., a 3.3V device) is to be added to an existing Dual Gate process that includes both high-voltage and low-voltage devices, the traditional approach would require adding separate well injection masks, separate threshold adjustment masks, and dedicated LDD masks for both the NMOS and PMOS devices at this medium voltage. While this approach allows for independent control of the new device's performance, it significantly increases the number of masks, thereby substantially increasing process costs and production cycles, which is detrimental to the product's market competitiveness.

[0005] Therefore, how to flexibly integrate MOSFET devices with various application voltages on existing process platforms without significantly increasing the number of photomasks and process costs is a technical problem that urgently needs to be solved in the current semiconductor manufacturing field. Summary of the Invention

[0006] To address the problem that integrating an additional application voltage device into a chip in existing semiconductor manufacturing processes typically requires adding multiple photomasks (e.g., 3-5 layers), resulting in a significant increase in process costs and a longer production cycle, this invention provides a process method for integrating multiple application voltage MOSFET devices.

[0007] This invention provides a process method for integrating multiple application voltage MOSFET devices, the method comprising the following steps:

[0008] Step 1: Provide a semiconductor substrate, defining a first voltage device region, a second voltage device region, and a third voltage device region on the semiconductor substrate; the first voltage device region is used to form a device with a first application voltage, the second voltage device region is used to form a device with a second application voltage, and the third voltage device region is used to form a device with a third application voltage, wherein the first application voltage is higher than the third application voltage, and the third application voltage is higher than the second application voltage.

[0009] Step 2: Form a plurality of well regions required for the first voltage device and a plurality of well regions required for the second voltage device in the semiconductor substrate; wherein, the third voltage first conductivity type device in the third voltage device region borrows the first conductivity type well region of the first voltage device or the first conductivity type well region of the second voltage device, and the third voltage second conductivity type device in the third voltage device region borrows the second conductivity type well region of the second voltage device or the second conductivity type well region of the first voltage device.

[0010] Step 3: Form a first gate dielectric layer on the semiconductor substrate, and form a third application voltage photomask pattern using a photolithography process, and open the third voltage device region using the third application voltage photomask pattern;

[0011] Step 4: Using the third application voltage photolithography mask pattern as a barrier, perform threshold voltage-adjustable ion implantation on the third voltage device region; the threshold voltage-adjustable ion implantation forms a threshold adjustment layer, and simultaneously adjusts the threshold voltage of the third voltage first conductivity type device and the third voltage second conductivity type device;

[0012] Step 5: Remove the first gate dielectric layer in the third voltage device region and form a third gate dielectric layer;

[0013] Step 6: Deposit the gate conductive material and etch to form the gate structure.

[0014] Preferably, in step one, an isolation structure is formed on the semiconductor substrate to isolate the first voltage device region, the second voltage device region, and the third voltage device region from each other.

[0015] Preferably, in step one, the process of forming the isolation structure includes: growing a pre-oxide layer and a silicon nitride layer on the semiconductor substrate; forming the isolation structure using a shallow trench isolation process; and removing the silicon nitride layer.

[0016] Preferably, the first conductivity type is N-type, and the second conductivity type is P-type; the first conductivity type device is an N-type metal-oxide-semiconductor field-effect transistor, and the first conductivity type well region is a P-type well region.

[0017] Preferably, the first conductivity type is P-type, and the second conductivity type is N-type; the first conductivity type device is a P-type metal-oxide-semiconductor field-effect transistor, and the first conductivity type well region is an N-type well region.

[0018] Preferably, in step two, the first voltage device is a high-voltage device, the second voltage device is a low-voltage device, and the third voltage device is a medium-voltage device; the third voltage first conductivity type device borrows the first conductivity type well region of the first voltage device; and the third voltage second conductivity type device borrows the second conductivity type well region of the second voltage device.

[0019] Preferably, in step four, the impurity type of the threshold voltage-adjustable ion implantation is a P-type impurity; by adjusting the threshold voltage ion implantation, the threshold voltage of the third voltage first conductivity type device is increased, while the threshold voltage of the third voltage second conductivity type device is decreased.

[0020] Preferably, in step four, the impurity type of the threshold voltage-regulated ion implantation is an N-type impurity; wherein, in step two, the third voltage first conductivity type device borrows the first conductivity type well region of the second voltage device; and the third voltage second conductivity type device borrows the second conductivity type well region of the first voltage device.

[0021] Preferably, the P-type impurity is boron.

[0022] Preferably, the process parameters for threshold voltage-regulated ion implantation include: implantation energy of 5 keV to 50 keV, implantation dose of 5.0e11 to 1.0e13, and implantation angle of 0° to 10°.

[0023] Preferably, in step three, the first gate dielectric layer is a silicon oxide layer.

[0024] Preferably, in step five, after removing the first gate dielectric layer of the third voltage device region, the third applied voltage photolithography mask pattern is removed; then, the third gate dielectric layer is grown by a thermal oxidation process; the thickness of the third gate dielectric layer of the third voltage device region is between the thickness of the gate dielectric layer of the first voltage device region and the thickness of the gate dielectric layer of the second voltage device region.

[0025] Preferably, the method further includes step seven: performing light doping drain implantation of the first conductivity type on the third voltage first conductivity type device, and performing light doping drain implantation of the second conductivity type on the third voltage second conductivity type device; wherein, the third voltage first conductivity type device utilizes the first conductivity type light doping drain implantation process of the first voltage first conductivity type device; and the third voltage second conductivity type device utilizes the second conductivity type light doping drain implantation process of the first voltage second conductivity type device.

[0026] Preferably, the method further includes step eight: forming sidewall dielectric layers on both sides of the gate structure, and performing ion implantation using the gate structure and the sidewall dielectric layers as masks; wherein, the first conductivity type device of the third voltage is subjected to heavy doping source / drain implantation of the first conductivity type to form a first conductivity type source / drain region; and the second conductivity type device of the third voltage is subjected to heavy doping source / drain implantation of the second conductivity type to form a second conductivity type source / drain region.

[0027] As described above, the process method for integrating multiple application voltage MOSFET devices of the present invention has the following beneficial effects:

[0028] This invention, based on existing Dual Gate technology, requires only the addition of a photomask (TGO mask). Through a well region borrowing strategy (e.g., borrowing high- or low-voltage well regions for medium-voltage devices) and a crucial threshold voltage adjustment injection step, the threshold voltages of newly added medium-voltage N-type and P-type devices can be simultaneously adjusted to the target range. Specifically, by utilizing the concentration difference between high-voltage and low-voltage well injections, combined with single-type impurity injection (P-type or N-type), the threshold voltage of one type of conductivity device can be increased, while the absolute value of the threshold voltage of another type of conductivity device can be decreased, thus avoiding the cumbersome process of adding separate photomasks for each type of device. Furthermore, by borrowing LDD injection from high-voltage devices, the breakdown voltage characteristics of the newly added medium-voltage devices are effectively improved. Ultimately, this invention achieves the goal of low-cost integration of a third application voltage device without significantly increasing process complexity and cost. Attached Figure Description

[0029] Figure 1 The diagram shows a process flow diagram of a method for integrating multiple application voltage MOSFET devices according to the present invention.

[0030] Figure 2 The diagram shows a schematic of the device structure after the isolation structure is formed in the process method of integrating multiple application voltage MOSFET devices according to the present invention.

[0031] Figure 3 The diagram shows a schematic of the device structure after the well region is formed in the process method of integrating multiple application voltage MOSFET devices according to the present invention.

[0032] Figure 4 The diagram shows a schematic of the device structure after threshold voltage regulation ion implantation in a process method for integrating multiple application voltage MOSFET devices according to the present invention.

[0033] Figure 5 The diagram shows a schematic of the device structure after the gate structure is formed in the process method of integrating multiple application voltage MOSFET devices according to the present invention.

[0034] Figure 6 The diagram shows a schematic of the device structure after forming a lightly doped drain region in a process method for integrating multiple application voltage MOSFET devices according to the present invention.

[0035] Figure 7 The diagram shown is a schematic of the device structure after the source-drain structure is formed in the process method of integrating multiple application voltage MOSFET devices according to the present invention. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] This invention provides a process method for integrating multiple application voltage MOSFET devices. Figure 1 This is a flow chart of the process. The method includes the following steps:

[0038] Step 1: Provide a semiconductor substrate 101, and define a first voltage device region, a second voltage device region, and a third voltage device region on the semiconductor substrate 101. The first voltage device region is used to form a device with a first application voltage, the second voltage device region is used to form a device with a second application voltage, and the third voltage device region is used to form a device with a third application voltage, wherein the first application voltage is higher than the third application voltage, and the third application voltage is higher than the second application voltage. By dividing the different voltage device regions, the requirement to integrate different functional modules on the same chip can be met. For example, the power management module uses the first voltage device, the digital logic module uses the second voltage device, and the analog or interface module uses the third voltage device, thereby improving the system integration.

[0039] In some embodiments, the semiconductor substrate 101 may include elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 101 may also include various doping configurations, depending on design requirements, such as a P-type substrate or an N-type substrate.

[0040] In some embodiments, in step one, an isolation structure 102 is formed on the semiconductor substrate 101 to isolate the first voltage device region, the second voltage device region, and the third voltage device region from each other.

[0041] In some embodiments, step one, the process of forming the isolation structure 102, includes: growing a front oxide layer 201 and a silicon nitride layer 202 on a semiconductor substrate 101; forming the isolation structure 102 using a shallow trench isolation process; and removing the silicon nitride layer 202. Please refer to [link to previous text]. Figure 2 , Figure 2 This is a schematic diagram of the device structure after the isolation structure is formed. (Example) Figure 2 As shown, a front oxide layer 201 and a silicon nitride layer 202 are grown on a semiconductor substrate 101; an isolation structure 102 is formed using a shallow trench isolation process; and the silicon nitride layer 202 is removed. The front oxide layer 201 can be formed by a thermal oxidation process or a chemical vapor deposition (CVD) process, and its material can be silicon oxide, used to relieve stress. The silicon nitride layer 202 can be formed by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), serving as a stop layer for subsequent planarization processes. The shallow trench isolation (STI) process includes photolithographic patterning, etching the substrate to form trenches, and depositing a dielectric material to fill the trenches. The filling material can include high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS) oxide, or high aspect ratio process (HARP) oxide. After deposition, excess dielectric material can be removed by chemical mechanical polishing (CMP) and silicon nitride layer 202 can be removed by wet etching with phosphoric acid, thereby forming a flat isolation structure 102, which effectively prevents latch-up effect and leakage current between different voltage domains.

[0042] Step 2: Form a plurality of well regions required for the first voltage device and a plurality of well regions required for the second voltage device in the semiconductor substrate 101; wherein, a third voltage first conductivity type device in the third voltage device region borrows a first conductivity type well region of the first voltage device or a first conductivity type well region of the second voltage device, and a third voltage second conductivity type device in the third voltage device region borrows a second conductivity type well region of the second voltage device or a second conductivity type well region of the first voltage device. Please refer to... Figure 3 , Figure 3 This is a schematic diagram of the device structure after the well region is formed. (See attached diagram.) Figure 3 As shown, using the existing mask and implantation process in the Dual Gate process, a first conductivity type well region 103 and a second conductivity type well region 104 are formed in the semiconductor substrate 101. This step makes full use of the existing high-voltage and low-voltage well resources in the existing process platform, eliminating the need to develop a dedicated well implantation mask for the newly added medium-voltage device, thereby saving photomask costs and simplifying the process flow.

[0043] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type; the first conductivity type device is an N-type metal-oxide-semiconductor field-effect transistor, and the first conductivity type well region is a P-type well region 103. The P-type well region 103 can be formed by implanting a P-type dopant, such as boron (B), boron difluoride (BF2), or indium (In).

[0044] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type; the first conductivity type device is a P-type metal-oxide-semiconductor field-effect transistor, and the first conductivity type well region is an N-type well region 104. The N-type well region 104 can be formed by implanting an N-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb).

[0045] In some embodiments, in step two, the first voltage device is a high-voltage device, the second voltage device is a low-voltage device, and the third voltage device is a medium-voltage device; the third voltage first conductivity type device borrows the first conductivity type well region 103 of the first voltage device; the third voltage second conductivity type device borrows the second conductivity type well region 104 of the second voltage device. For example... Figure 3 As shown, the medium-voltage NMOS device is disposed in the high-voltage P-type well region 103, and the medium-voltage PMOS device is disposed in the low-voltage N-type well region 104. The wells of high-voltage devices are typically designed with deeper junction depths and lower density to withstand high breakdown voltages, while the wells of low-voltage devices have higher density to suppress punch-through. By utilizing high-voltage wells in conjunction with subsequent regulation injection, or by using low-voltage wells for reverse compensation, medium-voltage devices can be flexibly adjusted within the existing process window to achieve the threshold voltage and withstand voltage characteristics required for medium-voltage applications.

[0046] Step 3: Form a first gate dielectric layer 203 on the semiconductor substrate 101, and form a third application voltage photomask pattern using a photolithography process, and open the third voltage device region using the third application voltage photomask pattern.

[0047] In some embodiments, in step three, the first gate dielectric layer 203 is a silicon oxide layer. The first gate dielectric layer 203 may be a gate dielectric layer retained in the high-voltage device region, or a sacrificial oxide layer specifically grown for the implantation process. Its formation methods include thermal oxidation, in-situ water vapor generation (ISSG) oxidation, or atomic layer deposition (ALD).

[0048] Step 4: Using the third applied voltage photolithographic mask pattern as a barrier, perform threshold voltage-adjusted ion implantation on the third voltage device region; the threshold voltage-adjusted ion implantation forms a threshold adjustment layer 105, simultaneously adjusting the threshold voltages of the first conductivity type device and the second conductivity type device of the third voltage. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a schematic diagram of the device structure after threshold voltage-regulated ion implantation.

[0049] Please see Figure 4 , Figure 4 This is a schematic diagram of the device structure after threshold voltage-regulated ion implantation. Figure 4 As shown, a threshold adjustment layer 105 is formed below the first gate dielectric layer 203. By adding this TGO mask, precise threshold voltage (Vt) adjustment can be performed simultaneously for both medium-voltage NMOS and PMOS. Due to the use of specific well region borrowing combinations (e.g., high-voltage P-well 103 for medium-voltage NMOS and low-voltage N-well 104 for medium-voltage PMOS), a single type of impurity implantation can simultaneously meet the Vt requirements of both devices, avoiding the cumbersome process of using two separate masks for N-type and P-type Vt adjustment.

[0050] In some embodiments, in step four, the impurity type of the threshold voltage-regulated ion implantation is a P-type impurity. In this embodiment, the third voltage first conductivity type device (e.g., a medium-voltage NMOS) borrows the first conductivity type well region (e.g., a high-voltage P-type well) of the first voltage device (e.g., a high-voltage device); the third voltage second conductivity type device (e.g., a medium-voltage PMOS) borrows the second conductivity type well region (e.g., a low-voltage N-type well) of the second voltage device (e.g., a low-voltage device).

[0051] This specific combination and injection type selection is based on the following device physics mechanisms:

[0052] For medium-voltage NMOS devices, when they borrow the P-type well region of the first voltage device (high-voltage device), the high-voltage P-type well region is usually designed with a low doping concentration to withstand high voltage. This results in a low hole concentration at the channel surface of the medium-voltage NMOS, leading to a low initial threshold voltage (e.g., perhaps only around 0.25V, resulting in excessive leakage current). In this case, by injecting P-type impurities (acceptor impurities), the P-type doping concentration at the channel surface is increased, increasing the gate voltage required for inversion during channel turn-on. This effectively raises the threshold voltage of the medium-voltage NMOS, bringing it to the design target (e.g., around 0.7V).

[0053] For medium-voltage PMOS devices, when they utilize the N-type well region of a second voltage device (low-voltage device), the low-voltage N-type well region typically has a high doping concentration to suppress punch-through effects. This leads to a higher absolute value of the initial threshold voltage of the medium-voltage PMOS (e.g., potentially reaching around -1.0V, resulting in decreased drive capability). In this case, the P-type impurities implanted through the same step described above, due to their opposite polarity to the donor impurities in the N-type well, will generate a reverse doping or compensation effect at the channel surface, reducing the net N-type concentration at the channel surface. This reduction in net concentration makes inversion more likely at the channel surface, thereby lowering the absolute value of the medium-voltage PMOS threshold voltage (e.g., adjusting it to around -0.7V) and improving the device's switching speed.

[0054] Therefore, this implementation fully utilizes the characteristics of "low concentration in high-voltage traps and high concentration in low-voltage traps". By combining "low-concentration traps for NMOS and high-concentration traps for PMOS" with a single "P-type" regulated injection, it successfully achieves synchronous and unidirectional (referring to the direction of performance optimization) correction of the threshold voltages of the two devices.

[0055] In some embodiments, the p-type impurity is boron or boron difluoride (BF2). Boron has a small atomic radius, making it suitable for shallow junction implantation by controlling the energy. In some embodiments, the process parameters for threshold voltage-regulated ion implantation include: implantation energy of 5 keV to 50 keV, implantation dose of 5.0e11 to 1.0e13, and implantation angle of 0° to 10°. The energy range of 5 keV to 50 keV is chosen to precisely control the impurity near the channel surface and effectively regulate the turn-on voltage; the dose range of 5.0e11 to 1.0e13 provides sufficient threshold shift while avoiding carrier mobility degradation caused by excessively high doses.

[0056] In some embodiments, in step four, the impurity type of the threshold voltage-regulated ion implantation is an N-type impurity. In this embodiment, the third voltage first conductivity type device (e.g., a medium-voltage NMOS) borrows the first conductivity type well region (e.g., a low-voltage P-type well) of the second voltage device (e.g., a low-voltage device); the third voltage second conductivity type device (e.g., a medium-voltage PMOS) borrows the second conductivity type well region (e.g., a high-voltage N-type well) of the first voltage device (e.g., a high-voltage device).

[0057] This specific combination and injection type selection is based on the following device physics mechanisms:

[0058] For medium-voltage NMOS devices, when they borrow the P-type well region of a second voltage device (low-voltage device), the low-voltage P-type well region typically has a high doping concentration to suppress short-channel effects. This leads to a higher initial threshold voltage of the medium-voltage NMOS (e.g., possibly higher than 1.0V, exceeding the design target of around 0.7V). In this case, by implanting N-type impurities (e.g., phosphorus or arsenic), inversion doping or a compensation effect can be formed on the channel surface, neutralizing some of the P-type impurities and reducing the net P-type concentration at the channel surface. This effectively lowers the threshold voltage of the medium-voltage NMOS, bringing it back to the target range.

[0059] For medium-voltage PMOS devices, when they borrow the N-type well region of the first voltage device (high-voltage device), the high-voltage N-type well region is usually designed with a low doping concentration to ensure a high breakdown voltage. This results in a lower absolute value of the initial threshold voltage of the medium-voltage PMOS (e.g., perhaps only around -0.3V, making it prone to false turn-on). At this time, the N-type impurities injected through the same step mentioned above will further increase the N-type impurity concentration on the channel surface (i.e., increase the background concentration), making channel inversion more difficult, thereby increasing the absolute value of the threshold voltage of the medium-voltage PMOS (e.g., adjusting it to around -0.7V), meeting the requirements of turn-off current and noise margin.

[0060] Therefore, this implementation utilizes the general principle of "high concentration in low-voltage traps and low concentration in high-voltage traps". By combining "high-concentration traps for NMOS and low-concentration traps for PMOS" and using a single "N-type" regulation injection, it achieves synchronous reverse correction of the threshold voltage of the two devices (NMOS decreases Vt, PMOS increases the absolute value of Vt).

[0061] In some embodiments, the aforementioned N-type impurities may include phosphorus (P), arsenic (As), or antimony (Sb). The implantation process parameters can be fine-tuned based on the actual concentration distribution in the well region to ensure that the implantation depth is precisely located at the channel surface and that the concentration is sufficient to achieve the aforementioned compensation or enhancement effects. This approach provides significant flexibility for process integration, allowing designers to select the most suitable well region combination and implantation type (N-type or P-type) when faced with well region baseline conditions from different foundries or process nodes, achieving the integration of medium-voltage devices at the lowest cost.

[0062] Step 5: Remove the first gate dielectric layer 203 in the third voltage device region and form the third gate dielectric layer 106.

[0063] In some embodiments, in step five, after removing the first gate dielectric layer 203 in the third voltage device region, the third applied voltage photolithographic mask pattern is removed; then, the third gate dielectric layer 106 is grown by a thermal oxidation process; the thickness of the third gate dielectric layer 106 in the third voltage device region is between the thickness of the gate dielectric layer in the first voltage device region and the thickness of the gate dielectric layer in the second voltage device region. The removal process can use dilute hydrofluoric acid (DHF) or buffered oxide etchant (BOE) for wet etching. The material of the third gate dielectric layer 106 includes silicon oxide, silicon oxynitride, or a high-k dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3. The moderately thick gate dielectric layer ensures that the device can operate reliably for a long period at the third applied voltage (e.g., 3.3V).

[0064] Step Six: Deposit the gate conductive material and etch to form the gate structure 107. (See also...) Figure 5 , Figure 5 This is a schematic diagram of the device structure after the gate structure is formed. (Example) Figure 5As shown, a gate structure 107 is formed on the third gate dielectric layer 106. The formation process of the gate conductive material may include depositing a polysilicon layer using a chemical vapor deposition (LPCVD) method or a CVD method. After forming the polysilicon layer, ion implantation may be performed on the polysilicon layer to increase conductivity. In some embodiments, the gate conductive material may include a metal gate material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), or combinations thereof, formed using physical vapor deposition (PVD) or atomic layer deposition (ALD). After depositing the gate conductive material, a photoresist pattern is formed using a photolithography process, and the gate conductive material not covered by the photoresist is removed using anisotropic dry etching (e.g., reactive ion etching, RIE), thereby defining the gate structure 107. The dry etching may use a chlorine-containing (e.g., Cl2), bromine-containing (e.g., HBr), or fluorine-containing (e.g., CF4, SF6) gas as an etchant to obtain a steep sidewall profile.

[0065] In some embodiments, the method further includes step seven: performing lightly doped drain implantation of the first conductivity type on the third voltage first conductivity type device, and performing lightly doped drain implantation of the second conductivity type on the third voltage second conductivity type device; wherein, the third voltage first conductivity type device utilizes the first conductivity type lightly doped drain implantation process 108 of the first voltage first conductivity type device; and the third voltage second conductivity type device utilizes the second conductivity type lightly doped drain implantation process 109 of the first voltage second conductivity type device. Please refer to [link to previous text]. Figure 6 , Figure 6 This is a schematic diagram of the device structure after the formation of the lightly doped drain region. (See diagram below.) Figure 6 As shown, a lightly doped drain region 108 of the first conductivity type is formed in a well region 103, and a lightly doped drain region 109 of the second conductivity type is formed in a well region 104. Lightly doped drain (LDD) implantation utilizes the gate structure 107 as a self-aligned mask. The first conductivity type lightly doped drain region 108 can be formed by tilting-angle implantation of N-type impurities, which may include phosphorus (P), arsenic (As), or antimony (Sb), with the implantation dose typically lower than that of the heavily doped source / drain. The second conductivity type lightly doped drain region 109 can be formed by tilting-angle implantation of P-type impurities, which may include boron (B), boron difluoride (BF2), or indium (In). After LDD implantation, pocket implantation or halo implantation may be performed, with the same conductivity type as the well region, to further suppress short-channel effects. By borrowing the LDD implantation process from high-voltage devices, these medium-voltage devices achieve deeper junction depths and optimized concentration gradients, thereby increasing drain breakdown voltage (BV) and reducing off-state leakage current.

[0066] In some embodiments, the method further includes step eight: forming sidewall dielectric layers 110 on both sides of the gate structure 107, and performing ion implantation using the gate structure 107 and the sidewall dielectric layers 110 as masks; wherein, for a third voltage first conductivity type device, heavy doped source / drain implantation of the first conductivity type is performed to form a first conductivity type source / drain region 111; for a third voltage second conductivity type device, heavy doped source / drain implantation of the second conductivity type is performed to form a second conductivity type source / drain region 112. Please refer to [link to previous text]. Figure 7 , Figure 7 This is a schematic diagram of the device structure after the source-drain structure is formed. (Example:) Figure 7 As shown, sidewall dielectric layers 110 are formed on both sides of the gate structure 107, and first conductivity type source / drain regions 111 and second conductivity type source / drain regions 112 are further formed. The formation process of the sidewall dielectric layer 110 may include: firstly, conformally depositing a dielectric layer, which may be silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the deposition method may include LPCVD or PECVD; subsequently, performing an anisotropic etch-back process to remove the dielectric layer on the horizontal surface, leaving only the dielectric layer on the sidewalls of the gate structure 107 to form the sidewalls. When forming the first conductivity type source / drain region 111, photoresist is used to mask the second conductivity type device region, and a high concentration of N-type impurities, such as arsenic (As) or phosphorus (P), is implanted. When forming the second conductivity type source / drain region 112, photoresist is used to mask the first conductivity type device region, and a high concentration of P-type impurities, such as boron (B) or boron difluoride (BF2), is implanted. Finally, a rapid thermal annealing (RTA) process is typically performed to activate the injected impurities and repair lattice damage, forming low-resistance source / drain regions.

[0067] This invention creatively proposes a cross-borrowing scheme (e.g., medium-voltage NMOS borrows high-voltage well, medium-voltage PMOS borrows low-voltage well, or vice versa), and, in conjunction with a specific threshold injection of a single photomask, successfully adjusts the threshold voltage of NMOS and PMOS to the ideal operating range (e.g., around 0.7V). Without significantly increasing the process cost (only adding one photomask), it achieves the integration of high-performance medium-voltage devices on the existing dual-gate oxide process platform.

[0068] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A process method for integrating multiple application voltage MOSFET devices, characterized in that, At least including: Step 1: Provide a semiconductor substrate (101) and define a first voltage device region, a second voltage device region, and a third voltage device region on the semiconductor substrate (101); the first voltage device region is used to form a device with a first application voltage, the second voltage device region is used to form a device with a second application voltage, and the third voltage device region is used to form a device with a third application voltage, wherein the first application voltage is higher than the third application voltage, and the third application voltage is higher than the second application voltage; Step 2: Form a plurality of well regions required for the first voltage device and a plurality of well regions required for the second voltage device in the semiconductor substrate (101); wherein, the third voltage first conductivity type device in the third voltage device region borrows the first conductivity type well region of the first voltage device or the first conductivity type well region of the second voltage device, and the third voltage second conductivity type device in the third voltage device region borrows the second conductivity type well region of the second voltage device or the second conductivity type well region of the first voltage device; Step 3: A first gate dielectric layer (203) is formed on the semiconductor substrate (101), and a third application voltage photomask pattern is formed using a photolithography process. The third application voltage photomask pattern is used to open the third voltage device region. Step 4: Using the third application voltage photolithography mask pattern as a barrier, perform threshold voltage-adjustable ion implantation on the third voltage device region; the threshold voltage-adjustable ion implantation forms a threshold adjustment layer (105), and simultaneously adjusts the threshold voltage of the third voltage first conductivity type device and the third voltage second conductivity type device; Step 5: Remove the first gate dielectric layer (203) in the third voltage device region and form a third gate dielectric layer (106). Step 6: Deposit the gate conductive material and etch to form the gate structure (107).

2. The process method for integrating multiple application voltage MOSFET devices according to claim 1, characterized in that: In step one, an isolation structure (102) is formed on the semiconductor substrate (101) to isolate the first voltage device region, the second voltage device region and the third voltage device region from each other.

3. The process method for integrating multiple application voltage MOSFET devices according to claim 2, characterized in that: In step one, the process of forming the isolation structure (102) includes: growing a front oxide layer (201) and a silicon nitride layer (202) on the semiconductor substrate (101); forming the isolation structure (102) using a shallow trench isolation process; and removing the silicon nitride layer (202).

4. The process method for integrating multiple application voltage MOSFET devices according to claim 1, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; the first conductivity type device is an N-type metal-oxide-semiconductor field-effect transistor, and the first conductivity type well region is a P-type well region (103).

5. The process method for integrating multiple application voltage MOSFET devices according to claim 1, characterized in that: The first conductivity type is P-type, and the second conductivity type is N-type; the first conductivity type device is a P-type metal-oxide-semiconductor field-effect transistor, and the first conductivity type well region is an N-type well region.

6. The process method for integrating multiple application voltage MOSFET devices according to claim 4, characterized in that: In step two, the first voltage device is a high-voltage device, the second voltage device is a low-voltage device, and the third voltage device is a medium-voltage device; the third voltage first conductivity type device borrows the first conductivity type well region (103) of the first voltage device; the third voltage second conductivity type device borrows the second conductivity type well region (104) of the second voltage device.

7. The process method for integrating multiple application voltage MOSFET devices according to claim 6, characterized in that: In step four, the impurity type of the threshold voltage-adjustable ion implantation is P-type impurity; by adjusting the threshold voltage, the threshold voltage of the third voltage first conductivity type device is increased, while the threshold voltage of the third voltage second conductivity type device is decreased.

8. The process method for integrating multiple application voltage MOSFET devices according to claim 4, characterized in that: In step four, the impurity type of the threshold voltage-regulated ion implantation is N-type impurity; wherein, the third voltage first conductivity type device borrows the first conductivity type well region of the second voltage device; and the third voltage second conductivity type device borrows the second conductivity type well region of the first voltage device.

9. The process method for integrating multiple application voltage MOSFET devices according to claim 7, characterized in that: The P-type impurity is boron.

10. The process method for integrating multiple application voltage MOSFET devices according to claim 9, characterized in that: The process parameters for threshold voltage-regulated ion implantation include: implantation energy of 5 keV to 50 keV, implantation dose of 5.0e11 to 1.0e13, and implantation angle of 0° to 10°.

11. The process method for integrating multiple application voltage MOSFET devices according to claim 1, characterized in that: In step three, the first gate dielectric layer (203) is a silicon oxide layer.

12. The process method for integrating multiple application voltage MOSFET devices according to claim 1, characterized in that: In step five, after removing the first gate dielectric layer (203) of the third voltage device region, the third applied voltage photomask pattern is removed; then the third gate dielectric layer (106) is grown by thermal oxidation process; the thickness of the third gate dielectric layer (106) of the third voltage device region is between the gate dielectric layer thickness of the first voltage device region and the gate dielectric layer thickness of the second voltage device region.

13. The process method for integrating multiple application voltage MOSFET devices according to claim 1, characterized in that: The method further includes step seven: performing light doping drain implantation of the first conductivity type on the third voltage first conductivity type device, and performing light doping drain implantation of the second conductivity type on the third voltage second conductivity type device; wherein, the third voltage first conductivity type device uses the first conductivity type light doping drain implantation (108) process of the first voltage first conductivity type device; the third voltage second conductivity type device uses the second conductivity type light doping drain implantation (109) process of the first voltage second conductivity type device.

14. The process method for integrating multiple application voltage MOSFET devices according to claim 13, characterized in that: The method further includes step eight: forming sidewall dielectric layers (110) on both sides of the gate structure (107), and performing ion implantation using the gate structure (107) and the sidewall dielectric layers (110) as masks; wherein, the first conductivity type heavy doped source / drain implantation is performed on the third voltage first conductivity type device to form a first conductivity type source / drain region (111); and the second conductivity type heavy doped source / drain implantation is performed on the third voltage second conductivity type device to form a second conductivity type source / drain region (112).

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