High-quality high-performance gan hemt power semiconductor epitaxial wafer

Abstract

The present application relates to a GaN HEMT power semiconductor epitaxial wafer, comprising: a silicon (Si) substrate; a nucleation region formed on the substrate; a stress relief region formed on the nucleation region; a buffer region formed on the stress relief region; a channel region formed on the buffer region; and a barrier region formed on the channel region. Wherein, below the channel region, specifically, at any position between the buffer region and the channel region, inside the buffer region, or between the stress relief region and the buffer region, a rear barrier region is provided. The rear barrier region has a superlattice structure or a multilayer structure in which layers of 2H-Al(Ga)N material and layers of 4H-SiC(N) material are alternately stacked.

Description

Technical Field

[0001] This invention relates to a power semiconductor device for use in next-generation power conversion devices.

[0002] More specifically, the invention relates to an epitaxial wafer structure for a gallium nitride (GaN)-based high electron mobility transistor (HEMT) fabricated by growing a nitride semiconductor on a silicon (Si) substrate, and particularly to an epitaxial wafer containing a back-barrier of a heteromaterial superlattice structure, which maximizes leakage current blocking characteristics and minimizes crystal defects. Background Technology

[0003] Recently, in the power electronics industry, research on wide bandgap (WBG) semiconductors is being actively conducted to overcome the physical limitations of silicon (Si)-based semiconductors.

[0004] Gallium nitride (GaN) is attracting attention as a core material for high-efficiency power conversion devices and high-frequency communication devices due to its high breakdown voltage, fast switching speed and low on-resistance.

[0005] Typically, GaN HEMT devices are fabricated on cost-competitive and easily scaled-up silicon (Si) substrates by growing multiple epitaxial layers using methods such as metal-organic chemical vapor deposition (MOCVD).

[0006] However, there is a significant difference in lattice constant and thermal expansion coefficient between silicon substrates and GaN materials, which can lead to high-density dislocation defects, wafer warping, and even cracks during growth.

[0007] These crystal defects increase the leakage current of the device and cause current collapse, thereby reducing reliability.

[0008] Especially in high-voltage driving environments, preventing electrons flowing through the channel layer from leaking toward the substrate is a very important issue that directly affects device performance.

[0009] To address this issue, existing technologies employ techniques such as introducing an AlGaN layer with a larger bandgap than GaN below the channel layer as a back-barrier, or doping the GaN buffer layer with carbon (C) or iron (Fe) to ensure high resistivity.

[0010] However, according to existing technology, if AlGaN or AlN with a large band gap is simply grown as a back barrier and grown to a thicker thickness, the crystal quality will decrease due to the lattice mismatch with the upper GaN channel layer.

[0011] Furthermore, increasing the doping concentration of carbon or iron to ensure high resistivity leads to an increase in impurities within the crystal, resulting in the side effect of reduced electron mobility or increased trap density.

[0012] Therefore, there is an urgent need to develop a new post-barrier technology that can maintain excellent crystallinity to ensure high-quality channels and block downward leakage current at the source. Summary of the Invention

[0013] Technical problems to be solved The main objective of this invention is to improve the structure of the back barrier located below the GaN channel layer, and to provide a high-quality, high-performance GaN HEMT power semiconductor epitaxial wafer that can epochally block leakage current without reducing crystallinity.

[0014] Specifically, by introducing superlattices or multilayer structures of alternating layers of 2H-AlN (or high-concentration AlGaN) and 4H-SiC materials with lattice constants very similar to those of 4H-SiC, stress caused by lattice mismatch is minimized, and the electron blocking effect is maximized through bandgap engineering.

[0015] Technical solution To achieve the above-mentioned technical objectives, the GaN HEMT power semiconductor epitaxial wafer (100) of the present invention includes: a silicon (Si) substrate (110); A nucleation region (120) is formed on the substrate (110); a stress relief region (130) is formed on the nucleation region (120); a buffer zone (140) is formed on the stress relief region (130); a channel region (160) is formed on the buffer zone (140); and a barrier region (170) is formed on the channel region (160).

[0016] Here, below the channel region (160), specifically, at any of the following locations: between the buffer zone (140) and the channel region (160), inside the buffer zone (140), or between the stress relief region (130) and the buffer zone (140), a rear barrier region (150) is provided.

[0017] As a characteristic structure of the present invention, the post-barrier region (150) has a superlattice structure or multilayer structure in which 2H-Al(Ga)N material layers (151) and 4H-SiC(N) material layers (152) are alternately stacked. In this case, the 4H-SiC(N) comprises 4H-SiC or 4H-SiCN material, and the thickness of each layer (151, 152) is preferably in the range of 1 nm to 3 nm.

[0018] Invention Effects According to the present invention, since the difference in lattice constant between 2H-AlN and 4H-SiC constituting the post-barrier region (150) is very small, about 1%, the generation of dislocations caused by lattice mismatch that may occur when heterogeneous materials are stacked can be suppressed, thereby epoch-making improvement on the crystallinity of the entire epitaxial layer.

[0019] Furthermore, by employing a superlattice structure made of a wide-bandgap material as a back barrier, the leakage of electrons from the channel layer (160) toward the substrate can be effectively blocked, thereby reducing the leakage current in the off state of the device and improving the breakdown voltage characteristics.

[0020] In addition, by introducing SiC-based materials with excellent electrical insulation as an insertion layer, the high resistance characteristics are enhanced, thereby ensuring reliability during high-voltage driving. Attached Figure Description

[0021] Figure 1 This is a cross-sectional view showing the stacked structure of a GaN HEMT power semiconductor epitaxial wafer according to an embodiment of the present invention.

[0022] Figure 2 This is a cross-sectional view used to illustrate the first embodiment in which the back barrier region is configured between the buffer zone and the channel region.

[0023] Figure 3 This is a cross-sectional view used to illustrate the second embodiment of the insertion buffer inside the post-barrier region.

[0024] Figure 4 This is a cross-sectional view used to illustrate the third embodiment in which the back barrier region is configured between the stress relief region and the buffer zone. Detailed Implementation

[0025] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the positional relationship of each component is based on the stacking order with the substrate as the bottommost layer.

[0026] Reference Figure 1 The GaN HEMT power semiconductor epitaxial wafer 100 according to the present invention has a multilayer structure in which the substrate 110 as the bottom layer is stacked sequentially to the barrier region 170 or p-GaN layer 180 as the top layer.

[0027] First, substrate 110 is the part that serves as the basis for epitaxial growth and uses a silicon (Si) substrate.

[0028] In particular, the crystal plane orientation of the silicon substrate 110 is preferably 111 plane.

[0029] This is because the atomic arrangement of the Si(111) plane is similar to the atomic arrangement (C-plane) of the hexagonal nitride semiconductor grown on it, which is beneficial for epitaxial growth.

[0030] Furthermore, it is advantageous to use a high-resistivity silicon substrate or a p-type silicon substrate in order to suppress leakage current in the vertical direction through the substrate.

[0031] A nucleation region 120 is formed on the substrate 110.

[0032] The nucleation region 120 is mainly composed of aluminum nitride (AlN), which plays a role in improving the wettability between the silicon substrate and the upper nitride layer and in aiding in initial nucleation.

[0033] In addition, it also serves to prevent diffusion walls, thus preventing the Si component of the silicon substrate from reacting with gallium (Ga) during high-temperature growth and causing the substrate to melt back.

[0034] A stress-relieving region 130 is formed on the upper part of the nucleation region 120.

[0035] There is a significant difference in the coefficient of thermal expansion between silicon and GaN. As a result, strong tensile stress is generated on the wafer during the cooling process after growth, which is the main cause of wafer warping or cracking.

[0036] The stress relief region 130 is a layer used to control this stress, and can typically be a multilayer AlGaN layer, an Al composition graded structure, or a superlattice structure.

[0037] A buffer region (140) is formed on the stress relief region 130.

[0038] The buffer layer 140 serves as both a physical support for the device and a layer ensuring sufficient thickness to achieve withstand voltage characteristics. The buffer layer 140 is formed of GaN, which has high resistivity, and is intentionally doped with impurities such as carbon (C) or iron (Fe) to compensate for residual electrons and enhance insulation properties.

[0039] On the other hand, the present invention includes a back-barrier region 150 located below the channel region 160 and which restricts the flow of electrons.

[0040] The post-barrier region 150 is formed as a superlattice structure or multilayer structure with alternating layers of 2H-Al(Ga)N material layer 151 and 4H-SiC(N) material layer (152).

[0041] Here, '2H-Al(Ga)N' refers to AlN or AlGaN with a hexagonal crystal structure, and '4H-SiC(N)' refers to silicon carbide (SiC) or nitrogen-containing silicon carbonitride (SiCN) with a hexagonal crystal structure.

[0042] The technical reason for using this combination of heterogeneous materials lies in the matching of lattice constants.

[0043] The in-plane lattice constant of 2H-AlN is about 0.311 nm, and the in-plane lattice constant of 4H-SiC is about 0.307 nm. The difference in lattice constant between the two materials is only within about 1%.

[0044] When the crystal structure is considered as a three-dimensional coordinate system (x, y, z), the direction of thin film growth (z-axis) is called the vertical direction (out-of-plane), and the bottom surface of the thin film (x, y-axis) is called the horizontal direction (in-plane).

[0045] Therefore, compared to existing GaN / AlGaN combinations, the lattice mismatch at the interface is significantly smaller, which can minimize the risk of dislocation caused by strain and grow high-quality crystals.

[0046] When the 2H-Al(Ga)N material layer 151 is AlGaN, the gallium (Ga) content is preferably limited to less than 20% (i.e., the aluminum content is more than 80%).

[0047] This is to ensure a sufficiently wide bandgap energy to form a higher potential barrier relative to the channel layer, thereby maximizing the leakage current blocking effect.

[0048] Furthermore, the thickness of each material layer 151, 152 is formed in the range of 1 nm to 3 nm. This thickness range is a critical numerical range that prevents quantum mechanical tunneling while maintaining the superlattice effect and preventing excessive stress accumulation.

[0049] On the other hand, the present invention forms a channel region 160 on the buffer zone 140 or the rear barrier region 150.

[0050] The channel region 160 is composed of high-purity GaN (u-GaN) that has not been intentionally doped, forming a path for electron movement.

[0051] A barrier region 170 is formed on the channel region 160.

[0052] The barrier region 170 is composed of AlGaN or similar materials with a band gap wider than that of the channel region 160. A high-concentration two-dimensional electron gas (2DEG) layer is formed in the channel region 160 through the polarization phenomenon that occurs at the interface of the heterojunction of the two materials.

[0053] In addition, in order to realize the device operating mode as normally-off (E-mode), a p-GaN layer 180 doped with p-type impurities can be formed in the gate predetermined formation region above the barrier region 170.

[0054] The following describes various embodiments of the configuration of the back barrier region 150 and their effects.

[0055] Depending on its vertical position, the rear barrier region 150 can be implemented through various embodiments to achieve different technical objectives, such as controlling electronic behavior within the channel, adjusting the electric field distribution, and blocking crystal defects.

[0056] First, refer to Figure 2 According to this embodiment, the rear barrier region 150 directly contacts and is disposed between the uppermost surface of the buffer zone 140 and the lowermost surface of the channel region 160.

[0057] This structure is a way of forming a heteromaterial potential barrier directly below the channel that forms the two-dimensional electron gas (2DEG).

[0058] Typically, when GaN HEMT devices operate under high voltage, the high drain voltage accelerates electrons, making them prone to punch-through phenomena where electrons detach from the channel and flow into the buffer layer.

[0059] When the rear barrier region 150 is positioned adjacent to the channel region 160, the electron confinement effect can be maximized by forming a conduction band discontinuity directly below the channel.

[0060] In particular, when the existing AlGaN single back barrier is configured directly below the channel, there is a problem that the interface roughness increases due to lattice mismatch, thereby reducing the channel electron mobility. However, this embodiment adopts a superlattice structure that utilizes the excellent lattice matching between 2H-AlN and 4H-SiC, which minimizes interface scattering while ensuring strong leakage current blocking characteristics. This is of critical technical significance.

[0061] Secondly, refer to Figure 3 According to this embodiment, the rear barrier region 150 is inserted and configured inside the buffer (140).

[0062] Specifically, the entire buffer zone 140 is divided into a lower buffer layer 140a and an upper buffer layer (140b), with a sandwich structure between which a subsequent barrier zone 150 is located.

[0063] This configuration is designed to effectively control the electric field distribution in the vertical direction.

[0064] When a high voltage is applied to the back barrier region (150), the electric field concentration formed inside the buffer layer plays a role in increasing the breakdown voltage.

[0065] Furthermore, from a crystallographic perspective, the superlattice structure of the back barrier region 150 serves to filter or bend the threading dislocations that propagate from the substrate or stress relief region (130) during the growth of the lower buffer layer 140a and block them.

[0066] As a result, the upper buffer layer 140b grown on the back barrier region 150 and the channel region (160) thereon have a lower defect density, thereby providing the effect of improving device reliability and suppressing current collapse.

[0067] Next, refer to Figure 4 In this embodiment, the post-barrier region 150 is disposed between the stress relief region 130 and the buffer layer 140. That is, it is a structure formed as a substrate layer before the GaN buffer layer begins to grow.

[0068] This embodiment enhances the role of the diffusion barrier layer, that is, it blocks impurities such as silicon (Si) that may diffuse from the silicon substrate 110 and stress relief region 130 into the high-resistivity buffer zone 140 at the source.

[0069] Furthermore, the stress relief region 130 is usually subjected to artificial strain in order to adjust the lattice constant, which often results in relatively low crystal quality. By forming the superlattice barrier region (150) of this embodiment on it, it can serve as a template for correcting the lattice arrangement again.

[0070] This improves the crystal quality of the entire buffer 140 grown thickly on it, resulting in a fundamental solution to reduce the defects themselves as leakage current paths.

[0071] According to the epitaxial wafer manufacturing method of the present invention, the above-mentioned layer is continuously grown in an in-situ process within a reaction chamber while changing the precursor gas and process conditions, thereby preventing interface contamination and improving productivity.

Claims

1. A GaN HEMT power semiconductor epitaxial wafer, comprising: silicon substrate; Nucleation regions formed on the substrate; Stress relief zones are formed in the nucleation region; A buffer zone is formed on the stress relief zone; The channel area formed on the buffer zone; and A barrier region is formed in the channel region; A post-barrier region is formed below the channel region. The post-barrier region comprises a superlattice structure or multilayer structure composed of alternating layers of 2H-Al(Ga)N and 4H-SiC(N) materials.

2. The GaN HEMT power semiconductor epitaxial wafer according to claim 1, characterized in that, The 4H-SiC(N) material comprises 4H-SiC (silicon carbide) or 4H-SiCN (silicon carbonitride).

3. The GaN HEMT power semiconductor epitaxial wafer according to claim 1, characterized in that, The thicknesses of the 2H-Al(Ga)N and 4H-SiC(N) constituting the post-barrier region are 1 nm to 3 nm, respectively.

4. The GaN HEMT power semiconductor epitaxial wafer according to claim 1, characterized in that, When the 2H-Al(Ga)N material is AlGaN, the gallium (Ga) content is less than 20%.

5. The GaN HEMT power semiconductor epitaxial wafer according to claim 1, characterized in that, The difference in lattice constant between the 2H-Al(Ga)N material and the 4H-SiC(N) material is within 1%.

6. The GaN HEMT power semiconductor epitaxial wafer according to claim 1, characterized in that, The post-barrier region is positioned between the buffer zone and the channel region.

7. The GaN HEMT power semiconductor epitaxial wafer according to claim 1, characterized in that, The post-barrier region is inserted and configured inside the buffer.

8. The GaN HEMT power semiconductor epitaxial wafer according to claim 1, characterized in that, The post-barrier region is positioned between the stress relief region and the buffer zone.

9. The GaN HEMT power semiconductor epitaxial wafer according to claim 1, characterized in that, The silicon substrate is a high-resistivity or p-type substrate with (111) crystal planes.

10. The GaN HEMT power semiconductor epitaxial wafer according to claim 1, characterized in that, The buffer is made of GaN doped with carbon or iron to ensure high resistance characteristics.

Images