Semiconductor chip with grooves on two sides and manufacturing method

Abstract

The invention relates to a semiconductor chip with double-sided grooves and a manufacturing method thereof. Belongs to the technical field of power semiconductor devices. The problems that an existing single-groove chip is low in production efficiency, high in cost and limited in forward and reverse blocking voltage boosting are mainly solved. The device is mainly characterized in that the trenches are terminal double-sided trenches and are respectively and symmetrically arranged at P-N junction terminals of the N-type substrate, the anode P layer and the cathode P layer, and the inner surfaces of the trenches are provided with protective layers; and cathode P short-circuit points and cathode P + short-circuit points embedded in the cathode P short-circuit points are uniformly arranged in the cathode N + region, so that a low-resistance conductive current channel is formed. According to the invention, the design of a P-type punch-through ring structure is canceled, and the low-concentration P-type doping and high-concentration P + design is adopted, so that the short-circuit punch-through resistance can be reduced, the through-current capability and the blocking voltage of the chip can be improved, and the method is mainly used for manufacturing medium-voltage and high-voltage power semiconductor device chips.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device design and manufacturing technology, and specifically relates to a double-sided trench semiconductor chip and its manufacturing method. Background Technology

[0002] In the manufacturing of power semiconductor devices, particularly in square power semiconductor chips, mesa etching technology is still widely used. Figure 1 As shown, the semiconductor chip structure using a single trench passivation layer mesa process is used for forward blocking voltage termination. For reverse blocking voltage termination, a P-type punch-through ring is required. The formation of the P-type punch-through ring requires a long propagation diffusion process. The higher the silicon wafer voltage, the thicker the wafer, requiring a longer time to complete the punch-through diffusion, which leads to reduced production efficiency and higher costs. At the same time, the improvement of forward and reverse blocking voltage is limited by the PN junction termination process. Summary of the Invention

[0003] The purpose of this invention is to provide a double-sided trench semiconductor chip and a method for implementing the double-sided trench semiconductor chip, so as to solve the problems of low production efficiency, high cost and difficulty in increasing forward and reverse blocking voltage.

[0004] The technical solution of this invention is: a double-sided trench semiconductor chip, comprising an anode P+ layer, an anode P layer, an N-type substrate, a cathode P layer, a gate P+, ​​a cathode N+, and a trench; the cathode P layer and the anode P layer are symmetrically disposed on both sides of the N-type substrate, and the gate P+ and cathode N+ are disposed on the cathode P layer away from the surface of the N-type substrate; an anode metal layer is disposed on the surface of the anode P+ layer to form an electrode anode; a gate metal layer is disposed on the surface of the gate P+ layer to form an electrode gate; the cathode P layer is disposed through a cathode metal layer on the surface of the cathode N+ to form an electrode cathode; a gate-cathode isolation region is formed between the gate metal layer and the cathode metal layer; characterized in that: the trench is a terminal double-sided trench, symmetrically disposed at the PN junction terminals of the N-type substrate and the anode P layer and the cathode P layer, respectively, and a protective layer is disposed on the inner surface of the trench; a cathode P short-circuit point and a cathode P+ short-circuit point embedded in the cathode P short-circuit point are uniformly disposed in the region of the cathode N+, forming a low-resistance conductive current channel.

[0005] The trench depth in the technical solution of the chip of the present invention is 120~150μm.

[0006] In the technical solution of the chip of the present invention, the protective layers, from the inside out, are the SIPOS layer, the glass passivation film, and the SiO2 passivation layer.

[0007] In the technical solution of the chip of the present invention, the junction depth of the anode P layer and the cathode P layer is 75-100 μm.

[0008] In the technical solution of this invention's chip, the surface concentration of the anode P+ layer is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 5–15 μm; the surface concentration of the anode P layer and cathode P layer is 0.2–6.0 × 10⁻⁶. 16 / cm 3 The depth is 75–100 µm; the cathode N+ is an N-type doped region, and the surface concentration of cathode N+ is 0.9–8.8 × 10⁻⁶. 20 / cm 3 The depth is 15–25 μm; the cathode P-type short-circuit point is cylindrical, uniformly arranged in squares or equilateral triangles, with a diameter of 0.10–0.36 mm, and connected to the cathode P layer under the cathode N+ doped region; the cathode P+ short-circuit point is embedded in the cathode P-type short-circuit point, with a diameter of 0.10–0.30 mm; the surface concentration of the cathode P+ short-circuit point and the gate P+ is 4.5–9.0 × 10⁻⁶. 19 / cm 3 The junction depth is 5–10 μm.

[0009] In the technical solution of the chip of the present invention, the anode metal layer is Ni-Ag, Al-Ti-Ni-Ag or Al-Ti-Ni-Au.

[0010] The cathode metal layer in the technical solution of the chip of the present invention is Al, Al-Ti-Ni-Ag or Al-Ti-Ni-Au.

[0011] In the technical solution of the chip of the present invention, a protective layer is provided on the surface of the SiO2 passivation layer, and the protective layer is polyimide.

[0012] The technical solution of the manufacturing method of the present invention is: a method for manufacturing a double-sided trench semiconductor chip, characterized by comprising the following steps: (1) Select type N <111> Crystal-oriented silicon wafers are used as substrates. The thickness of the silicon wafers is 400-500 μm, the resistivity is 50-80 Ω•cm or 80-100 Ω•cm, and the diameter is Ø101.6-Ø150. They are chemically etched and polished on both sides. (2) P diffusion: After wafer cleaning, aluminum is pre-deposited on both sides at 950–1150℃, followed by low-concentration diffusion and oxidation at 1200–1250℃ for 10–30 hours, forming P1 and P2 regions with a junction depth of 70–80 μm and a surface impurity concentration of 0.35–8.5 × 10⁻⁶. 16 / cm 3 ; (3) N+ photolithography: Photoresist is applied to the cathode surface of the wafer, exposed, and developed to protect the anodic oxide layer and remove the oxide layer in the N+ window area of ​​the cathode; markings are etched on both sides, and then the photoresist is removed; (4) N+ diffusion: After wafer cleaning, phosphorus pre-deposition or phosphorus implantation is performed at 1000–1125℃; then, it is advanced and oxidized at 1120–1250℃ for 8–12 hours to form a P1-N1-P2-N+ structure. The N+ surface impurity concentration at the cathode is 0.58–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 12–20 μm; (5) P+ lithography: Photoresist is applied to the cathode surface of the wafer, exposed, developed, the oxide layer of the gate P+ and cathode P+ window areas is removed, the oxide layer of the anode surface is removed, and then the photoresist is removed. (6) P+ diffusion: After wafer cleaning, boron is sprayed onto the wafer surface and diffused to form an anode P+ layer, a gate P+ layer, and a cathode P+ short-circuit point. The depth of the anode P+ layer is 5–15 μm, and the depth of the gate P+ and cathode P+ short-circuit points is 5–10 μm. The impurity concentration on the surface of the anode P+ layer is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The surface impurity concentration at the gate P+ and cathode P+ short-circuit points is 4.5–9.0 × 10⁻⁶. 19 / cm 3 The process conditions are as follows: the boron source is an alcohol source or a latex source, which is a saturated solution of boron oxide in alcohol or latex source, and the constant surface source diffusion method of boron spraying is adopted. Propulsion conditions: 1180~1250℃, N2=6L / min, O2=0.5L / min, time 60~200min; (7) Trench area photolithography: Photoresist is applied to the anode and cathode surfaces of the wafer, exposed, and developed to remove the photoresist in the trench window area; (8) Trench etching: Double-sided annular trench etching, with a trench depth of 120-150 μm and a trench surface width of 400-600 μm; (9) SIPOS deposition: After wafer cleaning, SIPOS thin film is deposited at 500℃~800℃ in the exposed PN junction area of ​​the trench to form SIPOS layer and protect the mesa; (10) Glass passivation: Glass powder is coated in the wafer trench by scraping or photoresist method, and then sintered at a low temperature of 500℃~580℃ and a high temperature of 800℃~850℃ to form a glass passivation film. (11) LTO deposition: SiO2 passivation layer is deposited on the wafer surface at a temperature of 400℃~600℃; (12) BOE etching: Photoresist is applied to the wafer surface, exposed, developed, and the SIPOS and SiO2 passivation layers in the window area are removed, and then the photoresist is removed. (13) First metal deposition: After the wafer is cleaned, a metal conductive layer is deposited on both sides of the wafer by evaporation. The thickness of the metal layer on the anode side is 2-4 μm and the thickness of the metal layer on the cathode side is 6-12 μm. (14) First metal etching: Photoresist is applied to both sides of the wafer surface, exposed, and developed to remove the metal layer of the trench window area and the gate cathode isolation area, and then the photoresist is removed. (15) Alloy: At a temperature of 500℃~550℃, the metal conductive layer is alloyed with the wafer to increase the ohmic contact and welding force between the metal and the wafer; (16) Second metal deposition: After wafer cleaning, multiple layers of conductive metal Ti-Ni-Ag or Ti-Ni-Au are sequentially deposited on the anode surface of the wafer. The thicknesses are 0.2 μm, 0.5 μm and 1.2 μm, respectively; (17) Second metal etching: Photoresist is applied to the anode surface of the wafer, exposed, developed, and the multilayer metal conductive layer in the trench location window area is removed, and then the photoresist is removed; (18) Test and sort semiconductor chip parameters, separate, inspect and label chips.

[0013] Between steps (17) and (18) of the technical solution of the manufacturing method of the present invention, polyimide is coated on both sides of the wafer surface, and then the polyimide on the metal layer is removed by photolithography to form a protective layer on the surface of the SiO2 passivation layer.

[0014] The present invention has the following advantages or beneficial effects: 1. The structure and process of this invention are mature and simple, and the manufactured chips have good breakdown voltage characteristics, high yield rate and high product reliability. A double-sided trench shared by adjacent chips is symmetrically dug in the passive area of ​​the chip. SIPOS layer, glass passivation film and SiO2 passivation layer are symmetrically arranged on the top and sidewalls of the trench, which can offset the shrinkage stress of the glass film and reduce the breakage rate of silicon wafers after glass passivation. The method of simultaneous processing on both sides further reduces the influence of glass expansion coefficient stress.

[0015] 2. This invention eliminates the design of the P-type punch-through ring structure, thus improving production efficiency; the anode P1 layer and cathode P2 layer are doped with low concentration, which can reduce the electric field strength of the trench blocking voltage and improve the reliability of voltage blocking; the design of the gate P+ and cathode P+ short-circuit points can reduce the short-circuit punch-through resistance, improve the short-circuit effect, and under the same conditions, reduce the size of the short-circuit point and increase the cathode current-passing area.

[0016] 3. The V of the double-sided trench semiconductor chip of the present invention DRM and V RRM The value can reach 2200V.

[0017] This invention features high production efficiency, reduced production costs, and improved forward and reverse blocking voltage, and is mainly used in medium and high voltage power semiconductor device chips. Attached Figure Description

[0018] The accompanying drawings are used to provide a further understanding of the technical solutions of this application or the prior art, and constitute a part of the specification. The accompanying drawings illustrating the embodiments of this application are used together with the embodiments of this application to explain the technical solutions of this application, but do not constitute a limitation on the technical solutions of this application.

[0019] Figure 1 This is a schematic diagram of the mesa process semiconductor chip structure mentioned in the background technology.

[0020] Figure 2 This is a cross-sectional schematic diagram of a semiconductor chip with double-sided trenches according to the present invention.

[0021] Figure 3 This is a schematic diagram of the angle gate and cathode surface in an embodiment of the present invention.

[0022] Figure 4 This is a schematic diagram of a double-sided trench semiconductor chip arranged in a wafer according to an embodiment of the present invention.

[0023] Figure 5 This is a schematic diagram of passive region protection for a semiconductor chip with double-sided trenches according to the present invention.

[0024] Figure 6 This is a schematic diagram of the cross-sectional structure of the central gate of a semiconductor chip with a double-sided trench according to the present invention.

[0025] Figure 7 This is a schematic diagram of the central gate and cathode surface of a semiconductor chip with a double-sided trench according to the present invention.

[0026] In the figure: A-anode electrode, G-gate electrode, K-cathode electrode, 1-anode metal layer, 2-anode P+ layer, 3-anode P layer, 4-N-type substrate, 5-cathode P layer, 6-gate P+, ​​7-gate metal layer, 8-cathode N+, 9-cathode P short circuit point, 10-cathode P+ short circuit point, 11-cathode metal layer, 12-SIPOS layer, 13-glass passivation film, 14-SiO2 passivation layer, 15-gate cathode isolation region, 16-protective layer. Detailed Implementation

[0027] The following is combined with Figures 2 to 7The embodiments of the present invention will be described in full here. Obviously, the described embodiments are only a part of the present invention, and not all of them. Any other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0028] Embodiment 1 of the present invention provides a semiconductor chip with double-sided trenches, as follows: Figure 2 A double-sided trench semiconductor chip is shown, comprising an anode P+ layer 2, an anode P layer 3, an N-type substrate 4, a cathode P layer 5, a gate P+ 6, a cathode N+ 8, and a terminal double-sided trench. The cathode P layer 5 and the anode P layer 3 are symmetrically disposed on opposite sides of the N-type substrate 4. On the side of the cathode P layer 5 away from the N-type substrate 4, the gate P+ 6, the cathode N+ 8 layer, a cathode P short-circuit point 9, and a cathode P+ short-circuit point 10 are respectively disposed. The cathode P+ short-circuit point 10 is embedded within the cathode P short-circuit point 9, forming a low-resistance conductive current channel. A cathode metal layer 11 is disposed on the surface of the cathode P layer 5 through the cathode P short-circuit point 9, the cathode P+ short-circuit point 10, and the cathode N+ 8 layer, forming the cathode electrode K. A gate metal layer 7 is disposed on the surface of the gate P+ 6, forming the gate electrode G. A gate-cathode isolation region 15 is formed between the gate metal layer 7 and the cathode metal layer 11. An anode metal layer 1 is disposed on the surface of the anode P+ layer 2, forming the anode electrode A. The j1 and j2 junctions of the anode P layer 3 or the cathode P layer 5 are provided with double-sided trenches, and the trenches are respectively provided with an SIPOS layer 12, a glass passivation film 13, and a SiO2 passivation layer 14, such as Figure 3 As shown, the gate electrode G is located at the corner of the semiconductor chip. The surface concentration of the anode P+ layer 2 is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 5–15 μm. The surface concentration of the anode P layer 3 and the cathode P layer 5 is 0.2–6.0 × 10⁻⁶. 16 / cm 3 The depth is 75–100 µm. The cathode N+8 is an N-type doped region with a surface concentration of 0.9–8.8 × 10⁻⁶. 20 / cm 3 The cathode has a depth of 15–25 μm. Within the N+8 region of the cathode, P-type short-circuit points 9 are uniformly distributed and connected to the P2 layer beneath the N+8 doped region. These P-type short-circuit points 9 are cylindrical, with a diameter of 0.10–0.36 mm, and are uniformly arranged in square or equilateral triangle shapes. Embedded within the P-type short-circuit points 9 are P+ short-circuit points 10, with a diameter of 0.10–0.30 mm. The surface concentration of the cathode P+ short-circuit point 10 and the gate P+6 is 4.5–9.0 × 10⁻⁶. 19 / cm 3 The junction depth is 5–10 μm; the depth of the junction terminal trench is 120–150 μm.

[0029] The anode metal layer 1 is either Al-Ti-Ni-Ag or Al-Ti-Ni-Au, with thicknesses of 3μm, 0.2μm, 0.5μm and 1.2μm, respectively, or is metallic Ni-Ag with thicknesses of 0.5μm and 1.2μm, respectively.

[0030] The cathode metal layers 11 are Al, Al-Ti-Ni-Ag, or Al-Ti-Ni-Au, with thicknesses of 3 μm, 0.2 μm, 0.5 μm, and 1.2 μm, respectively. When wire bonding is used for the cathode surface, the metal layer is Al; when welding is used for the connection, multiple metal layers are required to improve ohmic contact and welding force.

[0031] like Figure 4 As shown, the double-sided trench semiconductor chips are uniformly arranged in the wafer, enabling large-diameter silicon wafer overlay, improving production efficiency and reducing costs.

[0032] Embodiment 2 of the present invention provides a semiconductor chip with double-sided trenches, as follows: Figure 2 , Figure 3 , Figure 5 As shown, unlike Embodiment 1, the surface of the SiO2 passivation layer 14 is provided with a protective layer 16, which is made of polyimide. This improves surface insulation performance and achieves higher chip reliability.

[0033] Embodiment 3 of the present invention provides a semiconductor chip with a double-sided trench, as follows: Figure 6 , Figure 7 As shown, unlike embodiment 2, the gate electrode G is located at the center of the semiconductor chip. When the size of the semiconductor chip increases, a centrally designed gate electrode G is more conducive to improving the carrier turn-on expansion speed and turn-on uniformity, thereby improving the chip's current carrying capacity.

[0034] This invention provides a double-sided trench semiconductor chip and its manufacturing method, comprising the following steps: (1) Select type N <111> Crystal-oriented silicon wafers are used as substrates. The thickness of the silicon wafers is 400-500 μm, the resistivity is 50-80 Ω•cm or 80-100 Ω•cm, and the diameter is Ø101.6-Ø150. They are chemically etched and polished on both sides. (2) P-diffusion: After wafer cleaning, aluminum is pre-deposited on both sides at a temperature of 950–1150℃ for 80–150 minutes. Then, low-concentration diffusion and oxidation are carried out at a temperature of 1200–1250℃ for 10–30 hours to form P1 and P2 regions with a junction depth of 70–80 μm and a surface impurity concentration of 0.35–8.5 × 10⁻⁶. 16 / cm 3 ; (3) N+ lithography: Photoresist is applied to the cathode surface of the wafer, an N+ mask is applied for exposure and development, while the anodic oxide layer is protected and the oxide layer in the N+ window area of ​​the cathode is removed; and markings are etched on both sides, and then the photoresist is removed. (4) N+ diffusion: After wafer cleaning, phosphorus pre-deposition or phosphorus implantation is performed at 1000–1125℃ for 60–120 minutes; then, the wafer is advanced and oxidized at 1120–1250℃ for 8–12 hours to form a P1-N1-P2-N+ structure. The impurity concentration on the cathode N+8 surface is 0.58–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 12–20 μm; (5) P+ lithography: Coat the cathode surface of the wafer with photoresist, expose with a P+ mask, develop, remove the oxide layer of the gate P+ and cathode P+ window areas, remove the oxide layer of the anode surface, and then remove the photoresist. (6) P+ diffusion: After wafer cleaning, boron is sprayed onto the wafer surface and diffused to form an anode P+ layer 2, a gate P+ 6, and a cathode P+ short-circuit point 10. The depth of the anode P+ layer 2 is 5–15 μm, and the depth of the gate P+ 6 and the cathode P+ short-circuit point 10 is 5–10 μm. The impurity concentration on the surface of the anode P+ layer 2 is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The surface impurity concentration at gate P+6 and cathode P+ short-circuit point 10 is 4.5–9.0 × 10⁻⁶. 19 / cm 3 The process conditions are as follows: the boron source is an alcohol source or a latex source, which is a saturated solution of boron oxide in alcohol or latex source, and the constant surface source diffusion method of boron spraying is adopted. Propulsion conditions: 1180~1250℃, N2=6L / min, O2=0.5L / min, time 60~200min; (7) Trench area photolithography: Photoresist is applied to the anode and cathode surfaces of the wafer, a trench mask is applied for exposure and development, and the photoresist in the trench window area is removed; (8) Trench etching: The exposed silicon is etched with a mixed acid of HF / HNO3 / CH3COOH in a double-sided annular trench with a trench depth of 120-150μm and a trench surface width of 400-600μm. Pay attention to the morphology of the trench surface and avoid sharp corners and beak-shaped edges. (9) SIPOS deposition: After wafer cleaning, SiH4 / N2O gas is introduced using LPCVD equipment to deposit a semi-insulating polycrystalline silicon thin film (SIPOS: Semi Insolated Polycrystalline Of Silicon) in the exposed PN junction area of ​​the trench at 500℃~800℃ to form SIPOS layer 12 to protect the mesa; (10) Glass passivation: Glass powder is coated in the wafer trench by scraping or photoresist method, and then sintered at a low temperature of 500℃~580℃ and a high temperature of 800℃~850℃ for 18 minutes to form a glass passivation film 13. (11) LTO deposition: The wafer is placed in the LPCVD equipment at a temperature of 400℃~600℃, and SiH4, N2O and PH3 gases are introduced to deposit a SiO2 passivation layer 14 on the wafer surface by LTO (Low Temperature Oxidation). (12) BOE etching: Photoresist is applied to the wafer surface, exposed, developed, and the SIPOS and SiO2 passivation layers in the window area are removed, and then the photoresist is removed. (13) First metal deposition: After the wafer is cleaned, a metal conductive layer is deposited on both sides of the wafer by evaporation. The thickness of the metal layer on the anode side is 2-4 μm and the thickness of the metal layer on the cathode side is 6-12 μm. (14) First metal etching: Photoresist is applied to both sides of the wafer surface, exposed, and developed to remove the metal layer of the trench window area and the gate cathode isolation area, and then the photoresist is removed. (15) Alloy: At a temperature of 500℃~550℃, the metal conductive layer is alloyed with the wafer to increase the ohmic contact and welding force between the metal and the wafer; (16) Second metal deposition: After wafer cleaning, multiple layers of conductive metal Ti-Ni-Ag or Ti-Ni-Au are sequentially deposited on the anode surface of the wafer, with thicknesses of 0.2 μm, 0.5 μm and 1.2 μm, respectively; (17) Second metal etching: Photoresist is applied to the anode surface of the wafer, exposed, developed, and the multilayer metal conductive layer in the trench location window area is removed, and then the photoresist is removed; (18) Test and sort semiconductor chip parameters, separate, inspect and label chips.

[0035] In the present invention, a self-protected thyristor with a transition voltage and a manufacturing method thereof, polyimide may be coated on both sides of the wafer surface between steps (17) and (18) above, and then the polyimide on the metal layer is removed by photolithography, so that a protective layer 16 is formed on the surface of the SiO2 passivation layer 14.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Therefore, any modifications, equivalent substitutions, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A double-sided trench semiconductor chip, comprising an anode P+ layer (2), an anode P layer (3), an N-type substrate (4), a cathode P layer (5), a gate P+ layer (6), a cathode N+ layer (8), and a trench; the cathode P layer (5) and the anode P layer (3) are symmetrically disposed on both sides of the N-type substrate (4), and the gate P+ layer (6) and the cathode N+ layer (8) are disposed on the surface of the cathode P layer (5) away from the N-type substrate (4); an anode metal layer (1) is disposed on the surface of the anode P+ layer (2) to form an electrode anode (A); a gate metal layer (7) is disposed on the surface of the gate P+ layer (6) to form an electrode gate (G); a cathode metal layer (11) is disposed on the surface of the cathode P layer (5) through the cathode N+ layer (8) to form an electrode cathode (K); a gate-cathode isolation region (15) is disposed between the gate metal layer (7) and the cathode metal layer (11); characterized in that: The trench is a terminal double-sided trench, which is symmetrically arranged at the PN junction (j1, j2) terminals of the N-type substrate (4) and the anode P layer (3) and the cathode P layer (5), respectively. A protective layer is provided on the inner surface of the trench. The cathode N+ (8) region is uniformly provided with cathode P short-circuit point (9) and cathode P+ short-circuit point (10) embedded in the cathode P short-circuit point (9), forming a low-resistance conductive current channel.

2. A semiconductor chip with double-sided trenches according to claim 1, characterized in that: The depth of the trench is 120~150μm.

3. A semiconductor chip with double-sided trenches according to claim 1 or 2, characterized in that: The protective layers, from the inside out, are a SIPOS layer (12), a glass passivation film (13), and a SiO2 passivation layer (14).

4. A semiconductor chip with double-sided trenches according to claim 3, characterized in that: The junction depth of the anode P layer (3) and the cathode P layer (5) is 75-100 μm.

5. A semiconductor chip with double-sided trench according to any one of claims 1-2 and 4, characterized in that: The surface concentration of the anode P+ layer (2) is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 5–15 μm; the surface concentration of the anode P layer (3) and cathode P layer (5) is 0.2–6.0 × 10⁻⁶. 16 / cm 3 The depth is 75–100 µm; the cathode N+(8) is an N-type doped region, and the surface concentration of the cathode N+(8) is 0.9–8.8 × 10⁻⁶. 20 / cm 3 The depth is 15-25 μm; the cathode P-type short-circuit point (9) is cylindrical, uniformly arranged in squares or equilateral triangles, with a diameter of 0.10-0.36 mm, and connected to the cathode P layer (5) under the cathode N+ (8) doped region; the cathode P+ short-circuit point (10) is embedded in the cathode P-type short-circuit point (9), with a diameter of 0.10-0.30 mm; the surface concentration of the cathode P+ short-circuit point (10) and the gate P+ (6) is 4.5-9.0 × 10⁻⁶. 19 / cm 3 The junction depth is 5–10 μm.

6. A semiconductor chip with double-sided trench according to any one of claims 1-2 and 4, characterized in that: The anode metal layer (1) is Ni-Ag, Al-Ti-Ni-Ag or Al-Ti-Ni-Au.

7. A semiconductor chip with double-sided trench according to any one of claims 1-2 and 4, characterized in that: The cathode metal layer (11) is Al, Al-Ti-Ni-Ag or Al-Ti-Ni-Au.

8. A semiconductor chip with double-sided trench according to any one of claims 1-2 and 4, characterized in that: The surface of the SiO2 passivation layer is provided with a protective layer (16), which is polyimide.

9. A method for manufacturing a double-sided trench semiconductor chip, characterized in that: Includes the following steps: (1) Select type N <111> Crystal-oriented silicon wafers are used as substrates. The thickness of the silicon wafers is 400-500 μm, the resistivity is 50-80 Ω•cm or 80-100 Ω•cm, and the diameter is Ø101.6-Ø150. They are chemically etched and polished on both sides. (2) P diffusion: After wafer cleaning, aluminum is pre-deposited on both sides at 950–1150℃, followed by low-concentration diffusion and oxidation at 1200–1250℃ for 10–30 hours, forming P1 and P2 regions with a junction depth of 70–80 μm and a surface impurity concentration of 0.35–8.5 × 10⁻⁶. 16 / cm 3 ; (3) N+ lithography: Photoresist is applied to the cathode surface of the wafer, exposed, and developed to protect the anodic oxide layer and remove the oxide layer in the cathode N+ window area; The markings are etched on both sides, and then the photoresist is removed; (4) N+ diffusion: After wafer cleaning, phosphorus pre-deposition or phosphorus implantation is performed at 1000-1125℃; then, it is advanced and oxidized at 1120-1250℃ for 8-12 hours to form a P1-N1-P2-N+ structure. The impurity concentration on the cathode N+ (8) surface is 0.58-8.0×10⁻⁶. 20 / cm 3 The junction depth is 12–20 μm; (5) P+ lithography: Photoresist is applied to the cathode surface of the wafer, exposed, developed, the oxide layer of the gate P+ and cathode P+ window areas is removed, the oxide layer of the anode surface is removed, and then the photoresist is removed. (6) P+ diffusion: After wafer cleaning, boron is sprayed onto the wafer surface and diffused to form an anode P+ layer (2), a gate P+ (6), and a cathode P+ short-circuit point (10). The depth of the anode P+ layer (2) is 5-15 μm, the depth of the gate P+ (6) and the cathode P+ short-circuit point (10) is 5-10 μm, and the impurity concentration on the surface of the anode P+ layer (2) is 0.6-8.0×10⁻⁶. 20 / cm 3 The surface impurity concentration at the gate P+ (6) and cathode P+ short-circuit point (10) is 4.5–9.0 × 10⁻⁶. 19 / cm 3 ; The process conditions are as follows: the boron source is an alcohol source or a latex source, which is a saturated solution of boron oxide in alcohol or latex source, and the constant surface source diffusion method of boron spraying is adopted. Propulsion conditions: 1180~1250℃, N2=6L / min, O2=0.5L / min, time 60~200min; (7) Trench area photolithography: Photoresist is applied to the anode and cathode surfaces of the wafer, exposed, and developed to remove the photoresist in the trench window area; (8) Trench etching: Double-sided annular trench etching, with a trench depth of 120-150 μm and a trench surface width of 400-600 μm; (9) SIPOS deposition: After the wafer is cleaned, a SIPOS thin film is deposited at 500℃~800℃ in the exposed PN junction area of ​​the trench to form a SIPOS layer (12) to protect the mesa; (10) Glass passivation: Glass powder is coated in the wafer trench by scraping or photoresist method, and then sintered at a low temperature of 500℃~580℃ and a high temperature of 800℃~850℃ to form a glass passivation film (13). (11) LTO deposition: SiO2 passivation layer is deposited on the wafer surface at a temperature of 400℃~600℃ (14). (12) BOE etching: Photoresist is applied to the wafer surface, exposed, developed, and the SIPOS and SiO2 passivation layers in the window area are removed, and then the photoresist is removed. (13) First metal deposition: After the wafer is cleaned, a metal conductive layer is deposited on both sides of the wafer by evaporation. The thickness of the metal layer on the anode side is 2-4 μm and the thickness of the metal layer on the cathode side is 6-12 μm. (14) First metal etching: Photoresist is applied to both sides of the wafer surface, exposed, and developed to remove the metal layer of the trench window area and the gate cathode isolation area, and then the photoresist is removed. (15) Alloy: At a temperature of 500℃~550℃, the metal conductive layer is alloyed with the wafer to increase the ohmic contact and welding force between the metal and the wafer; (16) Second metal deposition: After wafer cleaning, multiple layers of conductive metal Ti-Ni-Ag or Ti-Ni-Au are sequentially deposited on the anode surface of the wafer, with thicknesses of 0.2 μm, 0.5 μm and 1.2 μm, respectively; (17) Second metal etching: Photoresist is applied to the anode surface of the wafer, exposed, developed, and the multilayer metal conductive layer in the trench location window area is removed, and then the photoresist is removed; (18) Test and sort semiconductor chip parameters, separate, inspect and label chips.

10. A method for manufacturing a double-sided trench semiconductor chip according to claim 9, characterized in that: Between steps (17) and (18), polyimide is coated on both sides of the wafer surface, and then the polyimide on the metal layer is removed by photolithography, and then SiO2 is applied. A protective layer (16) is formed on the surface of the passivation layer (14).

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