Preparation method of silicon micro-strip detector and silicon micro-strip detector
By incorporating trench isolation units into the silicon microstrip detector, the problem of poor energy resolution of the microstrip was solved, the uniformity of the microstrip leakage current and the reduction of crosstalk characteristics were achieved, and the energy resolution of the detector was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2024-11-04
- Publication Date
- 2026-05-08
AI Technical Summary
Silicon microstrip detectors suffer from poor energy resolution and uneven leakage current due to interstrip crosstalk characteristics in high-energy physics experiments, space physics, and cosmic ray science experiments.
Trench isolation units are set in the silicon substrate to reduce crosstalk between microstrips through physical and electrical isolation, reduce capacitance and charge sharing effects, and maintain the uniformity of microstrip leakage current.
This improved the energy resolution of the silicon microstrip detector, reduced crosstalk between microstrips, ensured leakage current uniformity, and enhanced detector performance.
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Figure CN122002940A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for fabricating a silicon microstrip detector and the silicon microstrip detector itself. Background Technology
[0002] Silicon microstrip detectors are widely used in high-energy physics experiments, space physics, and cosmic ray science experiments due to their advantages such as good position resolution, high energy resolution, wide linear range, and fast response time. The working principle of a silicon microstrip detector is as follows: when the detector is in operation, a reverse bias voltage is applied to the back electrode, causing the substrate to be in a fully depleted state. High-energy rays strike the incident window, forming electron-hole pairs. The holes drift along the electric field to the P-type doped layer, while the electrons drift to the N-type doped layer, and are subsequently collected by the front and back electrodes.
[0003] With the continuous development of silicon microstrip detector design and the continuous improvement of performance, the problem of interstrip crosstalk in microstrip detectors is becoming increasingly prominent. The crosstalk characteristics can cause charge sharing effect, leading to an increase in microstrip leakage current, which in turn leads to a deterioration in microstrip energy resolution. This limits the application of silicon microstrip detectors in high-energy physics experiments, space physics, and cosmic ray science experiments.
[0004] Therefore, in order to improve the working performance of silicon microstrip detectors, it is urgent to design a technical solution that can improve and reduce the crosstalk characteristics of silicon microstrip detectors and ensure uniform leakage current of microstrips, so as to solve the problem of poor energy resolution of silicon microstrip detectors in the existing technology. Summary of the Invention
[0005] The present invention aims to provide a method for fabricating a silicon microstrip detector and a silicon microstrip detector. By utilizing trench isolation units disposed between adjacent microstrip units in a silicon substrate, the crosstalk characteristics between microstrips of the silicon microstrip detector are reduced, the capacitance and charge sharing effects between microstrip units are reduced, and the uniformity of leakage current of microstrip units is maintained, thereby improving the microstrip energy resolution of the silicon microstrip detector; and solving the problem of poor microstrip energy resolution of silicon microstrip detectors in the prior art.
[0006] To achieve the above objectives, the present invention provides the following technical solution:
[0007] In a first aspect, the present invention provides a method for fabricating a silicon microstrip detector, which may include:
[0008] Provide silicon substrates;
[0009] A first doped layer, a passivation layer, and an electrode layer are sequentially deposited on the first surface of the silicon substrate.
[0010] The first doped layer, passivation layer, and electrode layer are pretreated to form a plurality of microstrip units and a plurality of guard ring units located on the silicon substrate; the plurality of guard ring units are located outside the plurality of microstrip units;
[0011] The silicon substrate between multiple adjacent microstrip units is pretreated to form multiple trench isolation units located in the silicon substrate, thereby obtaining a silicon microstrip detector.
[0012] Preferably, the pretreatment of the silicon substrate between multiple adjacent microstrip units to form multiple trench isolation units located in the silicon substrate may include:
[0013] Physical isolation is performed on the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units;
[0014] Electrical isolation is performed on multiple intermediate trench isolation units to obtain multiple target trench isolation units with a first doped layer;
[0015] The multiple target trench isolation units are configured as multiple trench isolation units located in the silicon substrate.
[0016] Preferably, the physical isolation of the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units may include:
[0017] A metal-catalyzed etching method is used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units, wherein the metal includes silver or copper;
[0018] Alternatively, an alkaline etching method can be used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units, wherein the alkaline solution includes KOH or NaOH solution, the etching temperature range is 20℃ to 90℃, and the concentration of the KOH or NaOH solution is 10% to 60%.
[0019] Preferably, the method of etching the silicon substrate between multiple adjacent microstrip units using metal-catalyzed etching to obtain multiple intermediate trench isolation units may include:
[0020] A vacuum deposition method is used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units;
[0021] Alternatively, a wet metal etching process can be used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units.
[0022] Preferably, the etching of the silicon substrate between multiple adjacent microstrip units using a wet metal etching process to obtain multiple intermediate trench isolation units may include:
[0023] A first mixture is used to deposit a metal layer on a silicon substrate between multiple adjacent microstrip units to obtain multiple metal layers; the first mixture is a mixture obtained by mixing silver nitrate, hydrofluoric acid and water, or copper sulfate, hydrofluoric acid and water in a first ratio of 1:5:200 to 3:7:240.
[0024] The silicon substrate is etched using a second mixture to obtain a plurality of first trenches; the second mixture is a mixture obtained by mixing hydrofluoric acid, hydrogen peroxide and water in a second ratio of 47:160:270 to 43:40:116.
[0025] A third mixture is used to etch away the metal layer around multiple first trenches to obtain multiple second trenches; the third mixture is a mixture obtained by mixing ammonia, hydrogen peroxide and water in a third ratio of 1:3:10 to 7:4:15.
[0026] A fourth mixture is used to roughen multiple second trenches to obtain multiple intermediate trench isolation units; the fourth mixture is a mixture obtained by mixing hydrofluoric acid, nitric acid and water in a fourth ratio of 80:54:116 to 72:100:124.
[0027] Preferably, the depth of the plurality of intermediate trench isolation units is 1 to 100 μm and the width is 5 μm to 200 μm.
[0028] Preferably, the junction depth of the doped layer of the plurality of target trench isolation units is 0.05–5 μm, and the peak surface doping concentration is 1e. 18 ~5e 20 / cm 3 .
[0029] Preferably, the silicon substrate comprises an N-type high-resistivity silicon substrate or a P-type high-resistivity silicon substrate; wherein, when the silicon substrate is an N-type high-resistivity silicon substrate, the resistivity of the N-type high-resistivity silicon substrate is 1000-20000 Ω·cm and the thickness is 100-500 μm.
[0030] Secondly, the present invention provides a silicon microstrip detector, wherein the silicon microstrip detector is fabricated using the silicon microstrip detector fabrication method described in the first aspect; the silicon microstrip detector may include:
[0031] silicon substrate;
[0032] Multiple microstrip units and multiple guard ring units are disposed on the first surface of the silicon substrate; the multiple guard ring units are located on the outside of the multiple microstrip units;
[0033] The silicon microstrip detector is obtained by placing multiple trench isolation units between multiple adjacent microstrip units in the silicon substrate.
[0034] Preferably, the plurality of microstrip units may include:
[0035] A first doped layer with a cross-sectional width of a first width is disposed on the first surface of the silicon substrate, a passivation layer with a cross-sectional width of a first width is disposed on the first doped layer away from the first surface of the silicon substrate, and an electrode layer with a cross-sectional width of a first width is disposed on the passivation layer away from the first doped layer.
[0036] The plurality of said protection ring units may include:
[0037] A first doped layer with a cross-sectional width of the second width is disposed on the first surface of the silicon substrate, a passivation layer with a cross-sectional width of the second width is disposed on the first doped layer away from the first surface of the silicon substrate, and an electrode layer with a cross-sectional width of the second width is disposed on the passivation layer away from the first doped layer.
[0038] Compared with the prior art, the present invention provides a method for fabricating a silicon microstrip detector, which involves providing a silicon substrate; sequentially depositing a first doped layer, a passivation layer, and an electrode layer on a first surface of the silicon substrate; pre-treating the first doped layer, passivation layer, and electrode layer to form multiple microstrip units and multiple guard ring units located on the silicon substrate; the multiple guard ring units being located outside the multiple microstrip units; and finally pre-treating the silicon substrate between the multiple adjacent microstrip units to form multiple trench isolation units located in the silicon substrate, thereby obtaining a silicon microstrip detector. Based on this, the trench isolation units can be used to reduce crosstalk between microstrip units, reduce capacitance and charge sharing effects between microstrip units, maintain the uniformity of microstrip leakage current, reduce the increase in leakage current caused by crosstalk between microstrips, and improve the microstrip energy resolution of the silicon microstrip detector. Attached Figure Description
[0039] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0040] Figure 1 The main flowchart of a method for fabricating a silicon microstrip detector provided by the present invention;
[0041] Figure 2A schematic diagram of the cross-sectional structure of a silicon microstrip detector provided by the present invention;
[0042] Figure 3 This is a top view of a silicon microstrip detector provided by the present invention.
[0043] Figure reference numerals: 101-Silicon substrate, 102-First doped layer, 103-Passivation layer, 104-Electrode layer, 105-Second doped layer, A-Microstrip unit, B-Guard ring unit, C-Trench isolation unit. Detailed Implementation
[0044] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.
[0045] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0046] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding related objects have an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.
[0047] Currently, due to the crosstalk characteristics of silicon microstrip detectors, the leakage current of the microstrips is uneven, which causes changes in the energy resolution of the microstrips at different locations. Furthermore, with the continuous development of silicon microstrip detector design and the continuous improvement of performance, the crosstalk problem between microstrips is becoming more and more prominent, which leads to a deterioration in the energy resolution of the microstrips.
[0048] In view of this, in order to improve the microstrip energy resolution of the microstrip detector, the present invention provides a method for fabricating a silicon microstrip detector and a silicon microstrip detector. By setting trench isolation units between microstrips, crosstalk between microstrips can be reduced, inter-strip capacitance and charge sharing effects can be reduced, the uniformity of microstrip leakage current can be maintained, and the microstrip energy resolution of the silicon microstrip detector can be improved.
[0049] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:
[0050] Firstly, please refer to Figure 1 , Figure 1 This is a main flowchart of a method for fabricating a silicon microstrip detector provided by the present invention. The execution entity is a server or terminal device equipped with the technical solution disclosed in the embodiments of the present invention, such as a silicon microstrip detector fabrication platform or microfabrication equipment, etc.
[0051] exist Figure 1 The method may include:
[0052] Step 110: Provide a silicon substrate.
[0053] In step 110, the provided silicon substrate can be single-crystal silicon or other semiconductor materials, such as sapphire or silicon carbide; the silicon substrate can be an N-type high-resistivity silicon substrate or a P-type high-resistivity silicon substrate, and no specific limitation is made in this invention; in this invention, an N-type high-resistivity silicon substrate is used as an example for illustration.
[0054] Step 120: A first doped layer, a passivation layer, and an electrode layer are sequentially deposited on the first surface of the silicon substrate.
[0055] Step 130: Pre-process the first doped layer, passivation layer and electrode layer to form a plurality of microstrip units and a plurality of guard ring units located on the silicon substrate; the plurality of guard ring units are located outside the plurality of microstrip units.
[0056] Step 140: Pre-process the silicon substrate between multiple adjacent microstrip units to form multiple trench isolation units located in the silicon substrate, thereby obtaining a silicon microstrip detector.
[0057] In steps 120 to 140, a first doped layer, a passivation layer, and an electrode layer are first deposited sequentially on the first surface of a silicon substrate by deposition. Then, the multilayer structure is etched according to a preset pattern to obtain multiple microstrip units and multiple guard ring units located on the silicon substrate, with the guard ring units located outside the multiple microstrip units. Finally, the silicon substrate between multiple adjacent microstrip units is etched to form multiple trench units within the silicon substrate, resulting in the silicon microstrip detector of this invention. The multiple microstrip units are used to absorb charge carriers generated by rays or particles in the substrate to read out the detection signal. The multiple guard ring units are used to reduce edge leakage current of the silicon microstrip detector and improve its high-voltage withstand performance. The multiple trench isolation units are used to reduce crosstalk characteristics of the multiple microstrip units, reduce capacitance and charge sharing effects between the multiple microstrip units, and ensure the uniformity of leakage current among the multiple microstrip units. This achieves the technical effect of improving the microstrip energy resolution of the silicon microstrip detector.
[0058] It should be noted that in step 130, the cross-sectional width of any one of the multiple microstrip units can be greater than the cross-sectional width of any one of the multiple protective ring units. Of course, the cross-sectional width of any one of the multiple microstrip units can also be less than or equal to the cross-sectional width of any one of the multiple protective ring units; it can be set according to the actual situation. In the embodiment of the present invention, the example is that the cross-sectional width of any one of the multiple microstrip units can be greater than the cross-sectional width of any one of the multiple protective ring units. Preferably, the width of any one microstrip unit is 5μm to 3mm, and the width of any one protective ring unit is 5μm to 500μm.
[0059] Based on this, the present invention sequentially deposits a first doped layer, a passivation layer, and an electrode layer on a first surface of a silicon substrate, and pre-treats the first doped layer, passivation layer, and electrode layer to form multiple microstrip units and multiple guard ring units on the silicon substrate. Then, the silicon substrate between multiple adjacent microstrip units is pre-treated to form multiple trench isolation units in the silicon substrate, thus obtaining a silicon microstrip detector. This utilizes multiple trench isolation units to reduce the crosstalk characteristics of the multiple microstrip units, reduce the capacitance and charge sharing effects between the multiple microstrip units, and ensure the uniformity of leakage current of the multiple microstrip units. This improves the microstrip energy resolution of the silicon microstrip detector and solves the problem of poor microstrip energy resolution in existing silicon microstrip detectors.
[0060] Preferably, the method for fabricating a silicon microstrip detector provided by the present invention may further include: sequentially depositing a second doped layer and an electrode layer on a second surface of a substrate; the first doped layer and the second doped layer have different doping types; the electrode layer formed on the second doped layer is used to apply an external bias voltage. The second surface is the opposite surface of the first surface.
[0061] Specifically, when the substrate is an N-type high-resistivity silicon substrate, the first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer; when the substrate is a P-type high-resistivity silicon substrate, the first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer. Preferably, when the silicon substrate is an N-type high-resistivity silicon substrate, the resistivity of the N-type high-resistivity silicon substrate is 1000–20000 Ω·cm, and the thickness is 100–500 μm. The junction depth of the P-type and N-type doped layers is between 0.05 and 5 μm, and the peak surface doping concentration is 1e. 18 ~5e 20 / cm 3 between.
[0062] Based on this, a reverse bias can be applied to the back electrode to bring the substrate to a fully depleted state. High-energy rays bombard the substrate, exciting electron-hole pairs. The holes drift along the electric field to the P-type doped layer and are collected by the front electrode, while the electrons drift to the N-type doped layer and are collected by the back electrode. The signal charge collected on the electrodes is amplified by a charge preamplifier connected to the readout chip to obtain a pulse signal. A multichannel counter counts the pulse signals at different heights, and the final energy spectrum result is obtained after software processing.
[0063] Preferably, in step 140, pre-processing the silicon substrate between multiple adjacent microstrip units to form multiple trench isolation units located in the silicon substrate may include:
[0064] First, the silicon substrate between multiple adjacent microstrip units is physically isolated to obtain multiple intermediate trench isolation units; then, the multiple intermediate trench isolation units are electrically isolated to obtain multiple target trench isolation units with a first doped layer; these multiple target trench isolation units are used as multiple trench isolation units located in the silicon substrate. Preferably, the trench isolation units are located between two adjacent microstrips, and both the microstrip units and the trench isolation units have multiple equally spaced arrangement features.
[0065] Based on this, the trench isolation unit in this invention includes physical isolation and electrical isolation, thereby reducing the crosstalk characteristics of microstrips and achieving uniformity of leakage current in each microstrip.
[0066] Specifically, physical isolation is achieved using a wet etching process, which includes metal-catalyzed etching and alkaline etching. This involves physically isolating the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units. This can be achieved using the following two methods:
[0067] Method 1: A metal-catalyzed etching method can be used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units, wherein the metal includes silver or copper.
[0068] Method 2: Alkaline etching can be used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units. The alkaline solution includes KOH or NaOH solution, the etching temperature range is 20℃ to 90℃, and the concentration of KOH or NaOH solution is 10% to 60%.
[0069] It should be noted that alkaline etching achieves physical isolation by preparing KOH or NaOH solution and etching the isolated areas on the substrate; metal catalytic etching achieves physical isolation by depositing metal, such as silver, in the isolated areas of the substrate, etching under the combined action of hydrofluoric acid and hydrogen peroxide, removing the silver under the action of ammonia and hydrogen peroxide, and finally achieving physical isolation under the action of hydrofluoric acid and nitric acid.
[0070] Specifically, in Method 1, a metal catalytic etching method is used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units. Alternatively, a vacuum deposition method can be used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units; or, a metal wet process can be used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units.
[0071] For example, etching the silicon substrate between multiple adjacent microstrip units using a wet metal etching process to obtain multiple intermediate trench isolation units may include the following steps:
[0072] S1: A first mixture is used to deposit a metal layer on a silicon substrate between multiple adjacent microstrip units to obtain multiple metal layers; the first mixture is preferably a mixture obtained by mixing silver nitrate, hydrofluoric acid and water, or copper sulfate, hydrofluoric acid and water in a first ratio of 1:5:200 to 3:7:240.
[0073] S2: The silicon substrate is etched using the second mixture to obtain multiple first trenches; the second mixture is a mixture obtained by mixing hydrofluoric acid, hydrogen peroxide and water in a second ratio of 47:160:270 to 43:40:116.
[0074] S3: The metal layer around the first trenches is etched away using a third mixture to obtain multiple second trenches; the third mixture is a mixture obtained by mixing ammonia, hydrogen peroxide and water in a third ratio of 1:3:10 to 7:4:15.
[0075] S4: The roughness of multiple second trenches is treated by the fourth mixture to obtain multiple intermediate trench isolation units; the fourth mixture is a mixture obtained by mixing hydrofluoric acid, nitric acid and water in a fourth ratio of 80:54:116 to 72:100:124.
[0076] Through the wet etching methods described in S1 to S4 above, high-quality intermediate trench isolation units are obtained, which are evenly distributed in multiple adjacent microstrip units; the depth of a single trench isolation unit formed by physical isolation is preferably 1 to 100 μm, and the width is preferably 5 μm to 200 μm.
[0077] Furthermore, the physically isolated trench units are electrically isolated using P-type doping; however, when a P-type high-resistivity substrate is used, N-type doping can also be employed for electrical isolation. Preferably, the junction depth of the doped layer for the multiple target trench isolation units is 0.05–5 μm, and the peak surface doping concentration is 1e⁻¹. 18 ~5e 20 / cm 3 .
[0078] Specifically, P-type and N-type doped layers can be formed by ion implantation, or amorphous, microcrystalline, or polycrystalline silicon layers can be deposited using processes such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), and Ultra-high Vacuum Chemical Vapor Deposition (UHVCVD). The thickness of the P-type and N-type doped amorphous, microcrystalline, or polycrystalline silicon layers is between 3 nm and 50 nm. This application does not limit the specific thickness of the P-type and N-type doped layers, and adjustments can be made according to the actual application scenario.
[0079] Based on this, the present invention provides a method for fabricating a silicon microstrip detector, in which multiple trench isolation units with physical and electrical isolation are formed, and the trench isolation units are located between two adjacent microstrip units. Both the microstrip units and the trench isolation units have the feature of multiple equally spaced arrangements; thereby, the crosstalk characteristics between multiple microstrip units can be reduced by using multiple trench isolation units, and the uniformity of leakage current of each microstrip unit can be achieved.
[0080] It should be noted that the formation of the doped layer can include ion implantation, amorphous silicon, or polycrystalline silicon layers; the passivation layer can include silicon oxide, silicon nitride, aluminum oxide, intrinsic amorphous silicon, or polycrystalline silicon layers. The passivation layer can be formed by silicon oxide, silicon nitride, aluminum oxide, amorphous silicon, polycrystalline silicon, or silicon oxide, or by a combination of silicon oxide, silicon nitride, aluminum oxide, amorphous silicon, polycrystalline silicon, or silicon oxide. No specific limitations are made in this scheme.
[0081] Secondly, the present invention provides a silicon microstrip detector, wherein the silicon microstrip detector is fabricated using the silicon microstrip detector fabrication method described in the first aspect; please refer to the following references. Figures 2 to 3 , Figure 2 This is a schematic diagram of the cross-sectional structure of a silicon microstrip detector provided by the present invention. Figure 3 A top view of a silicon microstrip detector provided by the present invention; Figure 2 for Figure 3 A schematic diagram of the cross section corresponding to the tangent line "OO".
[0082] exist Figure 2 In this context, silicon microstrip detectors may include:
[0083] A silicon substrate 101; a plurality of microstrip units A and a plurality of guard ring units B disposed on the first surface of the silicon substrate 101; the plurality of guard ring units B being located outside the plurality of microstrip units A; and a plurality of trench isolation units C disposed between the plurality of adjacent microstrip units A and located in the silicon substrate 101 to obtain the silicon microstrip detector.
[0084] See also Figure 3 It can be concluded without a doubt that the multiple microstrip units A, multiple guard ring units B, and multiple trench isolation units C in the silicon microstrip detector are evenly distributed. The multiple guard ring units B are distributed around the perimeter to form a guard ring for the multiple microstrip units, and the multiple trench isolation units C are distributed between each adjacent microstrip unit A, forming physical isolation and electrical isolation.
[0085] Preferably, the plurality of microstrip units A may include: a first doped layer 102 with a cross-sectional width of a first width disposed on the first surface of the silicon substrate 101, a passivation layer 103 with a cross-sectional width of a first width disposed on the first doped layer 102 away from the first surface of the silicon substrate 101, and an electrode layer 104 with a cross-sectional width of a first width disposed on the passivation layer 103 away from the first doped layer 102.
[0086] Multiple guard ring units B may include: a first doped layer 102 with a cross-sectional width of a second width disposed on the first surface of the silicon substrate 101; a passivation layer 103 with a cross-sectional width of a second width disposed on the first doped layer 102 away from the first surface of the silicon substrate 101; and an electrode layer 104 with a cross-sectional width of a second width disposed on the passivation layer 103 away from the first doped layer 102. The first width may be greater than the second width, or the first width may be less than or equal to the second width. In this embodiment of the invention, the first width is greater than the second width as an example.
[0087] Preferably, the silicon microstrip detector may further include: a second doped layer 105 and an electrode layer 104 sequentially deposited on the second surface of the silicon substrate 101; wherein the first doped layer 102 and the second doped layer 105 have different doping types; the electrode layer 104 on the second doped layer 105 is used to apply an external bias voltage; and the second surface is the opposite surface of the first surface.
[0088] When the silicon substrate 101 is an N-type high-resistivity silicon substrate, the first doped layer 102 is P-type doped and the second doped layer 105 is N-type doped. The electrode layer 104 on the second doped layer 105 and the electrode layer on the passivation layer 103 are used to apply voltage. Their polarities can be the same or different, and can be set according to actual needs.
[0089] Preferably, the silicon microstrip detector may further include an integral structure formed by connecting the trench isolation unit C with the innermost guard ring; wherein, the connection between the isolation region and the innermost guard ring to form an integral structure ensures that the guard ring and the isolation region are at the same potential when a bias voltage is applied to the guard ring, and a potential of the same as that of the microstrip unit is applied to the innermost guard ring, thereby creating a uniform electric field around the microstrip unit. Furthermore, the connection between the trench isolation region and the innermost guard ring can conduct away crosstalk caused by charge sharing and surface-generated charges, reducing inter-strip capacitance, thereby ensuring the uniformity of leakage current of the microstrip under reverse bias, reducing device noise, improving signal accuracy, and thus enhancing the energy resolution of the device.
[0090] The N-type high-resistivity silicon substrate can also be a P-type high-resistivity silicon substrate. The P-type doped layer on the front side can be an N-type doped layer, and the N-type doped layer on the back side can be a P-type doped layer. The resistivity of the N-type high-resistivity silicon substrate is between 1000 and 20000 Ω·cm, and the thickness is between 100 and 500 μm.
[0091] The trench isolation region includes both physical and electrical isolation to reduce crosstalk and achieve uniformity of leakage current across all microstrips. The trench isolation region is located between two adjacent microstrips, and both the microstrips and the trench isolation region are characterized by multiple equally spaced segments.
[0092] In summary, the silicon microstrip detector provided in this application includes a strip electrode disposed on two surfaces of a semiconductor substrate. The strip electrode on the front side forms the microstrip portion of the device, while the all-metal electrode on the back side forms an ohmic contact and is also used to apply an external bias voltage. The front electrode collects signals generated by irradiation. An isolation region is provided between the microstrips on the front side to improve the uniformity of leakage current, reduce crosstalk caused by charge sharing, and improve the energy resolution of the microstrips. Furthermore, several guard rings are disposed around the microstrips and can interconnect with the isolation regions between the strips. This reduces the overall leakage current of the device and improves its withstand voltage performance. Additionally, the interconnection between the guard rings and the isolation regions effectively improves the uniformity of leakage current under reverse bias.
[0093] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.
[0094] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.
Claims
1. A method for fabricating a silicon microstrip detector, characterized in that, include: Provide silicon substrates; A first doped layer, a passivation layer, and an electrode layer are sequentially deposited on the first surface of the silicon substrate. The first doped layer, passivation layer and electrode layer are pretreated to form multiple microstrip units and multiple guard ring units located on the silicon substrate; The plurality of the protective ring units are located outside the plurality of the microstrip units; The silicon substrate between multiple adjacent microstrip units is pretreated to form multiple trench isolation units located in the silicon substrate, thereby obtaining a silicon microstrip detector.
2. The method as described in claim 1, characterized in that, The step of pre-processing the silicon substrate between multiple adjacent microstrip units to form multiple trench isolation units located in the silicon substrate includes: Physical isolation is performed on the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units; Electrical isolation is performed on multiple intermediate trench isolation units to obtain multiple target trench isolation units with a first doped layer; The multiple target trench isolation units are configured as multiple trench isolation units located in the silicon substrate.
3. The method as described in claim 2, characterized in that, The process of physically isolating the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units includes: A metal-catalyzed etching method is used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units, wherein the metal includes silver or copper; Alternatively, an alkaline etching method can be used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units, wherein the alkaline solution includes KOH or NaOH solution, the etching temperature range is 20℃ to 90℃, and the concentration of the KOH or NaOH solution is 10% to 60%.
4. The method as described in claim 3, characterized in that, The method employs metal-catalyzed etching to etch the silicon substrate between multiple adjacent microstrip units, resulting in multiple intermediate trench isolation units, including: A vacuum deposition method is used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units; Alternatively, a wet metal etching process can be used to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units.
5. The method as described in claim 4, characterized in that, The method employs a wet metal etching process to etch the silicon substrate between multiple adjacent microstrip units to obtain multiple intermediate trench isolation units, including: A first mixture is used to deposit a metal layer on a silicon substrate between multiple adjacent microstrip units to obtain multiple metal layers; the first mixture is a mixture obtained by mixing silver nitrate, hydrofluoric acid and water, or copper sulfate, hydrofluoric acid and water in a first ratio of 1:5:200 to 3:7:
240. The silicon substrate is etched using a second mixture to obtain a plurality of first trenches; the second mixture is a mixture obtained by mixing hydrofluoric acid, hydrogen peroxide and water in a second ratio of 47:160:270 to 43:40:
116. A third mixture is used to etch away the metal layer around multiple first trenches to obtain multiple second trenches; the third mixture is a mixture obtained by mixing ammonia, hydrogen peroxide and water in a third ratio of 1:3:10 to 7:4:
15. A fourth mixture is used to roughen multiple second trenches to obtain multiple intermediate trench isolation units; the fourth mixture is a mixture obtained by mixing hydrofluoric acid, nitric acid and water in a fourth ratio of 80:54:116 to 72:100:
124.
6. The method as described in claim 2, characterized in that, The depth of the plurality of intermediate trench isolation units is 1 to 100 μm and the width is 5 μm to 200 μm.
7. The method as described in claim 2, characterized in that, The junction depth of the doped layer of the multiple target trench isolation units is 0.05–5 μm, and the peak surface doping concentration is 1e. 18 ~5e 20 / cm 3 .
8. The method as described in claim 1, characterized in that, The silicon substrate includes an N-type high-resistivity silicon substrate or a P-type high-resistivity silicon substrate; wherein, when the silicon substrate is an N-type high-resistivity silicon substrate, the resistivity of the N-type high-resistivity silicon substrate is 1000 to 20000 Ω·cm and the thickness is 100 to 500 μm.
9. A silicon microstrip detector, characterized in that, The silicon microstrip detector is fabricated using the method described in any one of claims 1 to 8. Silicon microstrip detectors include: silicon substrate; Multiple microstrip units and multiple guard ring units are disposed on the first surface of the silicon substrate; the multiple guard ring units are located on the outside of the multiple microstrip units; The silicon microstrip detector is obtained by placing multiple trench isolation units between multiple adjacent microstrip units in the silicon substrate.
10. The silicon microstrip detector as described in claim 9, characterized in that, The plurality of said microstrip units include: A first doped layer with a cross-sectional width of a first width is disposed on the first surface of the silicon substrate, a passivation layer with a cross-sectional width of a first width is disposed on the first doped layer away from the first surface of the silicon substrate, and an electrode layer with a cross-sectional width of a first width is disposed on the passivation layer away from the first doped layer. The plurality of said protection ring units include: A first doped layer with a cross-sectional width of the second width is disposed on the first surface of the silicon substrate, a passivation layer with a cross-sectional width of the second width is disposed on the first doped layer away from the first surface of the silicon substrate, and an electrode layer with a cross-sectional width of the second width is disposed on the passivation layer away from the first doped layer.