Preparation method of three-dimensional silicon detector
By optimizing the fabrication process of three-dimensional silicon detectors through staged etching and solid-state source thermal diffusion doping, the problems of flexibility and repeatability in the etching and doping stages are solved, achieving high-precision, high-reliability, and environmentally friendly fabrication, which is suitable for high-energy physics research, medical detection, and other fields.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF SCI & TECH OF CHINA
- Filing Date
- 2026-04-03
- Publication Date
- 2026-05-08
AI Technical Summary
In existing three-dimensional silicon detector fabrication processes, monolithic deep reactive ion etching has poor flexibility, in-situ doping processes have poor repeatability and are prone to environmental pollution, making it difficult to achieve high-precision and high-reliability fabrication of highly doped electrodes.
A staged etching and solid-state source thermal diffusion doping method is adopted. By etching p-type and n-type electrodes in stages and combining them with a solid-state diffusion source for high-temperature thermal diffusion doping, the Bosch process parameters are optimized, and the etching depth and doping process are gradually adjusted to achieve high aspect ratio and high doping concentration.
This technology enables the high-precision, high-reliability, and environmentally friendly fabrication of three-dimensional silicon detectors, reducing fabrication costs and improving process flexibility and repeatability, making it suitable for large-scale production.
Smart Images
Figure CN122002953A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of detector technology, and in particular to a method for fabricating a three-dimensional silicon detector. Background Technology
[0002] Silicon-based radiation detectors, with their superior detection performance, have found wide and crucial applications in various fields such as medical detection, high-energy physics research, national defense and security, and industrial inspection. They are particularly important in detecting charged particles such as protons, soft X-rays, and neutrons, serving as a vital carrier for acquiring core information about particle space, time, and energy. In high-energy physics, the measurement accuracy of charged particle information by silicon-based radiation detectors directly determines the quality of reconstructed physical events. In clinical medical diagnosis, the sensitivity and accuracy of X-ray detection are crucial to the reliability of diagnostic results. Therefore, promoting the technological upgrading of silicon-based radiation detectors has significant industrial and scientific research value.
[0003] Three-dimensional silicon detectors, as an important development direction for silicon-based radiation detectors, possess excellent radiation resistance and... High spatial resolution at the m-level, along with the potential for ultrafast temporal resolution, has become a research hotspot in the field of radiation detection. The cylindrical or trench electrodes of this type of detector are perpendicular to the wafer surface, partially or completely penetrating the silicon substrate. To effectively reduce the insensitive area of the detector while ensuring that it can generate a sufficiently strong induced signal (the intensity of the induced signal is positively correlated with the thickness of the silicon substrate), the electrode structure needs to have a large aspect ratio (the ratio of depth to width). This places stringent requirements on the fabrication process of three-dimensional silicon detectors.
[0004] Currently, the fabrication process of 3D silicon detectors still faces many key technical difficulties and challenges. Among them, the fabrication of highly doped electrodes is the core difficulty, mainly reflected in the two major stages of electrode etching and electrode doping. Existing technical solutions have significant technical defects in these two stages, making it difficult to meet the fabrication requirements of high-performance 3D silicon detectors.
[0005] In the electrode etching stage, existing technologies mainly employ the Bosch process within Deep Reactive Ion Etching (DRIE) to fabricate deep holes or trench electrodes with high aspect ratios. The Bosch process, also known as Alternating Sidewall Passivation Deep Silicon Etching, achieves anisotropic etching of silicon through rapid cycles of etching and passivation steps: during the passivation stage, polymer films are deposited on the sidewalls and bottom of the etched holes / trenches using gases such as C4F8 under plasma conditions; during the etching stage, ions generated by fluorine-containing gases such as SF6 bombard the bottom passivation layer, ensuring that fluorine radicals react only with the exposed silicon at the bottom, thus forming a vertical etching profile. However, existing solutions all employ a monolithic DRIE process, meaning the entire etching process uses the same set of process parameters. To improve the aspect ratio and verticality of the etched holes / trenches and enhance sidewall morphology, complex overall optimization of multiple parameters, such as gas flow rate, RF power, substrate temperature, and vacuum pressure, is required, resulting in extremely poor flexibility in process adjustments. Meanwhile, the inherent cyclic characteristics of the Bosch process cause the etched sidewalls to form a wavy, scallop-like morphology. In the monolithic etching process, the passivation-etching cycle cannot precisely adapt the parameters to the process requirements of different etching depths, further exacerbating problems such as lateral over-etching at the top of the etched area, shrinkage at the bottom, and poor sidewall roughness, which seriously affects the accuracy of the electrode structure.
[0006] In the electrode doping stage, the electrode region of the three-dimensional silicon detector needs to be highly doped to achieve low-resistance ohmic contact between the doped region and the metal electrode, ensuring efficient transmission of electrical signals. In existing technologies, ion implantation, as a conventional high-concentration doping technique, can precisely control the doping dose and depth, but it is limited by the incident angle and transmission path of ions, making it impossible to achieve uniform doping on the sidewalls and bottom of holes / trenches with large aspect ratios. To solve this problem, the industry often uses in-situ doping processes for high aspect ratio holes / trenches. The principle is to simultaneously introduce dopant gas (such as B2H6, PH3) and silicon source gas into the reaction chamber during chemical vapor deposition or molecular beam epitaxy, so that the doped atoms directly bind to the grown thin film lattice. However, this process has many fatal flaws: on the one hand, dopant gases are easily adsorbed on the walls of the reaction chamber and the inner walls of the gas pipes, and will be slowly released in subsequent processes, resulting in serious cross-contamination between different batches and different doping types, which greatly reduces process repeatability and product yield; on the other hand, commonly used dopant gases such as B2H6 and PH3 have dangerous characteristics such as high toxicity, flammability and explosiveness, which puts extremely high technical and equipment requirements on the gas transportation, storage and exhaust gas treatment systems, which not only increases the preparation cost, but also poses potential hazards to the personal safety of experimental operators and the ecological environment.
[0007] In summary, current three-dimensional silicon detector fabrication processes suffer from poor flexibility in monolithic deep reactive ion etching, poor repeatability of in-situ doping processes, and easy environmental pollution. There is an urgent need to design a technical solution that can achieve high-precision, high-reliability, and environmentally friendly fabrication of highly doped electrodes. Summary of the Invention
[0008] The purpose of this invention is to provide a method for fabricating a three-dimensional silicon detector to solve the problems existing in the prior art, and to achieve high-precision, high-reliability, and environmentally friendly fabrication of highly doped electrodes.
[0009] To achieve the above objectives, the present invention provides the following solution: This invention provides a method for fabricating a three-dimensional silicon detector, comprising the following steps: S1, wafer pretreatment to meet electrode etching requirements; S2, staged etching of p-type electrodes, each stage contains multiple cyclic etching processes, the cyclic etching parameters are the same in the same stage, and the etching parameters of different stages gradually change according to the etching depth; S3, solid-state source thermal diffusion doping, fills the holes or trenches of the p-type electrode with polysilicon, and uses a solid-state diffusion source to perform high-temperature thermal diffusion doping to achieve doping of the holes or trenches. S4, post-processing to form a complete p-type electrode structure; S5. Repeat steps S2 to S4 to etch the n-type electrode in stages, thermally diffuse doping of the solid source wafer, and post-processing to form a complete n-type electrode structure. S6, metal connection of n-type electrode and passivation of wafer surface; S7, the back side of the wafer is etched with windows and metal is deposited on the back side to achieve metal connection of the p-type electrode.
[0010] In one embodiment, in step S2, each cycle of each stage includes three steps: depositing a passivation layer, anisotropically etching the bottom of the passivation layer, and isotropically etching silicon. As the etching depth increases, the chamber pressure during the passivation layer deposition step gradually decreases from the initial stage to the final stage, while the deposition time gradually increases. As the etching depth increases, the bias power of the bottom process step of the anisotropic etching passivation layer gradually increases from the beginning to the end, the chamber pressure gradually decreases, and the etching time gradually increases. As the etching depth increases, the etching time for each isotropic silicon etching process step gradually increases from the beginning to the end.
[0011] In one embodiment, step S3 includes: The wafer is placed on a quartz boat inside the furnace tube; The quartz boat is pushed into the furnace tube, and the pressure and flow rate of the deposition gas inside the furnace tube are adjusted to deposit polycrystalline silicon into the holes or trenches under low pressure vapor phase. After deposition is complete, the quartz boat is pushed out of the furnace tube; The wafer and the solid-state diffusion source are placed on the same quartz boat in the furnace tube; The quartz boat was pushed into the furnace tube, the furnace tube temperature and gas atmosphere were adjusted, and high-temperature thermal diffusion doping was performed using a solid diffusion source. After diffusion doping, the quartz boat is pushed out of the furnace tube, and the unreduced glass layer is removed with a buffer oxide etchant.
[0012] In one embodiment, step S1 includes: S101, clean the wafer and prepare a field oxide layer on its surface; S102, UV lithography forms the isolation structure p-stop; S103, the windowing and oxidation of the isolation structure p-stop; S104, UV lithography is used to form the isolation structure p-stop; S105, ion implantation of the isolated p-stop structure; S106, high-temperature annealing and oxidation of the isolation structure p-stop; S107, for preparing an etching mask; S108, p-type electrode is formed by ultraviolet photolithography; S109, etching mask and field oxide layer.
[0013] In one embodiment, step S4 includes: S401, prepare a silicon dioxide barrier layer; S402, fill the pores of the p-type electrode by depositing polycrystalline silicon to fill the pores of the p-type electrode; S403, UV lithography is used to form the cap structure on top of the p-type electrode; S404, etching undoped polysilicon / silicon dioxide / doped polysilicon; S405 is used to prepare a silicon dioxide barrier layer.
[0014] In one embodiment, the following step is further included between step S4 and step S5: Preparation of etching masks; Ultraviolet lithography is used to form n-type electrodes; Etching mask and field oxide layer.
[0015] In one embodiment, step S6 includes: S601, Etching the undoped polysilicon layer on top of the n-type electrode; S602, used to prepare the n-type electrode contact region; S603, deposited metal layer forms ohmic contact; S604, UV lithography and metal etching; S605, used to prepare a surface passivation layer; S606, surface passivation layer with windows; S607, prepare a temporary metal layer.
[0016] In one embodiment, step S7 includes: First, etch the polysilicon, then etch the silicon dioxide, then continue etching the polysilicon, and finally etch the silicon dioxide. Metal deposition on the back side.
[0017] In one embodiment, the isolation structure p-stop has a geometric structure such as a ring, square, or hexagon. If an n-type substrate wafer is used, the fabrication of the isolation structure p-stop can be omitted.
[0018] In one embodiment, the two-stage etching can be performed using a single-sided processing technology, where both stages are performed on the same side of the wafer; or a double-sided processing technology can be selected, where the two stages are performed from opposite sides of the wafer. If a double-sided processing technology is selected, step S6 should be repeated on the back side of the wafer after step S7 to achieve the metal connection of the p-type electrode.
[0019] The present invention achieves the following technical effects compared to the prior art: The fabrication method of the three-dimensional silicon detector of this invention is simple, low-cost, safe, reliable, environmentally friendly, efficient, and conducive to large-scale production. This invention optimizes the Bosch process, employing a staged etching method. Each stage includes multiple cyclic etching processes, with identical etching parameters within the same stage. The etching parameters in different stages gradually change according to the etching depth, achieving good controllability, high aspect ratio, vertical sidewalls, and a micro-scallop morphology, resulting in high precision and reliability. The fabrication method employs a two-step doping strategy: the first step fills the holes or trenches with polycrystalline silicon, and the second step uses a solid-state diffusion source for high-temperature thermal diffusion doping. High-temperature thermal diffusion doping using a solid-state diffusion source is safer and more environmentally friendly than traditional doping gases, achieving a low-cost, safe, reliable, environmentally friendly, and efficient high-concentration doping process. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1This is a schematic diagram of the field oxygen layer during the process of the method of the present invention; Figure 2 This is a schematic diagram of the windowing and oxidation of the p-stop region of the isolation structure in the process of the present invention; Figure 3 This is a schematic diagram of ion implantation during the method of the present invention; Figure 4 This is a schematic diagram of the high-temperature annealing and oxidation process after ion implantation in the method of the present invention. Figure 5 This is a schematic diagram of the electron beam evaporation of aluminum mask in the process of the present invention. Figure 6 This is a schematic diagram of the etching mask used in the method of the present invention; Figure 7 This is a schematic diagram of the DRIE process for etching the p-type electrode in the method of the present invention; Figure 8 This is a schematic diagram of LPCVD deposition of polycrystalline silicon and thermal diffusion doping of boron source solid wafer in the process of the present invention. Figure 9 This is a schematic diagram of the thermal oxidation formation of a silicon dioxide barrier layer during the process of the present invention. Figure 10 This is a schematic diagram of the pores filling the p-type electrode during the process of the method of the present invention; Figure 11 This is a schematic diagram of the three-layer structure of polysilicon / silicon oxide / polysilicon etched during the method of the present invention; Figure 12 This is a schematic diagram of the thermo-oxidation process in the method of the present invention; Figure 13 This is a schematic diagram of the DRIE process for etching the n-type electrode in the method of the present invention; Figure 14 This is a schematic diagram of the LPCVD deposition of polycrystalline silicon and the thermal diffusion doping of phosphorus source solid wafers during the process of the present invention. Figure 15 This is a schematic diagram of the pores used to fill the n-type electrode during the process of the method of the present invention; Figure 16 This is a schematic diagram of the etching of polysilicon during the method of the present invention; Figure 17 This is a schematic diagram of the etching of polysilicon to form the contact region during the process of the present invention. Figure 18 This is a schematic diagram of the deposited metal electrode in the method of the present invention; Figure 19 A schematic diagram showing the deposited passivation layer and its opening during the method process of this invention; Figure 20 This is a schematic diagram of the back-side metal electrode deposition process in the method of the present invention; Figure 21 This is a SEM image of the cross-section of a deep hole after segmented deep reactive ion etching in the process of the present invention. Figure 22 This is a SEM image of the cross-section of the fully filled deep hole during the process of the present invention. Detailed Implementation
[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0023] The purpose of this invention is to provide a method for fabricating a three-dimensional silicon detector to solve the problems existing in the prior art, and to achieve high-precision, high-reliability, and environmentally friendly fabrication of highly doped electrodes.
[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0025] The abbreviations and key terms involved in this invention are defined as follows: RIE: Reactive Ion Etching.
[0026] DRIE: Deep Reactive Ion Etching.
[0027] ICP: Inductively Coupled Plasma.
[0028] LPCVD: Low-Pressure Chemical Vapor Deposition.
[0029] PECVD: Plasma Enhanced Chemical Vapor Deposition.
[0030] ICP-PECVD: Inductively Coupled Plasma-Plasma Enhanced Chemical Vapor Deposition.
[0031] Ebeam: Electron Beam Evaporation.
[0032] Sputtering: Magnetron Sputtering.
[0033] SEM: Scanning Electron Microscope.
[0034] SIMS: Secondary Ion Mass Spectroscope.
[0035] VDP: Van der Pauw, the Van der Pauw method.
[0036] SiO2: Silicon Dioxide.
[0037] SiN: Silicon Nitride.
[0038] Si(OC2H5)4(TEOS): Tetraethyl Orthosilicate.
[0039] SOI: Silicon-On-Insulator.
[0040] Si-on-Si: Silicon-on-Silicon.
[0041] SF6: Sulfur Hexafluoride.
[0042] C4F8: Octafluorocyclobutane.
[0043] B2H6: Diborane, diborane.
[0044] BCl3: Boron Trichloride.
[0045] HBr: Hydrogen Bromide.
[0046] PH3: Phosphine.
[0047] C5H9NO (NMP): N-Methylpyrrolidone.
[0048] BOE: Buffered Oxide Etchant.
[0049] C3H8O (IPA): Isopropanol.
[0050] Al: Aluminum.
[0051] Al2O3: Aluminum Oxide.
[0052] Ti: Titanium.
[0053] Cr: Chromium.
[0054] Ni: Nickel.
[0055] S1813 Positive Photoresist: Shipley Microposit™ S1813 positive photoresist.
[0056] NR9-3000Y Negative Photoresist: Futurex NR9-3000Y negative photoresist.
[0057] LOR: Lift-Off Resist.
[0058] AZ ® 300 MIF: AZ ® 300 Metal Ion Free, AZ® 300 Metal Ion Free Developer.
[0059] SCCM: Standard Cubic Centimeter per Minute.
[0060] LPM: Liter Per Minute.
[0061] Min: Minute.
[0062] This invention provides a method for fabricating a three-dimensional silicon detector, with reference to... Figures 1-22 As shown, it includes the following steps: S1, wafer pretreatment to meet electrode etching requirements; S101, cleaning the wafer and preparing a field oxide layer on its surface; dry or wet oxidation can be selected, with a temperature range of 950-1100℃. o C, the process time is several to more than ten hours.
[0063] S102, UV lithography forms the p-stop isolation structure; the UV lithography process uses a mercury lamp wavelength of 365nm (i-line type), with an overlay accuracy of 1μm. Hard contact mode or vacuum mode can be selected during exposure. If higher overlay accuracy is required, such as electrode dimensions less than 1μm or the difference between the cap structure on the electrode top and the electrode diameter less than 1μm, step-through lithography can be selected. The p-stop, or P-type barrier layer, is a high-concentration P-type doped isolation structure fabricated on the surface of an n-type substrate / field region in semiconductor device and detector processes.
[0064] S103, the opening and oxidation of the p-stop isolation structure; after ICP or RIE etching of silicon oxide, the photoresist can be cleaned by using NMP solution in a water bath with heating combined with ultrasound, acetone and isopropanol solution, and depending on the situation, combined with ultrasound or dry photoresist removal. When preparing the shielding oxide layer, dry oxide is preferred, with a temperature range of 850-950°C. o C. The process time is ten to several tens of minutes to form a 10-20nm shielding oxide layer.
[0065] S104, UV lithography is used to form the isolation structure p-stop; S105, Ion implantation of the isolation structure p-stop; after high-dose ion implantation, the photoresist can be cleaned by repeatedly cleaning with NMP solution in a water bath and combined with ultrasonication, or by short-term treatment with piranha solution (concentrated sulfuric acid and hydrogen peroxide volume ratio 3:1) (5-10 min). S106, high-temperature annealing and oxidation of the isolation structure p-stop; the isolation structure p-stop of ion implantation and annealing processes can be designed with geometric structures such as ring, square, and hexagonal. Ion implantation can select different combinations of implantation energy and implantation dose, with implantation energy of 50-55 keV and implantation dose of 1×10⁻⁶. 13 -1×10 15 cm -2 The annealing process can be carried out at temperatures ranging from 1000-1100°C. o C. Suitable gases include oxygen and water vapor. High-temperature processes in subsequent treatments should be considered during injection and annealing; the maximum p-stop concentration should be higher than 10%. 15 cm -3 .
[0066] S107, Prepare an etching mask by depositing an Al mask layer on the wafer surface. The Al mask can be prepared using processes such as electron beam evaporation or magnetron sputtering. Besides Al masks, other hard mask materials that can be selected in other embodiments include Al, SiO2, Al2O3, Cr, and Ni. For deep reactive ion etching, a single-sided processing technique can be used, where both types of electrodes are prepared from the same side of the wafer; alternatively, a double-sided processing technique can be used, where the two types of electrodes are prepared from opposite sides of the wafer.
[0067] S2 involves staged etching of the p-type electrode. Each stage comprises multiple cyclic etching processes, with identical etching parameters within the same stage. The etching parameters for different stages gradually change according to the etching depth. Each stage includes three steps: depositing a passivation layer, anisotropically etching the bottom of the passivation layer, and isotropically etching silicon. As the etching depth increases, the chamber pressure in the passivation layer deposition step gradually decreases from the beginning to the end, while the deposition time gradually increases. As the etching depth increases, the bias power in the anisotropically etched bottom of the passivation layer step gradually increases from the beginning to the end, while the chamber pressure gradually decreases and the etching time gradually increases. As the etching depth increases, the etching time in the isotropic silicon etching step gradually increases from the beginning to the end.
[0068] S3, solid-state source thermal diffusion doping, involves filling polysilicon into the holes or trenches of the p-type electrode with a solid-state diffusion source and performing high-temperature thermal diffusion doping to achieve doping of the holes or trenches. Specifically, this includes placing the wafer on a quartz boat in a furnace tube; pushing the quartz boat into the furnace tube, adjusting the pressure and deposition gas flow rate within the furnace tube, and depositing polysilicon into the holes or trenches using low-pressure vapor deposition; after deposition, removing the quartz boat from the furnace tube; placing the wafer and solid-state diffusion source on the same quartz boat in the furnace tube; pushing the quartz boat into the furnace tube, adjusting the furnace tube temperature and gas atmosphere, and performing high-temperature thermal diffusion doping using the solid-state diffusion source; after diffusion doping, removing the quartz boat from the furnace tube and removing any unreduced glass layer using a buffered oxide etchant. Different thicknesses of polysilicon can be selected for low-pressure vapor deposition, such as 500nm, 1μm, and 1.5μm. Different diffusion temperatures and times can be selected for solid-state source thermal diffusion doping; the temperature range for boron-based solid-state sources is 800-1200°C. o C, The selectable temperature range for the solid-state phosphorus source is 900-1000°C. o C. After the thermal diffusion process, a thin SiO2 barrier layer is first prepared on the surface of the doped polycrystalline silicon, and then completely filled with polycrystalline silicon. Furthermore, the etched holes can be filled entirely with polycrystalline silicon; or they can be filled with SiO2; or they can be filled with the desired conversion material, for example, a material containing... 10 B 6Li materials are used to achieve neutron detection. When preparing the oxide layer (preferably at least 200 nm thick) on the polycrystalline silicon surface, wet oxidation can be used at a temperature range of 1000-1100°C. o C, wet oxygen for 10-20 minutes; or choose dry oxygen-wet oxygen-dry oxygen, temperature range 1000-1100℃. o C, dry oxygen for 10 min, wet oxygen for 10-20 min, dry oxygen for 10 min; or a deposition process, such as low-pressure vapor deposition TEOS, can be selected.
[0069] S4, post-processing to form a complete p-type electrode structure; S401, Preparation of a silicon dioxide barrier layer. A silicon dioxide barrier layer is grown on the surface of doped polycrystalline silicon by wet oxidation. S402, fill the pores of the p-type electrode by depositing polycrystalline silicon to fill the pores of the p-type electrode; S403, UV lithography forms the cap structure on top of the p-type electrode; S404, etching undoped polysilicon / silicon dioxide / doped polysilicon; S405, Preparation of a silicon dioxide barrier layer. A silicon dioxide barrier layer is grown on the wafer surface by wet oxidation. S406, thermal oxidation forms a silicon dioxide barrier layer.
[0070] Prepare an Al mask; form an n-type electrode using ultraviolet lithography; etch the Al mask and the field oxide layer.
[0071] S5. Repeat steps S2 to S4 to form a complete n-type electrode structure by etching the n-type electrode in stages, thermal diffusion doping of the solid source wafer, and post-processing.
[0072] S6, metal connection of n-type electrode and passivation of wafer surface; S601, Etching the undoped polysilicon layer on top of the n-type electrode; S602, fabrication of the n-type electrode contact region; when fabricating the electrode contact region, a lift-off process can be selected, with the process flow being: spin coating-UV lithography-deposition-lift-off; alternatively, an etching process can be selected, with the process flow being: deposition-UV lithography-ICP etching. Before depositing Al, 20-50 nm Ti can be deposited first to increase the adhesion of the metal layer.
[0073] S603, deposited metal layer forms ohmic contact; S604, UV lithography and metal etching; S605 is used to prepare a surface passivation layer; the deposition process can be selected, such as PECVD, ICP-PECVD, etc.
[0074] S606, surface passivation layer with openings; S607, prepare a temporary metal layer.
[0075] S7, the back side of the wafer is etched to create a window and deposit metal on the back side to achieve metal connection of the p-type electrode; first, polysilicon is etched, then silicon dioxide is etched, then polysilicon is etched again, and finally silicon dioxide is etched; back side metal is deposited.
[0076] This invention optimizes the Bosch process by employing a segmented etching strategy, using gradually varying process parameters across different depth ranges to achieve high controllability, high aspect ratio, vertical sidewalls, and very low roughness. This invention introduces a thermal diffusion process using a two-step strategy: first, low-pressure vapor deposition fills the deep holes or trenches with polysilicon; second, a solid-state diffusion source performs high-temperature thermal diffusion doping to achieve high-concentration doping in the deep holes or trenches. Furthermore, this invention improves the overall fabrication process of three-dimensional silicon detectors, achieving a compatible and reliable process.
[0077] Example 1 This embodiment uses a six-inch epitaxial wafer as an example for illustration. The steps of this embodiment are as follows: Step 1: Clean the wafer and prepare the field oxide layer. A 6-inch epitaxial wafer is selected, consisting of an epitaxial high-resistivity layer and a substrate low-resistivity layer. The thickness of the epitaxial high-resistivity layer is 45-55 μm, and the thickness of the substrate low-resistivity layer is 610-640 μm. The wafer is cleaned using the RCA standard cleaning method to remove organic contaminants, metal ions, particles, and the native oxide layer from the wafer surface. The wafer is then heated to 1050 °C in an oxygen atmosphere. o The sample is kept in the furnace tube of type C for 10 hours to form a field oxygen layer of approximately 400-500 nm on its surface. For example... Figure 1 As shown.
[0078] Step 2: UV photolithography to form the p-stop isolation structure. Spin coating: Spin a 1μm layer of S1813 photoresist onto the wafer surface; Baking: 115 o C, 90s; UV exposure: mercury lamp wavelength 365nm (i-line type), hard contact mode, exposure dose 120mJ / cm². 2 Development: in AZ ® Immerse in 300 MIF solution (2.38% by weight) for 50-60 seconds; rinsing: rinse with deionized water, then dry with a nitrogen gun; hardening: 100-110 o C, 3-5 min.
[0079] Step 3: Isolate the p-stop structure by opening windows and removing oxidation. Completely etch away the unprotected silicon oxide layer using RIE (Removable Image Erector Etching). The etching gases are CHF3 (25 sccm) and Ar (25 sccm), with an etching rate of 31-33 nm / min. Then remove any remaining photoresist from the surface. The specific steps are: sonicate the wafer in acetone solution for 3-5 minutes, then sonicate it in IPA solution for 3-5 minutes, then sonicate it in deionized water for 3-5 minutes. After removing the wafer from the deionized water, rinse it with deionized water for 20-30 seconds, and finally dry the wafer surface with a nitrogen gun. Then, heat the wafer at 900°C. o Dry oxidation at C for 40 min is used to form a 10-20 nm shielding oxide layer on the exposed silicon surface. For example... Figure 2 As shown.
[0080] Step 4: UV photolithography to form the p-stop isolation structure. Spreading: Spread a 2μm layer of S1813 photoresist onto the wafer surface; Baking: 115 o C, 90s; UV exposure: mercury lamp wavelength 365nm (i-line type), hard contact mode, exposure dose 140mJ / cm². 2 Development: Immerse in AZ300MIF solution (2.38% by weight) for 60-65 seconds; Washing: Rinse with deionized water, then dry with a nitrogen gun; Hardening: 100-110 o C, 3-5 min.
[0081] Step 5: Ion implantation of the isolation structure p-stop. Boron doping is performed on the isolation structure below the shielding oxide layer, and the area outside the isolation structure p-stop is masked by photoresist. The ion implantation energy is 55 keV, and the implantation dose is 4 × 10⁻⁶. 14 cm -2 .like Figure 3 As shown.
[0082] Step 6: High-temperature annealing and oxidation of the p-stop isolation structure. First, the photoresist on the surface is removed with NMP solution. Specifically, the wafer is placed at 80°C... o The wafer is heated in a water bath in C NMP solution for 20-40 minutes, then sonicated for 5-10 minutes, and this process is repeated 2-3 times. Next, the wafer is placed in IPA solution and sonicated for 5-10 minutes. Then, the wafer is placed in deionized water and sonicated for 3-5 minutes. After removing the wafer from the deionized water, it is rinsed with deionized water for 20-30 seconds. Finally, the surface moisture of the wafer is dried using a nitrogen gun. The wafer is then subjected to high-temperature annealing and oxidation at 1050°C. oC. Annealing and oxidation time is 31 minutes. First, oxygen is introduced for 10 minutes, then water vapor (hydrogen-oxygen ignition synthesis) is introduced for 11 minutes, and finally oxygen is introduced again for 10 minutes. The silicon oxide thickness above the p-stop is 200-300 nm, and the silicon oxide thickness at other locations on the wafer surface is 500-600 nm. For example... Figure 4 As shown.
[0083] Step 7, Prepare the Al mask. A thin Al film (200 nm) is deposited on the wafer surface using electron beam evaporation at a rate of 10 angstroms per second. For example... Figure 5 As shown.
[0084] Step 8: Form a p-type electrode using ultraviolet lithography. Repeat step 4.
[0085] Step 9, Etching the Al mask. During mask etching, the aluminum mask is first etched using ICP with a mixed gas of Cl2 (10 sccm), BCl3 (30 sccm), and HBr (10 sccm) at an etching rate of 140-180 nm / min; then the silicon oxide is etched using RIE with CHF3 (25 sccm) and Ar (25 sccm) at an etching rate of 31-33 nm / min. Figure 6 The diagram shows the process of photolithography and etching.
[0086] Step 10, Etch the p-type electrode. Etch a hole with a diameter of 5 μm and a depth of 50 μm using the optimized Bosch process. (Example:...) Figure 7 As shown, the entire etching process is divided into five stages, each stage consisting of three steps: depositing a passivation layer, anisotropically etching the bottom of the passivation layer, and isotropically etching silicon. The cycle numbers for the five stages are 100, 100, 100, 110, and 130, respectively. With increasing etching depth, the chamber pressure in the passivation layer deposition step gradually decreases from 29 mTorr in the first stage to 24 mTorr in the fifth stage, while the deposition time gradually increases from 850 ms to 2050 ms. In the anisotropic etching of the bottom of the passivation layer step, the bias power increases from 28 W in the first stage to 31 W in the fifth stage, the chamber pressure decreases from 18 mTorr to 14 Torr, and the etching time increases from 1500 ms to 2500 ms. In the isotropic silicon etching step, the etching time increases from 150 ms in the first stage to 1050 ms. In all five stages, the ICP power for the passivation layer deposition step was 1200W, and the C4F8 gas flow rate was 200sccm; the ICP power for the anisotropic etching of the passivation layer bottom process was 1000W, and the SF6 gas flow rate was 100sccm; the ICP power for the isotropic silicon etching process step was 1200W, the SF6 gas flow rate was 200sccm, and the chamber pressure was 25mTorr. Figure 21The image shows a SEM image of the cross-section of the deep hole after etching.
[0087] Step 11, Remove residual photoresist and aluminum mask. First, clean the surface of residual photoresist with NMP solution. Specifically, place the wafer at 80°C. o The wafer is heated in a water bath in C NMP solution for 20-30 minutes, then sonicated for 5-10 minutes; then placed in IPA solution and sonicated for 5-10 minutes; next, the wafer is placed in deionized water and sonicated for 3-5 minutes; after removing the wafer from the deionized water, it is rinsed with deionized water for 40-60 seconds; finally, the surface moisture of the wafer is dried with a nitrogen gun. The remaining aluminum mask is then etched using an aluminum etching solution. This aluminum etching solution is a mixture of phosphoric acid, acetic acid, nitric acid, and water in a volume ratio of 16:1:1:2. The specific steps for removing the remaining aluminum mask using the aluminum etching solution are as follows: the wafer is heated in a water bath in C NMP solution for 50 minutes. o Immerse the wafer in the aluminum etching solution of C for 5-10 minutes, then transfer it to a deionized water bath and immerse it for 3-5 minutes. Repeat the above steps 3 times, then rinse the wafer with deionized water for 1-2 minutes, and then put the wafer into an automatic cleaning machine for cleaning and spin drying.
[0088] Step 12: Deposit polysilicon to partially fill the p-type electrode. A 1μm thick layer of polysilicon is uniformly deposited on the wafer surface and the inner walls of the etched vias using LPCVD. The process temperature is 630°C. o C, the process gas is SiH4 (75 sccm), the pressure is 150 mTorr, and the deposition rate is 2.25 nm / min. For example... Figure 8 As shown. The main chemical reaction equations involved in the deposition process are as follows: Step 13, Thermal diffusion doping of the boron source solid-state wafer. The wafer and the boron source solid-state wafer are placed on the same quartz boat in the furnace tube for thermal diffusion doping. The specific process steps are: pushing the quartz boat into the furnace tube, 800... o C, 10 min, N2 gas flow rate 15 LPM; stable, 800 o C, 5 min, N2 gas flow rate 15 LPM; first stage of temperature increase, 10 o C / min, N2 gas flow rate 15 LPM; oxidation, 900 o C, 10 min, O2 flow rate 15 LPM; second stage temperature increase, 2.5 o C / min, N2 gas flow rate 15 LPM; diffusion, 950 o C, 40 min, N2 gas flow rate 15 LPM; cooling, 5 o C / min, N2 gas flow rate 15 LPM; push the quartz boat out of the furnace tube, 550 o C (or 700) oC), 10 min, N2 gas flow rate 15 LPM. After diffusion, remove the unreduced borosilicate glass layer with BOE solution, etching time 2-5 min. Since a boron skin forms on the wafer surface, this Si-B layer can be removed by low-temperature oxidation and rinsing processes. During low-temperature oxidation, the process temperature is 700 °C. o C. The process time is 20 min, and the process gas atmosphere is 100% O2. After the low-temperature oxidation process, the boron-silicon oxide is removed with BOE solution, and the etching time is 2-5 min. SIMS can analyze the distribution of doping concentration with depth on the wafer surface, and the VDP method can measure the resistivity of the wafer surface and thus calculate the average doping concentration. The main chemical reaction equations involved in the boron source doping process are as follows: Step 14: Thermal oxidation to form a silicon dioxide barrier layer. A thin silicon dioxide barrier layer is grown on the doped polycrystalline silicon surface by wet oxidation. The process temperature is 1050 °C. o C, the process time is 15 minutes, and the process gas atmosphere is water vapor (hydrogen-oxygen ignition synthesis). The grown silicon oxide thickness is 200-300 nm. For example... Figure 9 As shown.
[0089] Step 15: Fill the pores of the p-type electrode. LPCVD deposition of 1.4 μm thick polycrystalline silicon is used to fill the p-type electrode. The process is the same as in step 12. Figure 10 As shown. Figure 22 SEM image of the cross-section of a deep hole after polycrystalline silicon filling.
[0090] Step 16: UV photolithography forms the cap structure on top of the p-type electrode. Spin coating: Spin a 2.2μm thick layer of NR9-3000Y photoresist onto the wafer surface; Baking: 120°C. o C, 90s; UV exposure: mercury lamp wavelength 365nm (i-line type), hard contact mode, exposure dose 300mJ / cm². 2 Post-baking: 120 o C, 90s; Development: Immerse in AZ300MIF solution (2.38% by weight) for 50-60s; Washing: Rinse with deionized water, then dry with a nitrogen gun; Hardening: 120 o C, 3-5 min.
[0091] Step 17: Etch undoped polysilicon / silicon oxide / doped polysilicon. Etch the polysilicon using a two-step deposition-etching Bosch process. The etching conditions are as follows: Deposition cycle: ICP power 800-1000W, C4F8 gas flow rate 100-150 sccm, chamber pressure 5-10 mTorr; Etching cycle: ICP power 500-800W, bias power 55-75W, SF6 gas flow rate 80-120 sccm, vacuum pressure 5-10 mTorr. Etch the silicon oxide using RIE, using the same process conditions as in Step 9. Figure 11 As shown.
[0092] Step 18: Remove residual photoresist from the wafer surface. This process is the same as the photoresist removal process in Step 3.
[0093] Step 19: Thermal oxidation to form a silicon dioxide barrier layer. The process temperature is 1050°C. o C, the process time is 15 minutes, and the process gas atmosphere is water vapor (hydrogen-oxygen ignition synthesis). For example... Figure 12 As shown.
[0094] Step 20: Prepare the aluminum mask. Repeat steps 7, 8, and 9.
[0095] Step 21, etch the n-type electrode. The DRIE process etches a hole with a diameter of 5 μm and a depth of 35 μm, such as... Figure 13 As shown. The entire etching process was adjusted to four stages, each stage consisting of three steps: depositing a passivation layer, anisotropically etching the bottom of the passivation layer, and isotropically etching silicon. The cycle numbers for the four stages are 100, 85, 85, and 85, respectively. The etching process parameters for each stage are the same as those for the first four stages in step 10.
[0096] Step 22: Deposit polycrystalline silicon to partially fill the n-type electrode. Repeat steps 11 and 12. (Example) Figure 14 As shown.
[0097] Step 23, Thermal diffusion doping of the phosphorus source solid-state wafer. The wafer and the phosphorus source solid-state wafer are placed on the same quartz boat in the furnace tube for thermal diffusion doping. Specific process conditions are: the quartz boat is pushed into the furnace tube, 800... o C, 10 min, N2 gas flow rate 15 LPM; stable, 800 o C, 60 min, nitrogen flow rate 15 LPM; first stage of heating, 10 o C / min, N2 gas flow rate 15 LPM; second stage temperature increase, 950 o C, 2.5 o C / min, N2 gas flow rate 15 LPM; diffusion, 950 o C, 40 min, N2 gas flow rate 15 LPM; cooling, 5 oC / min, N2 gas flow rate 15 LPM; push the quartz boat out of the furnace tube, 550 o C (or 700) o C), 10 min, N2 gas flow rate 15 LPM. After diffusion, the phosphorus silicate glass layer is removed with BOE solution, etching time 3-5 min. SIMS can analyze the distribution of doping concentration with depth on the wafer surface, and VDP method can measure the resistivity of the wafer surface and thus calculate the average doping concentration. The main chemical reaction equations involved in the phosphorus source doping process are as follows: Step 24: Fill the pores of the n-type electrode. LPCVD deposition of 1.5 μm thick polycrystalline silicon is used to fill the n-type electrode. Process parameters are the same as in step 12. Figure 15 As shown.
[0098] Step 25: Ultraviolet lithography is used to form the cap structure on top of the n-type electrode. Repeat step 16.
[0099] Step 26: Etch undoped / doped polysilicon. The polysilicon etching process is the same as in step 17. Figure 16 As shown.
[0100] Step 27: Remove residual photoresist. Same as step 3.
[0101] Step 28: Etch the undoped polysilicon layer on top of the n-type electrode. Etch the polysilicon using ICP process, with the same process parameters as in step 17. Figure 17 As shown.
[0102] Step 29: The lift-off process forms the n-type electrode contact area. After uniformly applying a layer of LOR release adhesive to the wafer surface, 180... o Baking the photoresist at C for 5 min; then uniformly applying a 1 μm layer of S1813 photoresist, the same process as in step 12; then performing UV lithography, the same as in step 2; next, depositing 20 nm of Ti using Ebeam at a rate of 2 Å / s; then performing the lift-off process. The specific steps of the lift-off process are as follows: placing the wafer in an NMP solution at 80 °C... o Heat the wafer in a water bath for 30-40 minutes, then sonicate for 5 minutes; then sonicate in an IPA solution for 5 minutes; next, sonicate in deionized water for 3-5 minutes; after removing the wafer from the deionized water, rinse the wafer with deionized water for 20-30 seconds; finally, dry the surface of the wafer with a nitrogen gun.
[0103] Step 30: Deposit a metal layer to form an ohmic contact. 30 nm Ti and 1 μm Al are deposited using Ebeam vapor deposition.
[0104] Step 31: UV lithography and metal etching. ICP etching of 30nm Ti and 1μm Al. Etching conditions are the same as in step 9. The resist removal process is the same as in step 3. Figure 18 As shown.
[0105] Step 32: Prepare the surface passivation layer. Deposit 1 μm SiO2 by ICP-PECVD at a deposition rate of 22 nm / min.
[0106] Step 33: Open windows in the surface passivation layer. UV lithography is the same as in step 4, then RIE etching of SiO2, and finally removal of residual photoresist is the same process as in step 3. Figure 19 As shown.
[0107] Step 34: Prepare a temporary metal layer and lead out the n-type electrode from one side for subsequent performance testing. First, deposit 500 nm Al using Ebeam at a rate of 10 Å / s. Then, perform UV lithography, the same as in step 16. Next, perform ICP etching under the same conditions as in step 9. Finally, remove the residual photoresist using the same process as in step 3.
[0108] Step 35, Backside Etching for Windowing. Because the thermal oxidation and LPCVD processes in the above steps also generate silicon dioxide and deposit polysilicon on the back side of the wafer, an etching process is required on the back side of the epitaxial wafer. The etching steps are: first etch polysilicon, then etch SiO2, then continue etching polysilicon, and finally etch SiO2. The etching conditions for SiO2 and polysilicon are the same as in steps 9 and 17, respectively. Step 36, Backside Metal Deposition. 500 nm Al is deposited using Ebeam at a rate of 10 Å / s. (Example: ...) Figure 20 As shown.
[0109] Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. Furthermore, those skilled in the art will recognize that, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention.
Claims
1. A method for fabricating a three-dimensional silicon detector, characterized in that: Includes the following steps: S1, wafer pretreatment to meet electrode etching requirements; S2, staged etching of p-type electrodes, each stage contains multiple cyclic etching processes, the cyclic etching parameters are the same in the same stage, and the etching parameters of different stages gradually change according to the etching depth; S3, solid-state source thermal diffusion doping, fills the holes or trenches of the p-type electrode with polysilicon, and uses a solid-state diffusion source to perform high-temperature thermal diffusion doping to achieve doping of the holes or trenches. S4, post-processing to form a complete p-type electrode structure; S5. Repeat steps S2 to S4 to etch the n-type electrode in stages, thermally diffuse doping of the solid source wafer, and post-processing to form a complete n-type electrode structure. S6, metal connection of n-type electrode and passivation of wafer surface; S7, the back side of the wafer is etched with windows and metal is deposited on the back side to achieve metal connection of the p-type electrode.
2. The method for fabricating a three-dimensional silicon detector according to claim 1, characterized in that: In step S2, each cycle of each stage includes three steps: depositing a passivation layer, anisotropically etching the bottom of the passivation layer, and isotropically etching silicon. As the etching depth increases, the chamber pressure during the passivation layer deposition step gradually decreases from the initial stage to the final stage, while the deposition time gradually increases. As the etching depth increases, the bias power of the bottom process step of the anisotropic etching passivation layer gradually increases from the beginning to the end, the chamber pressure gradually decreases, and the etching time gradually increases. As the etching depth increases, the etching time for each isotropic silicon etching process step gradually increases from the beginning to the end.
3. The method for fabricating a three-dimensional silicon detector according to claim 1, characterized in that: Step S3 includes: The wafer is placed on a quartz boat inside the furnace tube; The quartz boat is pushed into the furnace tube, and the pressure and flow rate of the deposition gas inside the furnace tube are adjusted to deposit polycrystalline silicon into the holes or trenches under low pressure vapor phase. After deposition is complete, the quartz boat is pushed out of the furnace tube; The wafer and the solid-state diffusion source are placed on the same quartz boat in the furnace tube; The quartz boat was pushed into the furnace tube, the furnace tube temperature and gas atmosphere were adjusted, and high-temperature thermal diffusion doping was performed using a solid diffusion source. After diffusion doping, the quartz boat is pushed out of the furnace tube, and the unreduced glass layer is removed with a buffer oxide etchant.
4. The method for fabricating a three-dimensional silicon detector according to claim 1, characterized in that: Step S1 includes: S101, clean the wafer and prepare a field oxide layer on its surface; S102, UV lithography forms the isolation structure p-stop; S103, the windowing and oxidation of the isolation structure p-stop; S104, UV lithography is used to form the isolation structure p-stop; S105, ion implantation of the isolated p-stop structure; S106, high-temperature annealing and oxidation of the isolation structure p-stop; S107, for preparing an etching mask; S108, p-type electrode is formed by ultraviolet photolithography; S109, etching mask and field oxide layer.
5. The method for fabricating a three-dimensional silicon detector according to claim 1, characterized in that: Step S4 includes: S401, prepare a silicon dioxide barrier layer; S402, fill the pores of the p-type electrode by depositing polycrystalline silicon to fill the pores of the p-type electrode; S403, UV lithography forms the cap structure on top of the p-type electrode; S404, etching undoped polysilicon / silicon dioxide / doped polysilicon; S405 is used to prepare a silicon dioxide barrier layer.
6. The method for fabricating a three-dimensional silicon detector according to claim 1, characterized in that: The following steps are also included between steps S4 and S5: Preparation of etching masks; Ultraviolet lithography is used to form n-type electrodes; Etching mask and field oxide layer.
7. The method for fabricating a three-dimensional silicon detector according to claim 1, characterized in that: Step S6 includes: S601, Etching the undoped polysilicon layer on top of the n-type electrode; S602, for preparing the n-type electrode contact region; S603, deposited metal layer forms ohmic contact; S604, UV lithography and metal etching; S605, used to prepare a surface passivation layer; S606, surface passivation layer with openings; S607, prepare a temporary metal layer.
8. The method for fabricating a three-dimensional silicon detector according to claim 1, characterized in that: Step S7 includes: First, etch the polysilicon, then etch the silicon dioxide, then continue etching the polysilicon, and finally etch the silicon dioxide. Metal deposition on the back side.
9. The method for fabricating a three-dimensional silicon detector according to claim 1, characterized in that: The isolation structure p-stop can be circular, square, or hexagonal.
10. The method for fabricating a three-dimensional silicon detector according to claim 1, characterized in that: The two-stage etching process can be performed using a single-sided process, where both stages are etched on the same side of the wafer; or a double-sided process can be selected, where the two stages are etched from opposite sides of the wafer. If the double-sided process is selected, step S6 is repeated on the back side of the wafer after step S7 is completed to achieve the metal connection of the p-type electrode.