Display panel, electronic device, and method of manufacturing display panel

Abstract

The invention relates to a display panel, an electronic device, and a method of manufacturing the display panel. The display panel includes: a pixel circuit disposed on a substrate and including a thin film transistor, a capacitor, and a dual contact hole; and a light emitting element electrically connected to the pixel circuit, in which the double contact hole includes: a lower contact hole defined in the first insulating layer on the substrate; a lower conductive layer disposed on a top surface of the first insulating layer and inside the lower contact hole; an inorganic material filled in a recess provided in the lower conductive layer due to the lower contact hole; an intermediate conductive layer disposed on the lower conductive layer and the inorganic material; an upper contact hole defined in the second insulating layer on the first insulating layer; and an upper conductive layer disposed on a top surface of the second insulating layer and inside the upper contact hole, and connected to the intermediate conductive layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0155682, filed on November 5, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to a display panel, an electronic device including the display panel, and a method of manufacturing the display panel. Background Technology

[0004] Recently, display devices have been used for a wide variety of purposes. As the thickness and weight of display devices have decreased, the range of applications for display devices has greatly expanded.

[0005] Display devices typically include a display panel, which includes display elements employing one or more pixels and one or more pixel circuits for controlling electrical signals applied to the display elements. Pixel circuits include one or more thin-film transistors (TFTs), one or more capacitors, and multiple wirings.

[0006] Major research and development efforts have recently focused on the arrangement of thin-film transistors, capacitors, wiring, and contact holes to achieve high resolution and high integration in display devices. Summary of the Invention

[0007] One or more aspects of the embodiments of this disclosure are intended to include display devices having a display panel with high resolution and high integration, electronic devices including the display panel, and methods of manufacturing the display panel. However, the aspects of this disclosure are not limited thereto.

[0008] Other aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present embodiments.

[0009] According to one or more embodiments, a display panel includes: a substrate; pixel circuitry disposed on (e.g., on) the substrate, and including: at least one thin-film transistor, at least one capacitor, and at least one dual contact hole; and a light-emitting element electrically connected to the pixel circuitry, wherein the dual contact hole includes: a lower contact hole defined in a first insulating layer on the substrate; a lower conductive layer disposed on (e.g., on) a top surface of the first insulating layer and inside the lower contact hole; an inorganic material filled in a recess provided in the lower conductive layer by the lower contact hole; an intermediate conductive layer disposed on (e.g., on) the lower conductive layer and the inorganic material; an upper contact hole defined in a second insulating layer on the first insulating layer; and an upper conductive layer disposed on (e.g., on) a top surface of the second insulating layer and inside the upper contact hole, and connected to the intermediate conductive layer.

[0010] In one or more embodiments, the inorganic material can be provided by the aggregation of nanoparticles formed of metal oxides and / or metals (e.g., including metal oxides and / or metals). For example, the inorganic material may comprise aggregated nanoparticles of metal oxides and / or metals.

[0011] In one or more embodiments, the inorganic material may include at least one material selected from BaTiO3, BaSO3, BaSO4, Ba(NO3)2, TiO2, SiO2 and ZnO.

[0012] In one or more embodiments, the inorganic material may include at least one material selected from silver (Ag), gold (Au), platinum (Pt), and palladium (Pd).

[0013] In one or more embodiments, the upper contact hole may overlap with the lower contact hole.

[0014] In one or more embodiments, the dual contact hole may further include: a protective film disposed inside the recess along the shape of the lower conductive layer; and a buffer film disposed on (e.g., on) the protective film.

[0015] In one or more embodiments, the buffer membrane may be formed of a material different from the inorganic material.

[0016] In one or more embodiments, the at least one thin-film transistor may include a first thin-film transistor and a second thin-film transistor, and the at least one dual contact hole may include a first dual contact hole and a second dual contact hole, wherein the first dual contact hole connects the semiconductor layer of the first thin-film transistor to the pixel electrode of the light-emitting element.

[0017] In one or more embodiments, the at least one capacitor may include a first capacitor and a second capacitor, wherein the second dual contact hole connects the semiconductor layer of the second thin-film transistor to the second capacitor.

[0018] In one or more embodiments, the first capacitor may overlap with the first thin-film transistor.

[0019] According to one or more embodiments, a method of manufacturing a display panel includes: forming a conductive layer on a substrate; forming a first insulating layer covering the conductive layer and forming a lower contact hole in the first insulating layer, a portion of the conductive layer being exposed through the lower contact hole; forming a lower conductive layer connected to the conductive layer from a top surface of the first insulating layer along an inner surface of the lower contact hole; coating a dispersion solution of inorganic nanoparticles dispersed on the first insulating layer to cover the lower conductive layer; and performing an annealing process such that the inorganic nanoparticles agglomerate and fill recesses provided in the lower conductive layer by the lower contact hole.

[0020] In one or more embodiments, the method may further include cleaning the inorganic nanoparticles disposed outside the recess after the annealing.

[0021] In one or more embodiments, the method may further include: forming an intermediate conductive layer over the recess filled with the inorganic nanoparticles; forming a second insulating layer covering the intermediate conductive layer on the first insulating layer, and forming an upper contact hole in the second insulating layer, a portion of the intermediate conductive layer being exposed through the upper contact hole; and forming an upper conductive layer connected to the intermediate conductive layer from the top surface of the second insulating layer along the inner surface of the upper contact hole.

[0022] In one or more embodiments, the inorganic nanoparticles may include at least one material selected from BaTiO3, BaSO3, BaSO4, Ba(NO3)2, TiO2, SiO2 and ZnO.

[0023] In one or more embodiments, the inorganic nanoparticles may include at least one material selected from silver (Ag), gold (Au), platinum (Pt), and palladium (Pd).

[0024] In one or more embodiments, the method may further include forming a protective film on the lower conductive layer prior to coating the dispersion solution.

[0025] In one or more embodiments, the method may further include: partially filling the interior region of the lower contact hole by depositing a buffer film thicker than the protective film on the protective film using a chemical vapor deposition method; and removing the buffer film formed on the first insulating layer by using a chemical mechanical polishing process.

[0026] In one or more embodiments, the buffer membrane may be formed of a material different from the inorganic nanoparticles.

[0027] According to one or more embodiments, an electronic device includes: a display panel including dual contact holes; and a cover unit supporting and receiving the display panel, wherein the dual contact holes include: a lower contact hole defined in a first insulating layer; a lower conductive layer disposed on (e.g., on) a top surface of the first insulating layer and inside the lower contact hole; an inorganic material filling a recess provided in the lower conductive layer by the lower contact hole; an intermediate conductive layer disposed on (e.g., on) the lower conductive layer and the inorganic material; an upper contact hole defined in a second insulating layer on the first insulating layer; and an upper conductive layer disposed on (e.g., on) a top surface of the second insulating layer and inside the upper contact hole, and connected to the intermediate conductive layer.

[0028] In one or more embodiments, the electronic device may be a smartphone or a glasses-type (or similar) display device. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The above and other aspects, features, and advantages of certain embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 This is a schematic plan view illustrating a display panel according to one or more embodiments of the present disclosure;

[0031] Figure 2A and Figure 2B Each is an equivalent circuit diagram illustrating a pixel circuit in a display panel according to one or more embodiments of the present disclosure;

[0032] Figure 3 This is a schematic cross-sectional view illustrating a display panel according to one or more embodiments of the present disclosure;

[0033] Figure 4 This is a schematic cross-sectional view illustrating a dual contact hole according to one or more embodiments of the present disclosure;

[0034] Figures 5 to 10 These are schematic cross-sectional views illustrating methods for forming dual contact holes according to one or more embodiments of the present disclosure.

[0035] Figure 11 This is a schematic cross-sectional view illustrating a dual contact hole according to one or more embodiments of the present disclosure;

[0036] Figures 12 to 15 These are schematic cross-sectional views illustrating methods for forming dual contact holes according to one or more embodiments of the present disclosure.

[0037] Figure 16 This is a schematic cross-sectional view illustrating a dual contact hole according to one or more embodiments of the present disclosure;

[0038] Figure 17 This is a perspective view illustrating an electronic device according to one or more embodiments of the present disclosure;

[0039] Figure 18 This is an exploded perspective view illustrating an electronic device according to one or more embodiments of the present disclosure;

[0040] Figure 19 This is a perspective view schematically illustrating an electronic device according to one or more embodiments of the present disclosure; and

[0041] Figure 20 This is an exploded view schematically illustrating an electronic device according to one or more embodiments of the present disclosure. Detailed Implementation

[0042] Reference will now be made in more detail to one or more embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout this disclosure, and for the sake of brevity, their repeated descriptions are omitted. In this respect, the presented embodiments may take different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, embodiments of this disclosure are described in more detail only with reference to the accompanying drawings to explain aspects of this disclosure. As used herein, the terms “and / or” or “or” can include any and all combinations of one or more of the associated listed items. Throughout this disclosure, expressions such as “at least one of…”, “one of…”, and “selected from…” modify the entire list of elements when following it, and not individual elements in the list. For example, “at least one of a, b, and c”, “at least one selected from a, b, and c”, “at least one selected from a to c”, etc., can indicate only a, only b, only c, both a and b (e.g., simultaneously), both a and c (e.g., simultaneously), both b and c (e.g., simultaneously), all of a, b, and c, or variations thereof.

[0043] Because this disclosure allows for one or more suitable variations and numerous embodiments, certain embodiments will be illustrated in the accompanying drawings and described in the detailed description. The effects and features of this disclosure, as well as methods for implementing them, will be elucidated with reference to one or more embodiments described herein in more detail with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments and may be embodied in one or more suitable forms.

[0044] In the following description, exemplary embodiments will be described in more detail with reference to the accompanying drawings, wherein the same or corresponding elements are represented by the same reference numerals / characters throughout the disclosure, and for the sake of brevity, their repeated description may be omitted.

[0045] Although the terms “first,” “second,” etc., may be used to describe one or more suitable elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, the first element described may also be referred to as the second element or the third element without departing from the spirit and scope of this disclosure.

[0046] As used herein, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] It will be understood that the terms “comprising” and / or “including” and / or “having” are intended to indicate the presence of a feature or element described in this disclosure and are not intended to exclude the possibility that one or more other features or elements may be present or added. Additionally, the terms “comprising,” “including,” “having,” or other similar terms include or support the terms “consisting of” and “substantially consisting of” that indicate the presence of stated features, integers, steps, operations, elements, and / or components and the absence or substantial absence of other features, integers, steps, operations, elements, components, and / or combinations thereof. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0048] It will be further understood that if a layer, area, or component is referred to as being "on" another layer, area, or component (e.g., when a layer, area, or component is referred to as being "on" another layer, area, or component), then it may be directly on that other layer, area, or component, or it may be indirectly on that other layer, area, or component with one or more intervening layers, areas, or components in between. In contrast, if an element is referred to as being "directly on" another element (e.g., when an element is referred to as being "directly on" another element), then there is no intervening element in between.

[0049] Furthermore, for ease of explanation, the dimensions of the components in the accompanying drawings may be exaggerated or reduced. For example, because the dimensions and thicknesses of the components in the drawings may be illustrated for ease of explanation, the embodiments of this disclosure are not limited thereto.

[0050] If an embodiment can be implemented differently (e.g., when an embodiment can be implemented differently), the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0051] It will be understood that if a layer, area, or component is referred to as "connected" to another layer, area, or component (e.g., when a layer, area, or component is referred to as "connected" to another layer, area, or component), then that layer, area, or component may be directly connected to the other layer, area, or component, or may be indirectly connected to the other layer, area, or component using one or more intervening layers, areas, or components therein. For example, if a layer, area, or component is referred to as "electrically connected" (e.g., when a layer, area, or component is referred to as "electrically connected"), then those layers, areas, or components may be directly electrically connected, or may be indirectly electrically connected using one or more intervening layers, areas, or components therein.

[0052] Figure 1 This is a schematic plan view illustrating a display panel according to one or more embodiments of the present disclosure.

[0053] refer to Figure 1 The display panel 10 may include a display area DA and a peripheral area PA outside (e.g., around) the display area DA. The display area DA is a portion (e.g., an area) for displaying an image, and multiple pixels PX may be arranged within the display area DA. The display area DA may have any of one or more suitable shapes, such as a circular shape, an elliptical shape, a polygonal shape, or a shape of a particular design. The multiple pixels PX are implemented by one or more suitable display elements (such as organic light-emitting elements, inorganic light-emitting elements, or quantum dot light-emitting elements), and the display elements may be driven by being connected to pixel circuitry.

[0054] The peripheral region PA of the display panel 10 can be arranged outside (e.g., around) the display region DA. The driver integrated circuit (IC) for providing electrical signals to be applied to the display region DA can be arranged in the peripheral region PA, and one or more suitable wirings for transmitting electrical signals generated in the driver IC can be located in the peripheral region PA.

[0055] Figure 2A and Figure 2B Each is an equivalent circuit diagram illustrating the pixel circuitry of a display panel according to one or more embodiments of the present disclosure.

[0056] refer to Figure 2A The pixel circuit PC can be electrically connected to the light-emitting element LED and can include a driving transistor T1, a switching transistor T2, and a storage capacitor Cst. The pixel circuit PC can be electrically connected to signal lines and voltage lines. The signal lines can include gate lines such as scan lines SL and data lines DL, and the voltage lines can include driving voltage lines PL.

[0057] The driving transistor T1 controls the driving current flowing through the light-emitting element LED. The driving transistor T1 can be connected to the driving voltage line PL and the storage capacitor (first capacitor) Cst. The driving transistor T1 can control the driving current flowing from the driving voltage line PL through the light-emitting element LED in response to the value of the voltage stored in the first capacitor Cst.

[0058] Switching transistor T2 can be electrically connected to scan line SL and data line DL. Scan line SL can provide scan signal Sn to the gate electrode of switching transistor T2. Switching transistor T2 can be used to transmit data signal Dm input from data line DL to driving transistor T1 according to scan signal Sn input from scan line SL.

[0059] The storage capacitor Cst can be electrically connected to the driving transistor T1 and the driving voltage line PL, and can store the voltage corresponding to the difference between the voltage received from the switching transistor T2 and the driving voltage ELVDD supplied by the driving voltage line PL.

[0060] An LED (Light Emitting Device) can be used to emit light with a certain brightness due to a driving current. The first electrode of the LED can be electrically connected to the driving transistor T1, and the second electrode of the LED can be electrically connected to the common voltage line supplying the common power supply voltage ELVSS.

[0061] Despite Figure 2A The pixel circuit PC includes two thin-film transistors and a storage capacitor, but in one or more embodiments, the pixel circuit PC may include three or more thin-film transistors.

[0062] refer to Figure 2B In one or more embodiments, the pixel circuit PC may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first capacitor Cst, and a second capacitor Cpr. The pixel circuit PC may be electrically connected to signal lines and voltage lines.

[0063] The signal lines may include the scan line SL for transmitting the scan signal Sn, the compensation control line GL for transmitting the compensation control signal Gc, and the data line DL for transmitting the data signal Dm.

[0064] The voltage lines may include a drive voltage line PL and an initialization voltage line VL. The drive voltage line PL can be used to transmit the drive voltage ELVDD to the drive transistor T1, and the initialization voltage line VL can be used to transmit the initialization voltage Vint to the first capacitor Cst.

[0065] The driving gate electrode G1 of the driving transistor T1 can be connected to the first electrode C1 of the first capacitor Cst, the source electrode S1 of the driving transistor T1 can be connected to the driving voltage line PL, and the driving drain electrode D1 of the driving transistor T1 can be electrically connected to the pixel electrode of the light-emitting element LED. The driving transistor T1 receives the data signal Dm and, according to the switching operation of the switching transistor T2, drives the driving current I... OLED Supply to light-emitting elements (LEDs).

[0066] The switching gate electrode G2 of switching transistor T2 is connected to the scan line SL, the switching source electrode S2 of switching transistor T2 is connected to the data line DL via the second capacitor Cpr, and the switching drain electrode D2 of switching transistor T2 is connected to the driving gate electrode G1 of driving transistor T1. Switching transistor T2 can be turned on according to the scan signal Sn received through the scan line SL, and can perform a switching operation to transmit the data signal Dm transmitted through the data line DL to driving transistor T1.

[0067] The compensation gate electrode G3 of the compensation transistor T3 is connected to the compensation control line GL, the compensation source electrode S3 of the compensation transistor T3 is connected to the pixel electrode of the light-emitting element LED, and the compensation drain electrode D3 of the compensation transistor T3 is connected to the data line DL via the second capacitor Cpr. The compensation transistor T3 is turned on by the compensation control signal Gc applied to the compensation gate electrode G3.

[0068] The first capacitor Cst can be connected between the driving gate electrode G1 of the driving transistor T1 and the initialization voltage line VL that supplies the initialization voltage Vint, and can be used as a storage capacitor. In this respect, the first electrode C1 of the first capacitor Cst can be connected to the driving gate electrode G1 of the driving transistor T1, and the second electrode C2 of the first capacitor Cst can be connected to the initialization voltage line VL.

[0069] The second capacitor Cpr can be connected between the switching source electrode S2 of the switching transistor T2 and the data line DL supplying the data signal Dm, and can be used as a programming capacitor. In this respect, the third electrode C3 of the second capacitor Cpr can be connected to the data line DL, and the fourth electrode C4 of the second capacitor Cpr can be connected to the switching source electrode S2 of the switching transistor T2.

[0070] Due to the operation of switching transistor T2, the data signal Dm applied to the second capacitor Cpr is applied to the first capacitor Cst to determine the driving gate voltage applied to the driving gate electrode G1 of driving transistor T1, and driving transistor T1 is turned on by the driving gate voltage. Accordingly, the light-emitting element LED can receive a driving current I from driving transistor T1. OLED It emits light. The other electrode of the light-emitting element LED can be electrically connected to the common voltage line that supplies the common power supply voltage ELVSS.

[0071] exist Figure 2B In this configuration, the source electrodes S1, S2, and S3, and the drain electrodes D1, D2, and D3 can be interchanged depending on the type (variety) of the transistor. Furthermore, although in Figure 2B In this embodiment, the driving transistor T1, the switching transistor T2, and the compensation transistor T3 are all NMOS transistors, but the embodiments of this disclosure are not limited thereto. For example, the driving transistor T1, the switching transistor T2, and the compensation transistor T3 may all be PMOS transistors. In one or more embodiments, one or more suitable modifications may be made. For example, some of the driving transistor T1, the switching transistor T2, and the compensation transistor T3 may be NMOS transistors, and the rest may be PMOS transistors.

[0072] Despite Figure 2B One or more embodiments of the present disclosure exemplify three thin-film transistors and two capacitors, but the embodiments of the present disclosure are not limited thereto, and the number of thin-film transistors and the number of capacitors may be varied in one or more suitable ways.

[0073] Figure 3 This is a schematic cross-sectional view illustrating a display panel according to one or more embodiments of the present disclosure. Figure 4 This is a schematic view illustrating a dual contact hole of a display panel according to one or more embodiments of the present disclosure.

[0074] refer to Figure 3 In one or more embodiments, the display panel 10 may include a pixel circuit PC disposed on a substrate 110 and an organic light-emitting diode (OLED) connected to the pixel circuit PC as a light-emitting element. The pixel circuit PC according to one or more embodiments may include a first thin-film transistor (TFT1), a second thin-film transistor (TFT2), a first capacitor Cst, a second capacitor Cpr, and at least one dual contact hole DCNT.

[0075] The first thin-film transistor TFT1 is a driving transistor and may include a first semiconductor layer A1 and a first gate electrode G1. The second thin-film transistor TFT2 is a compensation transistor and may include a second semiconductor layer A2 and a second gate electrode G2. The first capacitor Cst may include a first electrode C1 and a second electrode C2. The second capacitor Cpr may include a third electrode C3, a fourth-first electrode C4-1, and a fourth-second electrode C4-2.

[0076] The substrate 110 may comprise glass, metal, or polymer resin. In one or more embodiments, the substrate 110 may comprise a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. In one or more embodiments, the substrate 110 may have a multilayer structure comprising two layers each comprising one or more of the above polymer resins, and an inorganic layer disposed between the two layers.

[0077] The buffer layer 101 may be disposed on the substrate 110. The buffer layer 101 may be an inorganic insulating layer containing inorganic insulating materials (such as silicon nitride and / or silicon oxide), and may have a single-layer structure or a multi-layer structure containing the above materials.

[0078] The first semiconductor layer A1 and the second semiconductor layer A2 can be disposed on the buffer layer 101. Each of the first semiconductor layer A1 and the second semiconductor layer A2 can be independently formed of a silicon semiconductor material or an oxide semiconductor material. Each of the first semiconductor layer A1 and the second semiconductor layer A2 can include a channel region and a source region and a drain region disposed on both sides (e.g., opposite sides) of the channel region. The source region and the drain region can be regions doped with impurities, and the impurities can include N-type (type) impurities or P-type (type) impurities. The source region and the drain region can correspond to the source electrode and the drain electrode, respectively. Although the first semiconductor layer A1 and the second semiconductor layer A2 are spaced apart and / or separated from each other in the figures (e.g., spaced apart or separated), in one or more embodiments, the first semiconductor layer A1 and the second semiconductor layer A2 can be integrally connected to each other.

[0079] A gate insulating film 111 may be provided on the buffer layer 101 to cover the first semiconductor layer A1 and the second semiconductor layer A2. The gate insulating film 111 may comprise materials such as silicon oxide (SiO2) or silicon nitride (SiN). x Inorganic insulating materials of silicon oxynitride (SiON) and / or silicon oxynitride (SiON), and may have a single-layer structure or a multi-layer structure containing one or more of the above materials.

[0080] The first gate electrode G1 and the second gate electrode G2 can be disposed on the gate insulating film 111. The first gate electrode G1 and the second gate electrode G2 can overlap with the channel region of the first semiconductor layer A1 and the channel region of the second semiconductor layer A2, respectively. Each of the first gate electrode G1 and the second gate electrode G2 can contain molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and can have a single-layer structure or a multi-layer structure.

[0081] The first gate electrode G1 can be used as the first thin-film transistor T1 (see...). Figure 2A and Figure 2B The gate electrode of the capacitor, and can also be used as the first capacitor Cst (see [reference]). Figure 2A and Figure 2B The first electrode C1. For example, the first gate electrode G1 and the first electrode C1 can be integrally formed with each other. As the first gate electrode G1 and the first electrode C1 are integrally formed with each other, the first gate electrode G1 and the first capacitor Cst overlap each other, thereby enabling high integration.

[0082] The first interlayer insulating film 113 can be disposed on the gate insulating film 111 to cover the first gate electrode G1 and the second gate electrode G2. The first interlayer insulating film 113 may contain materials such as silicon oxide (SiO2) and silicon nitride (SiN). x Inorganic insulating materials of silicon oxynitride (SiON) and / or silicon oxynitride (SiON), and may have a single-layer structure or a multi-layer structure containing one or more of the above materials.

[0083] The second electrode C2 of the first capacitor Cst can be disposed on the first interlayer insulating film 113 to overlap with the first gate electrode G1. As described above, the first gate electrode G1 can be the first electrode C1 of the first capacitor Cst.

[0084] The second interlayer insulating film 115 can be disposed on the first interlayer insulating film 113 to cover the second electrode C2 of the first capacitor Cst. The second interlayer insulating film 115 may contain materials such as silicon oxide (SiO2) and silicon nitride (SiN). x The insulating material is an inorganic insulating material of silicon oxynitride (SiON) and / or may have a single-layer structure or a multilayer structure containing one or more of the above materials. The gate insulating film 111, the first interlayer insulating film 113 and the second interlayer insulating film 115 may constitute the first insulating layer IL1.

[0085] The fourth electrode C4-1 of the second capacitor Cpr can be disposed on the second interlayer insulating film 115. The fourth electrode C4-1 can have a multilayer structure. The fourth electrode C4-1 can be electrically connected to the second semiconductor layer A2 of the second thin-film transistor TFT2.

[0086] The third interlayer insulating film 117 can be disposed on the second interlayer insulating film 115 to cover the fourth-1 electrode C4-1. The third interlayer insulating film 117 can contain materials such as silicon oxide (SiO2) and silicon nitride (SiN). x Inorganic insulating materials of silicon oxynitride (SiON) and / or silicon oxynitride (SiON), and may have a single-layer structure or a multi-layer structure containing one or more of the above materials.

[0087] The third electrode C3 of the second capacitor Cpr and the data line DL can be arranged on the third interlayer insulating film 117. The third electrode C3 can be provided as part of the data line DL. The third electrode C3 can overlap with the fourth electrode C4-1.

[0088] The fourth interlayer insulating film 119 can be disposed on the third interlayer insulating film 117 to cover the third electrode C3. The fourth interlayer insulating film 119 can contain materials such as silicon oxide (SiO2) and silicon nitride (SiN). x The insulating material is an inorganic insulating material of silicon oxynitride (SiON) and / or may have a single-layer structure or a multi-layer structure containing one or more of the above materials. The third interlayer insulating film 117 and the fourth interlayer insulating film 119 may constitute the second insulating layer IL2.

[0089] The 4-2 electrode C4-2 of the second capacitor Cpr can be disposed on the fourth interlayer insulating film 119. The 4-2 electrode C4-2 can be electrically connected to the 4-1 electrode C4-1 and the second semiconductor layer A2 of the second thin-film transistor TFT2. The 4-2 electrode C4-2 can overlap with the third electrode C3 and the 4-1 electrode C4-1.

[0090] Because the second capacitor Cpr has a dual structure with the third electrode C3, the fourth electrode C4-1 and the fourth electrode C4-2 arranged on different layers overlapping each other, high integration can be achieved.

[0091] Each of the third electrode C3, the fourth electrode C4-1, and the fourth electrode C4-2 of the second capacitor Cpr may contain a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure containing one or more of the above materials.

[0092] The via layer 121 can be disposed on the fourth interlayer insulating film 119 to cover the fourth-2 electrode C4-2 of the second capacitor Cpr. The via layer 121 can be formed of an organic insulating material such as acrylic acid, benzocyclobutene (BCB) resin, polyimide and / or hexamethyldisiloxane (HMDSO).

[0093] An organic light-emitting diode (OLED) can be disposed on the via layer 121. The OLED may include a pixel electrode 310, an intermediate layer 320 including an organic emitting layer, and a counter electrode 330. Either the pixel electrode 310 or the counter electrode 330 of the OLED can be used as an anode electrode, and the other can be used as a cathode electrode.

[0094] Pixel electrode 310 may be disposed on via layer 121. Pixel electrode 310 may comprise indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, and / or In2O3 having a high work function. If the display device (e.g., display apparatus) is a top-emitting (or similar) display device (e.g., when the display device is a top-emitting (or similar) display device), pixel electrode 310 may further comprise a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), ytterbium (Yb), or calcium (Ca), which may be used individually or in combination with each other. Furthermore, pixel electrode 310 may have a single-layer or multi-layer structure comprising one or more of the above metals and / or alloys thereof. In one or more embodiments, pixel electrode 310 is a reflective electrode and may have an ITO / Ag / ITO structure.

[0095] A pixel defining film 123 may be provided on the via layer 121 to cover the edge of the pixel electrode 310. The pixel defining film 123 may include an opening 123OP through which the central portion of the pixel electrode 310 is exposed.

[0096] Because the intermediate layer 320, including the organic emitting layer, is arranged in the opening 123OP of the pixel defining film 123, the emitting region of the organic light-emitting diode (OLED) can be defined by the opening 123OP of the pixel defining film 123. Furthermore, the pixel defining film 123 can increase the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310 to prevent or reduce the generation of electric arcs at the edge of the pixel electrode 310. The pixel defining film 123 can be formed using spin coating or the like from at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, BCB-type resin, and phenolic resin.

[0097] At least a portion of the intermediate layer 320 of the organic light-emitting diode (OLED) may be located in the opening 123OP of the pixel defining film 123. The intermediate layer 320 may contain organic materials, including fluorescent or phosphorescent materials that emit red, green, blue, or white light. The intermediate layer 320 may include an organic emission layer formed of low-molecular-weight or high-molecular-weight organic materials, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be selectively arranged below and / or above the organic emission layer.

[0098] The counter electrode 330 can be a transparent electrode or a reflective electrode. For example, in one or more embodiments, the counter electrode 330 can be a transparent or translucent electrode and can include a metal thin film comprising Li, Ca, LiF, Al, Ag, Mg, or compounds thereof having a low work function. Furthermore, the counter electrode 330 can further include a transparent conductive oxide (TCO) film comprising, for example, ITO, IZO, ZnO, or In2O3, located on the metal thin film. The counter electrode 330 can be integrally formed throughout the entire display area and can be disposed on the intermediate layer 320 and the pixel defining film 123.

[0099] In one or more embodiments, a dual contact hole DCNT may be disposed between the substrate 110 of the display panel 10 and the organic light-emitting diode (OLED). A dual contact hole DCNT may refer to a lower contact hole CNTb and an upper contact hole CNTu that overlap each other and are connected by an intermediate conductive layer MCL (see [link to documentation]). Figure 4 The DCNT dual contact hole connects the light-emitting element to a component of the pixel circuit PC, or connects the wiring to a component of the pixel circuit PC or some components of the pixel circuit PC.

[0100] refer to Figure 4 The dual contact hole DCNT may include a lower contact hole CNTb, a lower conductive layer BCL, an inorganic material FM, an intermediate conductive layer MCL, an upper contact hole CNTu, and an upper conductive layer UCL.

[0101] The lower contact hole CNTb can be defined within the first insulating layer IL1 to expose a portion of the conductive layer CL disposed on the substrate 110. The lower contact hole CNTb can be a hole passing through the first insulating layer IL1.

[0102] The lower conductive layer BCL can be disposed inside the lower contact hole CNTb to electrically connect to the conductive layer CL disposed in the lower portion of the first insulating layer IL1. The lower conductive layer BCL can be disposed from the top surface of the first insulating layer IL1 onto the inner surface of the lower contact hole CNTb. In other words, the lower conductive layer BCL can be disposed both on the top surface of the first insulating layer IL1 and inside the lower contact hole CNTb.

[0103] The recess RS recessed toward the substrate 110 can provide a region in which the lower conductive layer BCL is disposed inside the lower contact hole CNTb, and the inorganic material FM can fill the recess RS.

[0104] The inorganic material FM filling the recess RS can be formed by the aggregation of nanoparticles. The inorganic material FM can be an inorganic insulating material or a metallic material. In one embodiment, the inorganic material FM can include aggregated nanoparticles of metal oxides and / or metals. The inorganic material FM can be formed by aggregating nanoparticles such as BaTiO3, BaSO3, BaSO4, Ba(NO3)2, TiO2, SiO2 and / or ZnO, which are metal oxides, or it can be formed from metallic nanoparticles such as Ag nanoparticles, Au nanoparticles, Pt nanoparticles and / or Pd nanoparticles.

[0105] If the thickness of the first insulating layer IL1 increases (e.g., when the thickness of the first insulating layer IL1 increases), then in the process, not only the depth of the lower contact hole CNTb but also the width of the lower contact hole CNTb may need to be large. In this case, the lower conductive layer BCL may not completely fill the lower contact hole CNTb, and a recess RS may be formed. That is, the recess RS may be provided in the lower conductive layer BCL due to the lower contact hole CNTb. If the recess RS is not filled or is filled with an organic material (e.g., when the recess RS is not filled or is filled with an organic material), robustness may not be guaranteed, or gas release may occur in subsequent processes. In this embodiment, because the recess RS provided in the lower contact hole CNTb is filled with inorganic nanoparticles, a display panel with robustness and high reliability can be formed.

[0106] The intermediate conductive layer MCL can be disposed on the lower conductive layer BCL to correspond to the lower contact hole CNTb. The intermediate conductive layer MCL can be provided on the lower conductive layer BCL to cover the inorganic material FM. The lower conductive layer BCL and the intermediate conductive layer MCL can be covered by a second insulating layer IL2.

[0107] The upper contact hole CNTu can be confined within the second insulating layer IL2 to expose a portion of the intermediate conductive layer MCL. The upper contact hole CNTu can be a hole that passes through the second insulating layer IL2.

[0108] The upper conductive layer UCL can be disposed inside the upper contact hole CNTu to be electrically connected to the intermediate conductive layer MCL disposed in the lower portion of the second insulating layer IL2. The upper conductive layer UCL can be electrically connected to the lower conductive layer BCL through the intermediate conductive layer MCL. In one embodiment, the upper conductive layer UCL can be located on the top surface of the second insulating layer IL2 and inside the upper contact hole CNTu.

[0109] Because the intermediate conductive layer MCL is positioned between the upper contact hole CNTu and the lower contact hole CNTb, the upper contact hole CNTu can overlap with the lower contact hole CNTb. This structure reduces the area occupied by the dual contact holes DCNT, thereby enabling high integration.

[0110] Each of the lower conductive layer (BCL), the intermediate conductive layer (MCL), and the upper conductive layer (UCL) may contain a conductive material, such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and / or a conductive oxide, and may have a single-layer or multi-layer structure. The lower conductive layer (BCL), the intermediate conductive layer (MCL), and the upper conductive layer (UCL) may be formed of the same material, or at least one of the lower conductive layer (BCL), the intermediate conductive layer (MCL), and the upper conductive layer (UCL) may be formed of different materials.

[0111] Each of the first insulating layer IL1 and the second insulating layer IL2 may contain materials such as silicon oxide (SiO2) and silicon nitride (SiN). x Inorganic insulating materials of silicon oxynitride (SiON) and / or silicon oxynitride (SiON), and may have a single-layer structure or a multi-layer structure containing one or more of the above materials.

[0112] To achieve high integration in the display panel, many layers may be introduced, and the combined thickness of the first insulating layer IL1 and the second insulating layer IL2 may exceed 2 µm. In this case, there are process limitations in forming contact holes for directly connecting components disposed on the second insulating layer IL2 to components disposed in the lower portion of the first insulating layer IL1. In the display panel according to embodiments of the present disclosure, by introducing dual contact holes (DCNT), the process can be simplified and space can be ensured.

[0113] Return to reference Figure 3 The display panel 10 may include a first dual contact hole DCNT1 and a second dual contact hole DCNT2.

[0114] The first insulating layer IL1 can be provided by stacking a gate insulating film 111, a first interlayer insulating film 113 and a second interlayer insulating film 115, and the second insulating layer IL2 can be provided by stacking a third interlayer insulating film 117 and a fourth interlayer insulating film 119.

[0115] The lower contact hole of each of the first dual contact holes DCNT1 and the second dual contact holes DCNT2 can pass through the gate insulating film 111, the first interlayer insulating film 113 and the second interlayer insulating film 115 of the first insulating layer IL1, and the upper contact hole of each of the first dual contact holes DCNT1 and the second dual contact holes DCNT2 can pass through the third interlayer insulating film 117 and the fourth interlayer insulating film 119 of the second insulating layer IL2.

[0116] The first dual contact hole DCNT1 electrically connects the first semiconductor layer A1 of the first thin-film transistor TFT1 to the pixel electrode 310. The lower conductive layer of the first dual contact hole DCNT1 is disposed on the second interlayer insulating film 115 and connected to the first semiconductor layer A1 through the lower contact hole. The upper conductive layer of the first dual contact hole DCNT1 can be disposed on the fourth interlayer insulating film 119 and can be connected to the intermediate conductive layer disposed on the lower conductive layer. The pixel electrode can be connected to the upper conductive layer of the first dual contact hole DCNT1 through a via VH passing through the via layer 121.

[0117] The second dual contact hole DCNT2 can electrically connect the second semiconductor layer A2 of the second thin film transistor TFT2 to the second capacitor Cpr.

[0118] The lower conductive layer of the second dual contact hole DCNT2 is disposed on the second interlayer insulating film 115 and is connected to the second semiconductor layer A2 through the lower contact hole. The lower conductive layer of the second dual contact hole DCNT2 can be connected to the 4-1 electrode C4-1 of the second capacitor Cpr. For example, the lower conductive layer of the second dual contact hole DCNT2 can form part of the 4-1 electrode C4-1. The 4-1 electrode C4-1 can be provided by stacking the lower conductive layer and the intermediate conductive layer.

[0119] The upper conductive layer of the second dual contact hole DCNT2 can be disposed on the fourth interlayer insulating film 119, and can be connected to the intermediate conductive layer disposed on the lower conductive layer through the upper contact hole. The upper conductive layer of the second dual contact hole DCNT2 can be connected to the 4-2 electrode C4-2. For example, the upper conductive layer of the second dual contact hole DCNT2 can be provided integrally with the 4-2 second electrode C4-2.

[0120] Figures 5 to 10 This is a cross-sectional view illustrating a method for forming a dual contact hole according to one or more embodiments of the present disclosure.

[0121] refer to Figure 5 A conductive layer CL is formed on the substrate 110. The conductive layer CL can be a metal layer or a semiconductor layer. The conductive layer CL can be formed by depositing a conductive material on the entire surface of the substrate 110 and performing patterning by photolithography.

[0122] Next, a first insulating layer IL1 is formed on the substrate 110 to cover the conductive layer CL. The first insulating layer IL1 can be made of materials such as silicon oxide (SiO2) or silicon nitride (SiN). x Inorganic insulating materials such as silicon oxynitride (SiON) and / or silicon oxynitride (SiON) can be formed, and can be formed by deposition methods such as chemical vapor deposition or atomic layer deposition (ALD).

[0123] Next, a lower contact hole CNTb is formed through the first insulating layer IL1. The lower contact hole CNTb can be formed to expose at least a portion of the conductive layer CL. The lower contact hole CNTb can be patterned by a photolithography process.

[0124] Next, a lower conductive layer BCL is formed on the first insulating layer IL1. To form the lower conductive layer BCL, a conductive material can be deposited on the top surface of the first insulating layer IL1 using one or more suitable deposition methods (such as chemical vapor deposition or sputtering), and can be patterned by a photolithography process. The lower conductive layer BCL can be formed to fill the inner surface of the lower contact hole CNTb and can be connected to the conductive layer CL. The lower conductive layer BCL can be deposited on the inner surface of the lower contact hole CNTb, and a recess RS recessed towards the substrate 110 can be formed in the lower contact hole CNTb.

[0125] refer to Figure 6 A coating process is performed such that a dispersion solution DS containing inorganic nanoparticles NP is filled inside the recess RS formed within the lower contact hole CNTb. The coating process can be performed using any of one or more suitable methods, such as spin coating, spray coating, and / or dip coating.

[0126] Inorganic nanoparticles (NPs) can be formed from metal oxides such as BaTiO3, BaSO3, BaSO4, Ba(NO3)2, TiO2, SiO2, and / or ZnO, or from metallic nanoparticles such as Ag nanoparticles, Au nanoparticles, Pt nanoparticles, and / or Pd nanoparticles. The diameter of the inorganic nanoparticles (NPs) can be from about 10 nanometers (nm) to about 1000 nm. The dispersion solution (DS) can contain a high molecular weight organic material, a low molecular weight organic material, or an inorganic material as a dispersant for dispersing the inorganic nanoparticles (NPs) in a solvent such as water.

[0127] refer to Figure 7After coating the dispersion solution, an annealing process is performed. The annealing process can be a process of applying heat for a certain period of time and then cooling for a certain period of time. If heat is applied using the annealing process (e.g., when heat is applied using the annealing process), the solvent in the dispersion solution evaporates, and the inorganic nanoparticles NP in the dispersion solution agglomerate together. Accordingly, the inorganic material FM formed by the agglomeration of the inorganic nanoparticles fills the recessed RS.

[0128] Inorganic nanoparticles NP arranged in portions other than the interior of the recess RS may be dispersed without agglomeration due to their small number. For example, unagglomerated inorganic nanoparticles NP may be present on the underlying conductive layer BCL.

[0129] refer to Figure 8 Inorganic nanoparticles NP disposed in portions other than the interior of the recess RS can be removed using wet and / or dry cleaning processes. Because excess (e.g., redundant) inorganic nanoparticles can be removed using common wet and / or dry cleaning processes, time and cost savings can be achieved.

[0130] Next, refer to Figure 9 An intermediate conductive layer MCL is formed on the lower conductive layer BCL to cover the inorganic material FM. To form the intermediate conductive layer MCL, the conductive material can be deposited on the first insulating layer IL1 to cover the lower conductive layer BCL using one or more suitable deposition methods, and can be patterned by a photolithography process. In this case, the intermediate conductive layer MCL can be formed using the same mask used to form the lower conductive layer BCL.

[0131] Next, refer to Figure 10 A second insulating layer IL2 is formed on the first insulating layer IL1 to cover the intermediate conductive layer MCL. The second insulating layer IL2 can be made of materials such as silicon oxide (SiO2) or silicon nitride (SiN). x Inorganic insulating materials such as silicon oxynitride (SiON) and / or silicon oxynitride (SiON) can be formed, and can be formed by using deposition methods such as chemical vapor deposition or ALD.

[0132] Next, an upper contact hole CNTu is formed through the second insulating layer IL2. The upper contact hole CNTu can be formed to expose at least a portion of the intermediate conductive layer MCL. The upper contact hole CNTu can be patterned by a photolithography process. The upper contact hole CNTu can be formed to overlap with the lower contact hole CNTb.

[0133] Next, an upper conductive layer UCL is formed on the second insulating layer IL2. To form the upper conductive layer UCL, a conductive material can be deposited on the second insulating layer IL2 using one or more suitable deposition methods (such as chemical vapor deposition or sputtering), and can be patterned by a photolithography process. The upper conductive layer UCL can be formed to fill the inner surface of the upper contact hole CNTu and can be connected to the intermediate conductive layer MCL. In one embodiment, the upper conductive layer UCL can be formed from the top surface of the second insulating layer IL2 along the inner surface of the upper contact hole CNTu.

[0134] Figure 11 This is a schematic cross-sectional view illustrating a dual contact hole DCNT' according to one or more embodiments of the present disclosure. Figure 11 In, with Figure 4 The same components are represented by the same reference numerals / characters, and therefore no duplicate descriptions will be provided.

[0135] refer to Figure 11 The dual contact hole DCNT' includes: a lower contact hole CNTb, connected to the conductive layer CL and defined in the first insulating layer IL1; a lower conductive layer BCL, disposed inside the lower contact hole CNTb; an upper contact hole CNTu, defined in the second insulating layer IL2; and an upper conductive layer UCL, disposed inside the upper contact hole CNTu.

[0136] In this embodiment, the dual contact hole DCNT' further includes a protective film PVX and a buffer film BF, each located within the lower contact hole CNTb, and the buffer film BF contains an inorganic material FM formed by the aggregation of nanoparticles in the recess RS recessed toward the substrate 110. In one embodiment, the protective film PVX may be arranged inside the recess RS along the shape of the lower conductive layer BCL.

[0137] The protective film PVX, used to prevent or reduce damage to the underlying conductive layer BCL during the process of forming the buffer film BF, can be formed from a material having an etch rate different from that of the buffer film BF and the underlying conductive layer BCL. For example, the protective film PVX can be formed as a thin film of an oxide semiconductor material (such as indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO)) or a transparent conductive oxide. The thickness of the protective film PVX can be less than the thickness of the buffer film BF. The thickness of the protective film PVX can be from about 100 Å to about 1000 Å. The protective film PVX can be formed using a deposition method such as sputtering.

[0138] A buffer film BF can be disposed inside the lower contact hole CNTb to cover the protective film PVX and can fill a portion of the lower contact hole CNTb. The buffer film BF can comprise a material different from the inorganic material FM (or inorganic nanoparticles), or can be formed from a material different from the inorganic material FM (or inorganic nanoparticles). In one embodiment, the buffer film BF can be made of materials such as silicon oxide (SiO2) or silicon nitride (SiN). x The buffer film (BF) is formed from inorganic insulating materials such as silicon oxynitride (SiON) and can be formed using deposition methods such as chemical vapor deposition or aluminosilicate glass (ALD). The buffer film (BF) can be thicker than the protective film (PVX). The thickness of the buffer film (BF) can be determined by taking into account the lower step portion and can be from about 1000 Å to about 10000 Å.

[0139] If the thickness of the first insulating layer IL1 is greater than a certain thickness (e.g., when the thickness of the first insulating layer IL1 is greater than a certain thickness), the recess formed in the lower contact hole CNTb may not be completely filled by inorganic material FM formed of nanoparticles alone. In this embodiment, because the buffer film BF partially fills the interior of the lower contact hole CNTb, the recess RS formed in the lower contact hole CNTb can be completely filled even if it is difficult to fill with inorganic material FM alone (e.g., when it is difficult to fill with inorganic material FM alone).

[0140] Figures 12 to 15 This sequentially illustrates the formation according to one or more embodiments of the present disclosure. Figure 11 A schematic cross-sectional view of the double contact hole method.

[0141] refer to Figure 12 After forming a conductive layer CL and a first insulating layer IL1 on the substrate 110, a lower contact hole CNTb is formed in the first insulating layer IL1, and a lower conductive layer BCL is formed on the inner wall (e.g., inner surface) of the lower contact hole CNTb.

[0142] Next, a protective film PVX is formed to cover the underlying conductive layer BCL, and a buffer film BF is formed on the protective film PVX. The protective film PVX, used to prevent or reduce damage to the underlying conductive layer BCL in subsequent processes, is formed to be thinner than the buffer film BF. The protective film PVX can be formed from an oxide semiconductor material (such as indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO)) or a transparent conductive oxide.

[0143] A buffer film (BF) is a component used to fill a portion of the lower contact hole (CNTb) and can be formed using chemical vapor deposition. The buffer film (BF) can be made of materials such as silicon oxide (SiO2) or silicon nitride (SiN). xIt is formed of an inorganic insulating material, such as silicon oxynitride (SiON). The buffer film BF can be disposed inside the lower contact hole CNTb to directly contact the top surface of the lower conductive layer BCL.

[0144] refer to Figure 13 The buffer film BF disposed on the first insulating layer IL1 can be removed by a chemical mechanical polishing (CMP) process. Correspondingly, the buffer film BF disposed inside the lower contact hole CNTb can remain unremoved, and only the buffer film BF disposed on the first insulating layer IL1 can be removed. In this respect, the protective film PVX can prevent or reduce damage to the lower conductive layer BCL by the reagents / chemicals used in the CMP process.

[0145] refer to Figure 14 The protective film PVX disposed on the first insulating layer IL1 is removed by wet etching. Then, as per reference... Figures 6 to 10 Described, Figure 15 The dual-contact hole DCNT' can be achieved by filling the recess with inorganic material FM using a dispersion solution containing inorganic or metal nanoparticles, forming an intermediate conductive layer MCL, a second insulating layer IL2, an upper contact hole CNTu, and an upper conductive layer UCL. For example, as referenced... Figures 6 to 10 Described, Figure 15 The dual contact hole DCNT' can be achieved by filling the recess with an inorganic material FM using a dispersion solution containing inorganic or metallic nanoparticles. The process also involves forming an intermediate conductive layer MCL, a second insulating layer IL2, an upper contact hole CNTu, and an upper conductive layer UCL.

[0146] Figure 16 It is an illustrative example. Figure 15 The cross-sectional view of the display panel in which the dual contact holes are applied. Figure 16 In, with Figure 3 Components that are identical in the figure are represented by the same reference numerals / characters.

[0147] refer to Figure 16 The display panel 10' includes: a pixel circuit PC disposed on a substrate 110; and an organic light-emitting diode (OLED) connected to the pixel circuit PC as a light-emitting element. The pixel circuit PC may include at least one thin-film transistor (e.g., TFT1 and TFT2), at least one capacitor (e.g., Cst and Cpr), and at least one dual contact hole (e.g., DCNT1' and DCNT2').

[0148] The dual contact hole DCNT' may include a first dual contact hole DCNT1' and a second dual contact hole DCNT2'. The first dual contact hole DCNT1' can connect the first semiconductor layer A1 of the first thin film transistor TFT1 to the pixel electrode 310 of the light-emitting element.

[0149] The second dual contact hole DCNT2' can connect the second semiconductor layer A2 of the second thin-film transistor TFT2 to one electrode of the second capacitor Cpr. More specifically, the lower conductive layer of the second dual contact hole DCNT2' can be connected to the fourth-first electrode C4-1 of the second capacitor Cpr. For example, the lower conductive layer of the second dual contact hole DCNT2' can form part of the fourth-first electrode C4-1. The fourth-first electrode C4-1 can be provided by stacking the lower conductive layer and the intermediate conductive layer.

[0150] The upper conductive layer of the second dual contact hole DCNT2' can be disposed on the fourth interlayer insulating film 119, and can be connected to the intermediate conductive layer disposed on the lower conductive layer through the upper contact hole. The upper conductive layer of the second dual contact hole DCNT2' can be connected to the 4-2 electrode C4-2. For example, the upper conductive layer of the second dual contact hole DCNT2' can be provided integrally with the 4-2 electrode C4-2.

[0151] In this embodiment, a protective film and a buffer film covering the lower conductive layer can be provided inside the lower contact hole of the dual contact hole DCNT', and an inorganic material formed by the aggregation of inorganic nanoparticles can be filled in the recess provided in the buffer film. Accordingly, a display panel 10' with robustness and high reliability can be provided.

[0152] Display panels 10 and 10' according to one or more embodiments may be included in an electronic device. According to one or more embodiments, the electronic device for displaying moving or still images can be used not only as a display screen for portable electronic devices (such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, or ultra-mobile PCs (UMPCs), but also as a display screen for any of one or more suitable electronic products such as televisions, laptops, monitors, billboards, or Internet of Things (IoT) products. Electronic device 1 according to one or more embodiments (see...) Figure 17 It can be used in wearable devices such as smartwatches, smartwatch phones, glasses-type (or similar) displays, or head-mounted displays (HMDs). Furthermore, the electronic device 1 according to one or more embodiments can be used as a central information display (CID) arranged on a vehicle's instrument panel, center console, or dashboard; an interior mirror display replacing the vehicle's side mirrors; or a display arranged on the back of the front seat for the entertainment of rear-seat passengers.

[0153] Figure 17 This is a perspective view illustrating an electronic device 1 according to one or more embodiments of the present disclosure. Figure 18This is an exploded perspective view illustrating an electronic device 1 according to one or more embodiments.

[0154] refer to Figure 17 and Figure 18 The electronic device 1 according to one or more embodiments can be a smartphone. The electronic device 1 according to one or more embodiments may include a cover window 70, a display panel 10, a data driver 20, a display circuit board 30, a component 40, a bracket 60, a main circuit board 50, a battery 80, and a bottom cover 90.

[0155] In this disclosure, "left," "right," "up," and "down" in the plan view refer to the directions when the display panel 10 is viewed in a direction orthogonal (e.g., perpendicular) to the display panel 10. For example, "left" refers to the -x direction, "right" refers to the +x direction, "up" refers to the +y direction, and "down" refers to the -y direction.

[0156] In one or more embodiments, the electronic device 1 may have a rectangular shape in a plan view. For example, as in... Figure 17 As shown, the electronic device 1 in the plan view can have a rectangular shape, which has a short side extending in the x-direction and a long side extending in the y-direction. The corners where the short side extending in the x-direction and the long side extending in the y-direction intersect each other can be rounded to have a certain curvature, or can be formed to have right angles. The planar shape of the electronic device 1 is not limited to a rectangular shape, and can be other polygonal shapes, elliptical shapes, or irregular shapes.

[0157] A cover window 70 can be arranged on the display panel 10 to cover the top surface of the display panel 10. Accordingly, the cover window 70 can protect the top surface of the display panel 10.

[0158] The cover window 70 may include a transmissive cover portion DA 70 corresponding to the display panel 10 and a light-shielding cover portion NDA 70 surrounding the transmissive cover portion DA 70 (e.g., around the transmissive cover portion DA 70). The light-shielding cover portion NDA 70 may contain an opaque material (e.g., a colored opaque material) for blocking light. The light-shielding cover portion NDA 70 may include a pattern that can be displayed to the user if no image is displayed (e.g., when no image is displayed).

[0159] The display panel 10 used to provide images can be a reference. Figures 1 to 16 The display panel described. The display panel 10 can be arranged below the cover window 70. The display panel 10 can overlap with the transmissive cover portion DA70 of the cover window 70.

[0160] Display panel 10 includes a display area DA. The display area DA for displaying images may include an area (hereinafter referred to as the component area) that transmits light emitted from a component 40 disposed below display panel 10. Component 40 may include a sensor and / or camera that uses visible light, infrared light, or sound.

[0161] Display panel 10 displays (outputs) information processed by electronic device 1. For example, display panel 10 may display execution screen information of an application driven by electronic device 1, or display user interface (UI) or graphical user interface (GUI) information based on the execution screen information.

[0162] Display panel 10 may be a light-emitting display panel including light-emitting diodes (LEDs). The LEDs may include organic light-emitting diodes (OLEDs) containing an organic emitting layer. In one or more embodiments, the LEDs may be inorganic LEDs containing inorganic materials. Inorganic LEDs may include PN junction diodes containing inorganic semiconductor materials. When a voltage is applied to a PN junction diode in the forward direction, holes and electrons can be injected, and the energy generated by the recombination of holes and electrons can be converted into light energy to emit light of a specific color. Inorganic LEDs may have a width of several micrometers to several hundred micrometers, and in one or more embodiments, the inorganic LED may be referred to as a micro LED.

[0163] The display panel 10 can be a rigid display panel that is not easily bent, or a flexible display panel that is easily bent, folded, or rolled. For example, in one or more embodiments, the display panel 10 can be a foldable display panel that can be folded and unfolded, a curved display panel with a curved display surface, a curved display panel in which the portion other than the display surface is bent, a rollable display panel that can be rolled or unfolded, or a stretchable display panel.

[0164] In one or more embodiments, the display panel 10 may be a transparent display panel, which is transparent so that objects or backgrounds disposed on the bottom surface of the display panel 10 can be observed from the top surface of the display panel 10. In one or more embodiments, the display panel 10 may be a reflective display panel, which is capable of reflecting objects or backgrounds on the top surface of the display panel 10.

[0165] In one or more embodiments, the data driver 20 may be mounted as an integrated circuit (IC) on the display panel 10. In one or more embodiments, the data driver 20 may be arranged on the display circuit board 30.

[0166] The display circuit board 30 can be attached to a side (e.g., one side) of the display panel 10. The display circuit board 30 can be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that is rigid and not easily bent, or a composite printed circuit board that includes both rigid and flexible printed circuit boards (e.g., including both rigid and flexible printed circuit boards).

[0167] In one or more embodiments, a touch sensor driver may be disposed on a display circuit board 30. The touch sensor driver may be formed as an IC. The touch sensor driver may be attached to the display circuit board 30. The touch sensor driver may be electrically connected via the display circuit board 30 to the touch electrodes of the touchscreen layer of the display panel 10.

[0168] The touchscreen layer of display panel 10 can detect user touch input using at least one of one or more suitable touch methods (such as resistive and / or capacitive methods). For example, if the touchscreen layer of display panel 10 detects user touch input using a capacitive method (e.g., when the touchscreen layer of display panel 10 detects user touch input using a capacitive method), the touch sensor driver can determine whether the user has touched the screen by applying a drive signal to the drive electrode in the touch electrodes and detecting the voltage charged in the mutual capacitance between the drive electrode and the sensing electrode in the touch electrodes. User touch can include contact touch and proximity touch. Contact touch refers to an object such as a user's finger or pen directly contacting the overlay window 70 arranged on the touchscreen layer. Proximity touch refers to an object such as a user's finger or pen being close to the overlay window 70, such as hovering. The touch sensor driver can be used to transmit sensor data to the main processor 510 based on the detected voltage, and the main processor 510 can calculate the touch coordinates of the touch input by analyzing the sensor data.

[0169] The controller, gate driver, and data driver 20 used to supply the driving voltage for driving the pixels of the display panel 10 can be arranged on the display circuit board 30.

[0170] A bracket 60 for supporting the display panel 10 may be disposed below the display panel 10. The bracket 60 may comprise plastic, metal, or both (e.g., both plastic and metal). A first camera hole CMH1 into which the camera device 531 is inserted, a battery hole BH into which the battery 80 is disposed, and a cable hole CAH through which cables connected to the display circuit board 30 pass may be formed in the bracket 60. A component hole CPH overlapping the display panel 10 may be formed in the bracket 60. The component hole CPH may overlap with a component 40 of the main circuit board 50 in the z-direction. In one or more embodiments, the display area DA of the display panel 10 may overlap with a component 40 of the main circuit board 50 in the z-direction. In one or more embodiments, the component hole CPH may not be formed in the bracket 60.

[0171] In one or more embodiments, component 40 may include first to fourth components 41, 42, 43, and 44 overlapping the display panel 10. The first to fourth components 41, 42, 43, and 44 may be provided as a proximity sensor, an illumination sensor, an iris sensor, a facial recognition sensor, and a camera (or image sensor), respectively. An infrared proximity sensor can detect objects positioned near the top surface of the electronic device 1, and an illumination sensor can detect the brightness of light incident on the top surface of the electronic device 1. Furthermore, an iris sensor can capture an image of the iris of a person located on the top surface of the electronic device 1, and a camera can capture an image of an object located on the top surface of the electronic device 1. Component 40 is not limited to proximity sensors, illumination sensors, iris sensors, facial recognition sensors, and cameras, and may be arranged with one or more suitable sensors described below.

[0172] The main circuit board 50 and the battery 80 can be arranged below the bracket 60. The main circuit board 50 can be a rigid printed circuit board or a flexible printed circuit board.

[0173] The main circuit board 50 may include a main processor 510, a camera device 531, a main connector 55, and a component 40. The main processor 510 may be formed as an IC. The camera device 531 may be disposed on both the top and bottom surfaces of the main circuit board 50 (e.g., disposed on both the top and bottom surfaces of the main circuit board 50 simultaneously), and each of the main processor 510 and the main connector 55 may be disposed independently on either the top or bottom surface of the main circuit board 50.

[0174] The main processor 510 can control all functions of the electronic device 1. For example, the main processor 510 can output digital video data to the data driver 20 via the display circuit board 30, causing the display panel 10 to display an image. The main processor 510 can receive detection data from the touch sensor driver. The main processor 510 can determine whether a user has touched the device based on the detection data and can perform operations corresponding to direct touch or proximity touch by the user. The main processor 510 can be an application processor, a central processing unit, or a system chip formed as an IC.

[0175] Camera device 531 processes image frames, such as still images or moving images, acquired by an image sensor in camera mode, and outputs the image frames to main processor 510. Camera device 531 may include at least one of a camera sensor (e.g., CCD or CMOS), a light sensor (or image sensor), and a laser sensor. Camera device 531 may be connected to the image sensor in component 40 overlapping with display area DA, and may process images input to the image sensor.

[0176] The cable passing through the cable hole CAH of the bracket 60 can be connected to the main connector 55, and thus the main circuit board 50 can be electrically connected to the display circuit board 30.

[0177] The battery 80 can be arranged so as not to overlap with the main circuit board 50 in the z-direction. The battery 80 can overlap with the battery hole BH of the bracket 60.

[0178] The lower cover 90 can form the appearance of the electronic device 1, and a portion of the display panel 10 can be formed in the front surface of the lower cover 90 through its exposed opening. The lower cover 90 has a shape with its corresponding surface open to the display panel 10 and can be assembled to the display panel 10. The lower cover 90 can be arranged opposite to the cover window 70, and the display panel 10 is located between the lower cover 90 and the cover window 70. The lower cover 90 can be disposed below the main circuit board 50 and the battery 80. The lower cover 90 can be fastened and fixed to the bracket 60. The lower cover 90 can form the appearance of the bottom surface of the electronic device 1. The lower cover 90 can be made of plastic, metal, or both plastic and metal (e.g., both plastic and metal). In one embodiment, the lower cover 90 and the cover window 70 can constitute a cover unit for supporting and accommodating the display panel 10.

[0179] The bottom surface of camera device 531, through which the exposed second camera aperture CMH2 can be formed in the lower cover 90. The position of camera device 531 and the corresponding positions of the first camera aperture CMH1 and second camera aperture CMH2 are not limited to... Figure 17 and Figure 18 The positions shown in the example can be changed in one or more suitable ways.

[0180] Figure 19 This is a perspective view schematically illustrating an electronic device 1' according to one or more embodiments of the present disclosure. Figure 20 This is an exploded view schematically illustrating an electronic device 1' according to one or more embodiments.

[0181] refer to Figure 19 and Figure 20 Electronic device 1' can be worn on a user's head. Electronic device 1' can be referred to as a glasses-type display device. Electronic device 1' can provide images whether the user's actual peripheral vision is obstructed or not. The user wearing electronic device 1' can easily immerse themselves in augmented reality or virtual reality. Electronic device 1' may include display panel 10, optical unit 2000, cover unit 3000, fixing unit 4000, and pad unit 5000.

[0182] The display panel 10 used to provide images can be a reference. Figures 1 to 16 The described display panel 10 may be housed within the cover unit 3000. In one or more embodiments, the electronic device 1' may include multiple display panels 10. For example, the electronic device 1' may include a first display panel 10A and a second display panel 10B. In these embodiments, the first display panel 10A and the second display panel 10B may overlap with multiple optical units 2000. The first display panel 10A may be a left-eye display panel. The second display panel 10B may be a right-eye display panel. In one or more embodiments, the electronic device 1' may include a single display panel 10. In these embodiments, multiple optical units 2000 may overlap with a single display panel 10.

[0183] The optical unit 2000 allows light emitted from the display panel 10 to pass through it. The optical unit 2000 can refract and / or reflect light emitted from the display panel 10. In one or more embodiments, the optical unit 2000 can magnify the image provided from the display panel 10. The optical unit 2000 can face the display panel 10. When a user wears the electronic device 1', the optical unit 2000 can be positioned between the user and the display panel 10. Accordingly, the user can perceive light emitted from the display panel 10 and refracted and / or reflected by the optical unit 2000. In one or more embodiments, the optical unit 2000 may include at least one of a lens and a mirror.

[0184] In one or more embodiments, the electronic device 1' may include a plurality of optical units 2000. For example, the electronic device 1' may include a first optical unit 2000A and a second optical unit 2000B. In these embodiments, a first display panel 10A may face the first optical unit 2000A. A second display panel 10B may face the second optical unit 2000B. The first optical unit 2000A may be a left-eye optical unit. The second optical unit 2000B may be a right-eye optical unit. In one or more embodiments, the electronic device 1 may include a single optical unit 2000.

[0185] The cover unit 3000 can accommodate the display panel 10 and the optical unit 2000. The cover unit 3000 may include an internal space in which the display panel 10 and the optical unit 2000 can be arranged. The cover unit 3000 can protect the display panel 10 and the optical unit 2000 from external impacts. In one or more embodiments, the cover unit 3000 may be divided into a first cover unit 31000 and a second cover unit 33000. In one or more embodiments, the first cover unit 31000 and the second cover unit 33000 may be provided integrally with each other. In one or more embodiments, the first cover unit 31000 may be opaque. In one or more embodiments, the first cover unit 31000 may be transparent.

[0186] The cover unit 3000 can support the curved display panel 10. For example, in one or more embodiments, the display panel 10 can be fixed in the cover unit 3000. Furthermore, the cover unit 3000 can support the display panel 10 to maintain the shape of the curved display panel 10.

[0187] The fixing unit 4000 can secure the covering unit 3000 to the user's head. Accordingly, the electronic device 1' can be worn on the user's head. In one or more embodiments, the length of the fixing unit 4000 can be adjusted. For example, the length of the fixing unit 4000 can be adjusted according to the circumference of the user's head.

[0188] The fixing unit 4000 allows the electronic device 1' to make close contact with the user's head. In one or more embodiments, the fixing unit 4000 may be elastic. Although in Figure 19 The fixing unit 4000 is a strap, but in one or more embodiments, the fixing unit 4000 can be one or more suitable types (types), such as a helmet attached to the cover unit 3000 or a temple attached to the cover unit 3000. The fixing unit 4000 can be attached to the cover unit 3000. In one or more embodiments, the fixing unit 4000 can be detached from the cover unit 3000.

[0189] The pad unit 5000 can improve wearability for the user. When the user wears the electronic device 1', the pad unit 5000 can be positioned between the user and the cover unit 3000. In one or more embodiments, the pad unit 5000 can be attached to the cover unit 3000. In one or more embodiments, the pad unit 5000 can be detached from the cover unit 3000. In one or more embodiments, the pad unit 5000 may not be provided.

[0190] The pad unit 5000 may comprise a material whose shape can be freely changed. For example, in one or more embodiments, the pad unit 5000 may comprise a polymer resin. For example, the pad unit 5000 may comprise at least one of polyurethane, polycarbonate, polypropylene, and polyethylene. In one or more embodiments, the pad unit 5000 may comprise a sponge foamed with a rubber liquid, a urethane-based material, or an acrylic material.

[0191] As described above, the display panel, display device (e.g., display apparatus) including the display panel, and electronic device including the display device and / or display panel according to this disclosure include dual contact holes, in which the lower contact hole is filled with inorganic nanoparticles, and thus can have robustness and high reliability. For example, the display panel and the electronic device including the display panel are characterized by dual contact holes. The dual contact holes include a lower contact hole filled with inorganic nanoparticles. The inclusion of inorganic nanoparticles enhances the robustness and reliability of the display panel, ensuring that it can withstand various operating stresses and environmental conditions. The dual contact hole design contributes to the overall durability and performance of the display panel, making it suitable for high-resolution and highly integrated applications.

[0192] Furthermore, because the dual contact holes are formed using a dispersion solution containing inorganic nanoparticles, processing time and costs can be saved. For example, the formation of dual contact holes utilizes a dispersion solution containing inorganic nanoparticles. This method using a dispersion solution not only simplifies the manufacturing process but also significantly reduces production-related time and costs. By effectively filling the recesses with inorganic materials and forming the necessary conductive layer, this process ensures high-quality and reliable connections within the pixel circuitry. This method streamlines the manufacturing of display panels, making them more cost-effective and time-efficient while maintaining high standards of quality and performance.

[0193] The effects and benefits described above are examples, and the effects and benefits of this disclosure are not limited thereto.

[0194] In the context of this application, and unless otherwise defined, the term “use” may be regarded as synonymous with the term “utilize”.

[0195] For descriptive purposes, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship of one element or feature as shown in the accompanying drawings to another element(s). The spatial relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped upside down (e.g., when the device in the accompanying drawings is flipped upside down), an element described as “below” or “under” other elements or features would then be oriented as “above” or “up” other elements or features. Thus, in one or more embodiments, the example term “below” may cover both above and below orientations (e.g., both above and below orientations simultaneously). Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptive terms used herein are interpreted accordingly.

[0196] As used herein, the terms “substantially,” “about,” or similar terms are used as approximations, not as terms of degree, and are intended to describe the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art considering the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0197] Any numerical range described herein is intended to include all subranges of the same numerical precision contained within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between the described minimum value of 1.0 and the described maximum value of 10.0 (and including both the described minimum value of 1.0 and the described maximum value of 10.0), i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described herein is intended to include all higher numerical limits contained therein. Accordingly, the applicant reserves the right to modify this disclosure, including the claims, to explicitly describe any subranges contained within the range explicitly described herein.

[0198] The display device / apparatus, electronic device / apparatus, display device manufacturing apparatus, or any other related device / apparatus or component according to the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of the device can be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of the device can be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of the device can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard storage devices (such as random access memory (RAM) as an example). The computer program instructions can also be stored in other non-transitory computer-readable media such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of the embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0199] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended to be limiting. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in one or more embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that one or more suitable changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: substrate; A pixel circuit, on the substrate, and comprising: At least one thin-film transistor; At least one capacitor; and At least one double contact hole; and The light-emitting element is electrically connected to the pixel circuit. The dual contact holes include: The lower contact hole is defined in the first insulating layer on the substrate; A lower conductive layer is located on the top surface of the first insulating layer and inside the lower contact hole; Inorganic material is filled in the recesses in the lower conductive layer due to the lower contact hole provided therein; An intermediate conductive layer is located on the lower conductive layer and the inorganic material; The upper contact hole is defined in the second insulating layer on the first insulating layer; and An upper conductive layer is located on the top surface of the second insulating layer and inside the upper contact hole, and is connected to the intermediate conductive layer.

2. The display panel according to claim 1, wherein the inorganic material comprises aggregated nanoparticles of metal oxides and / or metals.

3. The display panel according to claim 1, wherein the inorganic material comprises at least one material selected from BaTiO3, BaSO3, BaSO4, Ba(NO3)2, TiO2, SiO2 and ZnO.

4. The display panel according to claim 1, wherein the inorganic material comprises at least one material selected from silver, gold, platinum and palladium.

5. The display panel according to claim 1, wherein the upper contact hole overlaps with the lower contact hole.

6. The display panel according to claim 1, wherein the dual contact holes further comprise: A protective film is arranged inside the recess along the shape of the lower conductive layer; And a buffer membrane on the protective membrane.

7. The display panel of claim 6, wherein the buffer film comprises a material different from the inorganic material.

8. The display panel according to claim 1, wherein The at least one thin-film transistor includes a first thin-film transistor and a second thin-film transistor, and The at least one dual contact hole includes a first dual contact hole and a second dual contact hole, and The first dual contact hole connects the semiconductor layer of the first thin-film transistor to the pixel electrode of the light-emitting element.

9. The display panel according to claim 8, wherein the at least one capacitor comprises a first capacitor and a second capacitor, and The second dual contact hole connects the semiconductor layer of the second thin-film transistor to the second capacitor.

10. The display panel of claim 9, wherein the first capacitor overlaps with the first thin-film transistor.

11. A method for manufacturing a display panel, comprising: A conductive layer is formed on the substrate; A first insulating layer is formed to cover the conductive layer, and a lower contact hole is formed in the first insulating layer, through which a portion of the conductive layer is exposed; A lower conductive layer is formed from the top surface of the first insulating layer along the inner surface of the lower contact hole and connected to the conductive layer; A dispersion solution containing inorganic nanoparticles is coated onto the first insulating layer to cover the lower conductive layer; as well as An annealing process is performed to cause the inorganic nanoparticles to agglomerate and fill the recesses in the lower conductive layer provided by the lower contact holes.

12. The method of claim 11, further comprising cleaning the inorganic nanoparticles disposed outside the recess after the annealing.

13. The method of claim 11, further comprising: An intermediate conductive layer is formed on the recess filled with the inorganic nanoparticles; A second insulating layer is formed on the first insulating layer to cover the intermediate conductive layer, and an upper contact hole is formed in the second insulating layer, through which a portion of the intermediate conductive layer is exposed; as well as An upper conductive layer is formed from the top surface of the second insulating layer along the inner surface of the upper contact hole and connected to the intermediate conductive layer.

14. The method of claim 11, wherein the inorganic nanoparticles comprise at least one material selected from BaTiO3, BaSO3, BaSO4, Ba(NO3)2, TiO2, SiO2, and ZnO.

15. The method of claim 11, wherein the inorganic nanoparticles comprise at least one material selected from silver, gold, platinum, and palladium.

16. The method of claim 11, further comprising forming a protective film on the lower conductive layer prior to coating the dispersion solution.

17. The method of claim 16, further comprising: The internal region of the lower contact hole is partially filled by depositing a buffer film thicker than the protective film on the protective film using a chemical vapor deposition method. as well as The buffer film formed on the first insulating layer is removed using a chemical mechanical polishing process.

18. The method of claim 17, wherein the buffer membrane is formed of a material different from the inorganic nanoparticles.

19. An electronic device comprising: Display panel, including dual contact holes; as well as Covering unit, supporting and accommodating the display panel, The dual contact holes include: The lower contact hole is confined within the first insulating layer; A lower conductive layer is located on the top surface of the first insulating layer and inside the lower contact hole; Inorganic material is filled in the recesses in the lower conductive layer due to the lower contact hole provided therein; An intermediate conductive layer is located on the lower conductive layer and the inorganic material; The upper contact hole is defined in the second insulating layer on the first insulating layer; and An upper conductive layer is located on the top surface of the second insulating layer and inside the upper contact hole, and is connected to the intermediate conductive layer.

20. The electronic device of claim 19, wherein the electronic device is a smartphone or a glasses-type display device.

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