Semiconductor structure forming method and semiconductor structure

Abstract

A method of forming a semiconductor structure includes etching at least one conductive structure to form an opening dividing the conductive structure into shorter portions, and applying at least one passivation treatment to a portion above the opening. The method may also include forming a non-conformal material layer having a lower fixed charge concentration than silicon nitride. In some embodiments, the non-conformal material layer has a first portion on an upper portion of the opening passivated by at least one passivation treatment, and the non-conformal material layer has a second portion extending to a base of the opening, the first portion of the non-conformal material layer having a thickness less than that of the second portion of the non-conformal material layer. In some embodiments, the method further includes depositing a fill dielectric on the non-conformal material layer.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Advances in integrated circuit (IC) materials and design technologies have resulted in generation after generation of ICs, each with circuits that are smaller and more complex than their predecessors. Throughout the development of ICs, functional density (e.g., the number of interconnect elements per unit wafer area) has increased overall, while geometric dimensions have decreased. This scaling down process typically benefits production efficiency and reduces associated costs.

[0003] This reduction in scale also increases the complexity of integrated circuit processes and manufacturing, and similar advancements are needed in integrated circuit processes and manufacturing to achieve these progresses. For example, dielectrics (such as dielectric materials) can be used as spacers, pads, and gap fillers to achieve device isolation. However, in some cases, dielectric materials can have high levels of positive fixed charge due to point defects. In some cases, high levels of positive fixed charge within semiconductor devices can lead to various device performance problems. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method of forming a semiconductor structure includes: etching at least one conductive structure to form an opening that divides the conductive structure into shorter portions; applying a passivation treatment to an upper portion of the opening; forming a nonconformal material layer having a first fixed charge concentration, wherein the nonconformal material layer has a first portion passivated by the passivation treatment on the upper portion of the opening, and the nonconformal material layer has a second portion extending to the base of the opening, the first portion of the nonconformal material layer having a thickness smaller than that of the second portion of the nonconformal material layer; and depositing a filling dielectric on the nonconformal material layer, the filling dielectric having a second fixed charge concentration higher than the first fixed charge concentration.

[0005] According to one embodiment of the present disclosure, a method of forming a semiconductor structure includes: etching at least one conductive structure to form an opening that divides the conductive structure into shorter portions; forming a buffer layer having a fixed charge concentration lower than that of silicon nitride; etching the buffer layer to produce a non-conformal thickness, wherein the non-conformal thickness of the buffer layer includes a first portion in the upper portion of the opening, the first portion having a thickness smaller than that of a second portion of the buffer layer in the base portion of the opening; and depositing a filling dielectric on the buffer layer having a non-conformal thickness.

[0006] According to one embodiment of this disclosure, a semiconductor structure includes at least one conductive feature, a trench, and a trench filler. The trench extends through the conductive feature. The trench filler includes a non-conformal material layer and a filling dielectric. The non-conformal material layer has a first fixed charge concentration, wherein the non-conformal material layer has a first portion located above the trench, the first portion having a first thickness, and the non-conformal material layer has a second portion extending through the base of the trench and having a second thickness, wherein the second thickness is less than the first thickness. The filling dielectric has a second fixed charge concentration, higher than the first fixed charge concentration on the non-conformal material layer. Attached Figure Description

[0007] This disclosure will be best understood by reading the following embodiments in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figures 1 to 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 11 A view illustrating an intermediate stage in transistor formation according to a partial embodiment;

[0009] Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 17H , Figure 17I , Figure 17J , Figure 17K , Figure 17L , Figure 17M , Figure 17N , Figure 17O as well as Figure 17PTo illustrate the formation of continuous polysilicon on diffusion edge (CPODE) according to a partial embodiment;

[0010] Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20 A view illustrating an intermediate stage in transistor formation according to a partial embodiment;

[0011] Figures 21 to 36 To illustrate the formation of a cut metal gate (CMG) isolation interface according to a partial embodiment;

[0012] Figure 37A , Figure 37B , Figure 38A as well as Figure 38B A view illustrating an intermediate stage in transistor formation according to a partial embodiment;

[0013] Figure 39 To illustrate the process flow for forming a transistor according to a partial implementation.

[0014] [Symbol Explanation]

[0015] 10: Wafer

[0016] 20: Substrate

[0017] 20': Substrate strip

[0018] 22,22': Multi-layer stacking

[0019] 22A: First layer / Sacrificial semiconductor layer

[0020] 22B: Second layer / nanostructure

[0021] 23,92: Trench

[0022] 24: Semiconductor Strip

[0023] 26: Quarantine Zone

[0024] 26T: Top surface

[0025] 28: Protruding fins

[0026] 30: Virtual gate stacking

[0027] 32: Virtual gate dielectric

[0028] 34: Virtual gate electrode

[0029] 36: Hard Photomask

[0030] 38: Gate spacer

[0031] 41: Horizontal groove

[0032] 42, 58: Groove

[0033] 44: Internal spacers

[0034] 48: Source / Drain Region, Epitaxial Region

[0035] 50: Contact Etching Stop Layer

[0036] 52,76: Interlayer dielectric

[0037] 62: Gate Dielectric

[0038] 68: Gate electrode

[0039] 70, 70A, 70B: Gate stack

[0040] 74: Gate Mask

[0041] 78: Silicide Region

[0042] 80A, 80B: Contact plugs

[0043] 82A, 82B: Transistors

[0044] 88: Hard photomask layer

[0045] 88A, 88C: Silicon nitride layer

[0046] 88B: Silicon layer

[0047] 90: Etched photomask

[0048] 110: Cut the metal gate region

[0049] 112: Fin isolation zone

[0050] 116: Hard Photomask

[0051] 117: Etched Photomask

[0052] 118, 120: Opening

[0053] 200: Process Flow

[0054] 202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232,234: Process

[0055] 300, 400: Buffer layer

[0056] 301: Inhibition / Passivation Treatment

[0057] 302: Upper part

[0058] 303: Lower part

[0059] 305: Filled dielectric

[0060] 306: Low-k dielectric filler material

[0061] A1-A1,BB: Cross section

[0062] W1, W2: Width

[0063] X, Y: Direction Detailed Implementation

[0064] The following disclosure provides many different implementations or embodiments to carry out the various features of this disclosure. The specific embodiments of composition and arrangement described below are used to simplify this disclosure. Of course, these are merely embodiments and are not intended to limit this disclosure. For example, in the description below, the formation of a first feature on or above a second feature may include implementations where the formed first and second features are in direct contact, and may also include implementations where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplification and clarity, and does not in itself specify the relationship between the various discussed implementations and / or configurations.

[0065] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower," "above," and "upper" may be used in this disclosure to facilitate the description of the relationship between one element or feature and another element or feature as shown in the accompanying drawings. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the element during use or operation. The device may also be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptive symbols used in this disclosure may be interpreted accordingly.

[0066] Dielectric materials are used for device isolation in semiconductor device fabrication, for example, as spacers, pads, and gap fillers. However, some dielectric materials have high levels of positive fixed charge caused by point defects, such as K+ centers that may be present in silicon nitride (SiN) deposited using plasma-assisted chemical vapor deposition (PEVD) or plasma-assisted atomic layer deposition (PEALD). High levels of positive fixed charge can lead to various device performance problems. In some cases, high levels of positive fixed charge in materials used as isolation structures can induce inversion layers in adjacent p-type or p-type doped wells, resulting in undesirable leakage currents.

[0067] The influence of induced charge on dielectric gap-filled isolation structures can be mitigated by positioning a buffer layer with a low fixed charge level between a material with a high fixed charge level and a gap-filled dielectric material for doped wells (e.g., n-type and / or p-type doped wells).

[0068] In some embodiments, increasing the thickness of a buffer layer with a low fixed charge level dielectric composition within the isolation structure is advantageous to mitigate leakage between transistors. However, increasing the thickness of the buffer layer positioned within a trench or opening using conformal deposition methods can simultaneously reduce the critical dimension (CD) of the gap opening. Reducing the gap opening of the isolation structure can lead to difficulties in depositing the dielectric gap filler used to fill the isolation opening or trench structure.

[0069] The methods and structures described herein can use a bottom-up filling process to create a thick buffer layer at the base of an opening or trench structure. The thickness of the buffer layer at the base of the trench isolation structure can mitigate the induced charge effect of the fixed charge of the isolation material within the trench structure in p-type and n-type wells without narrowing the opening (e.g., critical dimension) of the trench isolation structure.

[0070] In the illustrated embodiments, the formation of a gate-all-around (GAA) transistor is used as an example to explain the concepts of this disclosure. Other types of transistors, such as FinFETs, planar transistors, etc., may also employ the concepts of this disclosure. The embodiments discussed herein are intended to provide examples that enable the manufacture or use of the subject matter of this disclosure, and those skilled in the art will readily understand that modifications can be made while remaining within the intended scope of the different embodiments. In the various views and illustrated embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0071] Figures 1 to 38B A view illustrating an intermediate stage of transistor formation according to a partial embodiment of this disclosure is shown.

[0072] Please refer to Figure 1 The image shows a perspective view of wafer 10. Wafer 10 comprises a multilayer structure, which includes a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, etc., or other substrates and / or structures may be used, such as semiconductor-on-insulator (SOI), strained semiconductor-on-insulator, silicon-germanium-on-insulator, etc. Substrate 20 may be doped to be a p-type semiconductor; however, in other embodiments, it may be doped to be an n-type semiconductor.

[0073] According to some embodiments, the multilayer stack 22 is formed through a series of deposition processes involving alternating deposition of materials. The corresponding process is described in... Figure 39 The process flow 200 shown is illustrated as process 202. According to a partial embodiment, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0074] According to some embodiments, the first semiconductor material of the first layer 22A is formed from or contains silicon germanium (SiGe), germanium (Ge), silicon (Si), gallium arsenide (GaAs), indium antimonide (InSb), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide antimony (GaAsSb), etc. According to some embodiments, the deposition of the first layer 22A (e.g., silicon germanium) is performed by epitaxial growth, and the corresponding deposition method can be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), ultra-high vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), etc. According to some embodiments, the first layer 22A is formed to have a first thickness between about 30 Å and about 300 Å. However, any suitable thickness can be used while remaining within the range of the embodiments.

[0075] Once the first layer 22A is deposited over the substrate 20, the second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or contains a second semiconductor material, such as silicon (Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium antimonide (InSb), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide (GaAsSb), and combinations thereof, wherein the second semiconductor material differs from the first semiconductor material of the first layer 22A. For example, according to a partial embodiment where the first layer 22A is silicon germanium, the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0076] According to some embodiments, a second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, for example, the thickness of the first layer 22A is approximately between 4 nm and 7 nm, while the thickness of the second layer 22B ranges from approximately 8 nm to 12 nm.

[0077] Once the second layer 22B is formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired top layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other, and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same thickness as or a different thickness than the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as sacrificial layer 22A throughout the description. According to an alternative embodiment, the second layer 22B is a sacrificial layer and is removed in a subsequent process.

[0078] According to some embodiments, several pad oxide layers (singular / plural) and hard photomask layers (singular / plural) may be formed over the multilayer stack 22 (not shown). These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0079] Please refer to Figure 2 A trench 23 is formed by patterning a portion of the multilayer stack 22 and the underlying substrate 20 using an etching process. The trench 23 extends into the substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as the multilayer stack 22'. Below the multilayer stack 22', a portion of the substrate 20 remains, hereinafter referred to as substrate strip 20'. The multilayer stack 22' contains semiconductor layers 22A and 22B. Semiconductor layer 22A is alternatively referred to as a sacrificial layer, and semiconductor layer 22B is alternatively referred to as a nanostructure. The portion of the multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0080] In the embodiments illustrated above, the transistor structure can be patterned using any suitable method. For example, one or more lithography processes (including dual or multiple patterning processes) can be used to pattern the structure. Generally, dual or multiple patterning processes combine lithography and self-alignment processes, allowing the creation of patterns, for example, with a pitch smaller than that obtained using a single, direct lithography process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the element structure.

[0081] Figure 3 The formation of isolation zone 26 is illustrated; throughout the description, the isolation zone is also referred to as the Shallow Trench Isolation (STI) zone. The corresponding process is as follows: Figure 39 The process flow 200 is illustrated in process 206. The shallow trench isolation region 26 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The pad oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition, high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition, etc. The shallow trench isolation region 26 may also include a dielectric material above the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, high-density plasma chemical vapor deposition, etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, may then be performed to flatten the top surface of the dielectric material, and the remaining portion of the dielectric material constitutes the shallow trench isolation region 26.

[0082] The shallow trench isolation region 26 is then recessed such that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the shallow trench isolation region 26 to form a protruding fin 28. The protruding fin 28 comprises the top of a multilayer stack 22' and a substrate strip 20'. The recess of the shallow trench isolation region 26 can be performed by a dry etching process, wherein, for example, nitrogen trifluoride (NF3) and nitrogen (NH3) are used as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the shallow trench isolation region 26 is performed by a wet etching process. For example, the etching chemicals may include hydrogen fluoride (HF).

[0083] Please refer to Figure 4 A virtual gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is described in... Figure 39The process flow 200 shown is illustrated as process 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 located above the dummy gate dielectric 32. The dummy gate dielectric 32 can be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. The dummy gate electrode 34 can be formed using, for example, polycrystalline silicon or amorphous silicon, or other materials such as amorphous carbon.

[0084] Each dummy gate stack 30 may also include one (or more) hard photomasks 36 located above the dummy gate electrode 34. The hard photomasks 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stack 30 may span one or more protruding fins 28 and shallow trench isolation regions 26 between the protruding fins 28. The dummy gate stack 30 also has a length direction perpendicular to the length direction of the protruding fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer above the dummy gate dielectric layer, depositing one or more hard photomask layers, and then patterning the formed layers using a patterning process.

[0085] Next, gate spacers 38 are formed on the sidewalls of the virtual gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), etc., and may have a single-layer structure or a multilayer structure comprising multiple dielectric layers. The formation process of the gate spacers 38 may include depositing one or more dielectric layers, followed by an anisotropic etching process on the dielectric layers. The remaining portion of the dielectric layers constitutes the gate spacers 38.

[0086] Figure 5A as well as Figure 5B It is illustrated Figure 4 The cross-sectional view of the structure shown. Figure 5A It is illustrated Figure 4 Reference cross section A1-A1 is shown in the figure. This cross section cuts through the portion of the protruding fin 28 not covered by the gate stack 30 and the gate spacer 38, and is perpendicular to the gate length direction. The gate spacer 38 located on the sidewall of the protruding fin 28 is also shown. Figure 5B It is illustrated Figure 4 The reference cross section BB is parallel to the length direction of the protruding fin 28.

[0087] Please refer to Figure 6A as well as Figure 6BThe portion of the protruding fin that is not directly below the virtual gate stack 30 and gate spacer 38 is recessed using an etching process to form a groove 42. The corresponding process is described in [the original text is missing here, likely due to an error in the original source]. Figure 39 The process flow 200 shown is illustrated as process 210. For example, a dry etching process can be performed using a mixture of hexafluoroethane (C2F6), carbon tetrafluoride (CF4), silicon dioxide (SO2), hydrogen bromide (HBr), chlorine (Cl2), and oxygen (O2), or a mixture of hydrogen bromide (HBr), chlorine (Cl2), oxygen (O2), and difluoromethane (CH2F2) to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20'. The base of the recess 42 is at least flush with the base of the multilayer semiconductor stack 22', or may be lower than the base of the multilayer semiconductor stack 22' (e.g., ...). Figure 6B (As shown). Etching can be anisotropic, such that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown. Figure 6B As shown.

[0088] Please refer to Figure 7A as well as Figure 7B The sacrificial semiconductor layer 22A is laterally recessed to form a lateral groove 41, which is recessed from the edges of the nanostructures 22B above and below them, respectively. The corresponding process is... Figure 39 The process flow 200 shown is illustrated as process 212. Lateral recesses in the sacrificial semiconductor layer 22A can be achieved via a wet etching process using an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon (Si)) than the material of the nanostructure 22B and the substrate 20 (e.g., silicon-germanium (SiGe)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon-germanium and the nanostructure 22B is formed of silicon, the wet etching process can be performed using an etchant such as hydrochloric acid (HCl). The wet etching process can be performed using immersion processes, spraying processes, spin coating processes, etc.

[0089] According to an alternative implementation, the lateral recess of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of dry etching and wet etching processes.

[0090] Please refer to Figure 8A as well as Figure 8B This forms internal spacers 44. The corresponding process is as follows: Figure 39 The process flow 200 shown is illustrated as process 214. According to a partial embodiment, the formation of the inner spacer 44 includes depositing a conformal dielectric layer that extends into the lateral groove 41. Figure 7B Next, an etching process (also known as a spacer trimming process) is performed to trim the portion of the spacer layer outside the transverse groove 41, leaving the portion of the spacer layer inside the transverse groove 41. The remaining portion of the spacer layer is called the inner spacer 44.

[0091] Figure 9A as well as Figure 9B A cross-sectional view is shown illustrating the formation of the source / drain region 48 in the groove 42 via epitaxy. The corresponding process is... Figure 39 The process flow 200 shown is illustrated as process 216. Source / drain regions (singular / plural) can refer to either the source or the drain, individually or collectively depending on the context. According to some embodiments, source / drain regions 48 can apply stress to nanostructure 22B, which serves as a channel for a corresponding gate-all-around transistor, thereby improving performance.

[0092] According to some embodiments, the corresponding transistor is n-type, and the epitaxial source / drain region 48 is thus formed as n-type by doping with an n-type dopant. For example, silicon phosphide (SiP), silicon phosphocarbon (SiCP), etc., can be grown to form the epitaxial source / drain region 48. According to an alternative embodiment, the corresponding transistor is p-type, and the epitaxial source / drain region 48 is thus formed as p-type by doping with a p-type dopant. For example, silicon boron (SiB), silicon germanium boron (SiGeB), etc., can be grown to form the epitaxial source / drain region 48. After the groove 42 is filled with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally and can form facets. Further growth of the epitaxial region 48 may also cause adjacent epitaxial regions 48 to merge with each other, forming gaps.

[0093] After the epitaxial process, n-type or p-type impurities can be implanted into the epitaxial region 48 to form the source and drain regions, which are also denoted by reference numeral 48. According to an alternative embodiment disclosed herein, when the epitaxial region 48 is doped with n-type or p-type impurities in situ during epitaxy, the implantation process can be omitted, and the epitaxial region 48 is also a source / drain region.

[0094] Figure 10A as well as Figure 10B A cross-sectional view of the structure after the formation of the contact etch stop layer (CESL) 50 and the interlayer dielectric (ILD) 52 is shown. The corresponding process was carried out in... Figure 39The process flow 200 shown is illustrated as process 218. The contact etch stop layer 50 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using chemical vapor deposition, atomic layer deposition, etc. The interlayer dielectric 52 can comprise a dielectric material formed using, for example, flowable chemical vapor deposition, spin coating, chemical vapor deposition, or any other suitable deposition method. The interlayer dielectric 52 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based material formed using tetraethyl silicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0095] The contact etch stop layer 50 and the interlayer dielectric 52 are planarized using a planarization process (e.g., chemical mechanical polishing or mechanical polishing). According to some embodiments, the planarization process may remove the hard photomask 36 to expose the dummy gate electrode 34, such as... Figure 10A As shown. According to an alternative embodiment, the planarization process may expose the hard photomask 36 and stop on the hard photomask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard photomask 36), gate spacer 38, and interlayer dielectric 52 are flat within the process variation.

[0096] Figure 10C The illustration shows a partial implementation method. Figure 10A as well as Figure 10B A top view of the structure shown. Multilayer stack 22', substrate strip 20', and protruding fins 28 (see reference). Figure 10A The gate stack 30, which includes the dummy gate electrode 34 (e.g., a polysilicon strip), has a length direction in the X direction, and the corresponding cross-sectional view is called the X-cut view. The gate stack 30, which includes the dummy gate electrode 34 (e.g., a polysilicon strip), has a length direction in the Y direction, and the corresponding cross-sectional view is called the Y-cut view. The source / drain region 48 is formed based on certain portions of the multilayer stack 22' (e.g., ...). Figure 5B as well as Figure 10B (As shown). The edge of the source / drain region may be in contact with the gate spacer 38, or may be separated from the gate spacer 38.

[0097] Figure 11 A top view illustrating the formation of the fin isolation region 112 is shown. According to some embodiments, such as... Figure 11 As shown, the fin isolation region 112 is a continuous polysilicon region on the diffusion edge, the formation of which involves etching the dummy gate stack 30, the multilayer stack 22', and the substrate strip 20'. The corresponding process is... Figure 39 The process flow shown in the diagram is illustrated as process 220. Figures 12A to 17P The detailed process of forming the fin isolation region 112 by cutting the virtual gate stack 30 is illustrated.

[0098] Figures 12A to 17P The illustration depicts a fin isolation region 112 formed according to a partial embodiment (using a continuous polysilicon process on a diffusion edge). In the following figures, figures with the letter A following the corresponding figure number are from... Figure 11 The image was obtained by Y-cutting (along the Y direction), while the image with the letter B after the corresponding figure number is obtained from... Figure 11 Obtained by X-cutting (along the X direction).

[0099] Figure 12A as well as Figure 12B It is illustrated Figure 10C The structures in the diagram are obtained from cross-sections cut by Y and X, respectively. Figure 12A as well as Figure 12B Also corresponding to Figure 10A as well as Figure 10B .therefore, Figure 12A The multilayer stack 22' and the virtual gate stack 30 on the multilayer stack 22' are illustrated. Figure 12B The source / drain region 48, the multilayer stack 22', the inner spacer 44, and the dummy gate stack 30 are illustrated.

[0100] Reference Figure 12A as well as Figure 12B A hard photomask 116 is formed. The hard photomask 116 may contain a dielectric material such as silicon nitride (SiN), silicon, or multiple layers thereof. A patterned etched photomask 117 (e.g., a three-layer photoresist) is formed over the hard photomask 116. Next, as... Figures 13A to 14B As shown, a hard photomask 116 is etched to form an opening 118, through which the virtual gate electrodes of the virtual gate stack 30 are exposed. Then, the lower virtual gate electrodes of the virtual gate stack 30 are etched using the hard photomask 116 until the virtual gate dielectric 32 is exposed, as shown. Figure 15A as well as Figure 15B As shown. The etching is anisotropic, ensuring that the edge of the dummy gate electrode facing the opening 118 is vertical and straight. In the etching process, the dummy gate dielectric 32 can be used as an etch stop layer.

[0101] Then, for example, the dummy gate dielectric 32 is removed by an isotropic etching process, thereby exposing the multilayer stack 22'. The final structure is as follows: Figure 16A as well as Figure 16B As shown. Next, an etching process is performed to remove the exposed multilayer stack 22', and then the underlying semiconductor material (e.g., substrate strip 20') is further etched. Thus, openings 120 are formed between adjacent shallow trench isolation regions 26, as... Figure 17A as well as Figure 17BAs shown. The opening 120 may extend to a level below the bottom surface of the shallow trench isolation region 26 to reduce leakage. In some embodiments, the opening 120 may extend into a region of the substrate 20 containing well regions containing n-type and / or p-type dopants.

[0102] Figures 17C to 17E An embodiment of a method for forming a buffer layer 300 within an opening 118 is illustrated to mitigate induced charges in wells within the substrate 20 due to the fixed charge of the insulating material, without reducing the width W1 of the opening 118, for example, without reducing the critical dimension of the opening 118. The wells within the substrate 20 are n-type or p-type doped regions that may surround the base and sidewalls of the opening 118. To avoid narrowing the width W1 of the opening 118, refer to... Figures 17C to 17E The described method and structure employ a bottom-up deposition approach, including a suppression treatment (passivation) in which the amount of material forming a buffer layer 300 at the base of the opening 118 is greater than the amount of material forming a buffer layer 300 at the top of the opening 118. This reduces the incidence of pinching of the opening 118.

[0103] Figure 17C The illustration depicts a suppression treatment 301, which can be a stage in a periodic suppression and deposition process, collectively providing a dense, thick buffer layer 300 at the base of the opening 118 (e.g., Figure 17D As shown), the growth of the buffer layer 300 in the upper portion 302 of the opening 118 is restricted. In some embodiments, the suppression treatment 301 may include at least one passivation treatment or heat treatment applied to the upper portion 302 of the opening 118. In some embodiments, when the suppression treatment 301 is a heat treatment, the heat treatment may be carried out at a temperature of about 600˚C in an inert gas atmosphere including hydrogen, helium, nitrogen, or combinations thereof, wherein the heat treatment includes a pressure of 10 Torr to 5 atmospheres (ATM). In some embodiments, when the suppression treatment 301 is a plasma treatment, the plasma treatment may include a plasma of argon, helium, hydrogen, or combinations thereof. In some embodiments, the temperature of the plasma treatment is 300˚C to 500˚C. In some embodiments, the plasma treatment includes a pressure of 10 Torr to 5 atmospheres (ATM). The plasma process for the suppression treatment 301 may be in-situ and / or non-in-situ. In-situ processes can use the same tools for suppression treatment 301 as a subsequent deposition step using plasma-enhanced chemical vapor deposition (PECVD) and / or plasma-enhanced atomic layer deposition. Off-situ processes use different tools for suppression treatment 301 as a subsequent deposition step using plasma-enhanced chemical vapor deposition and / or plasma-enhanced atomic layer deposition.

[0104] The process conditions for the suppression treatment 301 are selected to ensure that only the upper portion 302 of the opening 118 is treated. For example, the suppression treatment 301 may be applied only to the upper half of the depth of the opening 118. In some embodiments, the diffusion path of the deposited material for the suppression treatment can be limited by controlling the pressure of the suppression treatment 301 within the range of 10 Torr to 5 Atmospheric Pressures (ATM). For example, the process conditions for the suppression treatment 301 are selected to control the diffusion path of the gaseous or plasma material to treat only the upper portion 302 of the opening 118. For example, the diffusion path of the gaseous or plasma material used for the suppression treatment can be controlled so that the suppression treatment can be limited to the range of 5 nm to 5 µm. In some embodiments, the gaseous or plasma material reacts with the sidewalls of the opening 118 (e.g., the interlayer dielectric layer 52) and removes hydroxyl groups (OH), thereby inhibiting the deposition of dielectric material (e.g., the material of the buffer layer 300) onto the sidewalls of the opening 118. After suppression treatment 301, the exposed sidewalls through the opening 118 of the interlayer dielectric layer 52 have a high concentration of silicon-hydrogen (Si-H) bonds, silicon-oxygen (Si-O) bonds and disilicide (Si-Si) bonds after the removal of hydroxyl (-OH) groups.

[0105] Figure 17D An embodiment of the deposition step is illustrated, which may be a stage of cyclic suppression and deposition steps, which together provide a dense, thick buffer layer 300 at the base of the opening 118 while restricting the growth of the buffer layer 300 at the upper portion 302 of the opening 118. In some embodiments, forming the buffer layer 300 includes forming a non-conformal material layer, such as Si3N4, having a lower fixed charge concentration than silicon nitride. The non-conformal material layer has a first portion passivated by at least one passivation treatment located on the upper portion 302 of the opening 118, and a second portion extending to the lower portion 303 of the opening 118, which includes the base of the opening 118. In some embodiments, the thickness of the first portion of the non-conformal material layer providing the buffer layer 300 in the upper portion 302 of the opening 118 is less than the thickness of the second portion of the non-conformal material layer providing the buffer layer 300 in the lower portion 303 of the opening 118. Compared to the thickness of the buffer layer 300 in the upper portion 302 of the opening 118, the buffer layer 300 in the lower portion 303 of the opening 118 is thicker, and the gap with a high fixed charge level is filled with a dielectric material (such as...). Figure 17E A larger amount of dielectric film with a lower fixed charge level is provided between the doped well region (e.g., n-type and / or p-type doped well) present in the substrate 20 and the opening 118. The smaller thickness of the buffer layer 300 in the upper portion 302 of the opening 118 does not significantly reduce the width W1 of the opening 118, and therefore does not limit the dielectric filling deposition process (e.g., using an insulating material to fill the opening 118) Figure 17E(As shown). A low fixed charge level dielectric is a material used as an insulator with a very small amount of trapped charge (fixed charge) within its structure. By minimizing the fixed charge, low fixed charge level dielectrics can minimize unwanted electrical effects, such as leakage current. Examples of low fixed charge level dielectrics for buffer layer 300 may include silicon oxide (SiO2), silicon carbide (SiCO), silicon carbonitride (SiCN), and / or silicon carbonoxynitride (SiCON). An example of a filled dielectric with a high fixed charge level is silicon nitride (SiN).

[0106] The buffer layer 300 can be deposited using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), or a combination thereof. The inhibition treatment 301 reduces the concentration of hydroxyl (-OH) groups in the upper portion 302 of the opening 118, thereby reducing the reactivity of the sidewalls of the opening 118 to the deposition of the buffer layer 300 in the upper portion of the opening 118. This reduced reactivity results in a thinner buffer layer 300 deposited in the upper portion 302 of the opening 118 than the thinner buffer layer 300 deposited in the lower portion 303 of the opening 118. The lower portion 303 of the opening 118 is more reactive with the deposited material, and because the diffusion path of the inhibition treatment 301 is shorter, the inhibition treatment 301 is prevented from reaching the lower portion 303 of the opening 118. In some embodiments, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 in the upper portion 302 of the opening 118 and the second portion of the non-conformal material layer of the buffer layer 300 in the lower portion 303 of the opening 118 ranges from 2 nm to 10 nm. In one embodiment, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 in the upper portion 302 of the opening 118 and the second portion of the non-conformal material layer of the buffer layer 300 in the lower portion 303 of the opening 118 can be from 2 nm to 5 nm. In some embodiments, the difference in thickness of the buffer layer 300 from the upper portion 302 of the opening 118 to the lower portion 303 of the opening 118 can be gradual.

[0107] It is worth noting that, Figure 17C The suppression steps shown and Figure 17D The deposition steps shown are repeatable cyclic stages to provide bottom-up filling of opening 118 using a non-conformal material layer with a lower fixed charge concentration than silicon nitride. For example, Figure 17C The inhibition steps described in the text and Figure 17D The deposition steps described herein can be repeated 2 to 100 times. However, the number of times the inhibition and deposition steps are repeated can be arbitrary to provide an appropriate amount of material for the buffer layer 300 at the base of the opening 118.

[0108] Figure 17EAn embodiment is illustrated in which a fill dielectric 305 is deposited on a non-conformal material layer providing a buffer layer 300. The fill dielectric 305 may be composed of an etch-resistant material. For example, the fill dielectric 305 may be composed of silicon nitride (e.g., Si3N4). The fill dielectric 305 composed of silicon nitride may be a high fixed charge level isolator (dielectric material). The fill dielectric 305 may be deposited using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), and combinations thereof. Notably, in some embodiments, the fill dielectric 305 is located directly on top of the buffer layer 300 and completely fills the opening 118.

[0109] Figures 17A to 17E An embodiment is illustrated where openings 118 and 120 are filled to form a continuous polysilicon isolation region 112 on the diffusion edge. A planarization process, such as chemical mechanical polishing (CMP), can then be performed to form the fin isolation region 112, which is a continuous polysilicon isolation region on the diffusion edge, also in… Figure 11 As shown in the image.

[0110] Figure 17F Another implementation is illustrated, in which adjustments can be made. Figure 17C The suppression steps shown are used to adjust the thickness of the buffer layer 300 on the sidewalls and base of the opening 118. For example, the thickness can be increased. Figure 17C The pressure and / or time period of the inhibition step shown are used to increase the removal of hydroxyl (-OH) from the upper portion 302 of the opening 118. By increasing the intensity of the inhibition step, a smaller degree of buffer layer 300 can be deposited in the upper portion 302 of the opening 118. Figure 17F In the illustrated embodiment, the buffer layer 300 is not present in the upper portion 302 of the opening 118, but is entirely present in the lower portion 303 of the opening 118, which includes the base. In some embodiments, the top surface of the buffer layer 300 is lower than the top surface of the source / drain 48.

[0111] Figures 17G to 17I Another embodiment of the method of forming a buffer layer 300 within the opening 118 is illustrated to mitigate the induced charge caused by the fixed charge of the insulating material in the well present in the substrate 20, without reducing the width W1 of the opening 118, for example, without reducing the critical dimension (CD) of the opening 118. To avoid narrowing the width W1 of the opening 118, refer to... Figures 17G to 17I The method and structure described herein employ a bottom-up deposition method, comprising a cyclic deposition step and a groove etching step, wherein the amount of material of the buffer layer 300 formed at the base of the opening 118 is greater than the amount of material of the buffer layer 300 formed at the top of the opening 118. Figures 17G to 17IThe method shown illustrates a cyclic deposition, which can be conformal or oriented, and removes the buffer layer in situ from the top and sidewalls of the opening 118. Figures 17G to 17I The method shown also reduces the incidence of pinch-off at opening 118.

[0112] Figure 17G An embodiment of a buffer layer 300 with a low fixed charge dielectric formed within an opening 118 is illustrated. For example, in some embodiments, the buffer layer 300 has a lower fixed charge concentration than silicon nitride. In some embodiments, the buffer layer 300 may be composed of silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonitride (SiCON), or combinations thereof.

[0113] The buffer layer 300 can be deposited onto the opening 118 using either directional deposition or conformal deposition. In some embodiments, directional deposition forms a buffer layer material of greater thickness at the base of the opening 118 and on the upper surface (referred to as the horizontally oriented surface) of the interlayer dielectric (ILD) layer 52 adjacent to the opening 118. The thickness of the buffer layer 300 material deposited on the sidewalls of the opening 118 using directional deposition is less than the thickness of the buffer layer 300 located at the base of the opening 118. Compared to directional deposition, conformal deposition deposits buffer layer 300 material of substantially the same thickness on both the sidewalls and the base of the opening 118.

[0114] The buffer layer 300 can be deposited onto the opening 118 using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), or a combination thereof. In some embodiments, to adjust the deposition process to provide directional deposition of the buffer layer 300, the deposition process pressure can be set to provide a low pressure of 1 Torr or lower.

[0115] Figure 17HAn embodiment of etching a buffer layer 300 to produce a non-conformal thickness is illustrated, wherein the non-conformal thickness of the buffer layer 300 includes a first portion in the upper portion 302 of the opening 118, the thickness of which is less than a second portion of the buffer layer 300 in the lower portion 303 of the opening 118, which includes the base of the opening 118. The etching process can be gas etching or plasma etching. The composition of the etchant used to etch the buffer layer 300 can be a fluorine-containing composition, such as hydrofluoric acid etchant (HF). The etching process conditions can be selected such that the amount of material removed by the etchant from the upper portion 302 of the opening 118 is greater than the amount of material removed from the lower portion 303 of the opening 118. For example, the non-conformal characteristics of the etch buffer layer 300 can be included in the thicker portion of the material of the buffer layer 300 at the base of the opening 118, and the maximum sidewall thickness of the etch buffer layer 300 towards the base of the opening 118. The sidewall thickness of the buffer layer 300 can decrease from the base of the opening 118 towards the upper surface of the opening 118. The thickness of the buffer layer 300 can be varied gradually.

[0116] For example, when the etching process is plasma etching, the etching conditions providing the non-conformal thickness of the buffer layer 300 may include a pressure range of 10 Torr to 30 Torr, a temperature range of 300 to 500 degrees Celsius, and a plasma with a large radical to ion ratio. In some embodiments, to enable the plasma etching to remove more material of the buffer layer 300 from the upper portion 302 of the opening 118, but not (or significantly remove) material of the buffer layer 300 from the lower portion 303 of the opening 118, the plasma can be adjusted to provide a greater radical concentration than that of ions. The diffusion path of ions is greater than that of radicals. By minimizing the ion concentration, the diffusion path of the etchant can be limited. In some embodiments, the radical to ion ratio of the plasma etchant can range from 1000:1 to 100000:1.

[0117] In some embodiments, the etching process reduces the thickness of the buffer layer 300 in the upper portion 302 of the opening 118 to less than the thickness of the buffer layer 300 in the lower portion 303 of the opening 118. In some embodiments, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 in the upper portion 302 of the opening 118 and the second portion of the non-conformal layer of the buffer layer 300 in the lower portion 303 of the opening 118 ranges from 2 nm to 10 nm. In one embodiment, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 in the upper portion 302 of the opening 118 and the second portion of the non-conformal layer of the buffer layer 300 in the lower portion 303 of the opening 118 can be from 2 nm to 5 nm.

[0118] It is worth noting that, Figure 17G The deposition steps shown and Figure 17IThe etching steps shown are repeatable cyclic stages to provide a bottom-up filled non-conformal material layer with a lower fixed charge concentration than silicon nitride. For example, Figure 17G The deposition steps illustrated in the figure and Figure 17H The etching cycle illustrated can be repeated 2 to 100 times. However, the deposition and etching cycles can be repeated any number of times to provide an appropriate amount of material for the buffer layer 300 at the base of the opening 118.

[0119] Figure 17I An embodiment is illustrated in which a fill dielectric 305 is deposited on a non-conformal material layer providing a buffer layer 300. The fill dielectric 305 may be composed of an etch-resistant material. For example, the fill dielectric 305 may be composed of silicon nitride (e.g., Si3N4). The fill dielectric 305 composed of silicon nitride may be a high fixed charge level isolator (dielectric material). The fill dielectric 305 may be deposited using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), and combinations thereof. Notably, in some embodiments, the fill dielectric 305 is located directly on top of the buffer layer 300 and completely fills the opening 118.

[0120] Figures 17G to 17I An embodiment is illustrated where openings 118 and 120 are filled to form a fin isolation region 112 (also referred to as a continuous polysilicon region 112 on the diffusion edge). A planarization process, such as a chemical mechanical polishing (CMP) process, can then be performed to form the fin isolation region, which is the fin isolation region 112 (also referred to as a continuous polysilicon region 112 on the diffusion edge), which also... Figure 11 As shown in the image.

[0121] Figure 17J Another embodiment of this disclosure is illustrated, which uses reference to the above description. Figure 17G The deposition steps described herein are combined with references similar to those in the text. Figure 17H The etching process described herein involves an etching step to form a buffer layer 300, wherein the etching process is adjusted to more aggressively remove material from the upper portion 302 of the opening 118. Figure 17J In this process, the buffer layer 300 has been removed from the entire upper portion 302 of the opening 118. For example, the etching time, etching temperature, or pressure of the etching process can be adjusted to increase the corrosiveness of the etchant in removing material.

[0122] Figures 17K to 17M Partial embodiments are illustrated, wherein the buffer layer 300 is fabricated using a directional deposition process (refer to the above description). Figure 17G ) and etching process (refer to the above) Figure 17HThe combination of these processes forms a buffer layer 300. Compared to conformal deposition, directional deposition deposits a larger amount (e.g., a thicker thickness) of material in the base of the lower part 303 of the opening 118.

[0123] Figure 17K An embodiment of the buffer layer 300 is illustrated, which is described above. Figure 17G The directional deposition process and references described above Figure 17H The combination of etching processes described herein is used to form the process. Figure 17K The directional deposition process shown for forming the buffer layer 300 produces a thicker buffer layer 300 in the lower part 303 of the opening 118 compared to the thickness of the buffer layer 300 in the upper part 302 of the opening 118. The buffer layer 300 has a flat upper surface at the base of the lower part 303 of the opening 118. A flat upper surface can be formed by adjusting the deposition conditions of the directional deposition process for forming the buffer layer 300.

[0124] Figure 17L An embodiment of the buffer layer 300 is illustrated, which is described above. Figure 17G The directional deposition process and references described above Figure 17H The combination of etching processes described herein is used to form the process. Figure 17K The directional deposition process shown for forming the buffer layer 300 produces a thicker buffer layer 300 in the lower part 303 of the opening 118 compared to the thickness of the buffer layer 300 in the upper part 302 of the opening 118. The buffer layer 300 has a raised upper surface at the base of the lower part 303 of the opening 118. The raised upper surface can be formed by adjusting the deposition conditions of the directional deposition process for forming the buffer layer 300.

[0125] Figure 17M An embodiment of the buffer layer 300 is illustrated, which is described above. Figure 17G The directional deposition process described herein and the reference as described above Figure 17H The combination of etching processes described herein is used to form the process. Figure 17M The directional deposition process shown for forming the buffer layer 300 produces a thicker buffer layer 300 in the lower part 303 of the opening 118 compared to the thickness of the buffer layer 300 in the upper part 302 of the opening 118. The buffer layer 300 has a recessed upper surface at the base of the lower part 303 of the opening 118. The recessed upper surface can be formed by adjusting the deposition conditions of the directional deposition process for forming the buffer layer 300.

[0126] Figures 17N to 17P Partial embodiments are illustrated, wherein the buffer layer 300 is deposited via a directional deposition process (refer to the above description). Figure 17G) and more aggressive etching processes (see above) Figure 17J It is formed by the combination of ) . Figure 17N The diagram illustrates the direct deposition step (refer to the description) Figure 17K ) and erosive etching process (refer to the above) Figure 17J The combined buffer layer 300 is formed. Figure 17N The buffer layer shown has a buffer layer 300 that has been removed from the entire upper portion 302 of the opening 118, and includes a thick portion of the buffer layer 300 in the lower portion 303 of the opening 118, which has a flat upper surface.

[0127] Figure 17O The diagram illustrates the direct deposition step (refer to the description) Figure 17L ) and erosive etching process (refer to the above) Figure 17J The combined buffer layer 300 is formed. Figure 17O The buffer layer shown has a buffer layer 300 that has been removed from the entire upper portion 302 of the opening 118, and includes a thick portion of the buffer layer 300 in the lower portion 303 of the opening 118, which has a raised upper surface.

[0128] Figure 17P The diagram illustrates the direct deposition step (refer to the description) Figure 17M ) and erosive etching process (refer to the above) Figure 17J The combined buffer layer 300 is formed. Figure 17P The buffer layer shown has a buffer layer 300 that has been removed from the entire upper portion 302 of the opening 118, and includes a thick portion of the buffer layer 300 in the lower portion 303 of the opening 118, which has a concave upper surface.

[0129] Reference Figure 18A as well as Figure 18B The dummy gate electrode 34 and dummy gate dielectric 32 (and hard photomask 36, if remaining) are removed in one or more etching processes to form the recess 58. Figure 39 As shown, the corresponding process is illustrated as process 222 in process flow 200. According to a partial embodiment, the dummy gate electrode 34 and dummy gate dielectric 32 are removed by an anisotropic dry etching process. For example, a reactive gas can be used to perform the etching process, selectively etching the dummy gate electrode 34 and dummy gate dielectric 32 at a faster rate than the interlayer dielectric (ILD) 52. Each recess 58 exposes and / or covers portions of the multilayer stack 22' containing future channel regions in the subsequently completed transistor.

[0130] Then the sacrificial layer 22A is removed to extend the groove 58 between the nanostructures 22B. For example... Figure 39As shown, the corresponding process is illustrated as process 224 in process flow 200. The sacrificial layer 22A can be removed by performing an isotropic etching process (e.g., a wet etching process using an etchant selective for the material of the sacrificial layer 22A), while the nanostructure 22B, substrate 20, and shallow trench isolation (STI) region 26 remain relatively unetched compared to the sacrificial layer 22A. According to some embodiments, the sacrificial layer 22A comprises, for example, SiGe, and the nanostructure 22B comprises, for example, Si or SiC. The sacrificial layer 22A can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0131] Reference Figure 19A as well as Figure 19B This forms a gate dielectric 62 and a gate electrode 68, thereby forming an alternative gate stack 70. (Example) Figure 39 As shown, the corresponding process is illustrated as process 226 in process flow 200. According to some embodiments, each gate dielectric 62 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer may be formed of or comprise silicon oxide, which may be deposited by conformal deposition processes (e.g., atomic layer deposition (ALD) or chemical vapor deposition (CVD)) or by oxidation processes. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, the high-k dielectric layer may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

[0132] A gate electrode 68 is also formed. During formation, a conductive layer is first formed on the high-k dielectric layer, filling the remaining portion of the trench 58. The gate electrode 68 may comprise a metallic material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, the gate electrode 68 may comprise any number of layers, any number of work function layers, and possible filler materials. The gate dielectric 62 and the gate electrode 68 also fill the space between adjacent nanostructures 22B and the space between the base of the nanostructure 22B and the underlying substrate strip 20'. After filling the trench 58, a planarization process (e.g., CMP or mechanical polishing) is performed to remove excess material from the gate dielectric and gate electrode 68 located on the top surface of the interlayer dielectric (ILD) 52. The gate electrode 68 and the gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting transistor.

[0133] After forming the gate stack 70, a diced metal gate (CMG) region 110 can be formed, such as... Figures 20 to 32 As shown. Figure 20 A top view of the diced metal gate (CMG) region 110 is shown, which separates / divides the replacement (metal) gate stack 70 into shorter portions. Figure 39As shown, the corresponding process is illustrated as process 228 in process flow 200. The dicing of the metal gate (CMG) isolation region 110 is also referred to as gate isolation region 110. For example... Figure 23 As shown, according to a partial embodiment, the cut metal gate (CMG) isolation region 110 is formed by cutting the alternative gate stack 70.

[0134] Detailed process for forming the diced metal gate (CMG) isolation region 110 can be found from [link to relevant documentation]. Figures 21 to 32 The process shown is implemented as described. Figure 22 A cross-sectional view of the intermediate structure is illustrated, in which a gate stack 70 has been formed and includes a gate dielectric 62 and a gate electrode 68, while a diced metal gate (CMG) isolation region 110 has not yet been formed. According to some embodiments, a hard photomask layer 88 is deposited, and the hard photomask layer 88 may comprise a multilayer structure with multiple layers. According to some embodiments, the hard photomask layer 88 includes a silicon nitride layer 88A, a silicon layer 88B, and a silicon nitride layer 88C. According to an alternative embodiment, a single-layer hard photomask 88 is used, which may be formed of or comprise silicon nitride.

[0135] like Figure 23 As shown, an etched photomask 90 is then formed. The etched photomask 90 may also have a single-layer structure (which may contain photoresist) or a two-layer structure containing a base anti-reflective coating (BARC) and photoresist. Alternatively, the etched photomask 90 may have three layers, which may include a bottom layer, an intermediate layer above the bottom layer, and a top layer, which may be a patterned photoresist. Trench 92 is formed in the etched photomask 90.

[0136] Next, an etch mask 90 is used to etch the mask layer 88, extending the trench 92 into the hard mask layer 88. The etching can be anisotropic. According to some embodiments, the trench 92 extends to the top surface of the hard mask. After the trench 92 is formed in the hard mask layer 88, the etch mask 90 can be removed.

[0137] Next, as Figure 23 As shown, the alternative gate stack 70 is etched. The etching of the alternative gate stack 70 is anisotropic. According to one embodiment, etching is performed until the shallow trench isolation (STI) region 26 is exposed. The trench 92 may or may not extend into the shallow trench isolation (STI) region 26. After the etching process, the hard photomask layer 88 may or may not be removed. Thus, the gate stack 70 is divided into gate stacks 70A and 70B.

[0138] Figures 24 to 32An embodiment of a method for forming a buffer layer 300 within a trench 92 to form a diced metal gate (CMG) isolation region 110 is illustrated. Similar to the buffer layer 300 used in the fin isolation region 112 (also referred to as the CPODE isolation region), the buffer layer 300 used in the diced metal gate (CMG) isolation region 110 can mitigate the induced charge caused by the fixed charge of the isolation material in the well present in the substrate 20 without reducing the opening width W2 of the trench 92, for example, without narrowing the critical dimension (CD) of the opening of the trench 92. To avoid narrowing the opening width W2 of the trench 92, refer to... Figures 24 to 32 The described method and structure employ a bottom-up deposition approach, where the amount of material forming the buffer layer 300 at the base of the trench 92 is greater than the amount of material forming the buffer layer 300 at the top of the trench 92. This reduces the incidence of pinch-off at the opening of the trench 92.

[0139] Figure 24 The formation of a buffer layer 300 is illustrated, which is formed by a series of cyclic inhibition and deposition steps that together provide a dense, thick buffer layer 300 at the base of the trench 92 while limiting the growth of the buffer layer 300 at the upper part 302 of the trench 92. Figure 24 One embodiment is illustrated, wherein a seam exists in the lower portion 303 of the groove 92. Figure 24 The buffer layer 300 shown for cutting the metal gate (CMG) isolation region 110 is the same as the one referenced above. Figure 17C and Figure 17D The buffer layer 300 described above for the fin isolation region 112 (continuous polysilicon (CPODE) region on the diffusion edge) is similar. Therefore, the above refers to... Figure 17C and Figure 17D The description of the buffer layer 300 is applicable to Figure 24 The description of the buffer layer 300 shown includes elements with the same reference number that can share a detailed description.

[0140] For example, Figure 24The buffer layer 300 shown may be formed after a suppression treatment is applied to the trench 92, the suppression treatment comprising applying one or more passivation treatments or heat treatments to the upper portion 302 of the trench 92. In some embodiments, when the suppression treatment 301 is a heat treatment, the heat treatment may be carried out at a temperature above 600˚C in an inert gas atmosphere comprising hydrogen, helium, nitrogen, or combinations thereof, wherein the heat treatment comprises a pressure ranging from 10 Torr to 5 Atm (ATM). In some embodiments, when the suppression treatment 301 is a plasma treatment, the plasma treatment may comprise a plasma of argon, helium, hydrogen, or combinations thereof, wherein the plasma treatment temperature is from 300˚C to 500˚C, and wherein the plasma treatment comprises a pressure ranging from 10 Torr to 5 Atm (ATM). See embodiments similar to those described above. Figure 17C You can choose Figure 24 The process conditions shown for forming the buffer layer 300 are such that only the upper portion 302 of the trench 92 is processed. After the suppression treatment, the sidewalls of the trench 92 exposed through the interlayer dielectric (ILD) 52 have a high concentration of silicon-hydrogen (Si-H), silicon-oxygen (Si-O), and silicon-silicon (Si-Si) bonds after the removal of hydroxyl groups (-OH), which will suppress the formation of dielectric material attempting to form directly thereon. The suppression treatment is a passivation treatment applied to the upper portion 302 of the trench 92.

[0141] After a suppression treatment (passivation treatment), a non-conformal material layer with a lower fixed charge concentration than silicon nitride is formed within the trench 92 as a buffer layer 300. For example, the non-conformal material layer may be composed of silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonitride (SiCON), or a combination thereof. The non-conformal material layer has a first portion located on the upper portion 302 of the trench 92, which is passivated by at least one passivation treatment (also called a suppression treatment), and a second portion located in the lower portion 303 of the trench 92, extending to the base of the trench. The thickness of the first portion of the non-conformal material layer of the buffer layer 300 located in the upper portion 302 of the trench 92 is less than the thickness of the second portion of the non-conformal material layer of the buffer layer 300 located in the lower portion 303 of the trench 92. For example, the thickness difference between the first portion of the non-conformal material layer of the buffer layer 300 located in the upper part 302 of the trench 92 and the second portion of the non-conformal material layer of the buffer layer 300 located in the lower part 303 of the trench 92 is 2 nm to 10 nm.

[0142] Refer to implementation methods similar to those described above. Figure 17C You can choose Figure 24The process conditions shown for forming the buffer layer 300 allow for a suppression step to be performed only on the upper portion 302 of the trench 92. After the suppression step, the buffer layer 300 can be deposited using plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and / or plasma-assisted atomic layer deposition (PEALD).

[0143] It is worth noting that, Figure 24 The suppression steps shown and Figure 24 The deposition steps shown are repeatable cyclic stages to provide bottom-up filling of a non-conformal material layer with a lower fixed charge concentration than silicon nitride. For example, Figure 24 The cycle of the inhibition and deposition steps shown can be repeated 2 to 100 times. However, the cycle of the inhibition and deposition steps can be repeated any number of times to provide an appropriate amount of material for the buffer layer 300 at the base of the trench 92.

[0144] Please continue reading. Figure 24 After the buffer layer 300 is formed, a filler dielectric 305 can be deposited on the buffer layer 300. Figure 24 The filled dielectric 305 shown is the same as the reference mentioned above. Figure 17I The filling dielectric 305 is similar. Therefore, Figure 17I The description of the filled dielectric 305 shown is applicable to Figure 24 Description of the filling dielectric 305 of the shown filling trench 92. For example, the filling dielectric 305 may be composed of silicon nitride.

[0145] After depositing the fill dielectric 305, a planarization process is performed, such as a chemical mechanical polishing (CMP) process or a mechanical polishing process. The planarization process can be stopped on the top surface of the gate stack 70. Figure 24 As shown, the remaining portion of the buffer layer 300 and the filling dielectric 305 are collectively referred to below as the CNC gate (CMG) isolation region 110. Due to the separation of the CNC gate (CMG) isolation region 110 from the fin isolation region 112, there may be some regions that separate the CNC gate (CMG) isolation region 110 from its adjacent fin isolation region 112 (also referred to as the CPODE isolation region). The length of the CNC gate (CMG) isolation region 110 can be selected according to the circuit layout.

[0146] Figure 25 Another embodiment of the diced metal gate (CMG) isolation region 110 is illustrated, wherein the formation of the buffer layer 300 comprises a series of cyclic suppression and deposition steps, which together provide a dense, thick buffer layer 300 at the base of the trench 92. Figure 25 In the embodiment shown, the suppression step is compared to Figure 24The embodiment shown is more radical. Because the upper part 302 of the trench 92 has a greater degree of passivation, therefore... Figure 25 In the embodiment shown, a buffer layer 300 will not be formed on the upper part 302 of the trench 92. (Refer to the above text) Figure 17F Further description Figure 25 The conditions for the suppression step of forming the buffer layer 300 are shown in the embodiment.

[0147] Figure 24 and Figure 25 The illustrated embodiment depicts a buffer layer geometry for the diced metal gate (CMG) isolation region 110, which can also be formed using a process sequence comprising depositing the buffer layer 300 using conformal or directional deposition processes (without a suppression step), followed by an etching step, wherein the etching step produces a non-conformal thickness of the buffer layer 300. More specifically, a method of forming a non-conformal thickness buffer layer 300 for the diced metal gate (CMG) isolation region 110 in the trench 92 using a cycle of deposition and etching steps can comprise forming a buffer layer 300 having a lower fixed charge concentration than silicon nitride, and etching the buffer layer 300 to produce a non-conformal thickness, wherein the non-conformal thickness of the buffer layer 300 includes a first portion in a first portion 302 of the trench 92, the thickness of which is less than the thickness of a second portion of the buffer layer 300 in a second portion 303 of the trench 92.

[0148] The above has been referred to Figure 17G Describes the formation Figure 24 and Figure 25 The deposition steps for the geometry of the buffer layer 300 shown above. Figure 17H Describes the formation Figure 24 The etching steps of the buffer layer 300 shown. Figure 25 As shown, the etching process of the etching step can be adjusted to remove the entire buffer layer 300 from the first portion 302 of the trench 92. In some embodiments, reference has been made above. Figure 17J Describes the formation Figure 25 The etching step of the buffer layer 300 shown. After a cycle of deposition and etching steps to form the buffer layer 300, the trench 92 can be filled with filling dielectric 305 and planarized.

[0149] Figures 26 to 28 Another embodiment of the diced metal gate (CMG) isolation region 110 is illustrated, including a buffer layer 300 with a non-conformal thickness, which provides a thick portion of dielectric material with a low fixed charge level at the base of the trench 92 without pinching off the upper portion 302 of the trench 92. Figures 26 to 28 In the illustrated embodiment, directional deposition is performed in conjunction with an extreme etching step to configure the geometry of the material of the buffer layer 300 at the base of the trench 92. For Figures 26 to 28 For each embodiment shown, the etching process has been referenced. Figure 17H It has been described.

[0150] For example, Figure 26 An embodiment of the buffer layer 300 is illustrated, showing that the buffer layer 300 in the lower part 303 of the trench 92 is thicker than the buffer layer 300 in the upper part 302. The buffer layer 300 has a flat upper surface at the base of the lower part 303 of the trench 92. (Refer to the above...) Figure 17K The flat upper surface can be formed by adjusting the deposition conditions of the directional deposition process used to form the buffer layer 300. The filler dielectric 305 is formed directly on top of the buffer layer 300.

[0151] Figure 27 An embodiment of the buffer layer 300 is illustrated, which is formed using a cycle of directional deposition and etching processes, thereby creating a greater thickness of the buffer layer 300 in the lower portion 303 of the trench 92. Figure 27 In the illustrated embodiment, the directional deposition process for forming the buffer layer 300 produces a buffer layer 300 with a greater thickness in the lower portion 303 of the trench 92 than the buffer layer 300 in the upper portion 302 of the trench 92. The buffer layer 300 has a raised upper surface at the base of the lower portion 303 of the trench 92. (Refer to the above...) Figure 17L The raised upper surface can be formed by adjusting the deposition conditions of the directional deposition process used to form the buffer layer 300. The filler dielectric 305 is formed directly on top of the buffer layer 300.

[0152] Figure 28 An embodiment of a buffer layer 300 for a diced metal gate (CMG) isolation region 110 is illustrated, wherein the buffer layer 300 is formed using a cycle of directional deposition and etching processes, thereby creating a greater buffer layer 300 thickness in the lower portion 303 of the trench 92. Figure 28 In the illustrated embodiment, the directional deposition process for forming the buffer layer 300 produces a buffer layer 300 with a greater thickness in the lower portion 303 of the trench 92 than the buffer layer 300 in the upper portion 302 of the trench 92. The buffer layer 300 has a recessed upper surface at the base of the lower portion 303 of the trench 92. (Refer to the above...) Figure 17M The recessed upper surface can be formed by adjusting the deposition conditions of the directional deposition process used to form the buffer layer 300. The filling dielectric 305 is formed directly on top of the buffer layer 300.

[0153] Figures 29 to 31Another embodiment of a diced metal gate (CMG) isolation region 110 is illustrated, comprising a buffer layer 300 having a thick portion of dielectric material with a low fixed charge level at the base of the trench 92 of the diced metal gate (CMG) isolation region 110. Figures 29 to 31 In the illustrated embodiment, the buffer layer 300 is formed through a cycle of deposition and etching steps, wherein the etch step is modified to remove the entire buffer layer 300 from the upper portion 302 of the trench 92, while the thicker portion of the buffer layer 300 remains at the base of the lower portion 303 of the trench 92. Figures 29 to 31 In the embodiment shown, the buffer layer 300 is deposited using a directional deposition process. (Refer to...) Figure 17J The etching process for removing the buffer layer 300 from the upper part 302 of the trench 92 is described.

[0154] Figure 29 An embodiment of the buffer layer 300 is illustrated, which is described above with reference to... Figure 26 The directional deposition process and as mentioned above Figure 17J The combination of the etching processes described above is used to form the process. Figure 29 The directional deposition process for forming the buffer layer 300 shown results in a greater thickness of the buffer layer 300 in the lower part 303 of the trench 92. The portion of the buffer layer 300 located at the base of the lower part 303 of the trench 118 has a flat upper surface. Figure 29 The buffer layer 300 shown has been removed from the entire upper portion 302 of the trench 92. The fill dielectric 305 is formed directly on top of the buffer layer 300.

[0155] Figure 30 The diagram illustrates the direct deposition process (see reference). Figure 27 The above) and the erosive etching process (refer to) Figure 17J The buffer layer 300 formed by the combination of the above) Figure 30 The buffer layer 300 shown has been removed from the entire upper portion 302 of the trench 92 of the cut metal gate (CMG) isolation region 110 and includes the thick portion of the buffer layer 300 in the lower portion 303 of the trench 92 having a raised upper surface. The fill dielectric 305 is formed directly on top of the buffer layer 300.

[0156] Figure 31 The buffer layer 300 of the diced metal gate (CMG) isolation region 110 is illustrated, which is referenced Figure 28 The described directional deposition steps and reference Figure 17J The aforementioned erosive etching process is combined to form the structure. Figure 31 The buffer layer shown has been removed from the entire upper portion 302 of the trench 92 and includes the thick portion of the buffer layer 300 in the lower portion 303 of the trench 92, which has a concave upper surface. The filling dielectric 305 is formed directly on top of the buffer layer 300.

[0157] Figure 32 An embodiment illustrating the application of a planarization process to the portion of the buffer layer 300 and the filling dielectric 305 extending outside the trench 92 of the diced metal gate (CMG) isolation region 110 is shown. The planarization process may include chemical mechanical polishing (CMP). It is noteworthy that, although... Figure 32 The illustration shows the target Figure 24 In the illustrated embodiment, the buffer layer 300 and the filling dielectric 305 undergo a planarization process, but Figure 32 The planarization process shown is also applicable to the reference. Figures 24 to 31 Any of the implementation methods described herein.

[0158] Figures 33 to 36 Another embodiment of how the buffer layer 300 is integrated into the trench 92 of the diced metal gate (CMG) isolation region 110 is illustrated. In the above embodiment, after the buffer layer 300 is formed, a fill dielectric 305 is deposited to fill the trench 92. In some embodiments, the fill dielectric 305 does not necessarily need to fill the entire trench. Figures 33 to 36 In the illustrated embodiment, after forming the filling dielectric 305, a low-k dielectric filler material 306 can be deposited to fill the trench 92. The integration of the low-k dielectric filler material 306 can reduce the incidence of parasitic capacitance in the region surrounding the isolation structure. In this embodiment, the filling dielectric 305 can have a liner geometry, while the low-k dielectric filler material 306 can be the filler material filling the remaining openings of the trench 92. In some embodiments, the low-k dielectric filler material 306 is composed of silicon oxide (SiO2). However, in other embodiments, the low-k dielectric filler material 306 can be composed of any material having a silicon oxide dielectric constant (e.g., about 4.0 or less) at room temperature. The low-k dielectric filler material 306 can be deposited by chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)) and / or atomic layer deposition (ALD) (e.g., plasma-enhanced atomic layer deposition (ALD)).

[0159] Figure 33 An embodiment of a low-k dielectric filler material 306 is illustrated, which is integrated onto a filler dielectric layer 305 that exists above a buffer layer 300, as shown in the above reference. Figure 24 The aforementioned deposition and etching cycle is formed. Figure 34 An embodiment of a low-k dielectric filler material 306 is illustrated, which is integrated onto a filler dielectric 305 located above a buffer layer 400, the buffer layer 400 being constructed using the above reference. Figure 25 Formed by the aforementioned deposition and etching cycles. Figure 34 In the embodiment shown, the buffer layer 300 is removed from the entire upper portion 302 of the trench 92. Figure 35 An embodiment of a low-k dielectric filler material 306 is illustrated, which is integrated onto a filler dielectric 305 located above a buffer layer 400, the buffer layer 400 being constructed using the above reference. Figure 26 The deposition and etching cycles described above are formed. Figure 35 The buffer layer shown has a thick portion of dielectric composition material with a low fixed charge level, and has a flat upper surface at the base of the trench 92. Figure 36 An embodiment of a low-k dielectric filler material 306 is illustrated, which is integrated onto a filler dielectric 305 located above a buffer layer 400, which is constructed using the above reference. Figure 29 The aforementioned deposition and etching cycle formed the buffer layer 300, which has been completely removed from the upper part 302 of the trench 92. Figure 36 The buffer layer 300 shown has a thick portion of dielectric composition material with a low fixed charge level, and has a flat upper surface at the base of the trench 92.

[0160] Although the low-k dielectric filler 306 is integrated into the isolation structure of the diced metal gate (CMG) isolation region 110, the low-k dielectric filler 306 is not limited to these embodiments. For example, the low-k dielectric filler 306 can also be used as a filler material on top of the filler dielectric 305 within the opening 118 of the fin isolation region 112 (using the CPODE process). It is worth noting that the low-k dielectric filler 306 can be integrated into any of the embodiments described herein, for example, referring to... Figure 17E , Figure 17F , Figures 17I to 17P and Figures 24 to 32 The implementation method described above.

[0161] exist Figure 36 After the process shown, proceed as follows Figure 37A , Figure 37B , Figure 38A , Figure 38B The remaining processes shown are used to complete the transistor fabrication.

[0162] Figure 37A It is illustrated Figure 21 The cross-section of the structure shown illustrates a cut metal gate (CMG) isolation region 110 formed to cut the long metal gate stack 70 into metal gate stacks (parts) 70A and 70B. Although the cut metal gate (CMG) isolation region 110 and... Figure 32The same applies, but any embodiment of the cut metal gate (CMG) isolation region 110 described herein is applicable, for example, with reference to Figures 24 to 36 The described implementation method. Next, as... Figure 37A and Figure 37B As shown, the gate stack 70 is recessed, thereby forming a groove directly above the gate stack 70 and between the opposite portion of the gate spacer 38 (occupied by the cut metal gate (CMG) isolation region 110). Each groove is filled with a gate photomask 74 containing one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), and then a planarization process is performed to remove excess dielectric material extending above the interlayer dielectric (ILD) 52.

[0163] like Figure 37A as well as Figure 37B As further shown, interlayer dielectric (ILD) 76 is deposited over interlayer dielectric (ILD) 52 and gate photomask 74. The corresponding process is as follows: Figure 39 The process flow 200 shown is illustrated as process 230. An etch stop layer (not shown) may or may not be deposited before forming the interlayer dielectric (ILD) 76. According to some embodiments, the interlayer dielectric (ILD) 76 is formed by flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. The interlayer dielectric (ILD) 76 is formed of a dielectric material, which may be selected from silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0164] At Figure 38A as well as Figure 38B In this process, interlayer dielectric (ILD) 76, interlayer dielectric (ILD) 52, contact etch stop layer (CESL) 50, and gate photomask 74 are etched to form grooves (occupied by contact plugs 80A and 80B), thereby exposing the surfaces of the source / drain regions 48 and / or the gate stack 70. The grooves can be formed by etching using anisotropic etching processes such as reactive ion etching (RIE), neutral beam etching (NBE), etc.

[0165] After the groove is formed, a silicide region 78 is formed above the source / drain region 48. The corresponding process is... Figure 39 The process flow 200 is illustrated as process 232. A contact plug 80B is then formed over the silicide region 78. Furthermore, a contact plug 80A (also referred to as a gate contact plug) is formed in a recess and is located above and in contact with the gate electrode 68. The corresponding process is described in... Figure 39 The process flow shown in 200 is illustrated as process 234. This results in transistors 82A and 82B. Although Figure 38B The illustration shows contact plugs 80A and 80B located in the same cross-section, but in various embodiments, contact plugs 80A and 80B may be formed in different cross-sections, thereby reducing the risk of short circuits between them.

[0166] The embodiments disclosed herein have several advantageous features. In the methods and structures disclosed herein, a bottom-up deposition technique is proposed to form a buffer layer 300 in the isolation region to prevent induced charges in the isolation structure. In some embodiments, the buffer layer 300 can be selectively deposited from the base without blocking the gap openings.

[0167] In one embodiment, a method of forming a semiconductor structure includes: etching at least one conductive structure to form an opening that divides the conductive structure into shorter portions; applying at least one passivation treatment to the upper portion of the opening; forming a nonconformal material layer having a first fixed charge concentration, wherein the nonconformal material layer has a first portion passivated by at least one passivation treatment located on the upper portion of the opening, and the nonconformal material layer has a second portion extending to the base of the opening, the first portion of the nonconformal material layer having a smaller thickness than the second portion of the nonconformal material layer; and depositing a filling dielectric having a second fixed charge concentration higher than the first fixed charge concentration on the nonconformal material layer.

[0168] In one embodiment, at least one conductive structure comprises a plurality of semiconductor regions. In one embodiment, at least one conductive structure comprises a gate structure present on a semiconductor region. In one embodiment, the nonconformal material layer comprises silicon oxide (SiO2), silicon oxynitride (SiON), or silicon oxycarbonitride (SiCON). In one embodiment, passivation is a heat treatment at a temperature above 600˚C in an inert gas atmosphere comprising hydrogen, helium, nitrogen, or combinations thereof, wherein the heat treatment comprises a pressure of 10 Torr to 5 atm (ATM). In one embodiment, passivation is a plasma treatment comprising a plasma comprising argon, helium, hydrogen, or combinations thereof, wherein the plasma treatment comprises a temperature of 300˚C to 500˚C, wherein the plasma treatment comprises a pressure of 10 Torr to 5 atm (ATM). In one embodiment, the thickness difference between a first portion of the nonconformal material layer and a second portion of the nonconformal material layer is 2 nm to 10 nm.

[0169] In one embodiment, a method of forming a semiconductor structure includes: etching at least one conductive structure to form an opening that divides the conductive structure into shorter portions; forming a buffer layer having a lower fixed charge concentration than silicon nitride; etching the buffer layer to produce a non-conformal thickness, wherein the non-conformal thickness of the buffer layer includes a first portion above the opening, the thickness of which is less than a second portion of the buffer layer at the base of the opening; and depositing a fill dielectric on the buffer layer having the non-conformal thickness. In one embodiment, the buffer layer comprises silicon oxide (SiO2), silicon oxynitride (SiON), or silicon carbon oxynitride (SiCON). In one embodiment, the etching comprises a fluorine-based etchant. In one embodiment, the etching comprises plasma etching, the plasma etching comprising a pressure of 10 Torr to 30 Torr, a temperature of 300˚C to 500˚C, and a plasma having a higher radical to ion ratio. In one embodiment, forming the buffer layer comprises directional deposition. In one embodiment, forming the buffer layer comprises conformal deposition. In one embodiment, the method further comprises forming a low-k dielectric filler on the fill dielectric, wherein the fill dielectric comprises silicon nitride.

[0170] In one embodiment, a semiconductor structure includes: at least one conductive feature; a trench extending through the conductive feature; and a trench filler comprising: a non-conformal material layer having a first fixed charge concentration lower than that of silicon nitride, wherein the non-conformal material layer has a first portion located above the trench and having a first thickness, and a second portion extending to the trench base and having a second thickness, wherein the second thickness is less than the first thickness; and a filling dielectric on the non-conformal material layer having a second fixed charge concentration higher than that of the first fixed charge concentration on the non-conformal material layer. In one embodiment, the at least one conductive feature is a gate structure. In one embodiment, the at least one conductive feature is a stack of nanosheets. In one embodiment, the non-conformal material layer comprises silicon oxide (SiO2), silicon oxynitride (SiON), or silicon oxycarbonitride (SiCON). In one embodiment, the thickness difference between the first thickness and the second thickness is 2 nm to 10 nm. In one embodiment, the filling dielectric comprises silicon nitride.

[0171] The numerous features of the embodiments or examples outlined above enable those skilled in the art to better understand the embodiments disclosed herein. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes or structures to achieve the same purpose and / or realize the same advantages of the embodiments or examples described herein. Those skilled in the art should also recognize that equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A method of forming a semiconductor structure, comprising: Include: Etch at least one conductive structure to form an opening that divides the conductive structure into a shorter portion; At least one passivation treatment is applied to the upper portion of the opening; A non-conformal material layer having a first fixed charge concentration is formed, wherein the non-conformal material layer has a first portion passivated by the at least one passivation treatment on the upper portion of the opening, and the non-conformal material layer has a second portion extending to a base of the opening, the first portion of the non-conformal material layer having a thickness smaller than that of the second portion of the non-conformal material layer; and A filler dielectric is deposited on the non-conformal material layer, the filler dielectric having a second fixed charge concentration higher than the first fixed charge concentration.

2. The method as described in claim 1, characterized in that, The at least one conductive structure contains multiple semiconductor regions.

3. The method as described in claim 1, characterized in that, The at least one conductive structure is contained in the gate structure on the semiconductor region.

4. The method as described in claim 1, characterized in that, The non-conformal material layer contains silicon oxide, silicon oxynitride, or silicon carbon oxynitride.

5. The method as described in claim 1, characterized in that, The passivation process is a heat treatment performed at a temperature above 600˚C in an inert gas atmosphere comprising hydrogen, helium, nitrogen, or a combination thereof, wherein the heat treatment comprises a pressure of 10 tor to 5 atmospheres.

6. The method as described in claim 1, characterized in that, The passivation process is a plasma process comprising a plasma including argon, helium, hydrogen, or a combination thereof, wherein the plasma process comprises a temperature of 300˚C to 500˚C, and wherein the plasma process comprises a pressure of 10 tor to 5 atmospheres.

7. The method as described in claim 1, characterized in that, The thickness difference between the first portion of the non-conformal material layer and the second portion of the non-conformal material layer is 2 nm to 10 nm.

8. A method for forming a semiconductor structure, characterized in that, Include: Etch at least one conductive structure to form an opening that divides the conductive structure into a shorter portion; A buffer layer with a fixed charge concentration lower than that of silicon nitride is formed; The buffer layer is etched to produce a non-conformal thickness, wherein the non-conformal thickness of the buffer layer includes a first portion in an upper portion of the opening, the first portion having a thickness smaller than a second portion of the buffer layer in a base portion of the opening; and A filler dielectric is deposited on the buffer layer having the non-conformal thickness.

9. The method as described in claim 8, characterized in that, A low-k dielectric filler is further formed on the filler dielectric, wherein the filler dielectric comprises silicon nitride.

10. A semiconductor structure, characterized in that, Include: At least one conductive feature; A trench extending through the conductive feature; and A trench filler comprising: A non-conformal material layer having a first fixed charge concentration, wherein the non-conformal material layer has a first portion located above a trench, the first portion having a first thickness, and the non-conformal material layer has a second portion extending through a base of the trench and having a second thickness, wherein the second thickness is less than the first thickness; and A filling dielectric having a second fixed charge concentration higher than the first fixed charge concentration on the non-conformal material layer.

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