Storage chip stacking interconnection method

Abstract

The invention belongs to the technical field of chips, and particularly relates to a storage chip stacking interconnection method. Adjusting the thickness of the wafer and the filling sheet, and respectively dividing the wafer and the filling sheet into a single independent storage chip and a single independent filling sheet; mounting a single storage chip on the pretreated glass substrate according to the design, and completing the stacking arrangement of multiple chips to form a storage chip stack body; mounting a single filling sheet to the top of the storage chip stack according to the design; leading out a signal pin of each memory chip in the memory chip stack through a metal wire, and connecting the signal pin to a preset bonding pad of the top filling sheet to obtain a composite structure; carrying out molding packaging on the composite structure to form a packaging body; manufacturing a rewiring layer on the surface of the ground packaging body, and manufacturing salient points; and stripping the pretreated glass substrate, wherein the residual structure is the required structure. According to the invention, the problems of signal delay, large packaging thickness and RDL alignment deviation are solved by combining the filling sheet bridging structure with the packaging material.

Description

Technical Field

[0001] This invention belongs to the field of chip technology, specifically to a method for stacking and interconnecting memory chips. Background Technology

[0002] With the increasing demands for bandwidth and size in memory chips from mobile terminals and high-performance computing, 3D packaging technology is facing severe technical bottlenecks. Current technologies mainly consist of two main approaches and their limitations: 1. Traditional wire bonding packaging technology: This technology usually adopts RDL First (Redistribution Layer First) or direct wire bonding to the substrate.

[0003] Its drawbacks are: (1) large signal delay: in order to connect multi-layer stacked chips, metal lines often need to cross a long distance to connect to the edge of the substrate, resulting in excessively long signal transmission paths, increased parasitic inductance and resistance, which seriously affects the high-frequency signal transmission rate and data access efficiency.

[0004] (2) Limited package thickness: In order to prevent short circuits in the metal wires, sufficient arc height must be reserved, which directly increases the thickness of the package in the Z-axis direction and cannot meet the design requirements of ultra-thin electronic products.

[0005] 2. Chip First (Chip-First Assembly) and Vertical Wire Bonding Post-Grinding Technology: To address the thickness issue, existing technologies attempt to first fix the chip, then perform vertical wire bonding or form pillars, mold it, and then expose the metal cross-section through grinding before finally fabricating the redistribution layer (RDL).

[0006] Its defects are: (1) Wire Sweep (gold wire offset) causes RDL alignment failure: During the molding process, the high viscosity of the encapsulating material fluid will generate a large shear force in the mold cavity. The thin metal wire is very easy to deform, bend or tilt under the impact of the material (i.e., gold wire offset phenomenon).

[0007] (2) Difficulty in identification: When performing RDL lithography, the equipment exposes based on the design coordinates (preset Pad position). Due to the gold line offset, the top position of the metal line is randomly offset, and the RDL line cannot be accurately connected to the metal line cross section, resulting in open circuit or poor contact, which greatly reduces the yield of finished products. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a method for stacking and interconnecting memory chips.

[0009] A method for interconnecting stacked memory chips includes the following steps: A temporary bonding layer is coated on the surface of a glass substrate to obtain a pretreated glass substrate. The thickness of the wafer and the filler wafer are adjusted by thinning process, and then the wafer and the filler wafer are divided into individual memory chips and individual filler wafers by chip cutting process. Individual memory chips are mounted onto a temporary bonding layer according to the design to complete the stacking arrangement of multiple chips and form a memory chip stack. Individual filler pieces are mounted on top of the memory chip stack according to the design; By using wire bonding technology, the signal pins of each memory chip in the memory chip stack are led out through metal wires and connected to the preset pads of the top filler layer to obtain a composite structure; For composite structure molding encapsulation, an encapsulation body is formed on a pretreated glass substrate; The package is ground, a redistribution layer is made on the surface of the ground package, and then bumps are made on the redistribution layer using a bumping process. After peeling off the pretreated glass substrate, the remaining structure is a structure containing one or more sets of memory chip stacked interconnects.

[0010] Furthermore, the temporary bonding layer includes a release layer and an adhesive layer.

[0011] Furthermore, during the grinding of the package, excess packaging material, the arc portion of the metal wires, and some filler sheets are removed from the top.

[0012] Furthermore, a redistribution layer is fabricated on the surface of the polished package, including the following steps: On the surface of the polished package, a redistribution layer is fabricated using the RDL process to redistribute the signals on the fill pads to the preset pin locations.

[0013] Furthermore, individual memory chips are mounted onto a temporary bonding layer according to the design to complete the stacking arrangement of multiple chips and form a memory chip stack, including the following steps: A stepped offset method is used for mounting. The first layer of memory chip is mounted on a temporary bonding layer. When subsequent memory chips are mounted on the lower layer, each layer is offset by the required distance along the long side of the lower layer to expose the pads of the lower memory chip. After mounting, a stack of memory chips is formed.

[0014] Furthermore, the individual filler wafers are mounted onto the top of the memory chip stack according to the design, including the following steps: A single filler pad is mounted on top of two sets of memory chip stacks, with each filler pad connecting the two sets of memory chip stacks.

[0015] Furthermore, when the remaining structure contains multiple sets of stacked interconnected memory chips, the remaining structure is cut to obtain a single independent finished chipset.

[0016] Furthermore, for the composite structure molding encapsulation, forming an encapsulation body on a pretreated glass substrate includes the following steps: The composite structure with wire bonding is molded, and the entire stack, filler sheets and metal wires are completely covered with encapsulation material to form an encapsulation on the pretreated glass substrate.

[0017] Preferably, the method for preparing the encapsulation material includes the following steps: By weight, 100 parts resin, 80-90 parts curing agent, 3-5 parts catalyst, 600-800 parts inorganic filler, and 5-6 parts other additives are added to a high-speed mixer and mixed at 500-1000 rpm for 5-10 minutes at room temperature until the powder is uniform, thus obtaining a mixed powder. The mixed powder is melted and extruded to obtain a compound product. After cooling, the compound product is pulverized to obtain an encapsulation material.

[0018] Preferably, the resin includes a biphenyl-type epoxy resin, the curing agent includes MHHPA and / or SMA; the catalyst includes zinc acetylacetonate; the inorganic filler includes spherical silica powder; and other additives include at least one of colorant, release agent, and accelerator, wherein the accelerator includes 2-ethyl-4-methylimidazole.

[0019] It should be noted that biphenyl-type epoxy resins, as matrix resins, have a crystalline biphenyl structure, which provides high modulus and low hygroscopicity; their low viscosity allows for a higher proportion of inorganic fillers.

[0020] Methylhexahydrophthalic anhydride (MHHPA) is used as a curing agent. Liquid anhydride helps reduce system viscosity, improves flowability, and ensures that the narrow gaps under the stacked chips and filler are filled.

[0021] Spherical silica powder is used as an inorganic filler. It provides mechanical strength, reduces the coefficient of thermal expansion, and improves wear resistance. The high loading rate of this inorganic filler allows for a match between the wear resistance of silicon wafers and metal wires.

[0022] Zinc acetylacetonate acts as a latent catalyst. It not only accelerates the reaction but also modulates the reaction kinetics. It forms coordination complexes with acid anhydrides / epoxy groups, remains relatively inert at low temperatures or in the initial mixing stage, and gently releases the active species at specific high temperatures, avoiding localized explosive reactions.

[0023] Resin, curing agent, and inorganic filler: The resin encapsulates the inorganic filler to form a composite material. In this invention, the low viscosity of the selected resin allows the inorganic filler to be densely packed, forming a hard structure similar to concrete, thus improving the material's compressive strength and abrasion resistance.

[0024] Packaging materials, metal wires, memory chips, fillers: Epoxy groups chemically bond with the hydroxyl groups on the surfaces of metal wires, memory chips, and fillers, providing adhesion.

[0025] The beneficial effects of this invention are: This invention provides a method for stacking interconnects of memory chips and provides suitable packaging materials. By combining a filler bridging structure with a dual-catalyzed high-density packaging material, problems such as signal delay, large package thickness, and RDL alignment deviation are solved.

[0026] 1. This invention shortens the signal path and reduces the package thickness: This invention uses a filler sheet as an intermediate bridging unit to interconnect different groups of memory chip stacks through a shared filler sheet, and combines it with a top polishing process.

[0027] The signal can be interconnected simply by connecting from the memory chip to the top filler plate. Compared to connecting to the edge of the substrate, this significantly shortens the physical length of the metal line, effectively reduces parasitic effects, and improves the signal transmission rate.

[0028] The grinding process directly removes the protruding arc portion of the metal wire, eliminating the limitation of the arc height on the total thickness of the package in traditional packaging, and achieving ultra-thin packaging.

[0029] 2. Suppress gold line misalignment to ensure precise RDL alignment: The encapsulation material of this invention employs a dual catalytic system of zinc acetylacetonate (latent catalyst) and 2E4MZ (trace promoter), combined with preferred liquid anhydride and biphenyl resin.

[0030] The dual catalytic system modulates the rheological behavior of the material within the mold. During the injection phase, the material maintains low viscosity and flows smoothly, avoiding severe impacts on the metal wire caused by sudden increases in viscosity or turbulent flow.

[0031] With the filler bridging structure, the two ends of the metal wire are fixed to the memory chip and the filler respectively, which makes the structure more rigid than a simple vertical line.

[0032] The superior fluidity and structural design work together to reduce the risk of gold wire misalignment. After grinding, the position of the metal wire cross-section highly coincides with the designed coordinates, ensuring that subsequent RDL processes can accurately identify and connect it, thus improving interconnect yield.

[0033] 3. Eliminate grinding depressions by utilizing the equal wear rate characteristic: The mild reaction kinetics achieved through the dual catalytic system result in a highly dense and uniform solidification network of the encapsulation material, enabling the encapsulation material to have a similar mechanical wear rate (i.e., equal wear rate) to the metal wires, memory chips, and filler sheets.

[0034] The surface height difference after grinding is very low, forming a flat surface, which solves the problem of RDL seed layer breakage or photolithography defocusing due to uneven substrate.

[0035] 4. Improve the reliability of complex stacks through low-stress protection: For the stress-sensitive structure where the filler sheet bridges two stacked bodies, the high filler content and mild curing characteristics of this invention reduce chemical shrinkage and thermal shrinkage stress.

[0036] It can prevent the filler sheet from breaking during encapsulation and reflow soldering, while the high-density resin layer provides sidewall retention for the polished solderless metal lines, preventing the generation of interface microcracks. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of step 1 of the present invention; Figure 2 This is a schematic diagram of the structure of step 3 of the present invention; Figure 3 This is a schematic diagram of the structure of step 5 of the present invention; Figure 4 This is a schematic diagram of the structure of step 6 of the present invention; Figure 5 This is a schematic diagram of the structure of step 7 of the present invention; Figure 6 This is a schematic diagram of the structure of step 8 of the present invention; Figure 7 This is a schematic diagram of the structure of step 9 of the present invention; The markings in the diagram are: 1. Glass substrate; 2. Temporary bonding layer; 3. Memory chip; 4. Filler sheet; 5. Metal wire; 6. Package; 7. Redundancy layer; 8. Bump. Detailed Implementation

[0039] The specific embodiments of the present invention will be described below with reference to the accompanying drawings. The embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operation processes. However, the scope of protection of the present invention is not limited to the following embodiments.

[0040] It should be noted that, for greater accuracy, some nouns have been accompanied by their corresponding English translations to avoid misunderstandings due to differences in Chinese translations.

[0041] Method 1: A method for interconnecting stacked memory chips includes the following steps: 1.Reference Figure 1 A temporary bonding layer 2 is coated on the surface of a glass substrate 1. The temporary bonding layer 2 includes a release layer and an adhesive layer to obtain a pretreated glass substrate 1.

[0042] 2. Upon receiving the incoming wafer, the wafer thickness is first adjusted to the design requirements through a thinning process, and then the wafer is divided into individual memory chips (Die) using a chip dicing process.

[0043] 3. Reference Figure 2 The chip pick-and-place machine picks up and places individual memory chips 3 onto the adhesive layer of the pre-treated glass substrate 1 according to a preset stacking scheme, thereby completing the stacking arrangement of multiple chips and forming a memory chip stack.

[0044] 4. Receive the incoming dummy wafer 4, first adjust the thickness of the dummy wafer 4 to the design requirements through a thinning process, and then use a chip cutting process to divide the dummy wafer 4 into individual dummy wafers 4.

[0045] 5. Reference Figure 3 A chip placement machine picks up and places individual filler chips 4 onto the top of two sets of memory chip stacks. In essence, each filler chip 4 connects two sets of memory chip stacks.

[0046] 6. Reference Figure 4 The signal pins of each memory chip 3 in the stack are led out through metal wires 5 and then connected to the preset pads on the top filler sheet 4 to obtain a composite structure.

[0047] 7. Reference Figure 5 The composite structure with completed wire bonding is molded, and the entire memory chip stack, filler 4 and metal wire 5 are completely covered by the encapsulation material to form the encapsulation body 6 on the pretreated glass substrate 1.

[0048] 8. Reference Figure 6 The package 6 is ground to remove excess packaging material at the top, the arc portion of the metal wire 5, and part of the filler sheet 4.

[0049] It should be noted that removing the arc portion of metal wire 5 does not mean removing the entire metal wire 5 or destroying the connection of metal wire 5. Metal wire 5 is divided into effective interconnection segments and arc portions.

[0050] The effective interconnection segment of metal line 5 is: the main metal line 5 that connects the chip pins and the filler pads, which is buried inside the packaging material and tightly integrated with the memory chip 3 and the filler 4.

[0051] The arc portion of the metal wire 5 is an arc-shaped protrusion that is naturally formed during the connection process, extending beyond the surface of the filler sheet 4 and exposed on the top of the package 6. It has no actual interconnection function and is merely a natural form of the wire bonding process.

[0052] 9. Reference Figure 7 On the surface of the polished package 6, a redistribution layer (RDL) 7 is fabricated using the RDL process to redistribute the signals on the pads of the filler 4 to preset pin positions. Then, bumps 8 are fabricated on the redistribution layer 7 using the bump process.

[0053] 10. The package 6 with the bump 8 fabricated is separated from the glass substrate 1 by a debonding process, which is achieved by debonding the adhesive layer and the package 6; then a cutting process is used to divide the multiple package structures that are connected together into individual finished chipsets.

[0054] It should be noted that the cutting at this time will not damage the connection structure between the memory chip 3 and the filler 4; it simply cuts the multiple composite structures into a single composite structure.

[0055] The specific implementation method is as follows: 1 Example 1 A method for interconnecting stacked memory chips, comprising the following steps: 1.Reference Figure 1 A 1μm release layer is coated on the surface of a 700μm glass substrate 1, and a 10μm adhesive layer is coated on the release layer. The release layer and the adhesive layer constitute a temporary bonding layer 2, thus obtaining the pretreated glass substrate 1. The release layer can be a photothermal conversion release layer, and the adhesive layer can be a temporary adhesive.

[0056] 2. Receive incoming wafers and use back-grinding to thin them to 40μm. Then, use laser stealth dicing technology to divide the wafers into individual memory chips.

[0057] 3. Reference Figure 2 The chip pick-and-place machine picks up and places individual memory chips 3 onto the adhesive layer of the pre-treated glass substrate 1 according to a preset stacking scheme, thereby completing the stacking arrangement of multiple chips and forming a memory chip stack.

[0058] Specifically, a stepped offset mounting method is used. The first layer of memory chip 3 is mounted onto the temporary bonding layer 2 via a die-attach film (DAF). Subsequent memory chips, the second to fourth layers, are then mounted onto the lower memory chip 3 sequentially via DAF. Each of the second to fourth layers is offset by 300μm along the long side of the lower layer, thus exposing the pads of the lower memory chip 3. The spacing between each stack of memory chips is 2mm.

[0059] 4. Upon receiving the incoming filler wafer 4, the thickness of the filler wafer 4 is first adjusted to the design requirements through a thinning process. Then, a chip dicing process is used to divide the filler wafer 4 into individual filler wafers 4. The filler wafer 4 is made of silicon wafer.

[0060] Among them, the length of the cut filler 4 is greater than or equal to that of the top layer memory chip 3, and the thickness is adjusted to 50μm.

[0061] 5. Reference Figure 3 A chip placement machine picks up and places individual filler chips 4 onto the top of two sets of memory chip stacks. In essence, each filler chip 4 connects two sets of memory chip stacks.

[0062] 6. Reference Figure 4 The signal pins of each memory chip 3 in the memory chip stack are led out through metal wires 5 and then connected to the preset pads on the top filler sheet 4 to obtain a composite structure. The metal wires 5 are made of copper.

[0063] 7. Reference Figure 5 The composite structure with completed wire bonding is molded, and the entire memory chip stack, filler 4 and metal wire 5 are completely covered by the encapsulation material to form the encapsulation body 6 on the pretreated glass substrate 1.

[0064] 8. Reference Figure 6 The package 6 is ground using a grinding machine to remove excess packaging material at the top, the arc portion of the metal line 5, and part of the filler sheet 4, ultimately retaining the 10µm thick filler sheet 4.

[0065] It should be noted that removing the arc portion of metal wire 5 does not mean removing the entire metal wire 5 or destroying the connection of metal wire 5. Metal wire 5 is divided into effective interconnection segments and arc portions.

[0066] The effective interconnection segment of metal line 5 is: the main metal line 5 that connects the chip pins and the filler pads, which is buried inside the packaging material and tightly integrated with the memory chip 3 and the filler 4.

[0067] The arc portion of the metal wire 5 is an arc-shaped protrusion that is naturally formed during the connection process, extending beyond the surface of the filler sheet 4 and exposed on the top of the package 6. It has no actual interconnection function and is merely a natural form of the wire bonding process.

[0068] 9. Reference Figure 7 On the surface of the polished package 6, a redistribution layer 7 is fabricated using the RDL process to redistribute the signals on the pads of the filler 4 to preset pin positions. Then, bumps 8 are fabricated on the redistribution layer 7 using the bump process.

[0069] Specifically, polyimide (PI) is spin-coated onto the surface of the polished package 6, and the opening is exposed and developed to reveal the pads of the underlying filler 4. A layer of titanium and a layer of copper are sputtered to form a seed layer. A 5μm thick copper layer is then electroplated onto the seed layer, and the redistribution layer 7 is etched. Tin-silver-copper (SAC305) solder balls with a diameter of 200μm are implanted and fixed by reflow soldering.

[0070] 10. The package 6 with completed bump fabrication is separated from the glass substrate 1 by a debonding process, which is achieved by debonding the adhesive layer and the package 6; then a cutting process is used to divide the multiple package structures that are connected together into individual finished chipsets.

[0071] It should be noted that the cutting at this time will not damage the connection structure between the memory chip 3 and the filler 4; it simply cuts the multiple composite structures into a single composite structure.

[0072] A single composite structure can connect two sets of memory chip stacks to a single filler plate 4.

[0073] That is, two sets of memory chip stacks (four memory chips 3 in each set) are interconnected through a shared filler 4 to form a compact dual-channel memory module.

[0074] It should be noted that in method 1, the package 6 needs to be ground, the metal wire 5 is usually copper wire, the filler 4 is usually made of silicon wafer, and the packaging material is usually EMC.

[0075] This will present some problems and difficulties: 1. The wear resistance of conventional EMC is usually lower than that of silicon wafers and copper wires. During the polishing process, more of the resin matrix of EMC is worn away, causing the resin surface to be lower than that of copper wires and silicon wafers, forming microscopic pits.

[0076] During subsequent RDL routing (sputtering seed layer), uneven substrate can easily lead to line breakage or blurry focus, severely affecting yield.

[0077] 2. Filler chip 4 acts like a bridge spanning the two sets of memory chip stacks. This is a mechanically double-supported simply supported beam structure, which is quite sensitive to stress.

[0078] Conventional EMC undergoes chemical shrinkage during curing and thermal shrinkage upon cooling. If the EMC shrinkage rate is high, it will generate significant tensile stress, which can easily break the brittle silicon filler 4 in the middle or cause it to delaminate from the adhesive layer of the underlying chip.

[0079] 3. In conventional wire bonding packaging, both ends of the metal wire 5 are secured with solder balls. However, in this application, after grinding, the metal wire 5 loses its mechanical anchor point at the top.

[0080] The grinding process is accompanied by high-frequency, intense vibrations. If the chemical bond between the encapsulation material and the sidewall of the metal wire 5 is not strong enough, the vibrations can cause microcracks between the metal wire 5 and the encapsulation material. These microcracks can subsequently lead to problems such as leakage, poor contact, and oxidation.

[0081] 4. The filler plate is mounted on two sets of chips, forming a tunnel-like gap in the middle. During molding, the encapsulation material fluid needs to flow through this narrow tunnel and completely fill it.

[0082] If the encapsulation material has unsuitable properties or poor flowability, air bubbles can easily form in the center directly below the filler sheet 4. These residual air bubbles will expand rapidly during subsequent high-temperature reflow soldering, affecting the structure of the package 6.

[0083] Therefore, the specific encapsulation method is given below.

[0084] Method 2 The preparation method of the encapsulation material, and the specific steps are as follows: Prepare the ingredients: Resin: Biphenyl type epoxy resin Curing agents: including methyl hexahydrophthalic anhydride (MHHPA) and / or styrene-maleic anhydride copolymer (SMA). Catalysts: including zinc acetylacetonate Inorganic fillers: including spherical fused silica powder Other additives: including colorants, release agents, and accelerators. Prepare using the above raw materials in parts by weight: Premixing: Add 100 parts resin, 80-90 parts curing agent, 3-5 parts catalyst, 600-800 parts inorganic filler, and 5-6 parts other additives to a high-speed mixer and mix at 500-1000 rpm for 5-10 minutes at room temperature until the powder is uniform to obtain a mixed powder.

[0085] Melt extrusion: The mixed powder is fed into a twin-screw extruder or a twin-roll mill and kept at 90-110℃ for mixing, so that the resin melts and encapsulates the filler to obtain the mixed product.

[0086] Post-processing: After cooling the compounded product, it is crushed into granules by a pulverizer and then sealed and refrigerated for storage.

[0087] The following is a detailed implementation method 2 Example 2 The preparation method of the encapsulation material, and the specific steps are as follows: Prepare the ingredients: Resin: Biphenyl type epoxy resin, YX-4000H, Mitsubishi Chemical, Japan.

[0088] Curing agent: Methylhexahydrophthalic anhydride (MHHPA), anhydride equivalent 168 g / eq, liquid.

[0089] Catalyst: Zinc acetylacetonate, powder, purity >99%.

[0090] Inorganic filler: Includes spherical fused silica microparticles treated with epoxy silane coupling agent (KBM-403). Average particle size 5μm, maximum particle size 20μm. FB series from Nippon Denka Co., Ltd. is also available.

[0091] Other additives include: colorant, release agent, and accelerator. The colorant is carbon black, the release agent is carnauba wax, and the accelerator is 2-ethyl-4-methylimidazole (2E4MZ).

[0092] Prepare using the above raw materials in parts by weight: Premixing: Add 100 parts resin, 85 parts curing agent, 4 parts catalyst, 750 parts inorganic filler, 2 parts colorant, 3 parts release agent, and 0.5 parts accelerator to a high-speed mixer and mix at 800 rpm for 10 minutes at room temperature until the powder is uniform to obtain a mixed powder.

[0093] Melt extrusion: The mixed powder is fed into a twin-screw extruder, kept at 95°C, with a screw speed of 80 rpm, and mixed for 30 seconds to obtain the mixed product.

[0094] Post-processing: After cooling the compounded product, it is crushed into granules by a pulverizer and then sealed and refrigerated for storage.

[0095] The method of using the encapsulation material prepared in Example 2 is as follows: In step 7 of Example 1, the encapsulation material prepared in Example 2 is placed into a molding machine and injected into a mold at 175°C and 8MPa pressure to fill the gaps below the memory chip stack and filler 4. The holding time is 120 seconds to obtain a composite structure.

[0096] The composite structure is demolded and then cured at 200°C for 4 hours to form an encapsulation 6 on the pretreated glass substrate 1.

[0097] It should be noted that during pressure holding in the mold, the material undergoes initial cross-linking, forming a network structure with sufficient hardness for demolding. After demolding, further curing occurs, and zinc acetylacetonate catalyzes rapid exchange of ester bonds. The stretched molecular chains release tension by breaking old bonds and instantly forming new ones. This reduces the internal stress of the encapsulated body 6.

[0098] Subsequently, during the grinding of the encapsulation structure, the instantaneous temperature (flash temperature) at the contact point between the grinding wheel and the material exceeds 200°C. This high temperature induces solid-state rheology on the surface of the encapsulation material: due to localized rearrangement of molecular chains, some of the tiny scratches left by the grinding wheel automatically heal. The resin exhibits transient plasticity under shear force, adhering tightly to the metal wires. This solid-state rheology is high-viscosity; it does not melt into water, but rather provides better support.

[0099] Comparative Example 1 The preparation method of the encapsulation material, and the specific steps are as follows: Prepare the ingredients: Resin: Biphenyl type epoxy resin, YX-4000H, Mitsubishi Chemical, Japan.

[0100] Curing agent: Methylhexahydrophthalic anhydride (MHHPA), anhydride equivalent 168 g / eq, liquid.

[0101] Inorganic filler: Includes spherical fused silica microparticles treated with epoxy silane coupling agent (KBM-403). Average particle size 5μm, maximum particle size 20μm. FB series from Nippon Denka Co., Ltd. is also available.

[0102] Other additives include: colorant, release agent, and accelerator. The colorant is carbon black, the release agent is carnauba wax, and the accelerator is 2-ethyl-4-methylimidazole (2E4MZ).

[0103] Prepare using the above raw materials in parts by weight: Premixing: Add 100 parts resin, 85 parts curing agent, 750 parts inorganic filler, 2 parts colorant, 3 parts release agent, and 2 parts accelerator to a high-speed mixer and mix at 800 rpm for 10 minutes at room temperature until the powder is uniform to obtain a mixed powder.

[0104] Melt extrusion: The mixed powder is fed into a twin-screw extruder, kept at 95°C, with a screw speed of 80 rpm, and mixed for 30 seconds to obtain the mixed product.

[0105] Post-processing: After cooling the compounded product, it is crushed into granules by a pulverizer and then sealed and refrigerated for storage.

[0106] The specific steps for using the encapsulation material prepared in Comparative Example 1 are as follows: In step 7 of Example 1, the encapsulation material of Comparative Example 1 is placed into a molding machine and injected into a mold at 175°C and 10MPa pressure to fill the gaps below the memory chip stack and filler sheet 4. The holding time is 120 seconds to obtain a composite structure.

[0107] The composite structure is demolded and then cured at 200°C for 4 hours to form an encapsulation 6 on the pretreated glass substrate 1.

[0108] Comparative Example 2 Low-viscosity epoxy molding compound (EMC) is used as the encapsulation material, and Sumitomo G770 is selected as the low-viscosity epoxy molding compound (EMC).

[0109] The specific steps for using the packaging material in Comparative Example 2 are as follows: In step 7 of Example 1, the encapsulation material of Comparative Example 2 is placed in a molding machine and injected into the mold at 125°C and 4MPa pressure to fill the gaps below the memory chip stack and filler sheet 4. The holding time is 300 seconds to obtain a composite structure.

[0110] The composite structure is demolded and then cured at 200°C for 4 hours to form an encapsulation 6 on the pretreated glass substrate 1.

[0111] test: Select the packaged bodies 6 of Example 2, Comparative Example 1, and Comparative Example 2, and perform the grinding process in step 8 of Example 1 on these packaged bodies 6, and then test them. Steps 9-10 are not performed.

[0112] 1. Grinding surface flatness test Using a profilometer, scan the surface of the polished package 6 at the junction of the metal wire 5 and the package material, and at the junction of the filler 4 and the package material. Measure the height difference between the surface of the package material and the surface of the metal wire 5 or the filler 4, i.e., the recess depth.

[0113] Results: The height difference in Example 2 was 0.1 μm, the height difference in Comparative Example 1 was 0.9 μm, and the height difference in Comparative Example 2 was 2.1 μm.

[0114] 2. Microstructure analysis of the slices Using a scanning electron microscope (SEM), the sample was physically cut and polished along the cross-section of metal wire 5. The area where metal wire 5 is wrapped with the encapsulation material was observed for microcracks.

[0115] Results: Example 2 showed no cracks, Comparative Example 1 showed obvious cracks, and Comparative Example 2 showed a small number of cracks.

[0116] analyze: 1. Regarding the smoothness of the surface after grinding: Comparative Example 1 used an accelerator (2E4MZ). This resulted in a faster reaction rate between the epoxy resin and the anhydride, leading to a more intense reaction within the mold. This resulted in uneven formation of the cured network, with some areas exhibiting high crosslinking density while others suffered from insufficient crosslinking density due to hindered reactant diffusion. During the grinding process, the microscopically softer, low-crosslinking areas were worn away first, leading to an increase in overall surface depression.

[0117] Comparative Example 2 used low-viscosity EMC. To achieve high flowability, the filler ratio was reduced or a softer resin matrix was used. During physical grinding, the soft resin wears down faster than the hard filler sheets and metal wires, forming indentations.

[0118] Example 2, through the addition of high amounts of inorganic fillers and a specific ratio of biphenyl resin and acid anhydride, formed a high-modulus, high-density cured network. The use of a catalyst ensured a mild and orderly reaction, allowing sufficient time for molecular chains to rearrange and stack, resulting in a denser structure. The difference in density directly affects wear resistance. Therefore, its wear resistance rate is close to that of filler sheets and metal wires, thus achieving high planarization and providing a flat surface for subsequent RDL processes.

[0119] 2. Regarding cracks: The reaction in Comparative Example 1 was more intense, with a high exothermic peak, resulting in greater curing shrinkage. This caused significant tensile stress at the center of filler sheet 4 (double-beam structure), leading to crack formation.

[0120] Comparative Example 2 shows a larger thermal expansion and contraction, resulting in interface delamination.

[0121] Example 2 shows a mild reaction, and the high filler content reduces the overall coefficient of thermal expansion, reduces thermal shrinkage stress, and protects the fragile stacked structure.

[0122] It should be noted that the preferred embodiments of the present invention are given in the specification and accompanying drawings, but are not limited to the embodiments described in this specification. Furthermore, those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for stacking and interconnecting memory chips, characterized in that, Includes the following steps: A temporary bonding layer is coated on the surface of a glass substrate to obtain a pretreated glass substrate. The thickness of the wafer and the filler wafer are adjusted by thinning process, and then the wafer and the filler wafer are divided into individual memory chips and individual filler wafers by chip cutting process. Individual memory chips are mounted onto a temporary bonding layer according to the design to complete the stacking arrangement of multiple chips and form a memory chip stack. Individual filler pieces are mounted on top of the memory chip stack according to the design; By using wire bonding technology, the signal pins of each memory chip in the memory chip stack are led out through metal wires and connected to the preset pads of the top filler layer to obtain a composite structure; For composite structure molding encapsulation, an encapsulation body is formed on a pretreated glass substrate; The package is ground, a redistribution layer is made on the surface of the ground package, and then bumps are made on the redistribution layer using a bumping process. After peeling off the pretreated glass substrate, the remaining structure is a structure containing one or more sets of memory chip stacked interconnects.

2. The memory chip stacking interconnection method according to claim 1, characterized in that, The temporary bonding layer includes a release layer and an adhesive layer.

3. The memory chip stacking interconnection method according to claim 1, characterized in that, When grinding the package, remove excess packaging material at the top, the arc portion of the metal wires, and some filler sheets.

4. The memory chip stacking interconnection method according to claim 1, characterized in that, A redistribution layer is fabricated on the surface of the polished package, including the following steps: On the surface of the polished package, a redistribution layer is fabricated using the RDL process to redistribute the signals on the fill pads to the preset pin locations.

5. The memory chip stacking interconnection method according to claim 1, characterized in that, Individual memory chips are mounted onto a temporary bonding layer according to the design to complete the stacking arrangement of multiple chips and form a memory chip stack. This includes the following steps: A stepped offset method is used for mounting. The first layer of memory chip is mounted on a temporary bonding layer. When subsequent memory chips are mounted on the lower layer, each layer is offset by the required distance along the long side of the lower layer to expose the pads of the lower memory chip. After mounting, a stack of memory chips is formed.

6. The memory chip stacking interconnection method according to claim 1, characterized in that, Assemble individual filler wafers onto the top of the memory chip stack according to the design, including the following steps: A single filler pad is mounted on top of two sets of memory chip stacks, with each filler pad connecting the two sets of memory chip stacks.

7. The memory chip stacking interconnection method according to claim 1, characterized in that, When the remaining structure contains multiple sets of stacked interconnected memory chips, the remaining structure is cut to obtain a single independent finished chipset.

8. The memory chip stacking interconnection method according to claim 1, characterized in that, For composite structure molding encapsulation, forming an encapsulation body on a pretreated glass substrate includes the following steps: The composite structure with wire bonding is molded, and the entire stack, filler sheets and metal wires are completely covered with encapsulation material to form an encapsulation on the pretreated glass substrate.

9. A method for stacking and interconnecting memory chips according to claim 8, characterized in that, The preparation method of the encapsulation material includes the following steps: By weight, 100 parts resin, 80-90 parts curing agent, 3-5 parts catalyst, 600-800 parts inorganic filler, and 5-6 parts other additives are added to a high-speed mixer and mixed at 500-1000 rpm for 5-10 minutes at room temperature until the powder is uniform, thus obtaining a mixed powder. The mixed powder is melted and extruded to obtain a compound product. After cooling, the compound product is pulverized to obtain an encapsulation material.

10. A method for stacking and interconnecting memory chips according to claim 9, characterized in that, The resin includes biphenyl-type epoxy resin, the curing agent includes MHHPA and / or SMA; the catalyst includes zinc acetylacetonate; the inorganic filler includes spherical silica powder, and other additives include at least one of colorant, release agent and accelerator, wherein the accelerator includes 2-ethyl-4-methylimidazole.

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