Packaging structure and packaging method

Abstract

According to the packaging structure and the packaging method, in the packaging structure, a first surface and a second surface of a chip structure are electrically connected; the conductive structure is electrically connected with the first connecting end on the other side of the bonding area through the first substrate, and electric connection between the first connecting ends located on the two sides of the bonding area and between the first connecting ends located on the two sides of the bonding area and the chip structure is achieved through the first substrate, the chip structure, the conductive structure and the second substrate. The first surface and the second surface of the chip structure and the conductive structure are electrically connected in the vertical direction, so that stray inductance can be reduced; besides, a part of an electric connection path is realized through the chip structure, the second substrate and the conductive structure, so that the area occupied by the electric connection path in the first substrate can be reduced, the heat dissipation area of the first substrate is increased, the area for bonding the chip structure in the first substrate is also increased, and the heat dissipation efficiency of the first substrate is improved. The bonding number of the chip structure is correspondingly increased, the outflow capacity of the packaging structure is improved, and the performance of the packaging structure is optimized.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a packaging structure and packaging method. Background Technology

[0002] With the rapid development of electronic technology, power electronic devices are playing an increasingly important role in various application fields. To meet the requirements of high power density and high reliability, power module packaging technology has become one of the key technologies. Among these, the heat dissipation capability of a power module can affect its operating performance and lifespan. To improve heat dissipation, double-sided heat dissipation packaging structures have emerged.

[0003] Compared to single-sided heat dissipation packaging structures, double-sided heat dissipation packaging structures have thermally conductive substrates on both sides of the chip, which can dissipate heat from both sides of the chip, thereby increasing the heat dissipation efficiency of the packaging structure.

[0004] However, the performance and heat dissipation efficiency of the current packaging structure still need to be improved. Summary of the Invention

[0005] This invention provides a packaging structure and packaging method for improving the performance of the packaging structure.

[0006] To address the aforementioned problems, the present invention provides a packaging structure comprising: a first substrate, including a bonding region and connection regions located on both sides of the bonding region; a first connection terminal, bonded to the connection regions and electrically connected to the first substrate; one or more chip structures, bonded to the bonding region of the first substrate, the chip structures including a first side and a second side facing away from each other; the first side being bonded to the first substrate, and the first side being electrically connected to the first connection terminal located on one side of the bonding region via the first substrate; a conductive structure, bonded to the exposed bonding region of the chip structures and electrically connected to the first substrate; the conductive structure being electrically connected to the first connection terminal located on the other side of the bonding region via the first substrate; and a second substrate, bonded to the second side of the chip structures and the top of the conductive structure, the second substrate being electrically connected to the second side of the chip structures and the conductive structure.

[0007] This invention provides a packaging method, comprising: providing a first substrate, including a bonding region and connection regions located on both sides of the bonding region; providing one or more chip structures, the chip structures including a first side and a second side facing away from each other; bonding one or more chip structures, a conductive structure, and a first connection terminal on the first substrate; the first side of the chip structure is bonded to the bonding region of the first substrate and electrically connected to the first substrate; the conductive structure is bonded to the exposed bonding region of the chip structure and electrically connected to the first substrate; the first connection terminal is bonded to the connection region and electrically connected to the first substrate; wherein the first connection terminal located on one side of the bonding region is electrically connected to the first side through the first substrate, and the first connection terminal located on the other side of the bonding region is electrically connected to the conductive structure through the first substrate; bonding a second substrate on the second side of the chip structure and the top of the conductive structure, the second substrate being electrically connected to the second side of the chip structure and the conductive structure.

[0008] Compared with the prior art, the technical solution of the present invention has the following advantages: The packaging structure provided in this embodiment of the invention includes an electrical connection between a first surface and a second surface of the chip structure. The first surface is electrically connected to a first connection terminal located on one side of the bonding region via a first substrate. The packaging structure also includes a conductive structure electrically connected to the first connection terminal on the other side of the bonding region via the first substrate. A second substrate electrically connects the conductive structure to the chip. Therefore, through the first substrate, the chip structure, the conductive structure, and the second substrate, electrical connections are achieved between the first connection terminals located on both sides of the bonding region and between the first connection terminals and the chip structure. Furthermore, a vertical electrical connection is achieved between the first surface and the second surface of the chip structure, and the conductive structure achieves a vertical connection between the first substrate and the second substrate. The electrical connections are made in opposite directions, allowing them to cancel each other out and reducing stray inductance. Furthermore, compared to solutions that only utilize the first substrate to establish the first connection point between the bonding area and the chip structure, the packaging structure of this invention also utilizes the chip structure, the second substrate, and the conductive structure to establish a partial electrical connection path. This reduces the area occupied by the electrical connection path in the first substrate, which not only increases the area of ​​the first substrate used for heat dissipation, thus improving the heat dissipation capacity of the packaging structure, but also increases the area of ​​the first substrate used for bonding the chip structure. Consequently, this increases the number of chips bonded, improves the outflow capacity of the packaging structure, and optimizes its performance.

[0009] In the packaging method provided by this embodiment of the invention, one or more chip structures, conductive structures, and first connection terminals are bonded to a first substrate; a first surface and a second surface of the chip structure are electrically connected; the conductive structure is electrically connected to the first substrate; the first connection terminal is bonded to the connection area and electrically connected to the first substrate; wherein, the first connection terminal located on one side of the bonding area is electrically connected to the first surface through the first substrate; the first connection terminal located on the other side of the bonding area is electrically connected to the conductive structure through the first substrate; therefore, after a second substrate is bonded to the second surface of the chip structure and the top of the conductive structure, and the second substrate electrically connects the second surface of the chip structure to the conductive structure, the first connection terminals located on both sides of the bonding area and the first connection terminal connected to the chip structure are electrically connected through the first substrate, the chip structure, the conductive structure, and the second substrate, thus achieving the connection between the first connection terminals located on both sides of the bonding area and the connection with the chip structure. The electrical connections between the chip structure and the second substrate are vertically connected, and the conductive structure also vertically connects the first and second substrates. Furthermore, the electrical connection paths of the two substrates are opposite in direction, allowing them to cancel each other out and reducing stray inductance. In addition, compared to a solution that only uses the first substrate to achieve the first connection point between the two sides of the bonding area and the electrical connection with the chip structure, this embodiment of the invention also uses the chip structure, the second substrate, and the conductive structure to achieve a partial electrical connection path. This reduces the area occupied by the electrical connection path in the first substrate, which not only increases the area of ​​the first substrate used for heat dissipation, thereby improving the heat dissipation capacity of the packaging structure, but also increases the area of ​​the first substrate used for bonding the chip structure. This correspondingly increases the number of bonds in the chip structure, improves the outflow capacity of the packaging structure, and optimizes the performance of the packaging structure. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a packaging structure; Figures 2 to 7 This is a schematic diagram of the packaging structure according to an embodiment of the present invention; Figure 8 This is a flowchart of the encapsulation method according to an embodiment of the present invention; Figures 9 to 21 This is a schematic diagram of the structure corresponding to each step in the encapsulation method of this invention. Detailed Implementation

[0012] As can be seen from the background technology, the performance and heat dissipation efficiency of current packaging structures still need to be improved.

[0013] Figure 1 This is a schematic diagram of a packaging structure.

[0014] The packaging structure includes: a substrate 10, including a bonding region 10a and connection regions 10b located on both sides of the bonding region 10a, wherein an electrical circuit (not shown) is disposed within the substrate 10; one or more chips 11, bonded to the bonding region 10a of the substrate 10 and electrically connected to the electrical circuit, wherein the chip 11 includes a first surface 11a and a second surface 11b facing away from each other, the first surface 11a being bonded to the substrate 10; an electrical connector 12, bonded to the connection region 10b of the substrate 10 and electrically connected to the electrical circuit, the electrical connector 12 extending along the surface of the substrate 10 and including a protrusion 12a protruding from the side of the substrate 10; a heat sink 13, bonded to the second surface 12b of the chip 11; and an encapsulation layer 14, covering the side of the substrate 10 and the heat sink 13 and filling the space between the substrate 10 and the heat sink 13, wherein the sidewalls of the encapsulation layer 14 expose the protrusion 12a.

[0015] Since the substrate 10 has a planar structure and the electrical circuits are also planar, the electrical circuit paths are relatively long, resulting in larger stray inductance, which can easily increase power consumption and reduce the performance of the packaging structure. Furthermore, the planar electrical circuits occupy a large area of ​​the substrate 10, resulting in a smaller area on the substrate 10 for heat dissipation of the chip 11. This not only easily leads to poor heat dissipation of the packaging structure, thus reducing its performance, but also easily leads to a smaller area on the substrate 10 for bonding the chip 11, which limits the number of chips 11 that can be bonded, thus limiting the outflow capacity of the packaging structure and resulting in poor performance of the packaging structure.

[0016] To address the aforementioned technical problem, the packaging structure provided in this embodiment of the invention includes an electrical connection between the first and second surfaces of the chip structure. The first surface is electrically connected to the first connection terminal located on one side of the bonding region via a first substrate. The packaging structure further includes a conductive structure electrically connected to the first connection terminal on the other side of the bonding region via the first substrate. A second substrate electrically connects the conductive structure to the chip. Therefore, through the first substrate, chip structure, conductive structure, and second substrate, electrical connections are achieved between the first connection terminals located on both sides of the bonding region and between the first connection terminals and the chip structure. Furthermore, a vertical electrical connection is achieved between the first and second surfaces of the chip structure, and the conductive structure connects the first substrate and the second substrate. The two components are electrically connected in a vertical direction, and their electrical connection paths are opposite in direction. The electrical connection paths can cancel each other out, which helps to reduce stray inductance. In addition, compared with the solution that only uses the first substrate to realize the first connection end located between the two sides of the bonding area and the electrical connection with the chip structure, the packaging structure of this embodiment of the invention also realizes part of the electrical connection path through the chip structure, the second substrate and the conductive structure. This can reduce the area occupied by the electrical connection path in the first substrate. This not only helps to increase the area of ​​the first substrate used for heat dissipation, thereby improving the heat dissipation capacity of the packaging structure, but also helps to increase the area of ​​the first substrate used for bonding the chip structure. Correspondingly, this helps to increase the number of bonding of the chip structure, improve the outflow capacity of the packaging structure and optimize the performance of the packaging structure.

[0017] The technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the invention.

[0018] Figures 2 to 6 This is a schematic diagram of the packaging structure according to an embodiment of the present invention. Figure 2 This is a three-dimensional structural diagram of the packaging structure according to an embodiment of the present invention; Figure 3 for Figure 2 A top-view structural diagram; Figure 4 (a) Figure 6 (a) is Figure 2 A top view of the structure on the first substrate; Figure 4 (b) for Figure 6 (b) Figure 2 A top view of the structure on the second substrate; Figure 5 for Figure 2 A cross-sectional view of the structure along the electrical connection path P1; Figure 7 for Figure 2A cross-sectional view of the structure along the electrical connection path P2.

[0019] refer to Figures 2 to 7 The packaging structure provided in this embodiment of the invention includes: a first substrate 100, including a bonding region 100a and connection regions 100b located on both sides of the bonding region 100a; a first connection terminal 110, bonded to the connection region 100b and electrically connected to the first substrate 100; and one or more chip structures 130, bonded to the bonding region 100a of the first substrate 100, wherein the chip structure 130 includes a first surface 130a and a second surface 130b opposite to each other; the first surface 130a is bonded to the first substrate 100, and the first surface 130a is bonded to the first substrate 100, and the first surface 130a is bonded to the first substrate 100b located on one side of the bonding region 100a. The first connection terminals 110 are electrically connected to each other via the first substrate 100; the conductive structure 140 is bonded to the exposed bonding area 100a of the chip structure 130 and electrically connected to the first substrate 100; the conductive structure 140 and the first connection terminals 110 located on the other side of the bonding area 100a are electrically connected via the first substrate 100; the second substrate 200 is bonded to the second surface 130b of the chip structure 130 and the top of the conductive structure 140, and the second substrate 200 electrically connects the second surface 130b of the chip structure 130 and the conductive structure 140.

[0020] The first substrate 100 is used to provide support and bonding platform for the packaging structure. Specifically, the first substrate 100 provides support and bonding platform for the first connection terminal 110, the chip structure 130, the conductive structure 140, and the second substrate 200.

[0021] In this embodiment, the first substrate 100 is also used to dissipate heat for the packaging structure, so as to reduce the power consumption of the packaging structure and improve the performance of the packaging structure.

[0022] Specifically, compared with the scheme that only uses the first substrate 100 to realize the first connection terminal 110 located between the two sides of the bonding region 100a and the electrical connection with the chip structure 130, this embodiment also realizes part of the electrical connection path through the chip structure 130, the second substrate 200 and the conductive structure 140. This can reduce the area occupied by the electrical connection path in the first substrate 100, which not only helps to increase the area of ​​the first substrate 100 used for heat dissipation, thereby improving the heat dissipation capacity of the packaging structure, but also helps to increase the area of ​​the first substrate 100 used for bonding the chip structure 130, which in turn helps to increase the number of bonding of the chip structure 130, improve the outflow capacity of the packaging structure and optimize the performance of the packaging structure.

[0023] In this embodiment, the first substrate 100 includes a first interconnect layer 103, which is used to bond the first connection terminal 110, the chip structure 130 and the conductive structure 140 to realize the electrical connection between the chip structure 130 and the first connection terminal 110 or between the conductive structure 140 and the first connection terminal 110.

[0024] Accordingly, in this embodiment, the first connection terminal 110, the chip structure 130, and the conductive structure 140 are bonded to the first interconnect layer 103; the first interconnect layer 103 is electrically connected to the first surface 130a and the first connection terminal 110 located on one side of the bonding region 100a; the first interconnect layer 103 is electrically connected to the conductive structure 140 and the first connection terminal 110 located on the other side of the bonding region 100a.

[0025] In this embodiment, the first interconnect layer 103 is made of copper. Copper has low resistivity and high thermal conductivity, which helps to reduce the resistance of the first interconnect layer 103 and improve the heat dissipation capacity of the first substrate 100. In other embodiments, the material of the first interconnect layer 103 is other metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0026] In this embodiment, the first substrate 100 is a stacked structure, and the first substrate 100 further includes: a first heat dissipation layer 101 located on the side of the first interconnect layer 103 opposite to the chip structure 130; and a first insulating layer 102 located between the first heat dissipation layer 101 and the first interconnect layer 103.

[0027] The first substrate 100 is further provided with a first heat dissipation layer 101, thereby further improving the heat dissipation capacity of the first substrate 100.

[0028] In this embodiment, the first heat dissipation layer 101 is made of a metallic material, which is beneficial to improving the heat dissipation effect of the first heat dissipation layer 101. The material of the first heat dissipation layer 101 is a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. In this embodiment, the material of the first heat dissipation layer 101 is copper.

[0029] The first insulating layer 102 is used to achieve insulation between the first interconnect layer 103 and the external circuit. In this embodiment, the first insulating layer 102 also achieves isolation between the first interconnect layer 103 and the first heat dissipation layer 101.

[0030] In this embodiment, the material of the first insulating layer 102 is silicon oxide. In other embodiments, the material of the first insulating layer 102 may also be other insulating materials, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0031] The first connection terminal 110 is used to connect the electrical connection terminal, which serves as the package structure, to achieve electrical connection between the package structure and external circuits or other circuit devices.

[0032] In this embodiment, the first connection terminal 110 includes a power terminal, which serves as an electrical connection channel between the package structure and the external circuit.

[0033] In this embodiment, the first connection terminal 110 is a block structure. Power terminals are typically used to conduct large currents. By selecting a block structure, the power terminal has a larger volume and cross-sectional area, correspondingly reducing its resistance. This facilitates the conduction of large currents, significantly improving the power transmission capability of the package structure. Furthermore, it allows for a larger power surface area, increasing the contact area between the power terminal and external circuits during subsequent electrical connections, reducing contact resistance, and thus improving the current transmission performance and stability between the external circuit and the package structure. Additionally, the block structure of the power terminal facilitates the conduction of heat generated by the power device to the outside during operation, improving the heat dissipation capability of the package structure. Moreover, the block structure of the first connection terminal 110 allows for flexible adjustment of its size and position, providing greater flexibility for subsequent electrical connections with external circuits.

[0034] In other embodiments, the shape and structure of the first connection terminal 110 can be flexibly adjusted based on actual device and process requirements. For example, the first connection terminal 110 can be a spherical structure, a columnar structure, a pin structure, etc.

[0035] In this embodiment, the first connection terminal 110 is made of copper. Copper has low resistivity, which helps to reduce the resistance of the first connection terminal 110. Furthermore, copper has high thermal conductivity, providing a low-thermal-resistance heat dissipation channel for the power device, improving heat dissipation capacity, and thus enhancing the power transmission capability of the package structure. In other embodiments, the first connection terminal 110 may also be made of other metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0036] As an example, the power terminal located on one side of the bonding region 100a is used as an AC power terminal 110b, and the power terminal located on the other side of the bonding region 100a is used as a DC power terminal 110a. Thus, through the first substrate 100, the chip structure 130, the conductive structure 140, and the second substrate 200, an electrical connection is achieved between the AC power terminal 110b and the DC power terminal 110a, as well as with the chip structure 130.

[0037] Specifically, in this embodiment, the DC power terminal 110a includes a positive DC power terminal 110a+ (DC+) and a negative DC power terminal 110a- (DC-). The positive DC power terminal 110a+ and the negative DC power terminal 110a- are located on the same side of the bonding region 100a, so as to realize electrical connection with the AC power terminal 110b located on the other side of the bonding region 100a, respectively.

[0038] In this embodiment, the electrical connection path between the positive DC power terminal 110a+ and the AC power terminal 110b is used as the first electrical connection path P1 to form an upper bridge circuit; the electrical connection path between the AC power terminal 110b and the negative DC power terminal 110a- is used as the second electrical connection path P2 to form a lower bridge circuit.

[0039] In this embodiment, the packaging structure further includes: a second connection terminal 120, which is bonded to the connection area 100b exposed by the first connection terminal 110; the second connection terminal 120 includes a signal terminal, which is used to lead out the signal terminals of the packaging structure to realize the signal connection between the packaging structure and the external circuit.

[0040] In this embodiment, the second connection terminal 120 includes a pin structure. In this embodiment, the second connection terminal 120 includes a signal terminal. Generally speaking, the current in the electrical signal path is small, and the signal can be transmitted through the pin structure. Moreover, the pin structure is low in cost and allows for flexible adjustment of the position of the second connection terminal 120, thereby reducing the cost of the packaging structure and improving the flexibility of the electrical connection between the second connection terminal 120 and the external circuit.

[0041] In other embodiments, the shape and structure of the second connection end 120 can be flexibly adjusted based on actual device and process requirements. For example, the second connection end 120 can be a block structure, a spherical structure, a columnar structure, etc.

[0042] Chip structure 130 is used as a functional device in a package structure to enable the package structure to perform specific functions. In this embodiment, the package structure is used to form a power device, and chip structure 130 also includes a power chip structure.

[0043] The first surface 130a and the second surface 130b are electrically connected, thereby enabling electrical connection between the first substrate 100 and the second substrate 200 in the vertical direction, thereby increasing the electrical connection path in the vertical direction.

[0044] In this embodiment, the chip structure 130 includes a chip 31 and an electrical connection layer 32 located on the chip 31, wherein the electrical connection layer 32 is electrically connected to the chip 31.

[0045] As an example, the packaging structure is used to form a power device, and chip 31 includes a power chip, such as a diode, transistor, etc.

[0046] The electrical connection layer 32 is located on the chip 31 along a direction perpendicular to the chip 31 and is electrically connected to the chip 31, thereby realizing the electrical connection between the first surface 130a and the second surface 130b of the chip structure 130 along the vertical direction.

[0047] In one embodiment, the electrical connection layer 32 is made of copper. Copper has low resistivity, which is beneficial for improving the electrical connection performance of the electrical connection layer 32. In other embodiments, the electrical connection layer can also be made of other metallic materials, such as silver.

[0048] In this embodiment, the side of the chip 31 opposite to the electrical connection layer 32 is designated as the first side 130a; the side of the electrical connection layer 32 opposite to the chip is designated as the second side 130b. That is, in this embodiment, the chip 31 is bonded to the first substrate 100 and electrically connected to it, which helps to reduce the signal transmission path between the chip 31 and the first substrate 100 and reduce signal transmission delay; the electrical connection layer 32 is bonded to and electrically connected to the second substrate 200, thereby enabling an electrical connection between the chip 31 and the second substrate 200 in the vertical direction.

[0049] In other embodiments, based on actual device and process requirements, the side of the chip opposite to the electrical connection layer 32 can be used as the second side 130b, and the side of the electrical connection layer 32 opposite to the chip can be used as the first side 130a, which can also serve to provide an electrical connection path in the vertical direction.

[0050] In one embodiment, the second connection terminal 120 is a signal terminal, and the chip 31 and the second connection terminal 120 are electrically connected only through the first substrate 100, thereby reducing changes to the signal transmission path and improving signal transmission stability and efficiency. Specifically, in this embodiment, the chip 31 and the second connection terminal 120 are electrically connected through the first interconnect layer 103.

[0051] In other embodiments, based on actual needs, the electrical connection path between the second connection terminal 120 and the chip can also be achieved through the conductive structure 140, the first substrate 100, and the second substrate 200.

[0052] The conductive structure 140 is used to realize the electrical connection between the first substrate 100 and the second substrate 200 in the vertical direction. The conductive structure 140 is located between the first substrate 100 and the second substrate 200, and can also provide support between the second substrate 200 and the first substrate 100, thereby improving the mechanical performance of the packaging structure.

[0053] In this embodiment, the conductive structure 140 includes a columnar structure. The columnar structure has a larger volume and cross-section, which helps reduce the resistance of the electrical connection path, improves current transmission capability, and provides good electrical contact performance between the conductive structure 140 and the first substrate 100 and the second substrate 200. Furthermore, the columnar structure improves the positional and dimensional flexibility of the conductive structure 140. In other embodiments, based on actual process and design requirements, the conductive structure 140 can also be other structures, such as a block structure, a spherical structure, etc.

[0054] In this embodiment, the conductive structure 140 is made of copper. Copper has low resistivity and high thermal conductivity, which can further reduce the resistance of the conductive structure 140 and improve the heat dissipation capability of the packaging structure. In other embodiments, the conductive structure 140 may also be made of other metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0055] The second substrate 200 is bonded to the top surface of the chip structure 130 and the conductive structure 140, and is used to electrically connect the chip structure 130 and the conductive structure 140. In this embodiment, the second substrate 200 is also used to dissipate heat from the packaging structure, thereby improving the heat dissipation capability of the packaging structure.

[0056] In this embodiment, the first surface 130a and the second surface 130b of the chip structure 130 are electrically connected. The first surface 130a is electrically connected to the first connection terminal 110 located on one side of the bonding region 100a via the first substrate 100. The conductive structure 140 is electrically connected to the first connection terminal 110 on the other side of the bonding region 100a via the first substrate 100. The second substrate 200 electrically connects the conductive structure 140 to the chip. Therefore, through the first substrate 100, the chip structure 130, the conductive structure 140, and the second substrate 200, electrical connections are achieved between the first connection terminals 110 on both sides of the bonding region 100a and between the first connection terminals 110 and the chip structure 130. Furthermore, a vertical electrical connection is achieved between the first surface 130a and the second surface 130b of the chip structure 130. The conductive structure 140 is integrated with the first substrate. The vertical electrical connection between the first substrate 100 and the second substrate 200 is opposite in direction, and the electrical connection paths can cancel each other out, which helps to reduce stray inductance. In addition, compared with the solution that only uses the first substrate 100 to realize the electrical connection between the first connection end 110 located between the two sides of the bonding region 100a and the chip structure 130, the packaging structure of this embodiment also realizes part of the electrical connection path through the chip structure 130, the second substrate 200 and the conductive structure 140. This can reduce the area occupied by the electrical connection path in the first substrate 100, which not only helps to increase the area of ​​the first substrate 100 used for heat dissipation, thereby improving the heat dissipation capacity of the packaging structure, but also helps to increase the area of ​​the first substrate 100 used for bonding the chip structure 130, which in turn helps to increase the number of bonding of the chip structure 130, improve the outflow capacity of the packaging structure and optimize the performance of the packaging structure.

[0057] In this embodiment, the second substrate 200 includes a second interconnect layer 21, which is bonded to the second surface 130b of the chip structure 130 and the top of the conductive structure 140. The second interconnect layer 21 electrically connects the second surface 130b of the chip structure 130 and the conductive structure 140.

[0058] In this embodiment, the second interconnect layer 21 is made of copper. Copper has low resistivity and high thermal conductivity, which helps to reduce the resistance of the first interconnect layer 103 and improve the heat dissipation capacity of the first substrate 100. In other embodiments, the material of the second interconnect layer 21 is other metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0059] In this embodiment, the second substrate 200 has a stacked structure, and the second substrate 200 further includes: a second insulating layer 22 located on the second interconnect layer 21; and a second heat dissipation layer 23 located on the second insulating layer 22.

[0060] The second insulating layer 22 is used to insulate the second interconnect layer 21 from external circuitry. In this embodiment, the second insulating layer 22 also isolates the second interconnect layer 21 from the second heat dissipation layer 23.

[0061] In this embodiment, the material of the second insulating layer 22 is silicon oxide. In other embodiments, the material of the second insulating layer 22 may also be other insulating materials, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0062] The second substrate 200 is further provided with a second heat dissipation layer 23, thereby further improving the heat dissipation capacity of the second substrate 200.

[0063] In this embodiment, the material of the second heat dissipation layer 23 is a metallic material, which is beneficial to improving the heat dissipation effect of the second heat dissipation layer 23. The material of the second heat dissipation layer 23 is a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. In this embodiment, the material of the second heat dissipation layer 23 is copper.

[0064] In this embodiment, the projection of the second substrate 200 onto the first substrate 100 exposes the connection area 100b, which facilitates the exposure of the top of the first connection terminal 110, making it easier to electrically connect the first connection terminal 110 from the top of the first connection terminal 110, thereby improving the flexibility of electrically connecting the first connection terminal 110 to an external circuit.

[0065] In this embodiment, the second substrate 200 also exposes the top of the first connection terminal 110 so as to electrically connect the second connection terminal 120 from the second connection terminal 120, thereby improving the flexibility of the second connection terminal 120 to be electrically connected to external circuits.

[0066] In this embodiment, the packaging structure further includes: a packaging layer 150, which covers the first substrate 100 and fills the space between the first substrate 100 and the second substrate 200.

[0067] The encapsulation layer 150 is used to realize the encapsulation integration between one or more device structures and the first substrate 100 and the second substrate 200. The encapsulation layer 150 can also play the roles of insulation, sealing and moisture protection, which helps to improve the reliability of the encapsulation.

[0068] As one embodiment, the encapsulation layer 150 is made of a molding compound, such as epoxy resin. Epoxy resin has advantages such as low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost. In other embodiments, the encapsulation layer 150 may also be made of other suitable encapsulation materials.

[0069] In this embodiment, the encapsulation layer 150 exposes the top of the first connection terminal 110, which facilitates electrical connection of the first connection terminal 110 from the top of the first connection terminal 110, improves the flexibility of electrically connecting the first connection terminal 110 to the external circuit, and thus improves the electrical connection freedom of the encapsulation structure.

[0070] In this embodiment, the encapsulation layer 150 also exposes the top of the second connection terminal 120, which facilitates electrical connection of the second connection terminal 120 from the top, improving the flexibility of electrically connecting the second connection terminal 120 to external circuits, and thus improving the electrical connection freedom of the encapsulation structure.

[0071] In this embodiment, the encapsulation layer 150 also exposes the top of the second substrate 200, thereby facilitating heat dissipation of the second substrate 200 and improving the heat dissipation effect of the encapsulation structure.

[0072] In this embodiment, a gap 160 exists between the side of the first connecting end 110 and the encapsulation layer 150, which reduces the risk of material overflow from the encapsulation layer 150 onto the top of the first connecting end 110. This helps ensure that the top of the first connecting end 110 can be completely exposed, thereby improving the process effect and stability of the electrical connection process when the top of the first connecting end 110 is electrically connected to form an electrical connection structure. It also improves the electrical contact performance between the subsequent electrical connection structure and the top of the first connecting end 110. In addition, heat is usually generated during the electrical connection process of forming the electrical connection structure. The gap 160 between the side of the first connecting end 110 and the encapsulation layer 150 also helps prevent materials or steps of the electrical connection process from contacting the encapsulation layer 150, thereby reducing the probability of the encapsulation layer 150 being deformed or damaged by the process and improving the integrity of the encapsulation layer 150.

[0073] The packaging structure can be formed using the packaging method described in the embodiments of the present invention, or it can be formed using other methods.

[0074] Accordingly, embodiments of the present invention also provide a packaging method. Figure 8 This is a flowchart of the encapsulation method according to an embodiment of the present invention; Figures 9 to 21 This is a schematic diagram of the structure corresponding to each step in the encapsulation method of this invention.

[0075] refer to Figures 9 to 11 , Figure 9 This is a schematic diagram of the three-dimensional structure. Figure 10 This is a top view. Figure 11 for Figure 9 A cross-sectional view along the AA direction shows a first substrate 100, including a bonding region 100a and connection regions 100b located on both sides of the bonding region 100a.

[0076] The first substrate 100 is used to provide support and bonding platform for subsequent processes. Specifically, the first substrate 100 provides support and bonding platform for the subsequent first connection terminal 110, chip structure 130, conductive structure 140 and second substrate 200.

[0077] In this embodiment, the first substrate 100 is also used to dissipate heat for the packaging structure, so as to reduce the power consumption of the packaging structure and improve the performance of the packaging structure.

[0078] In this embodiment, during the step of providing the first substrate 100, the bonding region 100a includes a first bonding region (not shown) for bonding chip structures and a second bonding region (not shown) for bonding conductive structures.

[0079] In this embodiment, in the step of providing the first substrate 100, the first substrate 100 includes a first interconnect layer 103. The first interconnect layer 103 is used for subsequent bonding of the first connection terminal 110, the chip structure 130 and the conductive structure 140 to realize electrical connection between the chip structure 130 and the first connection terminal 110, or between the conductive structure 140 and the first connection terminal 110.

[0080] In this embodiment, the first interconnect layer 103 is made of copper. Copper has low resistivity and high thermal conductivity, which helps to reduce the resistance of the first interconnect layer 103 and improve the heat dissipation capacity of the first substrate 100. In other embodiments, the material of the first interconnect layer 103 is other metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0081] In this embodiment, the first substrate 100 has a stacked structure. Specifically, the first substrate 100 includes: a first heat dissipation layer 101; a first insulating layer 102 located on the first heat dissipation layer 101; and a first interconnect layer 103 located on the first insulating layer 102.

[0082] The first substrate 100 is further provided with a first heat dissipation layer 101, thereby further improving the heat dissipation capacity of the first substrate 100.

[0083] In this embodiment, the first heat dissipation layer 101 is made of a metallic material, which is beneficial to improving the heat dissipation effect of the first heat dissipation layer 101. The material of the first heat dissipation layer 101 is a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. In this embodiment, the material of the first heat dissipation layer 101 is copper.

[0084] The first insulating layer 102 is used to achieve insulation between the first interconnect layer 103 and the external circuit. In this embodiment, the first insulating layer 102 also achieves isolation between the first interconnect layer 103 and the first heat dissipation layer 101.

[0085] In this embodiment, the material of the first insulating layer 102 is silicon oxide. In other embodiments, the material of the first insulating layer 102 may also be other insulating materials, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0086] Continue to refer to Figures 9 to 11 Provide one or more chip structures 130, the chip structure 130 including a first side 130a and a second side 130b opposite to each other.

[0087] The chip structure 130 is used to achieve package integration with the first substrate 100 and the subsequent second substrate 200.

[0088] Specifically, the chip structure 130 is used as a functional device in the package structure to enable the package structure to perform a specific function. In this embodiment, the package structure is used to form a power device, and the chip structure 130 also includes a power chip structure 130.

[0089] The first surface 130a and the second surface 130b are electrically connected, so that after the second substrate 200 is subsequently bonded to the second surface 130b of the chip structure 130 and the top of the conductive structure 140, an electrical connection between the first substrate 100 and the second substrate 200 can be realized in the vertical direction, thereby increasing the electrical connection path in the vertical direction.

[0090] Specifically, in this embodiment, in the step of providing the one or more chip structures 130, the chip structure 130 includes a chip 31 and an electrical connection layer 32 formed on the chip 31, and the electrical connection layer 32 is electrically connected to the chip 31.

[0091] As an example, the packaging structure is used to form a power device, and chip 31 includes a power chip, such as a diode, transistor, etc.

[0092] The electrical connection layer 32 is located on the upper surface of the chip along a direction perpendicular to the chip 31 and is electrically connected to the chip 31, thereby realizing the electrical connection between the first surface 130a and the second surface 130b of the chip structure 130 along the vertical direction.

[0093] In one embodiment, the electrical connection layer 32 is made of copper. Copper has low resistivity, which is beneficial for improving the electrical connection performance of the electrical connection layer 32. In other embodiments, the electrical connection layer can also be made of other metallic materials, such as silver, aluminum, etc.

[0094] Reference Figures 9 to 14One or more chip structures 130, conductive structures 140, and first connection terminals 110 are bonded on the first substrate 100. The first surface 130a of the chip structure 130 is bonded to the bonding area 100a of the first substrate 100 and is electrically connected to the first substrate 100. The conductive structure 140 is bonded to the exposed bonding area 100a of the chip structure 130 and is electrically connected to the first substrate 100. The first connection terminal 110 is bonded to the connection area 100b and is electrically connected to the first substrate 100. The first connection terminal 110 located on one side of the bonding area 100a is electrically connected to the first surface 130a through the first substrate 100, and the first connection terminal 110 located on the other side of the bonding area 100a is electrically connected to the conductive structure 140 through the first substrate 100.

[0095] One or more chip structures 130, conductive structures 140, and first connection terminals 110 are bonded on the first substrate 100 to provide a process platform for subsequently bonding a second substrate on the second surface 130b of the chip structure 130 and the top of the conductive structure 140.

[0096] Subsequently, after bonding a second substrate to the second surface 130b of the chip structure 130 and the top of the conductive structure 140, the second substrate electrically connects the second surface 130b of the chip structure 130 and the conductive structure 140. Thus, in this embodiment, through the first substrate 100, the chip structure 130, the conductive structure 140, and the second substrate, an electrical connection can be achieved between the first connection ends 110 on both sides of the bonding region 100a and between the first connection ends 110 and the chip structure 130. Moreover, a vertical electrical connection is achieved between the first surface 130a and the second surface 130b of the chip structure 130, and a vertical electrical connection is achieved between the first substrate 100 and the second substrate by the conductive structure 140. Furthermore, the electrical connection paths of the two are opposite, and the electrical connection paths can cancel each other out, which helps to reduce stray inductance.

[0097] Furthermore, compared to the scheme that only uses the first substrate to realize the first connection end located between the two sides of the bonding area and the electrical connection with the chip structure, this embodiment also realizes part of the electrical connection path through the chip structure 130, the second substrate and the conductive structure 140. This can reduce the area occupied by the electrical connection path in the first substrate 100, which not only helps to increase the area of ​​the first substrate 100 used for heat dissipation, thereby improving the heat dissipation capacity of the packaging structure, but also helps to increase the area of ​​the first substrate 100 used for bonding the chip structure 130, which in turn helps to increase the number of bonding of the chip structure 130, improve the outflow capacity of the packaging structure and optimize the performance of the packaging structure.

[0098] Specifically, in this embodiment, in the step of bonding one or more chip structures 130, conductive structures 140, and first connection terminals 110 on the first substrate 100, the chip structures 130, conductive structures 140, and first connection terminals 110 are bonded on the first interconnect layer 103; the conductive structure 140 is in contact with the first interconnect layer 103; the first surface 130a is electrically connected to the first connection terminal 110 located on one side of the bonding region 100a through the first interconnect layer 103; the conductive structure 140 is electrically connected to the first connection terminal 110 located on the other side of the bonding region 100a through the first interconnect layer 103.

[0099] The following combination Figures 9 to 14 The specific steps for bonding one or more chip structures 130, conductive structures 140 and first connection terminals 110 on the first substrate 100 are described in detail.

[0100] Continue to refer to Figures 9 to 11 One or more chip structures 130 are bonded on the bonding region 100a of the first substrate 100, and the first surface 130a is bonded to and electrically connected to the first substrate 100.

[0101] One or more chip structures 130 are bonded on the bonding region 100a of the first substrate 100 to achieve package integration between the chip structures 130 and the first substrate 100. In this embodiment, one or more chip structures 130 are bonded on the first bonding region.

[0102] In this embodiment, the step of bonding the one or more chip structures 130 includes bonding the chip structure 130 on the first interconnect layer 103 of the bonding region 100a, so that after the first connection terminal is subsequently bonded on the connection region 100b, the first surface 130a and the first connection terminal located on one side of the bonding region 100a are electrically connected through the first interconnect layer 103.

[0103] In this embodiment, the side of the chip 31 opposite to the electrical connection layer 32 is designated as the first side 130a; the side of the electrical connection layer 32 opposite to the chip 31 is designated as the second side 130b. That is, after the second substrate 200 is subsequently bonded to the second side 130b of the chip structure 130 and the top of the conductive structure 140, the chip 31 is bonded to the first substrate 100 and electrically connected to it. This shortens the signal transmission path between the chip 31 and the first substrate 100, reducing signal transmission delay. The electrical connection layer 32 is bonded to and electrically connected to the second substrate 200, thereby enabling a vertical electrical connection between the chip 31 and the second substrate 200.

[0104] In other embodiments, based on actual device and process requirements, the side of the chip opposite to the electrical connection layer 32 can be used as the second side 130b, and the side of the electrical connection layer 32 opposite to the chip can be used as the first side 130a, which can also serve to provide an electrical connection path in the vertical direction.

[0105] refer to Figures 12 to 14 , Figure 12 This is a schematic diagram of the three-dimensional structure. Figure 13 for Figure 12 The corresponding top view, Figure 14 for Figure 12 A cross-sectional view along the AA direction provides a conductive structure 140 and a first connection terminal 110.

[0106] The conductive structure 140 is subsequently bonded to the bonding region 100a of the first substrate 100 to achieve an electrical connection with the first substrate 100.

[0107] In this embodiment, the conductive structure 140 includes a columnar structure. The columnar structure has a larger volume and cross-section, which helps reduce the resistance of the electrical connection path, improves current transmission capability, and provides good electrical contact performance between the conductive structure 140 and the first substrate 100 and the second substrate. Furthermore, the columnar structure improves the positional and dimensional flexibility of the conductive structure 140. In other embodiments, based on actual process and design requirements, the conductive structure 140 can also be other structures, such as a block structure, a spherical structure, etc.

[0108] In this embodiment, the conductive structure 140 is made of copper. Copper has low resistivity and high thermal conductivity, which can further reduce the resistance of the conductive structure 140 and improve the heat dissipation capability of the packaging structure. In other embodiments, the conductive structure 140 may also be made of other metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0109] The first connection terminal 110 is used to be subsequently bonded to the connection area 100b of the first substrate 100 to achieve an electrical connection with the first substrate 100.

[0110] The first connection terminal 110 is used to connect the electrical connection terminal, which serves as the package structure, to achieve electrical connection between the package structure and external circuits or other circuit devices.

[0111] In this embodiment, the first connection terminal 110 includes a power terminal, which serves as an electrical connection channel between the package structure and the external circuit.

[0112] In this embodiment, the first connection terminal 110 is a block structure. Power terminals are typically used to conduct large currents. By selecting a block structure, the power terminal has a larger volume and cross-sectional area, correspondingly reducing its resistance. This facilitates the conduction of large currents, significantly improving the power transmission capability of the package structure. Furthermore, it allows for a larger power surface area, increasing the contact area between the power terminal and external circuits during subsequent electrical connections, reducing contact resistance, and thus improving the current transmission performance and stability between the external circuit and the package structure. Additionally, the block structure of the power terminal facilitates the conduction of heat generated by the power device to the outside during operation, improving the heat dissipation capability of the package structure. Moreover, the block structure of the first connection terminal 110 allows for flexible adjustment of its size and position, providing greater flexibility for subsequent electrical connections with external circuits.

[0113] Moreover, in this embodiment, the first connection end 110 adopts a block structure, which can form multiple first connection ends 110 on multiple first substrates in batches at one time, which is beneficial to improve packaging efficiency. Compared with the solution using lead frame, it also eliminates the step of cutting off excess frame edges, thereby not only improving the efficiency of the packaging process, but also reducing the generation of process waste and lowering costs.

[0114] In other embodiments, the shape and structure of the first connection terminal 110 can be flexibly adjusted based on actual device and process requirements. For example, the first connection terminal 110 can be a spherical structure, a columnar structure, a pin structure, etc.

[0115] In this embodiment, the first connection terminal 110 is made of copper. Copper has low resistivity, which helps to reduce the resistance of the first connection terminal 110. Furthermore, copper has high thermal conductivity, providing a low-thermal-resistance heat dissipation channel for the power device, improving heat dissipation capacity, and thus enhancing the power transmission capability of the package structure. In other embodiments, the first connection terminal 110 may also be made of other metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0116] Continue to refer to Figures 12 to 14 The conductive structure 140 is bonded on the second bonding region.

[0117] The conductive structure 140 is bonded on the second bonding region, thereby realizing the electrical connection between the conductive structure 140 and the first substrate 100.

[0118] As an example, after bonding the chip structure 130 to the first substrate 100, a conductive structure 140 is bonded to the first substrate 100. Therefore, the conductive structure 140 is bonded to the bonding region 100a exposed on the chip structure 130, and the conductive structure 140 is electrically connected to the first substrate 100. In other embodiments, the order in which the chip structure and the conductive structure are bonded to the first substrate can be flexibly adjusted. For example, the conductive structure can be bonded to the first substrate before the chip structure is bonded to the first substrate.

[0119] After the second substrate 200 is subsequently bonded to the second surface 130b of the chip structure 130 and the top of the conductive structure 140, the conductive structure 140 is used to realize the electrical connection between the first substrate 100 and the second substrate 200 in the vertical direction. The conductive structure 140 is located between the first substrate 100 and the second substrate 200, and can also provide support between the second substrate 200 and the first substrate 100, thereby improving the mechanical performance of the packaging structure.

[0120] In this embodiment, the step of bonding the conductive structure 140 on the first substrate 100 includes bonding the conductive structure 140 on the first interconnect layer 103, wherein the conductive structure 140 is in contact with the first interconnect layer 103. Specifically, in this embodiment, the conductive structure 140 is bonded on the first interconnect layer 103 exposed on the chip structure 130.

[0121] Accordingly, after the first connection end is subsequently bonded on the connection region 100b, the conductive structure 140 is electrically connected to the first connection end located on the other side of the bonding region 100a through the first interconnect layer 103.

[0122] Specifically, in this embodiment, the process of bonding the conductive structure 140 on the second bonding region includes a mounting process. The mounting process is simple and mature, which helps improve the process stability and bonding effect of the bonded conductive structure 140, and reduces costs.

[0123] refer to Figure 12 and Figure 14 , Figure 12 This is a schematic diagram of the three-dimensional structure. Figure 13 for Figure 12 The corresponding top view, Figure 14 for Figure 12 A cross-sectional view along the AA direction shows that a first connection terminal 110 is bonded to the connection area 100b, and the first connection terminal 110 is electrically connected to the first substrate 100.

[0124] Accordingly, in this embodiment, after the chip structure 130, the conductive structure 140 and the first connection terminal 110 are bonded on the first substrate 100, the first connection terminal 110 located on one side of the bonding area 100a is electrically connected to the first surface 130a through the first substrate 100, and the first connection terminal 110 located on the other side of the bonding area 100a is electrically connected to the conductive structure 140 through the first substrate 100.

[0125] As an example, the power terminal located on one side of the bonding region 100a is used as an AC power terminal 110b, and the power terminal located on the other side of the bonding region 100a is used as a DC power terminal 110a. Thus, the AC power terminal 110b and the DC power terminal 110a, as well as the chip structure 130, can be electrically connected through the first substrate 100, the chip structure 130, the conductive structure 140, and the second substrate 200.

[0126] Specifically, in this embodiment, the DC power terminal 110a includes a positive DC power terminal 110a+ (DC+) and a negative DC power terminal 110a- (DC-). The positive DC power terminal 110a+ and the negative DC power terminal 110a- are located on the same side of the bonding region 100a, so as to realize electrical connection with the AC power terminal 110b located on the other side of the bonding region 100a, respectively.

[0127] In this embodiment, the step of bonding the first connection terminal 110 on the connection region 100b includes bonding the first connection terminal 110 on the first interconnect layer 103 of the connection region 100b, thereby electrically connecting the first connection terminal 110 and the first interconnect layer 103.

[0128] Specifically, in this embodiment, the process of bonding the first connection terminal 110 to the connection area 100b includes a surface mount process. The surface mount process is simple and mature, which helps improve the stability and bonding effect of bonding the first connection terminal 110, and reduces process costs. As an example, the first connection terminal 110 is bonded to the connection area 100b using conductive adhesive or solder.

[0129] Continue to refer to Figures 12 to 14In this embodiment, before the step of bonding one or more chip structures 130, conductive structures 140 and first connection terminals 110 on the first substrate 100, the packaging method further includes: bonding a second connection terminal 120 on the connection area 100b; the second connection terminal 120 includes a signal terminal for leading out the signal terminals of the packaging structure to realize the signal connection between the packaging structure and the external circuit.

[0130] As an example, after bonding the first connector 110 to the first substrate 100, the second connector 120 is bonded to the exposed connection area 100b of the first connector 110. In other embodiments, the order in which the first and second connectors are bonded to the first substrate can be flexibly adjusted. For example, the first and second connectors can be bonded to the first substrate in the same step; or, the first connector can be bonded to the exposed connection area of ​​the second substrate after the second connector is bonded to the first substrate.

[0131] In this embodiment, the second connection terminal 120 is bonded to the first interconnect layer 103.

[0132] In this embodiment, the second connection terminal 120 includes a pin structure. In this embodiment, the second connection terminal 120 includes a signal terminal. Generally, the current in an electrical signal path is relatively small, and signal transmission can be achieved through a pin structure. Furthermore, the pin structure is low-cost and allows for flexible adjustment of the position of the second connection terminal 120, thereby reducing the cost of the packaging structure and improving the flexibility of the electrical connection between the second connection terminal 120 and external circuits.

[0133] In other embodiments, the shape and structure of the second connection end 120 can be flexibly adjusted based on actual device and process requirements. For example, the second connection end 120 can be a block structure, a spherical structure, a columnar structure, etc.

[0134] In this embodiment, the process of bonding the second connection terminal 120 on the connection area 100b includes a mounting process. The mounting process is highly mature and can bond multiple second connection terminals 120 on multiple first substrates 100 in a single batch, which is beneficial for improving packaging efficiency. Compared with the lead frame process, it also eliminates the step of cutting off excess frame edges, thereby not only improving the efficiency of the packaging process but also reducing process waste and lowering costs. As an example, the second connection terminal 120 is bonded on the connection area 100b using conductive adhesive or solder.

[0135] In one embodiment, the second connection terminal 120 is a signal terminal, and the chip 31 and the second connection terminal 120 are electrically connected only through the first substrate 100, thereby reducing changes to the signal transmission path and improving signal transmission stability and efficiency. Specifically, in this embodiment, the chip 31 and the second connection terminal 120 are electrically connected through the first interconnect layer 103.

[0136] In other embodiments, based on actual needs, the electrical connection path between the second connection terminal 120 and the chip structure can also be achieved through the conductive structure 140, the first substrate 100, and the second substrate 200.

[0137] In this embodiment, the bonding of the conductive structure 130, the first connection terminal 110, and the second connection terminal 120 onto the first substrate 100 is described as an example after the chip structure 130 is bonded onto the first substrate 100. In other embodiments, the order in which the chip structure, the conductive structure, the first connection terminal, and the second connection terminal are bonded onto the first substrate can be flexibly adjusted. For example, the conductive structure, the first connection terminal, and the second connection terminal can be bonded onto the first substrate in the same step, or they can be bonded onto the first substrate in different steps.

[0138] refer to Figures 15 to 19 , Figure 15 This is a schematic diagram of the three-dimensional structure. Figure 16 (a) Figure 18 (a) A top view on the first substrate, excluding the first electrical connection path and the second electrical connection path. Figure 16 (b) Figure 18 (b) A top view on the second substrate, excluding the first electrical connection path and the second electrical connection path, respectively. Figure 17 This is a cross-sectional view along the first electrical connection path. Figure 19 The image is a cross-sectional view along the second electrical connection path. A second substrate 200 is bonded to the second surface 130b of the chip structure 130 and the top of the conductive structure 140. The second substrate 200 electrically connects the second surface 130b of the chip structure 130 to the conductive structure 140.

[0139] The second substrate 200 is bonded to the top surface of the chip structure 130 and the conductive structure 140, and is used to electrically connect the chip structure 130 and the conductive structure 140. In this embodiment, the second substrate 200 is also used to dissipate heat from the packaging structure, thereby improving the heat dissipation capability of the packaging structure.

[0140] In this embodiment, the first surface 130a is electrically connected to the first substrate 100; a conductive structure 140 is bonded to the bonding area 100a exposed on the chip structure 130, and is electrically connected to the first substrate 100; a first connecting end 110 is bonded to the connecting area 100b, the first connecting end 110 located on one side of the bonding area 100a being electrically connected to the first surface 130a through the first substrate 100; the first connecting end 110 located on the other side of the bonding area 100a being electrically connected to the conductive structure 140 through the first substrate 100; therefore, a second substrate 200 is bonded to the second surface 130b of the chip structure 130 and the top of the conductive structure 140, the second substrate 200 being electrically connected to the second surface 130b of the chip structure 130 and the conductive structure 140. After the electrical structure 140, electrical connections are achieved between the first connection terminals 110 on both sides of the bonding region 100a and between the first connection terminal 110 and the chip structure 130 through the first substrate 100, the chip structure 130, the conductive structure 140 and the second substrate 200. Moreover, a vertical electrical connection is achieved between the first surface 130a and the second surface 130b of the chip structure 130, and a vertical electrical connection is achieved between the first substrate 100 and the second substrate 200 through the conductive structure 140. The electrical connection paths of the two are opposite, and the electrical connection paths can cancel each other out, which helps to reduce stray inductance.

[0141] Furthermore, compared to the scheme that only uses the first substrate to realize the first connection end located between the two sides of the bonding area and the electrical connection with the chip structure, this embodiment also realizes part of the electrical connection path through the chip structure 130, the second substrate 200 and the conductive structure 140. This can reduce the area occupied by the electrical connection path in the first substrate 100, which not only helps to increase the area of ​​the first substrate 100 used for heat dissipation, thereby improving the heat dissipation capacity of the packaging structure, but also helps to increase the area of ​​the first substrate 100 used for bonding the chip structure 130, which in turn helps to increase the number of bonding of the chip structure 130, improve the outflow capacity of the packaging structure and optimize the performance of the packaging structure.

[0142] In this embodiment, the step of bonding the second substrate 200 to the second surface 130b of the chip structure 130 and the top of the conductive structure 140 includes: providing the second substrate 200, which includes a second interconnect layer 21.

[0143] Accordingly, in the step of bonding the second substrate 200 to the second surface 130b of the chip structure 130 and the top of the conductive structure 140, the second interconnect layer 21 is bonded to the second surface 130b of the chip structure 130 and the top of the conductive structure 140, and the second interconnect layer 21 is electrically connected to the second surface 130b of the chip structure 130 and the conductive structure 140.

[0144] In this embodiment, the second interconnect layer 21 is made of copper. Copper has low resistivity and high thermal conductivity, which helps to reduce the resistance of the first interconnect layer 103 and improve the heat dissipation capacity of the first substrate 100. In other embodiments, the material of the second interconnect layer 21 is other metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0145] In this embodiment, in the step of providing the second substrate 200, the second substrate 200 is a stacked structure; the second substrate 200 further includes: a second insulating layer 22 located on the second interconnect layer 21; and a second heat dissipation layer 23 located on the second insulating layer 22.

[0146] The second insulating layer 22 is used to insulate the second interconnect layer 21 from external circuitry. In this embodiment, the second insulating layer 22 also isolates the second interconnect layer 21 from the second heat dissipation layer 23.

[0147] In this embodiment, the material of the second insulating layer 22 is silicon oxide. In other embodiments, the material of the second insulating layer 22 may also be other insulating materials, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0148] The second substrate 200 is further provided with a second heat dissipation layer 23, thereby further improving the heat dissipation capacity of the second substrate 200.

[0149] In this embodiment, the material of the second heat dissipation layer 23 is a metallic material, which is beneficial to improving the heat dissipation effect of the second heat dissipation layer 23. The material of the second heat dissipation layer 23 is a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. In this embodiment, the material of the second heat dissipation layer 23 is copper.

[0150] In this embodiment, during the step of bonding the second substrate 200 to the second surface 130b of the chip structure 130 and the top of the conductive structure 140, the projection of the second substrate 200 onto the first substrate 100 exposes the connection area 100b, which facilitates the exposure of the top of the first connection terminal 110, making it easier to electrically connect the first connection terminal 110 from the top, thereby improving the flexibility of electrically connecting the first connection terminal 110 to external circuits.

[0151] In this embodiment, during the step of bonding the second substrate 200 to the second surface 130b of the chip structure 130 and the top of the conductive structure 140, the second substrate 200 also exposes the top of the first connection terminal 110 so as to electrically connect the second connection terminal 120 from the second connection terminal 120, thereby improving the flexibility of electrically connecting the second connection terminal 120 to external circuits.

[0152] Specifically, in this embodiment, the electrical connection path between the positive DC power terminal 110a+ and the AC power terminal 110b is used as the first electrical connection path P1 to form an upper bridge circuit; the electrical connection path between the AC power terminal 110b and the negative DC power terminal 110a- is used as the second electrical connection path P2 to form a lower bridge circuit.

[0153] In this embodiment, reference Figure 20 and Figure 21 , Figure 20 This is a schematic diagram of the three-dimensional structure. Figure 21 for Figure 20 According to the cross-sectional view along the first electrical connection path, the packaging method further includes: bonding a first connection terminal 110 on the connection region 100b, and bonding a second substrate 200 on the second surface 130b of the chip structure 130 and the top of the conductive structure 140, and then covering the first substrate 100 with an encapsulation layer 150, the encapsulation layer 150 filling the space between the first substrate 100 and the second substrate 200 and exposing the top of the first connection terminal 110.

[0154] The encapsulation layer 150 is used to realize the encapsulation integration between one or more device structures and the first substrate 100 and the second substrate 200. The encapsulation layer 150 can also play the roles of insulation, sealing and moisture protection, which helps to improve the reliability of the encapsulation.

[0155] As one embodiment, the encapsulation layer 150 is made of a molding compound, such as epoxy resin. Epoxy resin has advantages such as low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost. In other embodiments, the encapsulation layer 150 may also be made of other suitable encapsulation materials.

[0156] In this embodiment, the encapsulation layer 150 exposes the top of the first connection terminal 110, which facilitates electrical connection of the first connection terminal 110 from the top of the first connection terminal 110, improves the flexibility of electrically connecting the first connection terminal 110 to the external circuit, and thus improves the electrical connection freedom of the encapsulation structure.

[0157] In this embodiment, the encapsulation layer 150 also exposes the top of the second connection terminal 120, which facilitates electrical connection of the second connection terminal 120 from the top, improving the flexibility of electrically connecting the second connection terminal 120 to external circuits, and thus improving the electrical connection freedom of the encapsulation structure.

[0158] In this embodiment, the encapsulation layer 150 also exposes the top of the second substrate 200, thereby facilitating heat dissipation of the second substrate 200 and improving the heat dissipation effect of the encapsulation structure.

[0159] In this embodiment, during the step of covering the encapsulation layer 150 on the first substrate 100, a gap 160 exists between the encapsulation layer 150 and the side of the first connection end 110. This reduces the risk of material overflow from the encapsulation layer 150 onto the top of the first connection end 110, thus ensuring that the top of the first connection end 110 is completely exposed. This, in turn, improves the process effect and stability of the electrical connection process when the top of the first connection end 110 is electrically connected to form an electrical connection structure, and also improves the electrical contact performance between the subsequent electrical connection structure and the top of the first connection end 110. Furthermore, during the electrical connection process of forming the electrical connection structure, heat is usually generated. The gap 160 between the side of the first connection end 110 and the encapsulation layer 150 also helps prevent materials or steps of the electrical connection process from contacting the encapsulation layer 150, thereby reducing the probability of the encapsulation layer 150 being deformed or damaged by the process and improving the integrity of the encapsulation layer 150.

[0160] In this embodiment, the encapsulation layer 150 is formed using a molding process.

[0161] While the embodiments of the present invention have been disclosed above, the invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the invention should be determined by the scope defined in the claims.

Claims

1. A packaging structure, characterized in that, include: The first substrate includes a bonding region and connection regions located on both sides of the bonding region; The first connection terminal is bonded to the connection area and electrically connected to the first substrate. One or more chip structures are bonded to a bonding area of ​​the first substrate. The chip structure includes a first side and a second side facing away from each other. The first side is bonded to the first substrate, and the first side is electrically connected to a first connection terminal located on one side of the bonding area through the first substrate. A conductive structure is bonded to the exposed bonding area of ​​the chip structure and electrically connected to the first substrate; the conductive structure is electrically connected to a first connection end located on the other side of the bonding area through the first substrate. The second substrate is bonded to the second side of the chip structure and the top of the conductive structure, and the second substrate is electrically connected to the second side of the chip structure and the conductive structure.

2. The packaging structure as described in claim 1, characterized in that, The projection of the second substrate onto the first substrate exposes the connection area.

3. The packaging structure as described in claim 1 or 2, characterized in that, The first connection terminal includes a power terminal.

4. The packaging structure as described in claim 3, characterized in that, The first connection end is a block structure.

5. The packaging structure as described in claim 3, characterized in that, The power terminal located on one side of the bonding region is used as an AC power terminal, and the power terminal located on the other side of the bonding region is used as a DC power terminal.

6. The packaging structure as described in claim 5, characterized in that, The DC power terminals include a positive DC power terminal and a negative DC power terminal.

7. The packaging structure as described in claim 2, characterized in that, The packaging structure further includes: a packaging layer covering the first substrate and filling the space between the first substrate and the second substrate; the packaging layer exposes the first connection end and the top of the second substrate.

8. The packaging structure as described in claim 7, characterized in that, There is a gap between the side of the first connection end and the encapsulation layer.

9. The packaging structure as described in claim 1, characterized in that, The chip structure includes a chip and an electrical connection layer located on the chip, and the electrical connection layer is electrically connected to the chip.

10. The packaging structure as described in claim 9, characterized in that, The side of the chip that is opposite to the electrical connection layer is called the first side; the side of the electrical connection layer that is opposite to the chip is called the second side.

11. The packaging structure as described in claim 1, characterized in that, The conductive structure includes a columnar structure.

12. The packaging structure as described in claim 1, characterized in that, The conductive structure is made of copper.

13. The packaging structure as described in claim 1, characterized in that, The first substrate includes a first interconnect layer; The first connection terminal, the chip structure, and the conductive structure are bonded to the first interconnect layer; The first interconnect layer electrically connects the first surface to a first connection terminal located on one side of the bonding region; The first interconnect layer electrically connects the conductive structure to a first connection terminal located on the other side of the bonding region.

14. The packaging structure as described in claim 1, characterized in that, The second substrate includes a second interconnect layer bonded to a second side of the chip structure and the top of the conductive structure, wherein the second interconnect layer is electrically connected to the second side of the chip structure and the conductive structure.

15. The packaging structure as described in claim 1, characterized in that, The packaging structure further includes: a second connection terminal, bonded to the connection area exposed by the first connection terminal; the second connection terminal includes a signal terminal.

16. The packaging structure as described in claim 15, characterized in that, The second connection end includes a pin structure.

17. A packaging method, characterized in that, include: A first substrate is provided, including a bonding region and connection regions located on both sides of the bonding region; One or more chip structures are provided, the chip structures including a first side and a second side facing away from each other; One or more chip structures, conductive structures, and first connection terminals are bonded on the first substrate; a first side of the chip structure is bonded to a bonding area of ​​the first substrate and is electrically connected to the first substrate; the conductive structure is bonded to the exposed bonding area of ​​the chip structure and is electrically connected to the first substrate; the first connection terminal is bonded to the connection area and is electrically connected to the first substrate; wherein, the first connection terminal located on one side of the bonding area is electrically connected to the first side through the first substrate, and the first connection terminal located on the other side of the bonding area is electrically connected to the conductive structure through the first substrate. A second substrate is bonded to the second side of the chip structure and the top of the conductive structure, and the second substrate is electrically connected to the second side of the chip structure and the conductive structure.

18. The packaging method as described in claim 17, characterized in that, In the step of bonding a second substrate to the second side of the chip structure and the top of the conductive structure, the projection of the second substrate onto the first substrate exposes the connection area.

19. The packaging method as described in claim 17 or 18, characterized in that, The first connection terminal includes a power terminal.

20. The packaging method as described in claim 17, characterized in that, The packaging method further includes: bonding one or more chip structures, conductive structures and first connection terminals on the first substrate, and bonding a second substrate on the second side of the chip structure and the top of the conductive structure, and then covering the first substrate with an encapsulation layer, the encapsulation layer filling the space between the first substrate and the second substrate and exposing the top of the first connection terminal and the second substrate.

21. The packaging method as described in claim 20, characterized in that, In the step of covering the encapsulation layer on the first substrate, there is a gap between the encapsulation layer and the side of the first connection end.

22. The packaging method as described in claim 17, characterized in that, In the step of providing a first substrate, the bonding region includes a first bonding region for bonding chip structures and a second bonding region for bonding conductive structures; the step of bonding one or more chip structures, conductive structures, and a first connection terminal on the first substrate includes: providing conductive structures and a first connection terminal; bonding one or more chip structures on the first bonding region; bonding the conductive structures on the second bonding region; and bonding the first connection terminal on the connection region.

23. The packaging method as described in claim 22, characterized in that, The process of bonding the conductive structure on the second bonding region includes a mounting process.

24. The packaging method as described in claim 22, characterized in that, The process of bonding the first connection end to the connection area includes a mounting process.

25. The packaging method as described in claim 17, characterized in that, In the step of providing the one or more chip structures, the chip structure includes a chip and an electrical connection layer formed on the chip, the electrical connection layer being electrically connected to the chip.

26. The packaging method as described in claim 25, characterized in that, The side of the chip that is opposite to the electrical connection layer is called the first side; the side of the electrical connection layer that is opposite to the chip is called the second side.

27. The packaging method as described in claim 17, characterized in that, In the step of providing a first substrate, the first substrate includes a first interconnect layer; In the step of bonding one or more chip structures, conductive structures, and first connection terminals on the first substrate, the chip structures, conductive structures, and first connection terminals are bonded on the first interconnect layer; the conductive structure is in contact with the first interconnect layer; the first surface and the first connection terminal located on one side of the bonding area are electrically connected through the first interconnect layer; the conductive structure and the first connection terminal located on the other side of the bonding area are electrically connected through the first interconnect layer.

28. The packaging method as described in claim 17, characterized in that, The step of bonding a second substrate to the second side of the chip structure and the top of the conductive structure includes: providing a second substrate, the second substrate including a second interconnect layer; In the step of bonding a second substrate to the second side of the chip structure and the top of the conductive structure, the second interconnect layer is bonded to the second side of the chip structure and the top of the conductive structure, and the second interconnect layer is electrically connected to the second side of the chip structure and the conductive structure.

29. The packaging method as described in claim 17, characterized in that, The packaging method further includes, in the step of bonding one or more chip structures, conductive structures and a first connection terminal on the first substrate, bonding a second connection terminal on the connection area exposed by the first connection terminal; the second connection terminal includes a signal terminal.

30. The packaging method as described in claim 29, characterized in that, The process of bonding the second connection end to the exposed connection area of ​​the first connection end includes a mounting process.

Images