Double-pulse test method suitable for three-phase common-substrate power module
By calculating the stray inductance of the common part of the three-phase common substrate power module and setting new constraints, the overvoltage stress problem of inverter operation in the existing test method is solved, and more reasonable test results and higher reliability are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHEJIANG YIKONG POWER SYST CO LTD
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-12
AI Technical Summary
Existing dual-pulse testing methods cannot effectively account for the phase-to-phase coupling in three-phase common-base power modules, which may lead to overvoltage stress problems during inverter operation.
By calculating the stray inductance of the common part of the three-phase common substrate power module and setting new constraints based on the calculation results, a double-pulse test is performed to avoid overvoltage stress caused by stray inductance voltage drop during inverter operation.
Accurate calculation of stray inductance improves the rationality of test results, enhances the reliability of power modules, and avoids overvoltage stress problems during inverter operation.
Smart Images
Figure CN122017508A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power module testing technology, specifically relating to a dual-pulse testing method suitable for three-phase common substrate power modules. Background Technology
[0002] Power modules are widely used in existing automotive high-voltage electric drive systems. Conventional power modules use three independent ceramic substrates; while three-phase common-substrate power modules integrate all three phases onto a single ceramic substrate, thus reducing module size and cost. Schematic diagrams of conventional and three-phase common-substrate power modules are attached. Figure 1 As shown.
[0003] The commonly used dynamic testing method for power modules is the double-pulse test. The conventional double-pulse test measures only one phase's double pulse at a time, adjusting the drive parameters to ensure the voltage stress on that phase's transistor does not exceed a set value. This conventional double-pulse test method works well for conventional power modules, but its applicability to three-phase common-base power modules is problematic. This is because in a conventional power module, each phase is connected to a DC support capacitor via its own independent DC terminal, resulting in less coupling between phases and a smaller stray inductance in the common section. However, in a three-phase common-base power module, the phases share a single base plate and are connected to the DC support capacitor via a common DC terminal, leading to greater coupling between phases and a larger stray inductance in the common section. If the conventional double-pulse test method is used to test a three-phase common-base power module, the influence of the tested phase on the other two phases cannot be considered. This can lead to a situation where, during inverter operation, a phase with a larger di / dt when turned on results in a larger voltage drop across the stray inductance in the common section, potentially causing overvoltage stress on the transistors in the other two phases that are turned off. Summary of the Invention
[0004] The main objective of this invention is to provide a double-pulse testing method suitable for three-phase common-base power modules. This method calculates the stray inductance of the common section based on the test waveform and then calculates new constraint conditions. Performing double-pulse testing according to these new constraint conditions avoids overvoltage stress caused by the stray inductance of the common section during inverter operation, resulting in more reasonable double-pulse test results.
[0005] To achieve the above objectives, the present invention provides a dual-pulse testing method suitable for three-phase common-substrate power modules, comprising the following steps: Step S1: Perform a double-pulse test with bridge-generated waveforms, assuming the stray inductance of the common part is... Each phase has the same stray inductance, which is _____. The specific implementation is as follows: Step S1.1: Calculate the stray inductance during single-phase wave generation. ; Step S1.2: Calculate the stray inductance when three phases are connected in parallel. ; Step S1.3: Calculate the stray inductance of the common part. ; Step S1.4: Calculate the newly added constraints. ; Step S2: Perform a double-pulse test for the lower bridge wave generation.
[0006] As a further preferred technical solution to the above technical solution, step S1.1 is specifically implemented as follows: Take any bridge arm of the upper phase of the bridge, measure the current flowing through the DC+ terminal using a current probe, and measure the voltage across the upper phase's transistor using a voltage probe, thus completing the construction of the double-pulse test circuit for single-phase waveform generation; and assume that the current and voltage acquired by the oscilloscope and the corresponding time series during the second turn-on are respectively... and The sampling data time interval of the oscilloscope is ; The original waveform is subjected to mean filtering, and the filtering order is n. f And the filtered current and voltage sequences are respectively and The bus voltage is calculated as follows: (1); right Perform the difference, where let Then there is, (2); First, assume there is no delay between the voltage probe and the current probe, that is, the delay between the voltage probe and the current probe... And define a curve sequence containing the gap interval. Its satisfaction (3); in, The total stray inductance of the power circuit to be calculated; Define the computation The gap range is ,in, For curve sequences The point corresponding to the minimum value in the range, that is, (4); The maximum gap amplitude is ,definition For curve sequences The point closest to the preset value in the data, i.e. (5); definition and exist The gap distance is d Then there is, (6); The stray inductance includes the DC support capacitor and the stray inductance of the power module, with a maximum value of [missing information]. for Using a step size of 0.1nH, points were scanned to obtain... ,for For each value of , there is a corresponding curve. and distance d Find all d minimum value Then the corresponding That is, during the delay The total stray inductance is calculated below; Because there is a time delay between the actual voltage probe and the current probe, it is necessary to convert the current data... Perform a translation, and let the absolute value of the maximum delay between the voltage probe and the current probe be [value missing]. Then the maximum number of translation points is obtained. satisfy, (7); when When translating to the left, the number of translation points is: , By filling in the missing data on the right side after the translation, we can obtain the translated current. for, (8); when When translating to the right, the number of translation points is: , By filling in the missing data on the left side after the translation, the current after translation can be obtained. for, (9); Referring to equations (2) to (6), the same translation point is used. The current after as well as Calculate the gap distance d as well as Find the minimum value in all cases. If the smallest Appearing in the current If there is no translation, then delay. If the smallest Appearing in the current During translation, let the minimum be... Translation point at the time of appearance Then the calculated probe delay is, (10); Among them, when When shifting to the left, the actual current probe lags behind the voltage probe. ;when When shifting to the right, the actual voltage probe lags behind the current probe. ; Therefore, in all cases, the smallest corresponding That is, during the delay The total stray inductance is calculated below. L 1; therefore, (11).
[0007] As a further preferred technical solution to the above technical solution, step S1.2 is specifically implemented as follows: The three-phase upper bridges are connected in parallel, using the same double-pulse waveform. Assuming the tested bridge arm is also the phase from step S1.1, the current probe measures the current flowing through the DC+ terminal, and the voltage probe measures the voltage across the upper bridge tube of phase U. Referring to step S1.1, based on the measured voltage and current waveforms during the second turn-on, the stray inductance during the three-phase parallel waveform generation is calculated. , (12).
[0008] As a further preferred technical solution to the above technical solution, in step S1.3, the calculations obtained from steps S1.1 and S1.2 are... and By combining equations (11) and (12), the stray inductance of the common part is obtained. for, (13).
[0009] As a further preferred technical solution to the above technical solution, in step S1.4, it is assumed that the allowable peak voltage of the power module in actual application is... Then we get the largest satisfy, (14); The newly added constraint is that, during the double-pulse test, appropriate drive parameters must be selected to ensure the current drop phase during the turn-on of the transistor. The absolute value does not exceed .
[0010] The beneficial effects of this invention are as follows: 1. This invention uses a dual-pulse test involving single-phase and three-phase parallel pulse generation to accurately calculate the stray inductance of the common part of a three-phase common substrate power module, thus overcoming the shortcomings of conventional testing methods.
[0011] 2. This invention calculates the current change rate constraint value based on the common stray inductance. Using this constraint for dual-pulse testing can effectively avoid overvoltage stress problems in other phase transistors caused by the common stray inductance voltage drop during inverter operation.
[0012] 3. The test method of the present invention is applicable to three-phase common substrate power modules, and the test results are more reasonable, which can improve the reliability of power modules in practical applications. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of a conventional power module and a three-phase common substrate power module.
[0014] Figure 2 This is a schematic diagram of the dual-pulse testing method applicable to three-phase common substrate power modules according to the present invention.
[0015] Figure 3 This is a schematic diagram of the installation of a single-phase double-pulse test circuit.
[0016] Figure 4 This is an example diagram of the current and voltage waveforms during the second turn-on.
[0017] Figure 5 for and Example diagram of waveform matching.
[0018] Figure 6 This is a schematic diagram of the installation of a three-phase parallel wave-generating double-pulse test circuit. Detailed Implementation
[0019] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.
[0020] In the preferred embodiments of the present invention, those skilled in the art should note that the three-phase common substrate power module and the like involved in the present invention can be regarded as prior art.
[0021] Preferred embodiment.
[0022] like Figure 2-6 As shown, this invention discloses a dual-pulse testing method suitable for three-phase common-substrate power modules, comprising the following steps: Step S1: Perform a double-pulse test with bridge-generated waveforms, assuming the stray inductance of the common part is... Each phase has the same stray inductance, which is _____. (Step S1 only takes the double-pulse test of the upper bridge wave as an example to explain the calculation of its stray inductance and the final constraint conditions.) The specific implementation is as follows: Step S1.1: Calculate the stray inductance during single-phase wave generation. ; Step S1.2: Calculate the stray inductance when three phases are connected in parallel. ; Step S1.3: Calculate the stray inductance of the common part. ; Step S1.4: Calculate the newly added constraints. ; Step S2: Perform a double-pulse test for the lower bridge wave (the calculation principle and method are the same as the sub-steps of step S1).
[0023] Specifically, step S1.1 is implemented as follows: Take any bridge arm of the upper phase (e.g., phase U), and measure the current flowing through the DC+ terminal using a current probe and the voltage across the upper phase transistor using a voltage probe. This completes the construction of the double-pulse test circuit for single-phase waveform generation (see attached diagram for the installation schematic of the double-pulse test circuit for single-phase waveform generation). Figure 3 (as shown); and assume that during the second power-on, the current and voltage acquired by the oscilloscope and the corresponding time series are respectively and (k=1,2,…,n), the sampling data time interval of the oscilloscope is (An example waveform diagram of the second activation is attached.) Figure 4 (as shown) The original waveform is subjected to mean filtering, and the filtering order is n. f (Filtering order n) f The value needs to be appropriate. If the filter order is too low, the waveform of the calculated di / dt may be too poor, thus affecting the accuracy of the calculated stray inductance. If the filter order is too high, it may be impossible to correctly select the gap interval for calculating the stray inductance, resulting in the inability to calculate the stray inductance or an incorrect calculated value. Typically, n can be chosen as the appropriate value. f =80), and the filtered current and voltage sequences are respectively and (k=1,2,…,nn) f +1), calculate the bus voltage as follows: (1); Where, n DC n is an integer greater than 1. To ensure calculation precision, n... DC It cannot be too small; usually n DC 100 is acceptable; right Perform the difference, where let Then there is, (2); First, assume there is no delay between the voltage probe and the current probe, that is, the delay between the voltage probe and the current probe... And define a curve sequence containing the gap interval. Its satisfaction (3); in, The total stray inductance of the power circuit to be calculated; Define the computation The gap range is ,in, For curve sequences The point corresponding to the minimum value in the range, that is, (4); The maximum gap amplitude is For ease of calculation, define For curve sequences The point closest to the preset value (10% of the maximum gap amplitude) is selected (ideally, 0% to 100% of the maximum gap amplitude, i.e., a complete gap; however, selecting 0% or too small a percentage may lead to finding an incorrect location point that is not within the gap range. Therefore, to avoid finding an incorrect location point, 10% of the maximum gap amplitude is selected as the preset value, i.e., the starting point of the gap interval used for calculation). (5); definition and exist The gap distance is d Then there is, (6); Stray inductance including DC support capacitors and stray inductance of power modules (different capacitor designs and different module designs will affect this). ), set the maximum for (generally (A value of 40nH can be used), with a step size of 0.1nH, by scanning points, respectively... ,for For each value of , there is a corresponding curve. and distance d Find all d minimum value Then the corresponding That is, during the delay The total stray inductance is calculated below; Because there may be a time delay between the actual voltage probe and the current probe, it is necessary to convert the current data... Perform a translation, and let the absolute value of the maximum delay between the voltage probe and the current probe be [value missing]. (generally (If we take 40ns), then we can obtain the maximum number of translation points. satisfy, (7); when When translating to the left, the number of translation points is: , By filling in the missing data on the right side after the translation, we can obtain the translated current. for, (8); when When translating to the right, the number of translation points is: , By filling in the missing data on the left side after the translation, the current after translation can be obtained. for, (9); Referring to equations (2) to (6), the same translation point is used. The current after (m=1,2,…,nn) f +1) and (k=1,2,…,nn) f +1) Calculate the gap distance d as well as Find the minimum value in all cases (i.e., translation to the left, no translation, and translation to the right). If the smallest Appearing in the current If there is no translation, then delay. If the smallest Appearing in the current During translation, let the minimum be... Translation point at the time of appearance Then the calculated probe delay is, (10); Among them, when When shifting to the left, the actual current probe lags behind the voltage probe. ;when When shifting to the right, the actual voltage probe lags behind the current probe. ; Therefore, in all cases (i.e., translation to the left, no translation, and translation to the right), the minimum... corresponding That is, during the delay The total stray inductance is calculated below. L 1 (Calculate probe delay by matching gap intervals) With stray inductance L 1 of and The waveform example is attached. Figure 5 (as shown) Therefore, according to the appendix Figure 3 It can be seen that, (11).
[0024] More specifically, step S1.2 is implemented as follows: The three phases are connected in parallel, and a single double-pulse waveform is used (the installation diagram for the double-pulse test when generating waveforms in parallel three phases is attached). Figure 6 As shown), assuming the bridge arm being tested is also the phase from step S1.1 (e.g., the upper bridge of phase U), where the current probe measures the current flowing through the DC+ terminal and the voltage probe measures the voltage across the upper bridge tube of phase U, then referring to step S1.1, based on the measured voltage and current waveforms during the second turn-on, the stray inductance during three-phase parallel waveform generation can also be calculated. According to the appendix Figure 6 It can be seen that, (12).
[0025] Furthermore, in step S1.3, the values calculated based on steps S1.1 and S1.2 are... and By combining equations (11) and (12), the stray inductance of the common part is obtained. for, (13).
[0026] Furthermore, in step S1.4, it is assumed that the allowable peak voltage of the power module in practical applications is... (For example, for a power module with a nominal maximum voltage of 750V, considering a safety margin, its allowable peak voltage can be set to 720V, i.e.) ), then the largest satisfy, (14); The newly added constraint is that, during the double-pulse test, appropriate drive parameters must be selected to ensure the current drop phase during the turn-on of the transistor. The absolute value does not exceed .
[0027] This invention provides a double-pulse testing method suitable for three-phase common-base power modules. Traditional double-pulse testing methods for three-phase common-base power modules only test the double pulse of one phase at a time, neglecting the coupling between phases. This can lead to a situation where, during inverter operation, one phase has a large di / dt when turned on, resulting in a large voltage drop across the stray inductance of the common section. This, in turn, can cause overvoltage stress on the transistors of the other two phases that are turned off. This invention calculates the stray inductance of the common section by using single-phase pulse generation and three-phase parallel pulse generation methods, and calculates new constraint conditions. The double-pulse test is performed under the new constraints to avoid overvoltage stress caused by stray inductance in the common part during inverter operation, thus making the double-pulse test results more reasonable.
[0028] It is worth mentioning that the technical features such as the three-phase common substrate power module involved in this patent application should be regarded as prior art. The specific structure, working principle, and possible control methods and spatial arrangement of these technical features can be adopted using conventional choices in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated in detail.
[0029] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.
Claims
1. A dual-pulse test method suitable for three-phase common-substrate power modules, characterized in that, Includes the following steps: Step S1: Perform a double-pulse test with bridge-generated waveforms, assuming the stray inductance of the common part is... Each phase has the same stray inductance, which is _____. The specific implementation is as follows: Step S1.1: Calculate the stray inductance during single-phase wave generation. ; Step S1.2: Calculate the stray inductance when three phases are connected in parallel. ; Step S1.3: Calculate the stray inductance of the common part. ; Step S1.4: Calculate the newly added constraints. ; Step S2: Perform a double-pulse test for the lower bridge wave generation.
2. The dual-pulse test method for a three-phase common-substrate power module according to claim 1, characterized in that, Step S1.1 is implemented as follows: Take any bridge arm of the upper phase of the bridge, measure the current flowing through the DC+ terminal using a current probe, and measure the voltage across the upper phase's transistor using a voltage probe, thus completing the construction of the double-pulse test circuit for single-phase waveform generation; and assume that the current and voltage acquired by the oscilloscope and the corresponding time series during the second turn-on are respectively... and The sampling data time interval of the oscilloscope is ; The original waveform is subjected to mean filtering, and the filtering order is n. f And the filtered current and voltage sequences are respectively and The bus voltage is calculated as follows: （1）； right Perform the difference, where let Then there is, （2）； First, assume there is no delay between the voltage probe and the current probe, that is, the delay between the voltage probe and the current probe... And define a curve sequence containing the gap interval. Its satisfaction （3）； in, The total stray inductance of the power circuit to be calculated; Define the computation The gap range is ,in, For curve sequences The point corresponding to the minimum value in the range, that is, （4）； The maximum gap amplitude is ,definition For curve sequences The point closest to the preset value in the data, i.e. （5）； definition and exist The gap distance is d Then there is, （6）； The stray inductance includes the DC support capacitor and the stray inductance of the power module, with a maximum value of [missing information]. for Using a step size of 0.1nH, points were scanned to obtain... ,for For each value of , there is a corresponding curve. and distance d Find all d minimum value Then the corresponding That is, during the delay The total stray inductance is calculated below; Because there is a time delay between the actual voltage probe and the current probe, it is necessary to convert the current data... Perform a translation, and let the absolute value of the maximum delay between the voltage probe and the current probe be [value missing]. Then the maximum number of translation points is obtained. satisfy, （7）； when When translating to the left, the number of translation points is: , By filling in the missing data on the right side after the translation, we can obtain the translated current. for, （8）； when When translating to the right, the number of translation points is: , By filling in the missing data on the left side after the translation, the current after translation can be obtained. for, （9）； Referring to equations (2) to (6), the same translation point is used. The current after as well as Calculate the gap distance d as well as Find the minimum value in all cases. If the smallest Appearing in the current If there is no translation, then delay. If the smallest Appearing in the current During translation, let the minimum be... Translation point at the time of appearance Then the calculated probe delay is, （10）； Among them, when When shifting to the left, the actual current probe lags behind the voltage probe. ;when When shifting to the right, the actual voltage probe lags behind the current probe. ; Therefore, in all cases, the smallest corresponding That is, during the delay The total stray inductance is calculated below. L 1; therefore, (11).
3. The dual-pulse test method for a three-phase common-substrate power module according to claim 2, characterized in that, Step S1.2 is implemented as follows: The three-phase upper bridges are connected in parallel, using the same double-pulse waveform. Assuming the tested bridge arm is also the phase from step S1.1, the current probe measures the current flowing through the DC+ terminal, and the voltage probe measures the voltage across the upper bridge tube of phase U. Referring to step S1.1, based on the measured voltage and current waveforms during the second turn-on, the stray inductance during the three-phase parallel waveform generation is calculated. , （12）。 4. The dual-pulse test method for a three-phase common-substrate power module according to claim 3, characterized in that, In step S1.3, the results calculated based on steps S1.1 and S1.2 are... and By combining equations (11) and (12), the stray inductance of the common part is obtained. for, （13）。 5. A dual-pulse test method for a three-phase common-substrate power module according to claim 4, characterized in that, In step S1.4, assume that the allowable peak voltage of the power module in practical applications is... Then we get the largest satisfy, （14）； The newly added constraint is that, during the double-pulse test, appropriate drive parameters must be selected to ensure the current drop phase during the turn-on of the transistor. The absolute value does not exceed .