Testing method and testing device for interface thermal resistance
By constructing and optimizing a thermal network model and using the actual cumulative structure function curves of comparative samples, the thermal resistance of each interface inside a semiconductor device was successfully measured, solving the problem that existing technologies cannot distinguish interface thermal resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HC SEMITEK ZHEJIANG CO LTD
- Filing Date
- 2025-12-23
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies cannot effectively distinguish the thermal resistance of various interfaces inside semiconductor devices, resulting in an inability to understand the heat transfer path and accumulation inside the device.
By obtaining the actual cumulative structure function curves of multiple comparative samples, a thermal structure model is constructed and a thermal network model is established. The model parameters are then optimized to determine the thermal resistance of each interface.
This method enables the measurement of thermal resistance at various interfaces within semiconductor devices, solving the problem that traditional methods cannot distinguish the thermal resistance of adjacent interfaces.
Smart Images
Figure CN122016918A_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of semiconductor device testing technology, and specifically relates to a method and apparatus for testing interface thermal resistance. Background Technology
[0002] Semiconductor devices are widely used in modern electronic systems due to their superior electrical performance. However, under high power density conditions, if the heat generated in the active region (junction) of the device cannot be dissipated efficiently, the junction temperature will rise sharply. Therefore, thermal issues have become a key bottleneck limiting device performance and reliability.
[0003] In related technologies, the thermal resistance of semiconductor devices is detected using an electrical method. The detection process is as follows: A test voltage is applied to the semiconductor device, causing heat to be generated inside the device and the junction temperature to rise. The device is then allowed to reach a thermal steady state, i.e., the junction temperature no longer changes. Within a very short time, the test voltage is turned off, and a very small measuring current that does not generate self-heating is immediately applied to the device. The forward voltage drop at this point is then measured, and the junction temperature and thermal resistance are calculated based on the forward voltage drop.
[0004] However, the above methods can only obtain an overall, macroscopic thermal resistance value, and cannot determine how heat accumulates and is transferred inside the device, that is, they cannot distinguish the thermal resistance of each interface inside the device. Summary of the Invention
[0005] This disclosure provides a method and apparatus for testing interface thermal resistance, which can clearly measure the thermal resistance of each interface inside a device. The technical solution is as follows: This disclosure provides a method for testing interfacial thermal resistance. The method includes: obtaining actual cumulative structure function curves of multiple comparative samples of a semiconductor device. The semiconductor device includes a substrate, multiple functional film layers located on the front side of the substrate, and a heat dissipation substrate connected to the back side of the substrate. The multiple comparative samples have the same film layer structure as the semiconductor device, and the substrate thickness of one of the comparative samples is the same as that of the substrate of the semiconductor device, while the substrate thicknesses of the comparative samples are different. The actual cumulative structure function curves are obtained by performing transient thermal tests on the comparative samples and are used to characterize the functional relationship between cumulative thermal resistance and cumulative heat capacity in the equivalent physical structure of the comparative samples along the heat flow path from the heating junction to the ambient medium. The method also includes: constructing a thermal structure model of the semiconductor device and establishing a thermal network model corresponding to the thermal structure model. The thermal network model is used to characterize the equivalent thermal structure of the heat flow path from the heating junction to the ambient medium in the semiconductor device. The method further includes: optimizing the parameters of the thermal network model using the actual cumulative structure functions of each of the comparative samples; and obtaining the thermal resistance values of each interface in the semiconductor device based on the optimized thermal network model.
[0006] In another implementation of this disclosure, the thermal structure model includes sub-models that correspond one-to-one with the heat dissipation substrate, the substrate, and each of the functional film layers and are stacked sequentially; the step of establishing a thermal network model corresponding to the thermal structure model includes: mapping each sub-model in the thermal structure model to a thermal node composed of parallel thermal resistance and thermal capacity, wherein the thermal resistance and thermal capacity values of the thermal node are calculated based on the geometric parameters and thermal property parameters of the layer structure corresponding to the sub-model; mapping the contact interface between two adjacent sub-models in the thermal structure model to a pure thermal resistance node; and connecting each thermal node and the pure thermal resistance node in series according to the stacking order of the corresponding sub-models to obtain the thermal network model.
[0007] In another implementation of this disclosure, the step of fitting and optimizing the parameters of the thermal network model using the actual cumulative structure function of each of the comparative samples includes: generating a theoretical cumulative structure function curve for each of the comparative samples based on the thermal resistance and thermal capacity values of the thermal network model and the substrate thickness of each of the comparative samples, wherein the theoretical cumulative structure function curve is the cumulative structure function curve calculated for the comparative sample based on the parameters of the thermal network model; calculating the error between the theoretical cumulative structure function curve and the actual cumulative structure function curve for each of the comparative samples; and adjusting the thermal resistance value in the thermal network model according to the error until the error between the theoretical cumulative structure function curve and the corresponding actual cumulative structure function curve is within the required range.
[0008] In another implementation of this disclosure, adjusting the thermal resistance value in the thermal network model based on the error includes: adjusting the thermal resistance of the contact interface under constraints such that the error of all the comparison samples is less than a first threshold and not less than a second threshold; when the error is less than the first threshold and not less than the second threshold, adjusting the thermal parameters of the layer structure corresponding to the sub-film type under the constraints until the sum of the errors of all the comparison samples is less than the second threshold, wherein the second threshold is less than the first threshold; wherein the constraints include that, among all the comparison samples, the heat capacity of the sub-models other than the sub-model corresponding to the substrate is the same, and the thermal resistance of the contact interface of the same sub-model is the same.
[0009] In another implementation of this disclosure, the actual cumulative structure function curve is obtained by: calculating the temperature rise cooling curve of the junction temperature of the comparative sample as a function of time based on the voltage data in the transient cooling curve of each comparative sample and the temperature-sensitive parameter coefficient of the semiconductor device; calculating the transient thermal impedance curve based on the heating power applied when the temperature rise cooling curve and the transient cooling curve are obtained; and transforming the transient thermal impedance curve to obtain the actual cumulative structure function curve.
[0010] Secondly, this disclosure also provides a testing apparatus for interface thermal resistance, the testing apparatus comprising a first determining module, a model building module, an optimization module, and a second determining module; the first determining module is used to acquire actual cumulative structure function curves of multiple comparative samples of a semiconductor device, the semiconductor device comprising a substrate, multiple functional film layers located on the front side of the substrate, and a heat dissipation substrate connected to the back side of the substrate, the multiple comparative samples having the same film layer structure as the semiconductor device, and the substrate thickness of one of the comparative samples being the same as the substrate thickness of the semiconductor device, while the substrate thicknesses of the various comparative samples being different, the actual cumulative structure function curves being obtained by transient analysis of the comparative samples. The comparison sample is obtained through thermal testing and used to characterize the cumulative thermal resistance as a function of cumulative thermal capacity in its equivalent physical structure along the heat flow path from the heating junction to the ambient medium. The model building module is used to construct a thermal structure model of the semiconductor device and establish a corresponding thermal network model, which characterizes the equivalent physical structure of the heat flow path from the heating junction to the ambient medium. The optimization module optimizes the parameters of the thermal network model using the actual cumulative structure function of each comparison sample. The second determination module obtains the thermal resistance values of each interface in the device based on the optimized thermal network model.
[0011] In another implementation of this disclosure, the thermal structure model includes sub-models that correspond one-to-one with the heat dissipation substrate, the substrate, and each of the functional film layers and are stacked sequentially; the thermal network model construction module is further configured to: map each sub-model in the thermal structure model to a thermal node composed of parallel thermal resistance and thermal capacity, wherein the thermal resistance and thermal capacity values of the thermal node are calculated based on the geometric parameters and thermal properties of the structure corresponding to the sub-model; map the contact interface between any two sub-models in the thermal structure model to a pure thermal resistance node, wherein the thermal resistance value of the pure thermal resistance node is calculated based on the material geometric parameters and thermal properties of the corresponding contact interface in the thermal structure model; and connect each thermal node and the pure thermal resistance node in series according to the stacking order of the corresponding sub-models to obtain the thermal network model.
[0012] In another implementation of this disclosure, the optimization module is used to: generate a theoretical cumulative structure function curve for each of the comparative samples based on the thermal resistance and thermal capacity values of the thermal network model and the substrate thickness of each of the comparative samples, wherein the theoretical cumulative structure function curve is a function of the cumulative thermal resistance with respect to the cumulative thermal capacity calculated based on the parameters of the thermal network model for the comparative sample; calculate the error between the theoretical cumulative structure function curve and the actual cumulative structure function curve for each of the comparative samples; and adjust the thermal resistance and thermal capacity values in the thermal network model according to the error until the error between the theoretical cumulative structure function curve and the corresponding actual cumulative structure function curve is within the required range.
[0013] In another implementation of this disclosure, the optimization module is used to: adjust the thermal resistance of the contact interface under constraints, such that the error of all the comparison samples is less than a first threshold and not less than a second threshold; when the error is less than the first threshold and not less than the second threshold, adjust the thermal parameters of the layer structure corresponding to the sub-film type under the constraints until the sum of the errors of all the comparison samples is less than the second threshold, wherein the second threshold is less than the first threshold; wherein the constraints include that, among all the comparison samples, the heat capacity of the sub-models other than the sub-model corresponding to the substrate is the same, and the thermal resistance of the contact interface of the same sub-model is the same.
[0014] Thirdly, this disclosure also provides a computer device including a processor and a memory configured to store processor-executable instructions; the processor is configured to perform the interface thermal resistance testing method described above.
[0015] The beneficial effects of the technical solutions provided in this disclosure are: This testing method acquires multiple comparative samples of semiconductor devices with substrates of different thicknesses but identical structures, and simultaneously obtains the actual cumulative structure function curves of each comparative sample. Then, the parameters of the thermal network model are optimized using the actual cumulative structure functions of each comparative sample, thereby obtaining the parameters of the optimized thermal network model. Based on this, the thermal resistance of each interface in the semiconductor device can be obtained, solving the problem that traditional methods cannot distinguish the thermal resistance of adjacent interfaces. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a flowchart of a method for testing interfacial thermal resistance provided in an embodiment of this disclosure; Figure 2 This is a flowchart of another method for testing interfacial thermal resistance provided in an embodiment of this disclosure; Figure 3 This is the temperature rise and cooling curve of one of the comparative samples of a GaN transistor in this embodiment. Figure 4 Transient impedance curves for four comparative samples; Figure 5 To compare the pulse response curves of sample a under different pulses; Figure 6 To compare the pulse response curves of sample b under different pulses; Figure 7 To compare the pulse response curves of sample c under different pulses; Figure 8 To compare the pulse response curves of sample d under different pulses; Figure 9 The actual cumulative structure function curves for different comparison samples; Figure 10 This is a graph of the cumulative structure function obtained through the network model; Figure 11 This is a block diagram of a test device for interface thermal resistance provided in an embodiment of this disclosure. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0019] To clearly explain the testing method provided in this embodiment, the following technical terms will be explained first.
[0020] Junction Temperature (T) j ( ) refers to the temperature of the active region inside a semiconductor device that generates heat.
[0021] A transient cooling profile is a curve showing the relationship between a temperature-sensitive parameter and time when the constant heating power applied to a semiconductor device is instantaneously cut off at a constant ambient temperature. For example, if the temperature-sensitive parameter is the forward junction voltage under a specific bias condition, the transient cooling profile is a voltage-time curve. Typically, the temperature-sensitive parameter decreases exponentially or non-exponentially with time.
[0022] The cumulative structure function curve is a monotonically increasing function curve obtained by deconvolving the time-domain thermal response after mathematically transforming the transient cooling curve (typically by calculating the transient thermal impedance and performing a Laplace transform). It is a curve with the accumulated heat capacity as the x-axis and the corresponding accumulated thermal resistance as the y-axis along the heat flow path from the heating junction to the ambient medium.
[0023] The thermal structure model is a digital description of multiple layers from the heat-generating junction to the ambient medium, based on the physical stacking order of the layers of a semiconductor device, the geometric parameters (thickness and area, etc.) of each layer, and the thermal properties (thermal conductivity and specific heat capacity, etc.).
[0024] A thermal network model is a Cauer-type equivalent thermal network model that maps each layer of material in a thermal structure model to a parallel thermal node with thermal resistance and thermal capacity, maps each physical interface to a pure thermal resistance node, and connects these nodes in series according to the physical stacking order.
[0025] This disclosure provides a method for testing the interface thermal resistance of a device, such as... Figure 1 As shown, the test method includes: S101: Obtain the actual cumulative structure function curves of multiple comparative samples of semiconductor devices.
[0026] The semiconductor device includes a substrate, multiple functional film layers located on the front side of the substrate, and a heat dissipation substrate connected to the back side of the substrate. Several comparative samples have the same film layer structure as the semiconductor device, and the substrate thickness of one of the comparative samples is the same as that of the semiconductor device substrate, while the substrate thicknesses of the various comparative samples are different.
[0027] Among them, identical film structure means that the number and stacking order of the layers contained in the comparative sample and the semiconductor device are the same, and that the geometric parameters of each layer structure are the same except for the substrate.
[0028] The actual cumulative structure function curve is obtained by performing transient thermal tests on the comparison sample and is used to characterize the cumulative thermal resistance as a function of the cumulative heat capacity in the equivalent physical structure of the comparison sample along the heat flow path from the heating junction to the ambient medium.
[0029] In this embodiment, the semiconductor device is a GaN transistor or similar device.
[0030] S102: Construct a thermal structure model of a semiconductor device and establish a thermal network model corresponding to the thermal structure model.
[0031] Thermal network models are used to characterize the equivalent thermal structure of the heat flow path from the heat-generating junction to the ambient medium in a semiconductor device.
[0032] S103: Optimize the parameters of the thermal network model by using the actual cumulative structure function of each comparative sample.
[0033] S104: Based on the optimized thermal network model, obtain the thermal resistance value of the interface in the semiconductor device.
[0034] This testing method acquires multiple comparative samples of semiconductor devices with substrates of different thicknesses but identical structures, and simultaneously obtains the actual cumulative structure function curves of each comparative sample. Then, the parameters of the thermal network model are optimized using the actual cumulative structure functions of each comparative sample, thereby obtaining the parameters of the optimized thermal network model. Based on this, the thermal resistance of the interface in the semiconductor device can be obtained, solving the problem that traditional methods cannot distinguish the thermal resistance of adjacent interfaces.
[0035] This disclosure also provides another method for testing the interface thermal resistance of a device, such as... Figure 2 As shown, the test methods include: S201: Prepare multiple comparison samples.
[0036] In this embodiment, the physical structure of the semiconductor device under test needs to be clearly defined, including but not limited to the complete stacked structure from the active region to the heat dissipation substrate. The stacked structure includes, but is not limited to: GaN layer, AlGaN layer, nucleation layer, substrate (such as Si, SiC, sapphire), chip adhesion layer (such as solder or epoxy resin), heat dissipation substrate (such as Cu, AlN, Al2O3), and the structure of the outer layer of the heat dissipation substrate. Furthermore, the thickness, area, and other geometric parameters of the materials used in each layer need to be recorded.
[0037] The comparison samples have the same structure as the semiconductor device, but the substrate thicknesses of the samples are different.
[0038] In other words, the comparison samples are devices that are completely identical in structure (such as epitaxial layer structure, bonding process, and packaging form) except for the substrate thickness.
[0039] For example, the substrate of comparison sample A has the same thickness as the substrate of the semiconductor device under test, the substrate of comparison sample B is a thinned substrate, and the substrate of comparison sample C is thicker than the substrate of the semiconductor device.
[0040] For semiconductor devices with Si as the substrate, comparative samples with different substrates can be obtained through back-side grinding and polishing processes. For example, a complete wafer with the original thickness, thinned to 100 μm, and thinned to 50 μm. It is worth noting that all other process steps (epitaxy growth, metallization, passivation, bonding, and packaging) must be completely consistent in all comparative samples to ensure that the structure is the same except for the substrate thickness.
[0041] Since changes in substrate thickness in the comparative samples linearly alter the substrate's thermal capacity and thermal resistance, this will manifest as specific changes in the subsequent theoretical cumulative structure function (CMS) curve. Therefore, the differences in the CMS curves can facilitate the optimization of the thermal network model.
[0042] S202: Perform transient thermal tests on each comparison sample to obtain the transient cooling curve of the comparison sample.
[0043] In this embodiment, the transient cooling curve of the comparison sample is obtained by using the transient thermal testing method described in the JESD51-1 standard.
[0044] Optionally, step S202 includes: Each comparison sample was fixedly mounted on a temperature-controlled hot stage, which was then stabilized at a set temperature. A small, constant heating power was applied to each comparison sample, causing a measurable temperature rise in its internal junction (active region). Subsequently, the heating power was cut off, and the transient response curve of the device's junction voltage (as a temperature-sensitive parameter) was rapidly acquired, thus obtaining the transient cooling curve.
[0045] S203: Construct a thermal structure model of a semiconductor device.
[0046] For example, the functional film layer of a semiconductor device includes a nucleation layer, a buffer layer, and an active region sequentially stacked on a substrate. The semiconductor device also includes an adhesion layer, a heat dissipation substrate, and a cold plate. The heat dissipation substrate is connected to the back side of the substrate away from the functional film layer via the adhesion layer. To facilitate reliable mechanical bonding between the substrate and the adhesion layer, the back side of the substrate needs to be metallized.
[0047] The active region comprises a heterojunction formed by a GaN channel layer and an AlGaN barrier layer. The buffer layer is a GaN layer. The nucleation layer is an AlN layer. The adhesion layer is solder or silver paste. The heat dissipation substrate can be an AlN, Al2O3, or similar substrate. In other words, the semiconductor device comprises multiple layered structures stacked sequentially. These multiple layered structures are: heat dissipation substrate, adhesion layer, substrate, nucleation layer, buffer layer, GaN channel layer, and AlGaN barrier layer.
[0048] When determining the above structure, it is also necessary to determine the geometric parameters and thermophysical parameters of each layer structure.
[0049] Geometric parameters include the area and thickness of each layer. The area of the layer is typically determined by the chip size and device layout. The thickness of the functional film can be obtained from the epitaxial growth process parameters. The substrate thickness is obtained using a micrometer or thickness gauge. The thickness of the adhesion layer is obtained from process specifications (such as stencil thickness, preform thickness) or cross-sectional scanning electron microscopy. The thickness of the heat dissipation substrate can be obtained from the supplier's datasheet or through direct measurement. Thermal properties include the specific heat capacity, thermal conductivity, and density of the materials used in the layer structure.
[0050] Then, based on the above structure and the parameters corresponding to each layer, a thermal structure model corresponding to the semiconductor device can be created.
[0051] The thermal structure model includes sub-models that correspond one-to-one with the heat dissipation substrate, the attachment layer, the substrate, the buffer layer, and the active region and are stacked sequentially.
[0052] Each sub-model in the thermal structure model is assigned a specific material type, thickness, and area to its corresponding layer structure. These parameters serve as the initial input values for subsequent construction of the thermal network model and fitting.
[0053] S204: Establish a thermal network model corresponding to the thermal structure model.
[0054] In this embodiment, step S204 is to transform the thermal structure model constructed in step S203 into an equivalent thermal structure that can be solved using circuit theory, namely, a thermal network model.
[0055] Optionally, S204 includes the following steps: 2041: Map each sub-model in the thermal structure model to a thermal node consisting of parallel thermal resistance and thermal capacity.
[0056] 2042: Map the contact interface between any two sub-models in the thermal structure model to a pure thermal resistance node.
[0057] 2043: Connect each thermal node and pure thermal resistance node in series according to the stacking order of their corresponding sub-models to obtain the thermal network model.
[0058] The parameters of the thermal network model include the thermal resistance and heat capacity of thermal nodes, as well as the thermal resistance of purely thermally resistive nodes. The thermal resistance and heat capacity of thermal nodes are calculated based on the geometric and thermophysical parameters of the corresponding layer structure of the sub-model. The thermal resistance of purely thermally resistive nodes at the interface is defined as a parameter to be optimized in the model, which can be preset based on experience or relevant literature.
[0059] In the thermal structure model of a semiconductor device, each sub-model corresponds to a thermal node in the Cauer model, which is a parallel connection of thermal resistance and thermal capacity. The contact interface between adjacent sub-models corresponds to a node with pure thermal resistance. Therefore, the thermal network model can be obtained by directly mapping each sub-model in the thermal structure model to the Cauer model.
[0060] The thermal resistance of each thermal node corresponding to a sub-model can be calculated according to the following formula (1): (1) Among them, R th d is the thermal resistance of the layer structure corresponding to the sub-model; d is the thickness of the layer structure corresponding to the sub-model; k is the thermal conductivity of the layer structure corresponding to the sub-model; A is the area of the layer structure corresponding to the sub-model.
[0061] The heat capacity of each thermal node corresponding to each layer of the structure can be calculated according to the following formula (2): (2) Among them, C th c is the heat capacity of the material used in the layered structure corresponding to the sub-model; p ρ is the specific heat capacity of the material used in the layer structure corresponding to the sub-model; ρ is the density of the material used in the layer structure corresponding to the sub-model; A is the transverse area of the layer structure corresponding to the sub-model; and d is the thickness of the layer structure corresponding to the sub-model.
[0062] The above steps, by mapping each layer structure and its interface of the semiconductor device to thermal resistance-capacity units with clearly defined mathematical relationships and connecting them in series according to their actual stacking order, construct a parameterized model that strictly corresponds to the physical structure. This allows transient heat conduction processes, which are difficult to calculate and analyze in a three-dimensional model, to be rapidly simulated and inverted in this one-dimensional equivalent circuit model, laying the computational foundation for subsequent quantitative separation of interface thermal resistance. Furthermore, the mapping in these steps ensures a one-to-one correspondence between the sub-models in the thermal structure model and each part in the thermal network model. When the substrate thickness of the comparison sample changes, only the thermal resistance and thermal capacity of the thermal node representing the substrate in the thermal network model change, while others remain unchanged. This allows the single variable of substrate thickness change to be used to obtain other parameters in subsequent steps. In other words, mapping the thermal structure model to a Cauer thermal network to obtain the thermal network model maintains a one-to-one correspondence between each thermal node and a sub-model or interface. This lays the foundation for optimizing the parameters of the thermal network model to extract the thermal resistance of the contact interface.
[0063] S205: Based on the transient cooling curve, the actual cumulative structure function curves of each comparative sample are obtained.
[0064] Optionally, S205 includes: 2051: Based on the voltage data in the transient cooling curve of each comparison sample and the temperature-sensitive parameter coefficient of the semiconductor device, the temperature rise and cooling curve of the junction temperature of the semiconductor device over time is calculated.
[0065] Figure 3 This is the temperature rise and cooling curve of three comparative samples b, c, and d of a GaN transistor in this embodiment. Figure 3 The horizontal axis represents time, and the vertical axis represents temperature. This curve is obtained by converting the transient cooling curve obtained in step S202 according to the following conversion formula (3).
[0066] (3) in, For junction temperature rise; It is a positive voltage; The forward voltage is the voltage at which the semiconductor device and the test equipment reach thermal equilibrium before heating. In other words, the voltage of the junction is measured and recorded when the semiconductor device and the heat control stage of the test equipment reach thermal equilibrium before the heating power is applied.
[0067] Where K is the temperature-sensitive parameter coefficient. This coefficient needs to be calibrated before or after testing. During calibration, the semiconductor device is placed in a temperature-controlled chamber. At multiple different and stable temperature points (e.g., 25°C, 50°C, 75°C), the same measuring current is applied, and the corresponding forward voltage is recorded. A linear fit is performed on these temperature and forward voltage data points; the absolute value of the slope of the resulting straight line is the temperature-sensitive parameter coefficient K.
[0068] 2052: The transient thermal resistance curve is calculated based on the temperature rise cooling curve and the heating power applied when obtaining the transient cooling curve.
[0069] Dividing the temperature rise curve by the applied constant heating power yields the transient thermal resistance curve.
[0070] Figure 4 The transient impedance curves for four comparative samples a, b, c, and d are shown. Figure 4 The horizontal axis represents time, and the vertical axis represents transient thermal resistance Zth (unit: Kelvin per watt (K / W)).
[0071] 2053: Transform the transient thermal impedance curve to obtain the actual cumulative structure function curve with cumulative heat capacity as the abscissa and cumulative thermal resistance as the ordinate.
[0072] In this embodiment, the transient thermal impedance curve can be transformed to obtain pulse response curves under different pulses. See [link / reference] Figure 5-8 . Figure 5 To compare the pulse response curves of sample a under different pulses. Figure 6 To compare the pulse response curves of sample b under different pulses. Figure 7 To compare the pulse response curves of sample c under different pulses. Figure 8 To compare the pulse response curves of sample d under different pulses.
[0073] The differential function obtained by differentiating or integrating the transient thermal impedance curve is plotted on the logarithmic time axis. The plotted function is then subjected to a Laplace transform to obtain the transfer function in the complex frequency domain. Using a specific algorithm (such as a "network identification" algorithm based on continued fraction expansion), a unique Cauer-type resistor-capacitor thermal network completely equivalent to this transfer function is inverted. From this identified Cauer network, starting from the heat source end (junction), the heat capacity (C) of each thermal node or purely thermally resistive node is accumulated stepwise. th ) and thermal resistance (R th ). Based on the accumulated heat capacity ΣC th The vertical axis represents the cumulative thermal resistance ΣR. th Using the x-axis as the horizontal axis, the monotonically increasing curve is plotted to obtain the actual cumulative structure function curve.
[0074] Figure 9 The figures show the actual cumulative structure function curves for different comparative samples. Curve a1 is the differential structure function curve for comparative sample a, and curve a2 is the integral structure function curve for comparative sample a. Curve b1 is the differential structure function curve for comparative sample b, and curve b2 is the integral structure function curve for comparative sample b. Curve c1 is the differential structure function curve for comparative sample c, and curve c2 is the integral structure function curve for comparative sample c. Curve d1 is the differential structure function curve for comparative sample d, and curve d2 is the integral structure function curve for comparative sample d.
[0075] The above steps, through physical calibration, power normalization (calculation of thermal impedance), and mathematical deconvolution (transformation into structure function) of the voltage data in the transient cooling curve, systematically transform the difficult-to-interpret time-domain electrical signal into a spatial distribution map that can intuitively and quantitatively reveal the thermal properties of each layer of structure and interface inside the semiconductor device from the junction to the ambient medium. This lays a unique and reliable data foundation for the subsequent accurate separation of interface thermal resistance.
[0076] S206: Optimize the parameters of the thermal network model using the actual cumulative structure function of each comparative sample.
[0077] During optimization, the actual cumulative structure function curves of all samples obtained in step S205 are used as the common fitting target. The following key constraints are set during the optimization process: Layer structure thermal capacity constraint: For all comparative samples except the substrate, the thermal capacity (C) within the same layer structure is the same. thi The thermal properties are the same because, apart from the substrate, the materials and volumes (area × thickness) of the corresponding layer structures in the different comparison samples are identical. For example, the thermal capacity of the barrier layer corresponding to the thermal structure models in comparison samples A, B, and C is the same.
[0078] Interface thermal resistance constraint: For all comparison samples, the thermal resistance (Rthi) of the same contact interface is the same because the processes and materials of these interfaces are identical. For example, the thermal resistance of the contact interface between the AlGaN barrier layer and the GaN channel layer corresponding to the thermal structure models in comparison samples A, B, and C is the same.
[0079] Optionally, S206 includes: 2061: Based on the current thermal resistance and thermal capacity values of the thermal network model, and the actual substrate thickness of each comparative sample, calculate and generate the theoretical cumulative structure function curves corresponding to each comparative sample.
[0080] The theoretical cumulative structure function curve is the cumulative structure function curve calculated based on the parameters of the thermal network model for the comparative sample.
[0081] 2062: Calculate the error between all theoretical cumulative structure function curves and their corresponding actual cumulative structure function curves.
[0082] In this embodiment, the error between the theoretical cumulative structure function curve and the corresponding actual cumulative structure function curve refers to the sum of the squares of the differences between the ordinates (cumulative thermal resistance) of all corresponding data points on the theoretical cumulative structure function curve and the corresponding actual cumulative structure function curve.
[0083] 2063: Optimize the parameters of the parameterized stepped heat network model based on the error.
[0084] The above steps created a corresponding theoretical cumulative structure function curve for each comparison sample with different substrate thicknesses. By comparing and adjusting the theoretical cumulative structure function curve with the measured actual cumulative structure function curve, a specific set of interfacial thermal resistance values was ultimately obtained to accommodate the test results of comparison samples with all different thicknesses.
[0085] Optionally, step 2063 can be implemented according to the following steps: Under constraints, the thermal resistance of the contact interface is adjusted so that the error of all comparison samples is less than the first threshold and not less than the second threshold.
[0086] When the error is less than the first threshold and not less than the second threshold, the thermal parameters of the layer structure corresponding to the sub-film type are adjusted under constraints until the sum of the errors of all comparison samples is less than the second threshold, wherein the second threshold is less than the first threshold.
[0087] The constraints include that, among all the comparison samples, the sub-models other than the one corresponding to the substrate have the same heat capacity, and the contact interface of the same sub-model has the same thermal resistance.
[0088] In this embodiment, the parameters of the thermal network model are optimized using the least squares method to minimize the sum of errors of all comparison samples or to keep it within a threshold range. Simultaneously, all comparison samples are constrained to have the same heat capacity for their respective sub-models (excluding the substrate) and the same thermal resistance at the contact interfaces within the same sub-model.
[0089] During optimization, the thermal resistance of the contact interface is first adjusted. If the sum of errors of all comparison samples is less than a first threshold but not less than a second threshold, the thermal parameters of the layer structure corresponding to the sub-film type are then adjusted until the sum of errors of all comparison samples is less than the second threshold. At this point, the parameters in the thermal network model are determined. Throughout the optimization process, the heat capacity remains constant.
[0090] The second threshold is less than the first threshold. The first threshold can be 1%-5% of the error, and the second threshold is less than 1% of the error.
[0091] Since the thermal resistance of the contact interface is the feature parameter with the highest uncertainty in the thermal structure model and the most significant impact on the shape of the cumulative structure function curve, the optimization process can be adjusted in stages. First, the thermal resistance parameter of the contact interface should be determined first to capture the core features on the thermal path. Then, based on this, the thermal parameters of each layer structure can be fine-tuned to achieve optimal matching.
[0092] S207: Based on the optimized thermal network model, obtain the thermal resistance value of the interface in the semiconductor device.
[0093] After optimization of the thermal network model, the value of each node representing the pure thermal resistance of the interface is uniquely determined. This allows for the direct determination of the interface's thermal resistance value.
[0094] Alternatively, the cumulative structure function curve of cumulative heat capacity - cumulative thermal resistance can be obtained by taking the derivative of the cumulative structure function of cumulative heat capacity - cumulative thermal resistance using the thermal network model with the parameters already determined above.
[0095] Figure 10 The cumulative structure function curve obtained through the network model is shown below. Figure 10 As shown, the curve in the differential structure function consists of multiple segments with varying degrees of gentleness or steepness, each segment representing a feature layer. Figure 10 The images displayed sequentially show the internal layers of the chip and the various layers of the packaging. (Through...) Figure 10 Each segment in the diagram corresponds to a specific layer structure. Then, by mapping the coordinates between the layers, the interfacial thermal resistance can be directly read. For example, the interface between the substrate and the attached layer corresponds to the area between the fourth and fifth segments in the diagram. Plotting this point on the coordinate system yields an interfacial thermal resistance of 0.028 K / W.
[0096] This disclosure also provides an apparatus for testing the thermal resistance of a device, such as... Figure 11 As shown, the testing device includes a first determining module 1101, a model building module 1102, an optimization module 1103, and a second determining module 1104.
[0097] The first determining module is used to obtain the actual cumulative structure function curves of multiple comparative samples of a semiconductor device. The semiconductor device includes a substrate, multiple functional film layers located on the front side of the substrate, and a heat dissipation substrate connected to the back side of the substrate. The multiple comparative samples have the same film layer structure as the semiconductor device, and the thickness of the substrate of one of the comparative samples is the same as the thickness of the substrate of the semiconductor device. The thickness of the substrates of each comparative sample is different. The actual cumulative structure function curve is obtained by performing transient thermal tests on the comparative samples and is used to characterize the functional relationship between the cumulative thermal resistance and the cumulative thermal capacity in the equivalent physical structure of the comparative sample along the heat flow path from the heating junction to the ambient medium.
[0098] The model building module is used to build a thermal structure model of a semiconductor device and establish a corresponding thermal network model. The thermal network model is used to characterize the equivalent thermal structure of the heat flow path from the heat-generating junction to the ambient medium in a semiconductor device.
[0099] The optimization module is used to optimize the parameters of the thermal network model using the actual cumulative structure function of each comparison sample.
[0100] The second determining module is used to obtain the thermal resistance value of the interface in the semiconductor device based on the optimized thermal network model.
[0101] Optionally, the thermal structure model includes sub-models that correspond one-to-one with the heat dissipation substrate, the substrate, and each functional film layer and are stacked sequentially.
[0102] The thermal network model construction module is also used to: map each sub-model in the thermal structure model to a thermal node consisting of parallel thermal resistance and thermal capacity, wherein the thermal resistance and thermal capacity values of the thermal node are calculated based on the geometric parameters and thermal properties of the corresponding layer structure of the sub-model; map the contact interface between two adjacent sub-models in the thermal structure model to a pure thermal resistance node; and connect each thermal node and the pure thermal resistance node in series according to the stacking order of the corresponding sub-models to obtain the thermal network model.
[0103] Optionally, the fitting optimization module is used to: generate theoretical cumulative structure function curves for each comparative sample based on the thermal resistance and thermal capacity values of the thermal network model and the substrate thickness of each comparative sample; the theoretical cumulative structure function curves are the cumulative structure function curves calculated based on the parameters of the thermal network model for each comparative sample; calculate the error between the theoretical cumulative structure function curve and the actual cumulative structure function curve for each comparative sample; and adjust the thermal resistance value in the thermal network model according to the error until the error between the theoretical cumulative structure function curve and the corresponding actual cumulative structure function curve is within the required range.
[0104] Optionally, the optimization module is used to: adjust the thermal resistance of the contact interface under constraints, such that the error of all comparison samples is less than a first threshold and not less than a second threshold; when the error is less than the first threshold and not less than the second threshold, adjust the thermal parameters of the layer structure corresponding to the sub-film type under constraints until the sum of the errors of all comparison samples is less than the second threshold, wherein the second threshold is less than the first threshold; wherein the constraints include that, among all comparison samples, the heat capacity of the sub-models other than the sub-model corresponding to the substrate is the same, and the thermal resistance of the contact interface of the same sub-model is the same.
[0105] Optionally, the first determining module is used to: calculate the temperature rise cooling curve of the junction temperature of the comparative sample as a function of time based on the voltage data in the transient cooling curve of each comparative sample and the temperature-sensitive parameter coefficient of the semiconductor device; calculate the transient thermal impedance curve based on the heating power applied when the temperature rise cooling curve and the transient cooling curve are obtained; and transform the transient thermal impedance curve to obtain the actual cumulative structure function curve.
[0106] It should be noted that the interface thermal resistance testing device provided in the above embodiments is only illustrated by the division of the functional modules described above. In practical applications, the functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the interface thermal resistance testing device and the interface thermal resistance testing method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be detailed here.
[0107] This disclosure also provides a computer device, which includes a processor and a memory configured to store processor-executable instructions; the processor is configured to implement the interface thermal resistance testing method described above.
[0108] The processor includes one or more processing cores. It executes various functional applications and information processing by running software programs and modules. Memory and a communication interface are connected to the processor via a bus. The memory can be used to store at least one instruction, which the processor executes to implement the steps in the aforementioned method.
[0109] Furthermore, the memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, including but not limited to: magnetic disks or optical disks, electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), read-only memory (ROM), magnetic storage, flash memory, and programmable read-only memory (PROM).
[0110] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.
[0111] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A method for testing interfacial thermal resistance, characterized in that, The testing method includes: The actual cumulative structure function curves of multiple comparative samples of a semiconductor device are obtained. The semiconductor device includes a substrate, multiple functional film layers located on the front side of the substrate, and a heat dissipation substrate connected to the back side of the substrate. The multiple comparative samples have the same film layer structure as the semiconductor device, and the thickness of the substrate of one of the comparative samples is the same as the thickness of the substrate of the semiconductor device. The thickness of the substrates of each of the comparative samples is different. The actual cumulative structure function curves are obtained by performing transient thermal tests on the comparative samples and are used to characterize the cumulative thermal resistance as a function of the cumulative thermal capacity in the equivalent physical structure of the comparative samples along the heat flow path from the heat-generating junction to the ambient medium. A thermal structure model of the semiconductor device is constructed, and a thermal network model corresponding to the thermal structure model is established. The thermal network model is used to characterize the equivalent thermal structure of the heat flow path of the semiconductor device from the heat-generating junction to the ambient medium. The parameters of the thermal network model are optimized using the actual cumulative structure functions of each of the comparative samples. Based on the optimized thermal network model, the thermal resistance value of the interface in the semiconductor device is obtained.
2. The test method according to claim 1, characterized in that, The thermal structure model includes sub-models that correspond one-to-one with the heat dissipation substrate, the substrate, and each of the functional film layers and are stacked sequentially. The establishment of the thermal network model corresponding to the thermal structure model includes: Each sub-model in the thermal structure model is mapped to a thermal node consisting of parallel thermal resistance and thermal capacity. The thermal resistance and thermal capacity values of the thermal node are calculated based on the geometric parameters and thermal properties of the layer structure corresponding to the sub-model. The contact interface between two adjacent sub-models in the thermal structure model is mapped to a pure thermal resistance node. The thermal nodes and the pure thermal resistance nodes are connected in series in the order of their corresponding sub-models to obtain the thermal network model.
3. The test method according to claim 2, characterized in that, The optimization of the parameters of the thermal network model using the actual cumulative structure function of each of the comparative samples includes: Based on the thermal resistance and thermal capacity values of the thermal network model, and the thickness of the substrate of each of the comparative samples, a theoretical cumulative structure function curve is generated for each of the comparative samples. The theoretical cumulative structure function curve is the cumulative structure function curve calculated for the comparative sample based on the parameters of the thermal network model. Calculate the error between the theoretical cumulative structure function curve and the actual cumulative structure function curve for each of the comparison samples; Based on the error, adjust the thermal resistance value in the thermal network model until the error between the theoretical cumulative structure function curve and the corresponding actual cumulative structure function curve is within the required range.
4. The test method according to claim 3, characterized in that, The step of adjusting the thermal resistance value in the thermal network model based on the error includes: Under constraints, the thermal resistance of the contact interface is adjusted so that the error of all the comparison samples is less than a first threshold and not less than a second threshold. When the error is less than the first threshold and not less than the second threshold, the thermal parameters of the layer structure corresponding to the sub-film type are adjusted under the constraint conditions until the sum of the errors of all the comparison samples is less than the second threshold, wherein the second threshold is less than the first threshold; The constraints include that, among all the comparison samples, the sub-models other than the one corresponding to the substrate have the same thermal capacity, and the contact interface of the same sub-model has the same thermal resistance.
5. The test method according to any one of claims 1-4, characterized in that, The actual cumulative structure function curve is obtained in the following way: Based on the voltage data in the transient cooling curve of each of the comparative samples and the temperature-sensitive parameter coefficient of the semiconductor device, the temperature rise and cooling curve of the junction temperature of the comparative sample over time is calculated. The transient thermal resistance curve is calculated based on the applied heating power obtained from the temperature rise cooling curve and the transient cooling curve. The transient thermal impedance curve is transformed to obtain the actual cumulative structure function curve.
6. A testing device for interfacial thermal resistance, characterized in that, The testing device includes a first determining module, a model building module, an optimization module, and a second determining module; The first determining module is used to acquire the actual cumulative structure function curves of multiple comparative samples of a semiconductor device. The semiconductor device includes a substrate, multiple functional film layers located on the front side of the substrate, and a heat dissipation substrate connected to the back side of the substrate. The multiple comparative samples have the same film layer structure as the semiconductor device, and the thickness of the substrate of one of the comparative samples is the same as the thickness of the substrate of the semiconductor device. The thickness of the substrates of each of the comparative samples is different. The actual cumulative structure function curve is obtained by performing transient thermal testing on the comparative samples and is used to characterize the cumulative thermal resistance as a function of the cumulative thermal capacity in the equivalent physical structure of the comparative samples along the heat flow path from the heat-generating junction to the ambient medium. The model building module is used to build a thermal structure model of the semiconductor device and establish a thermal network model corresponding to the thermal structure model. The thermal network model is used to characterize the equivalent physical structure of the heat flow path of the semiconductor device from the heat-generating junction to the ambient medium. The optimization module is used to optimize the parameters of the thermal network model using the actual cumulative structure function of each of the comparison samples. The second determining module is used to obtain the thermal resistance value of each interface in the device based on the optimized thermal network model.
7. The testing apparatus according to claim 6, characterized in that, The thermal structure model includes sub-models that correspond one-to-one with the heat dissipation substrate, the substrate, and each of the functional film layers and are stacked sequentially; the thermal network model construction module is also used for: Each sub-model in the thermal structure model is mapped to a thermal node consisting of parallel thermal resistance and thermal capacity. The thermal resistance and thermal capacity values of the thermal node are calculated based on the geometric parameters and thermal property parameters of the structure corresponding to the sub-model. The contact interface between any two sub-models in the thermal structure model is mapped to a pure thermal resistance node. The thermal resistance value of the pure thermal resistance node is calculated based on the material geometric parameters and thermophysical parameters of the corresponding contact interface in the thermal structure model. The thermal nodes and the pure thermal resistance nodes are connected in series in the order of their corresponding sub-models to obtain the thermal network model.
8. The testing apparatus according to claim 7, characterized in that, The optimization module is used for: Based on the thermal resistance and thermal capacity values of the thermal network model, and the substrate thickness of each of the comparative samples, a theoretical cumulative structure function curve is generated for each of the comparative samples. The theoretical cumulative structure function curve is a function of the cumulative thermal resistance with respect to the cumulative thermal capacity, calculated based on the parameters of the thermal network model. The error between the theoretical cumulative structure function curve and the actual cumulative structure function curve for each of the comparative samples is calculated. Based on the error, the thermal resistance and thermal capacity values in the thermal network model are adjusted until the error between the theoretical cumulative structure function curve and the corresponding actual cumulative structure function curve is within the required range.
9. The testing apparatus according to claim 8, characterized in that, The optimization module is used to: adjust the thermal resistance of the contact interface under constraints so that the error of all the comparison samples is less than a first threshold and not less than a second threshold. When the error is less than the first threshold and not less than the second threshold, the thermal parameters of the layer structure corresponding to the sub-film type are adjusted under the constraint conditions until the sum of the errors of all the comparison samples is less than the second threshold, wherein the second threshold is less than the first threshold; The constraints include that, among all the comparison samples, the sub-models other than the one corresponding to the substrate have the same thermal capacity, and the contact interface of the same sub-model has the same thermal resistance.
10. A computer device, characterized in that, The computer device includes a processor and a memory configured to store processor-executable instructions; the processor is configured to perform the test method for interface thermal resistance according to any one of claims 1 to 5.