Wide-range high-speed data acquisition system

Abstract

The invention discloses a wide-range high-speed data acquisition system. The system comprises a signal acquisition front end, a pre-amplifier, a filter network, an A / D conversion module, an FPGA, an ARM processor and a dual-port RAM. The ARM processor is used for writing sampling rate parameters and channel selection parameters, and the FPGA completes channel selection and sampling time sequence control based on the parameters and generates an A / D sampling clock through the clock module; the FPGA performs serial-parallel conversion on the serial conversion data output by the A / D and then writes the serial conversion data into the dual-port RAM, a ping-pong cache mechanism with at least two cache regions is adopted, an interruption notification is sent to the ARM processor when the dual-port RAM is full of the data, and the ARM processor reads the cache data to perform local storage or network transmission.

Description

Technical Field

[0001] This invention relates to the field of data acquisition, and more specifically to a wide-range, high-speed data acquisition system. Background Technology

[0002] Wide-range, high-speed data acquisition technology is widely used in radiation detection, nuclear instrument measurement, industrial non-destructive testing, and high-speed pulse signal analysis. Taking radiation detection as an example, gamma rays entering the detector generate photoelectric signals, which are then amplified by a preamplifier to form analog pulses. These pulses are then filtered by a filtering network to suppress high-frequency noise and power frequency interference. A high-resolution A / D converter is then used to sample the pulses at high speed, and the sampled data is provided to the back-end processing unit for storage, transmission, and further analysis. Because pulse signals have a large amplitude range, random arrival, and significant transient characteristics, data acquisition systems typically need to possess both high sampling rates and resolution, as well as wide dynamic range and stable clock quality to meet measurement requirements such as energy resolution and time resolution.

[0003] In existing technologies, common data acquisition architectures include a combination of "analog front-end + high-speed ADC + processor (or DSP / FPGA)". Limited by processor real-time performance, bus bandwidth, and cache structure, increasing the sampling rate or number of channels can easily lead to problems such as untimely data transfer, buffer overflow causing sample loss, and discontinuous data transmission. Furthermore, when switching sampling channels and rates according to different application scenarios, the system often needs to provide multiple operating clocks for clock generation and allocation. Poor clock jitter and delay control will further affect high-speed sampling accuracy and system stability. In addition, some applications require on / off control and status management of the sampling link or key components. Inappropriate coupling between control and acquisition links can increase system complexity and reduce reliability. Summary of the Invention

[0004] To achieve the above and other related objectives, this invention discloses a wide-range, high-speed data acquisition system, comprising: A signal acquisition front-end for outputting analog pulse signals, a preamplifier connected to the signal acquisition front-end, a filter network connected to the preamplifier, an A / D conversion module connected to the filter network, an FPGA, an ARM processor, and a dual-port RAM; The ARM processor is used to write sampling rate parameters and channel selection parameters to the FPGA during system initialization; The FPGA includes a PWM control module, a channel and sampling rate selection module, a clock module, an A / D sampling control module, a serial-to-parallel conversion module, a data storage control module, and an ARM interface control module; The channel and sampling rate selection module generates a clock configuration instruction based on the sampling rate parameter, and the clock module generates an A / D sampling clock based on an external input clock. The A / D sampling control module outputs a conversion timing control signal to the A / D conversion module based on the channel selection parameters and acquires serial conversion data. The serial-to-parallel conversion module converts the serial conversion data into parallel sampling data; the data storage control module writes the parallel sampling data into the corresponding buffer of the dual-port RAM, and outputs an interrupt notification to the ARM processor when the preset buffer is full. The ARM interface control module decodes the access address of the ARM processor to enable the ARM processor to read and write to the dual-port RAM, so that the ARM processor can read the sampled data and store it locally or transmit it to the host computer via the network.

[0005] Preferably, the dual-port RAM is logically divided into at least a first buffer and a second buffer; the data storage control module adopts a ping-pong buffer writing mechanism, which sends a first interrupt to the ARM processor after the first buffer is full to notify the readout of data from the first buffer and switches to writing to the second buffer; after the second buffer is full, it sends a second interrupt to the ARM processor to notify the readout of data from the second buffer and switches back to the first buffer, thereby realizing continuous sampling and continuous transmission.

[0006] Preferably, the PWM control module includes a microcontroller and an isolation drive module; the microcontroller is used to output PWM control signals, and the isolation drive module performs opto-isolation and driving on the PWM control signals before outputting them to the on / off control terminal of the A / D conversion module to realize the on / off control of the A / D conversion module; the microcontroller also reads and writes to the external EEPROM through the I / O port to expand the external memory.

[0007] Preferably, the PWM control module includes a counter, a judgment circuit, a counting step size setting circuit, and an upper and lower limit setting circuit; the counter counts based on a clock signal of a set period to form a reference value; the judgment circuit is used to determine the update direction of the reference value based on a duty cycle threshold; the counting step size setting circuit is used to provide the counter with an incrementing counting step size and a decrementing counting step size; the upper and lower limit setting circuit is used to generate an upper limit value and a lower limit value of the reference value to limit the amplitude of the reference value.

[0008] Preferably, the PWM control module satisfies the following duty cycle calculation and reference value update relationship: in, This refers to the PWM duty cycle. This is the conduction count value; This is the periodic count value; For the first The updated reference value; For the first The updated reference value; This is the upper limit of the reference value; This is the lower limit of the reference value; To increase the counting step size; To decrease the counting step size; This is the duty cycle threshold.

[0009] Preferably, the channel and sampling rate selection module includes register A and register B, and the ARM processor writes a command word to register A and register B according to the target sampling channel and target sampling rate; the clock module generates an A / D sampling clock corresponding to the command word based on an external input clock, and satisfies: in, This refers to the A / D sampling clock frequency; External input clock frequency; This refers to the PLL frequency multiplication factor; is the frequency division coefficient.

[0010] Preferably, the data storage control module is used to write the sampled data of each sampling channel into the dual-port RAM in channel order, and write byte by byte in order from low byte to high byte; wherein, the sampled data bit width of each channel is 24 bits, and the data storage control module outputs byte data for writing and write control signal to drive the dual-port RAM to complete the writing.

[0011] Secondly, this invention discloses a wide-range high-speed data acquisition method, executed based on the aforementioned wide-range high-speed data acquisition system, comprising: After system initialization, the ARM processor writes sampling rate parameters and channel selection parameters to the FPGA; the FPGA's channel and sampling rate selection module generates clock configuration instructions based on the sampling rate parameters, and the clock module generates the A / D sampling clock based on the external input clock. The A / D sampling control module outputs a conversion timing control signal based on the channel selection parameters to drive the A / D conversion module to complete sampling and output serial conversion data. The serial-to-parallel conversion module converts the serially converted data into parallel sampled data; The data storage control module writes parallel sampled data into the corresponding buffer of the dual-port RAM, and outputs an interrupt notification to the ARM processor when the preset buffer is full; After receiving an interrupt, the ARM processor reads the dual-port RAM through the ARM interface control module to complete the local storage of the sampled data or the network transmission to the host computer for processing.

[0012] Preferably, it further includes: during the sampling process, the PWM control module adaptively updates the reference value based on the duty cycle threshold, and calculates the duty cycle and the updated reference value according to the following relationship: in, This refers to the PWM duty cycle. This is the conduction count value; This is the periodic count value; For the first The updated reference value; For the first The updated reference value; This is the upper limit of the reference value; This is the lower limit of the reference value; To increase the counting step size; To decrease the counting step size; This is the duty cycle threshold.

[0013] Thirdly, the present invention discloses a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by an ARM processor, the ARM processor performs the wide-range high-speed data acquisition method described above.

[0014] By adopting the above technical solutions, high-speed timing logic such as A / D sampling control, serial-to-parallel conversion, and cache writing is integrated into the FPGA, and coupled with the ping-pong caching mechanism of dual-port RAM, the sampling and data reading / transmission are decoupled. This allows for continuous and stable operation under high sampling rates and wide dynamic range conditions while reducing the risk of sample loss. Simultaneously, the ARM processor is only responsible for parameter configuration, cache reading, and local storage or network transmission, reducing the real-time data handling pressure on the processor side and improving overall data throughput. Furthermore, the system achieves flexible switching of sampling channels and sampling rates through the coordinated configuration of the channel and sampling rate selection module and the clock module, and utilizes the FPGA's PLL clock resources to improve sampling clock stability, thereby improving high-speed sampling accuracy and system reliability. Further, PWM control and isolated driving are used to control the on / off states of key components, and combined with external memory expansion, the system's state management and engineering adaptability are enhanced, comprehensively improving the continuity, configurability, and reliability in wide-range, high-speed data acquisition scenarios. Attached Figure Description

[0015] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of this disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1 This is the overall system structure according to an embodiment of the present invention; Figure 2 This is a logic diagram of the PWM function module in an embodiment of the present invention; Figure 3 This is the channel and sampling rate selection module in an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Reference Figure 1 This invention provides a wide-range, high-speed data acquisition system, comprising: A signal acquisition front-end for outputting analog pulse signals, a preamplifier connected to the signal acquisition front-end, a filter network connected to the preamplifier, an A / D conversion module connected to the filter network, an FPGA, an ARM processor, and a dual-port RAM; The ARM processor is used to write sampling rate parameters and channel selection parameters to the FPGA during system initialization; The FPGA includes a PWM control module, a channel and sampling rate selection module, a clock module, an A / D sampling control module, a serial-to-parallel conversion module, a data storage control module, and an ARM interface control module; The channel and sampling rate selection module generates a clock configuration instruction based on the sampling rate parameter, and the clock module generates an A / D sampling clock based on an external input clock. The A / D sampling control module outputs a conversion timing control signal to the A / D conversion module based on the channel selection parameters and acquires serial conversion data. The serial-to-parallel conversion module converts the serial conversion data into parallel sampling data; the data storage control module writes the parallel sampling data into the corresponding buffer of the dual-port RAM, and outputs an interrupt notification to the ARM processor when the preset buffer is full. The ARM interface control module decodes the access address of the ARM processor to enable the ARM processor to read and write to the dual-port RAM, so that the ARM processor can read the sampled data and store it locally or transmit it to the host computer via the network.

[0018] Preferably, the dual-port RAM is logically divided into at least a first buffer and a second buffer; the data storage control module adopts a ping-pong buffer writing mechanism, which sends a first interrupt to the ARM processor after the first buffer is full to notify the readout of data from the first buffer and switches to writing to the second buffer; after the second buffer is full, it sends a second interrupt to the ARM processor to notify the readout of data from the second buffer and switches back to the first buffer, thereby realizing continuous sampling and continuous transmission.

[0019] Preferably, the PWM control module includes a microcontroller and an isolation drive module; the microcontroller is used to output PWM control signals, and the isolation drive module performs opto-isolation and driving on the PWM control signals before outputting them to the on / off control terminal of the A / D conversion module to realize the on / off control of the A / D conversion module; the microcontroller also reads and writes to the external EEPROM through the I / O port to expand the external memory.

[0020] Preferably, the PWM control module includes a counter, a judgment circuit, a counting step size setting circuit, and an upper and lower limit setting circuit; the counter counts based on a clock signal of a set period to form a reference value; the judgment circuit is used to determine the update direction of the reference value based on a duty cycle threshold; the counting step size setting circuit is used to provide the counter with an incrementing counting step size and a decrementing counting step size; the upper and lower limit setting circuit is used to generate an upper limit value and a lower limit value of the reference value to limit the amplitude of the reference value.

[0021] Preferably, the PWM control module satisfies the following duty cycle calculation and reference value update relationship: in, This refers to the PWM duty cycle. This is the conduction count value; This is the periodic count value; For the first The updated reference value; For the first The updated reference value; This is the upper limit of the reference value; This is the lower limit of the reference value; To increase the counting step size; To decrease the counting step size; This is the duty cycle threshold.

[0022] Preferably, the channel and sampling rate selection module includes register A and register B, and the ARM processor writes a command word to register A and register B according to the target sampling channel and target sampling rate; the clock module generates an A / D sampling clock corresponding to the command word based on an external input clock, and satisfies: in, This refers to the A / D sampling clock frequency; External input clock frequency; This refers to the PLL frequency multiplication factor; is the frequency division coefficient.

[0023] Preferably, the data storage control module is used to write the sampled data of each sampling channel into the dual-port RAM in channel order, and write byte by byte in order from low byte to high byte; wherein, the sampled data bit width of each channel is 24 bits, and the data storage control module outputs byte data for writing and write control signal to drive the dual-port RAM to complete the writing.

[0024] Preferably, this invention provides a wide-range, high-speed data acquisition system. The system employs a collaborative architecture of FPGA and ARM processor, and incorporates PWM control functionality to achieve high-speed, high-precision acquisition and continuous data transmission of wide dynamic range analog pulse signals. This embodiment features a scalable design, easily expandable to multi-channel acquisition, and adaptable to other A / D conversion module interfaces while maintaining the overall framework, thereby enhancing system application flexibility.

[0025] like Figure 1 As shown, the system includes: a signal acquisition front-end, a preamplifier, a filter network, an A / D conversion module, an FPGA, an ARM processor, and a dual-port RAM.

[0026] In this embodiment, the signal acquisition front end can be a radiation detection link. Taking gamma-ray detection as an example, gamma rays enter the detector's front window, generating photoelectrons and forming a photoelectric signal. The photoelectric signal is amplified by a preamplifier and output as an analog pulse signal. A filtering network is used to filter out high-frequency noise and power frequency interference, thereby improving the signal-to-noise ratio of subsequent sampling.

[0027] In this embodiment, a variable gain amplification stage can also be set to adapt to a wide input range. The variable gain amplification stage can be configured by the control signal output by the ARM processor to ensure that the analog pulse signal is within a suitable dynamic range before entering the A / D conversion module. The aforementioned variable gain amplification stage can be implemented as part of the signal acquisition front end or integrated into the analog link after the preamplifier / filter network.

[0028] The A / D conversion module converts the pulse analog signal processed by the analog link into a digital signal. The A / D conversion module can be configured with a function selection mode; its sampling clock is provided by the FPGA, and the sampling rate can be adjusted by changing the FPGA output sampling clock frequency.

[0029] The FPGA is used for parallel control of multi-channel sampling and data transfer, writing sampled data into a dual-port RAM in byte sequence for buffering. The dual-port RAM serves as a high-speed buffer between FPGA writing and ARM reading, achieving decoupling between sampling and transmission. The ARM processor is used for system initialization configuration, reading sampled data from the dual-port RAM, and storing it locally or transmitting it over a network to a host computer for further processing.

[0030] In this embodiment, the dual-port RAM is logically divided into at least a first buffer and a second buffer (e.g., an upper half and a lower half). When the FPGA fills the first buffer, it sends an interrupt notification to the ARM processor. The ARM responds to the interrupt and reads the data from the first buffer into its own memory for storage or forwarding; simultaneously, the FPGA switches to writing to the second buffer. When the second buffer is full, the FPGA sends another interrupt notification to the ARM processor, which reads the data from the second buffer, and the FPGA switches back to the first buffer. This ping-pong caching mechanism ensures continuous system data sampling and data reading / transmission, reducing the risk of lost samples.

[0031] In this embodiment, the PWM control module can be used to control the on / off state of the A / D conversion module, thereby achieving state management of key components in the acquisition link. The PWM control signal can be output by a microcontroller. This invention uses an AT13C3051 microcontroller, which is opto-isolated and driven by an isolation driver module before being applied to the on / off control terminal of the A / D conversion module to realize the PWM control process.

[0032] Furthermore, the microcontroller can read and write to the external EEPROM through a simulated IIC bus via a common I / O port to expand external memory (e.g., for storing configuration parameters, calibration data, or status information).

[0033] Reference Figure 2 Preferably, the PWM control module may logically include: a counter, a judgment circuit, a counting step size setting circuit, and an upper and lower limit setting circuit.

[0034] The counter is used to count under a clock signal of a set period to form a reference value, and to count and count the input pulse signal to obtain PWM-related counting information; The determination circuit is connected to the counter and is used to determine the update direction of the reference value based on the duty cycle threshold. The counting step setting circuit is connected to the judgment circuit and is used to determine the increment and decrement counting steps according to the duty cycle threshold and provide them to the counter. The upper and lower limit setting circuit is used to generate the upper and lower limits of the reference value, limit the reference value, and prevent the control quantity from exceeding the safe range.

[0035] Preferably, the PWM duty cycle and the reference value update can satisfy the following relationship: in, This refers to the PWM duty cycle. This is the conduction count value; This is the periodic count value; For the first The updated reference value; For the first The updated reference value; This is the upper limit of the reference value; This is the lower limit of the reference value; To increase the counting step size; To decrease the counting step size; This is the duty cycle threshold.

[0036] Preferably, the PWM control module can also adopt a "microcontroller + isolation driver module" structure: the microcontroller outputs the PWM control signal, and the isolation driver module performs opto-isolation and driving on the PWM control signal before outputting it to the on / off control terminal of the A / D conversion module to realize the on / off control of the A / D conversion module. The microcontroller can also read and write to the external EEPROM through the I / O port to simulate the IIC bus, thereby expanding the external memory.

[0037] Preferably, to meet the requirements of selectable sampling channels and adjustable sampling rates, the channel and sampling rate selection module is used to receive the configuration command written by the ARM processor and output clock configuration and channel selection control information accordingly.

[0038] Preferably, the channel and sampling rate selection module may include register A and register B: Reference Figure 3 Register A is used to store channel selection related bits. For example, bits 0 to 4 of register A can be used to select the A / D conversion module channel (e.g., CH0 to CH4), while the remaining bits are reserved or used for expansion. Register B is used to store sampling rate selection related bits. For example, several bits of register B are used to represent sampling rate selection codes (e.g., FS0 to FS7).

[0039] Before data acquisition begins, the ARM processor writes the corresponding command words to registers A and B according to the required channel and sampling rate; the channel and sampling rate selection module generates clock configuration instructions and outputs channel selection parameters accordingly.

[0040] Preferably, the external input clock frequency is 16.384 MHz. Since the operating clocks of each module in the system are different and the sampling rate is variable, the clock module needs to generate multiple clock signals to drive the sampling of each logic module and the A / D conversion module respectively. To reduce the impact of clock jitter and delay on sampling accuracy, this embodiment uses the FPGA's internal PLL clock resources to generate the master clock and derive the required clocks.

[0041] Preferably, the A / D sampling clock frequency can meet the following requirements: in, This refers to the A / D sampling clock frequency; External input clock frequency; This refers to the PLL frequency multiplication factor; This represents the frequency division coefficient. The sampling rate parameter written by the ARM processor can be mapped to... With / or The configuration allows for dynamic switching of the sampling rate.

[0042] Preferably, the dual-port RAM is used for data caching: on one hand, it stores the sampled data written by the FPGA, and on the other hand, it is read by the ARM processor for further storage and processing. The dual-port RAM has independent control lines, address lines, and data lines, enabling parallel access to both ports, thus supporting continuous writing on the FPGA side and asynchronous reading on the ARM side.

[0043] Preferably, the dual-port RAM module can be implemented using a parameterized model library provided by the FPGA manufacturer (e.g., by calling the Mega-lpm library included with the FPGA to generate the dual-port RAM). Simultaneously, the dual-port RAM is logically divided into a first buffer and a second buffer, and combined with the data storage control module, it enables ping-pong buffer writing and interrupt notification.

[0044] Preferably, the task of the A / D sampling control module is to output corresponding timing control signals on its pins according to the conversion timing requirements of the A / D conversion module, so that the A / D conversion module can complete operations such as startup, configuration and data reading.

[0045] Preferably, the A / D sampling control module can initiate a conversion when the trigger condition is met: output a conversion timing control signal to the A / D conversion module, and read its serial output data bit by bit after the A / D conversion module is ready to form a frame of serial conversion data; after each sampling operation is completed, it enters a waiting state until the next trigger event arrives.

[0046] Preferably, the data storage control module is used to write the parallel sampling data of each sampling channel into the dual-port RAM buffer, and to send an interrupt notification to the ARM processor when the buffer is full.

[0047] Preferably, the sampling data width for each channel is 24 bits. The data storage control module organizes the sampling data according to the channel order and writes it byte by byte into the dual-port RAM in ascending order of low byte: for example, splitting the 24-bit data into low byte, middle byte, and high byte and writing them sequentially. The data storage control module outputs byte data and write control signals to drive the writing to the dual-port RAM.

[0048] When the first buffer is full, the data storage control module triggers an interrupt to notify the ARM processor to read the data from the first buffer and simultaneously switches to writing to the second buffer; when the second buffer is full, it switches back to the first buffer in the same way, thus realizing continuous sampling and continuous transmission.

[0049] Preferably, the ARM interface control module is used to realize data and control interaction between the ARM processor, the FPGA, and the dual-port RAM: When the ARM processor writes the sampling rate parameter and channel selection parameter to the control register, the ARM interface control module sends the information to the corresponding logic such as the channel and sampling rate selection module and the clock module. When the ARM processor reads sampled data from the dual-port RAM, the ARM interface control module decodes the ARM access address. Secondly, this invention discloses a wide-range high-speed data acquisition method, executed based on the aforementioned wide-range high-speed data acquisition system, comprising: After system initialization, the ARM processor writes sampling rate parameters and channel selection parameters to the FPGA; the FPGA's channel and sampling rate selection module generates clock configuration instructions based on the sampling rate parameters, and the clock module generates the A / D sampling clock based on the external input clock. The A / D sampling control module outputs a conversion timing control signal based on the channel selection parameters to drive the A / D conversion module to complete sampling and output serial conversion data. The serial-to-parallel conversion module converts the serially converted data into parallel sampled data; The data storage control module writes parallel sampled data into the corresponding buffer of the dual-port RAM, and outputs an interrupt notification to the ARM processor when the preset buffer is full; After receiving an interrupt, the ARM processor reads the dual-port RAM through the ARM interface control module to complete the local storage of the sampled data or the network transmission to the host computer for processing.

[0050] Preferably, it further includes: during the sampling process, the PWM control module adaptively updates the reference value based on the duty cycle threshold, and calculates the duty cycle and the updated reference value according to the following relationship: in, This refers to the PWM duty cycle. This is the conduction count value; This is the periodic count value; For the first The updated reference value; For the first The updated reference value; This is the upper limit of the reference value; This is the lower limit of the reference value; To increase the counting step size; To decrease the counting step size; This is the duty cycle threshold.

[0051] Thirdly, the present invention discloses a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by an ARM processor, the ARM processor performs the wide-range high-speed data acquisition method described above.

[0052] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the meaning consistent with their meaning in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined.

[0053] For the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0054] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wide-range, high-speed data acquisition system, characterized in that, include: A signal acquisition front-end for outputting analog pulse signals, a preamplifier connected to the signal acquisition front-end, a filter network connected to the preamplifier, an A / D conversion module connected to the filter network, an FPGA, an ARM processor, and a dual-port RAM; The ARM processor is used to write sampling rate parameters and channel selection parameters to the FPGA during system initialization; The FPGA includes a PWM control module, a channel and sampling rate selection module, a clock module, an A / D sampling control module, a serial-to-parallel conversion module, a data storage control module, and an ARM interface control module; The channel and sampling rate selection module generates a clock configuration instruction based on the sampling rate parameter, and the clock module generates an A / D sampling clock based on an external input clock. The A / D sampling control module outputs a conversion timing control signal to the A / D conversion module based on the channel selection parameters and acquires serial conversion data. The serial-to-parallel conversion module converts the serial conversion data into parallel sampling data; the data storage control module writes the parallel sampling data into the corresponding buffer of the dual-port RAM, and outputs an interrupt notification to the ARM processor when the preset buffer is full. The ARM interface control module decodes the access address of the ARM processor to enable the ARM processor to read and write to the dual-port RAM, so that the ARM processor can read the sampled data and store it locally or transmit it to the host computer via the network.

2. The wide-range high-speed data acquisition system according to claim 1, characterized in that, The dual-port RAM is logically divided into at least a first cache area and a second cache area; the data storage control module adopts a ping-pong cache writing mechanism, which sends a first interrupt to the ARM processor after the first cache area is full to notify the readout of the data in the first cache area, and then switches to writing to the second cache area. After the second buffer is full, a second interrupt is sent to the ARM processor to notify the readout of the data in the second buffer and switch back to the first buffer, thereby achieving continuous sampling and continuous transmission.

3. The wide-range high-speed data acquisition system according to claim 1, characterized in that, The PWM control module includes a microcontroller and an isolation driver module. The microcontroller outputs a PWM control signal, and the isolation driver module performs opto-isolation and driving on the PWM control signal before outputting it to the on / off control terminal of the A / D conversion module to realize the on / off control of the A / D conversion module. The microcontroller also reads and writes to the external EEPROM through the I / O port to expand the external memory.

4. The wide-range high-speed data acquisition system according to claim 1, characterized in that, The PWM control module includes a counter, a judgment circuit, a counting step size setting circuit, and an upper and lower limit setting circuit. The counter counts based on a clock signal with a set period to form a reference value. The judgment circuit determines the update direction of the reference value based on a duty cycle threshold. The counting step size setting circuit provides the counter with an incrementing and decrementing counting step size. The upper and lower limit setting circuit generates an upper limit and a lower limit of the reference value to limit the amplitude of the reference value.

5. The wide-range high-speed data acquisition system according to claim 1, characterized in that, The PWM control module satisfies the following duty cycle calculation and reference value update relationship: in, This refers to the PWM duty cycle. This is the conduction count value; This is the periodic count value; For the first The updated reference value; For the first The updated reference value; This is the upper limit of the reference value; This is the lower limit of the reference value; To increase the counting step size; To decrease the counting step size; This is the duty cycle threshold.

6. The wide-range high-speed data acquisition system according to claim 1, characterized in that, The channel and sampling rate selection module includes register A and register B. The ARM processor writes a command word to register A and register B according to the target sampling channel and target sampling rate. The clock module generates an A / D sampling clock corresponding to the command word based on an external input clock, and satisfies the following: in, This refers to the A / D sampling clock frequency; This is the external input clock frequency; This refers to the PLL frequency multiplication factor; is the frequency division coefficient.

7. The wide-range high-speed data acquisition system according to claim 1, characterized in that, The data storage control module is used to write the sampled data of each sampling channel into the dual-port RAM in channel order, and write it byte by byte from low byte to high byte; wherein, the sampling data bit width of each channel is 24 bits, and the data storage control module outputs the byte data for writing and the write control signal to drive the dual-port RAM to complete the writing.

8. A wide-range, high-speed data acquisition method, characterized in that, Execution based on the wide-range high-speed data acquisition system according to any one of claims 1 to 7, including: After system initialization, the ARM processor writes sampling rate parameters and channel selection parameters to the FPGA; the FPGA's channel and sampling rate selection module generates clock configuration instructions based on the sampling rate parameters, and the clock module generates the A / D sampling clock based on the external input clock. The A / D sampling control module outputs a conversion timing control signal based on the channel selection parameters to drive the A / D conversion module to complete sampling and output serial conversion data. The serial-to-parallel conversion module converts the serially converted data into parallel sampled data; The data storage control module writes parallel sampled data into the corresponding buffer of the dual-port RAM, and outputs an interrupt notification to the ARM processor when the preset buffer is full; After receiving an interrupt, the ARM processor reads the dual-port RAM through the ARM interface control module to complete the local storage of the sampled data or the network transmission to the host computer for processing.

9. The wide-range high-speed data acquisition method according to claim 8, characterized in that, Also includes: During the sampling process, the PWM control module adaptively updates the reference value based on the duty cycle threshold, and calculates the duty cycle and updated reference value according to the following relationship: in, This refers to the PWM duty cycle. This is the conduction count value; This is the periodic count value; For the first The updated reference value; For the first The updated reference value; This is the upper limit of the reference value; This is the lower limit of the reference value; To increase the counting step size; To decrease the counting step size; This is the duty cycle threshold.

10. A computer-readable storage medium having a computer program stored thereon, wherein when executed by an ARM processor, the computer program causes the ARM processor to perform the wide-range high-speed data acquisition method of claim 8 or 9.

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