Multi-test channel distribution method for electronic component detection

Abstract

The invention relates to the technical field of electronic component detection, in particular to a multi-test channel distribution method for electronic component detection, which comprises the following steps of: obtaining pin topological structure data and I / O (Input / Output) characteristic parameters of a multi-pin electronic component, and performing pin functional domain division and channel topological segment decomposition in combination with test task requirements; and realizing structured modeling of the test task. Based on the load balancing state of the current test channel, dynamic load compensation estimation is carried out, and the perspectiveness of resource scheduling is improved. And a test channel operation dependency graph is further constructed, resource conflicts and signal interference in the test process are quantified, and a collaborative optimization channel allocation scheme is generated. According to the method, real-time dynamic allocation of multi-channel test tasks is realized, the channel utilization rate is effectively improved, the test conflict is reduced, the test parallelism and the system efficiency are enhanced, and the method is suitable for automatic detection scenes of high-pin-number and multifunctional electronic components.

Description

Technical Field

[0001] This invention relates to the field of electronic component testing technology, and in particular to a method for allocating multiple test channels for electronic component testing. Background Technology

[0002] With the rapid development of electronic manufacturing technology, integrated circuits and multi-pin electronic components are increasingly widely used in communications, automotive electronics, industrial control, and consumer electronics products, with their complexity and integration levels constantly increasing. In the manufacturing and quality inspection stages, comprehensive, efficient, and accurate testing of the electrical performance of multi-pin components has become a crucial step in ensuring product reliability. Traditional electronic component testing often employs single-channel or fixed-channel allocation methods, which struggle to meet the parallel testing needs of devices with high pin counts, multiple I / O types, and complex topologies. This can easily lead to uneven utilization of test channel resources, timing conflicts, and signal crosstalk, severely impacting testing efficiency and accuracy.

[0003] Existing test systems, when handling multi-task parallel testing, typically lack in-depth modeling of pin topology and I / O functional characteristics. They fail to adequately consider the timing dependencies, resource contention, and electrical coupling characteristics between different test signals, resulting in rigid channel allocation strategies and difficulty in achieving dynamic optimization. This is particularly pronounced in complex scenarios involving heterogeneous test tasks (such as digital I / O, analog signals, and power pins), where issues like unbalanced test channel load, critical path delays, and frequent test conflicts become especially prominent. Furthermore, traditional methods often rely on static configuration for channel mapping, lacking the ability to perceive and adjust real-time test states, thus failing to achieve closed-loop optimization.

[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this invention is to provide a method for allocating multiple test channels for electronic component testing. This method aims to solve the technical problems of existing methods for allocating multiple test channels in electronic component testing, which are unable to take into account multi-pin topology, I / O characteristics and real-time load status, resulting in low channel resource utilization, frequent test conflicts, and a lack of dynamic collaborative optimization capabilities.

[0006] To achieve the above objectives, the present invention provides a method for allocating multiple test channels for testing electronic components, the method comprising: Obtain the pin topology data and I / O characteristic parameters of multi-pin electronic components, and divide the pin functional domains according to the pin topology data and I / O characteristic parameters to obtain the pin functional domain data. Obtain test task requirement data; decompose the test channel topology segment into test task requirement data and pin function domain data to obtain channel topology decomposition data. Obtain the current test channel load balancing data, and perform dynamic load compensation estimation based on the current test channel load balancing data and channel topology decomposition data to obtain load compensation estimation data; Based on the load compensation estimation data, a test channel operation dependency graph is constructed to obtain channel operation dependency graph data; based on the channel operation dependency graph data, test conflict quantification is performed to obtain channel conflict quantification data; based on the channel conflict quantification data, test channel collaborative allocation is generated to obtain test channel collaborative allocation data, so as to realize real-time dynamic optimization allocation of multiple test channels.

[0007] Optionally, the step of dividing the pin functional domains based on the pin topology data and I / O characteristic parameters to obtain pin functional domain data includes: Pin-channel coupling relationship analysis is performed based on pin topology data and I / O characteristic parameters to obtain pin-channel coupling matrix data; Obtain pin test timing data, and calculate the test coordination frequency based on the pin test timing data to obtain the test coordination frequency data; Digital twin connected domains are constructed based on pin-channel coupling matrix data and test coordination frequency data to obtain pin functional domain data.

[0008] Optionally, the step of constructing a digital twin connected domain based on pin-channel coupling matrix data and test coordination frequency data to obtain pin functional domain data includes: Based on the pin-channel coupling matrix data and test coordination frequency data, virtual test topology coverage features and dynamic signal transmission features are extracted, resulting in virtual topology coverage feature data and dynamic signal transmission feature data, respectively. Based on the virtual topology coverage feature data and dynamic signal transmission feature data, a twin coupling diagram is generated from the pin-channel coupling matrix data to obtain twin coupling diagram data; The virtual-real mismatch region detection is performed on the twin coupling graph data to obtain virtual-real calibration graph data. The virtual-real mismatch region detection includes signal delay mismatch detection, level anomaly tomography detection, and dynamic verification detection of test permissions. Test condition timing constraints are injected into the virtual and real calibration map data to obtain timing constraint map data; Functional connectivity subdomains are extracted from the timing constraint diagram data to obtain pin functional domain data.

[0009] Optionally, the step of decomposing the test task requirement data and pin functional domain data into test channel topology segments to obtain channel topology decomposition data includes: The test channel segment topology is divided based on the test task requirement data and pin functional domain data to obtain channel topology division data. Based on the channel topology partitioning data, signal transmission characteristics and key test nodes are extracted to obtain signal transmission characteristic data and key test node data, respectively. Based on signal transmission characteristic data and key test node data, the channel topology partitioning data is processed for test timing dependency to obtain timing dependency data. Dynamic dependency graphs are constructed based on temporal dependency data to obtain channel topology decomposition data.

[0010] Optionally, the step of performing dynamic load compensation estimation based on the current test channel load balancing data and channel topology decomposition data to obtain load compensation estimation data includes: Based on the current test channel load balancing data and channel topology decomposition data, multi-signal test timing overlay calculations are performed to obtain timing overlay data; Signal density kernel distribution is calculated based on time-series superimposed data to obtain local load clustering intensity data; Based on the current test channel load balancing data, the channel carrying capacity and test response cycle are calculated to obtain the carrying capacity data and response cycle data respectively. Based on the load capacity data and response cycle data, dynamic load compensation time extrapolation is performed on the local load concentration intensity data to obtain load compensation estimation data.

[0011] Optionally, the step of constructing the test channel operation dependency graph based on the load compensation estimation data to obtain the channel operation dependency graph data includes: Based on the current test channel load balancing data and channel topology decomposition data, an operation dependency subgraph is constructed for the test channel segment to obtain the operation dependency subgraph data. Dynamic weighting is performed on the operation dependency subgraph data based on the load compensation estimation data to obtain dynamic weighted graph data. Directed acyclic allocation optimization is performed based on dynamic weight graph data to obtain channel operation dependency graph data.

[0012] Optionally, the step of performing test conflict quantization based on channel operation dependency graph data to obtain channel conflict quantization data includes: Based on the channel operation dependency graph data, test resource usage mapping is performed to obtain resource usage data; Conflicting tuples are extracted from resource usage data to obtain conflicting tuple data. Based on the conflict tuple data, signal overlap tension quantization is performed to obtain channel conflict quantization data.

[0013] Optionally, the step of performing signal overlap tension quantization based on conflict tuple data to obtain channel conflict quantization data includes: The overlap of non-steady-state signals and the intersection of time-series occupancy are calculated based on the conflict tuple data, and the dynamic boundary overlap data and the intersection of time-series occupancy data are obtained respectively. Based on the dynamic boundary overlap data and the time sequence occupancy intersection data, the shared test node contention is analyzed to obtain node contention analysis data; Based on the node competition analysis data, signal tension propagation modeling is performed to obtain tension propagation matrix data; Based on the tension propagation matrix data, gravity compensation control was performed on a high-priority test task to obtain channel conflict quantification data.

[0014] Optionally, the step of generating test channel collaborative allocation data based on channel conflict quantification data to achieve real-time dynamic optimization allocation of multiple test channels includes: Conflict core clusters are identified based on channel conflict quantification data to obtain conflict core cluster data; Based on the conflict core cluster data, the test channel topology-level allocation sequence is optimized to obtain the allocation sequence optimization data; Based on the allocation sequence optimization data, test channel collaborative allocation data is generated to drive the digital twin test platform to perform real-time dynamic optimization allocation of multiple test channels.

[0015] Furthermore, to achieve the above objectives, the present invention also provides a multi-test channel allocation device for electronic component testing, the device comprising: a memory, a processor, and a multi-test channel allocation program for electronic component testing stored in the memory and executable on the processor, the multi-test channel allocation program for electronic component testing being configured to implement the steps of the multi-test channel allocation method for electronic component testing as described in any one of the above descriptions.

[0016] This invention provides a multi-test channel allocation method for electronic component testing. The method integrates the pin topology and I / O characteristic parameters of multi-pin electronic components to achieve intelligent partitioning of pin functional domains. By combining test task requirements with channel topology decomposition, a dynamic load sensing mechanism is constructed, enabling accurate estimation and compensation of channel load changes. Furthermore, by establishing a test channel operation dependency graph and conflict quantification model, resource contention and signal interference risks are effectively identified, thereby generating a collaboratively optimized channel allocation scheme. This method achieves high-concurrency, low-conflict, and load-balanced intelligent allocation of multiple test tasks under complex pin structures, significantly improving test channel utilization, test efficiency, and system stability. It supports real-time dynamic optimization of the electronic component testing process and is suitable for large-scale automated testing scenarios of high-density, multi-functional integrated circuits. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating an embodiment of the multi-test channel allocation method for electronic component testing according to the present invention.

[0018] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] Reference Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the multi-test channel allocation method for electronic component testing according to the present invention.

[0021] In one embodiment, the multi-test channel allocation method for electronic component testing includes: Step S100: Obtain the pin topology data and I / O characteristic parameters of the multi-pin electronic component, and divide the pin functional domains according to the pin topology data and I / O characteristic parameters to obtain the pin functional domain data.

[0022] Multi-pin electronic components can be integrated circuits or packaged devices with multiple electrical connection pins, used for signal transmission, power supply, and functional control. Multi-pin electronic components can serve as the object under test (DUT), and their pin structure and functional characteristics determine the complexity and adaptation requirements of the test channel allocation strategy. Pin topology data can be structural information describing the physical layout, electrical, and spatial adjacency relationships of each pin of the multi-pin electronic component. In an exemplary embodiment, pin topology data can be extracted from component package specifications, CAD models, or automated optical inspection systems to determine pin positions. Pin topology data can provide a physical structural basis for functional domain partitioning, avoiding misjudgments due to signal crosstalk caused by pin proximity. I / O characteristic parameters can be a set of data characterizing the electrical behavior attributes of each pin, including signal type, drive capability, voltage domain, timing constraints, etc. For example, I / O characteristic parameters can be obtained from component datasheets, design netlists, or functional simulation models. I / O characteristic parameters can be used to support the classification of pins according to functional semantics, distinguishing different functional types such as digital, analog, power, and ground.

[0023] Pin functional domain partitioning can be based on pin topology data and I / O characteristic parameters, clustering pins into logical groups with the same or similar functional semantics. Further, pin functional domain partitioning can employ clustering algorithms or rule engines to group pins with similar functional attributes and spatial proximity into the same functional domain. In a specific embodiment, pin functional domain partitioning can be performed through hard partitioning based on I / O type labels and voltage domains, combined with posterior verification using topological adjacency; or graph neural networks can be used to embed pin nodes, generating functional domains through similarity clustering. Pin functional domain partitioning can form semantically consistent and electrically isolated functional groups, reducing the risk of crosstalk in subsequent allocation. Pin functional domain data can be structured data output from the pin functional domain partitioning operation, containing the pin set and its attribute labels within each functional domain. Pin functional domain data can be used as an intermediate mapping layer between test tasks and physical channels, improving the semantic consistency of channel allocation. In an exemplary embodiment, pin functional domain data can include, but is not limited to, one or more of power functional domains, high-speed digital I / O functional domains, and analog signal functional domains.

[0024] Step S200: Obtain test task requirement data. Perform test channel topology segment decomposition on the test task requirement data and pin function domain data to obtain channel topology decomposition data.

[0025] The test task requirement data can be a set of specific requirements for pin functions, signal types, timing requirements, and resource consumption of the test project to be executed. In a specific embodiment, the test task requirement data can be generated by the test program configuration file or the automated test equipment (ATE) task scheduler. The test task requirement data can be used to drive channel topology decomposition to ensure that the test logic matches the physical resources. The test channel topology segment decomposition can be a joint mapping of test task requirements and pin functional domain data, dividing the channel into several independently schedulable channel resource segments. Further, the test channel topology segment decomposition can match test tasks by functional domain and decompose them into several sub-task units aligned with physical channel segments. For example, the test channel topology segment decomposition can adopt a greedy matching strategy, prioritizing the allocation of tasks to the channel segment with the highest functional domain matching degree; or construct a bipartite graph matching model to solve the optimal mapping of task-functional domain-channel segment. The test channel topology segment decomposition can achieve the initial alignment of logical test requirements with physical channel resources and support parallel scheduling. The channel topology decomposition data can be a data structure output by the test channel topology segment decomposition operation, containing the pin set corresponding to each topology segment, the required channel type, and resource constraints. Channel topology decomposition data can be used to provide input for dynamic load estimation and support resource scheduling at the segment level.

[0026] Step S300: Obtain the current test channel load balancing data, and perform dynamic load compensation estimation based on the current test channel load balancing data and channel topology decomposition data to obtain load compensation estimation data.

[0027] The current test channel load balancing data can be a dynamic set of indicators reflecting the current resource utilization, task queuing status, and real-time throughput of each test channel. In one specific embodiment, the current test channel load balancing data can be collected by the test system runtime monitoring module, collecting indicators such as channel occupancy and task completion latency. The current test channel load balancing data can be used as input for dynamic load compensation estimation to identify resource bottlenecks and idle areas. Dynamic load compensation estimation can be a process of predicting future resource demand changes and calculating compensation adjustments based on the current load status and channel topology decomposition data. Furthermore, dynamic load compensation estimation can combine historical load trends and current topology segment demands to predict future load deviations and calculate compensation amounts. In an exemplary embodiment, dynamic load compensation estimation can use a sliding window regression model to predict the load of each channel segment in the next cycle; or it can use a reinforcement learning agent to evaluate the impact of different compensation strategies on system throughput. Dynamic load compensation estimation can generate load rebalancing suggestions to avoid local overload or resource idleness. The load compensation estimation data can be the adjustment suggestion data output by the dynamic load compensation estimation operation, including the expected load deviation and compensation direction for each channel segment. Load compensation estimation data can be used to guide subsequent dependency graph construction, introducing a load-aware dimension to optimize channel allocation.

[0028] Step S400: Construct a test channel operation dependency graph based on the load compensation estimation data to obtain channel operation dependency graph data. Quantify test conflicts based on the channel operation dependency graph data to obtain channel conflict quantification data. Generate test channel collaborative allocation data based on the channel conflict quantification data to achieve real-time dynamic optimization allocation of multiple test channels.

[0029] The test channel operation dependency graph construction can be a directed graph model based on load compensation estimation data, establishing temporal dependencies, resource sharing, and electrical coupling relationships between test operations. Further, the test channel operation dependency graph construction can use topology segments as nodes, adding dependency or interference edges according to load compensation suggestions and electrical coupling rules. In a specific embodiment, if two topology segments share a power domain or have adjacent wiring, a high-weight interference edge is added; if there are temporal constraints on the tasks, a directed dependency edge is added. The test channel operation dependency graph construction can integrate load and topology information into a structured dependency model, explicitly expressing the interactions between operations. The channel operation dependency graph data can be the graph structure data output by the test channel operation dependency graph construction operation, where nodes represent test operations and edges represent dependency or interference relationships. The channel operation dependency graph data can be used as input to a conflict quantification model, supporting systematic analysis of resource contention and signal interference.

[0030] Test conflict quantification can be used to numerically evaluate the edge relationships in a channel operation dependency graph, calculating risk indicators such as signal crosstalk strength and timing competition probability. Furthermore, test conflict quantification can assign conflict weights to each edge in the graph, comprehensively considering factors such as signal type, frequency, and voltage difference. For example, test conflict quantification can calculate crosstalk strength as a conflict value based on an electromagnetic coupling model; or it can use an empirical rule base to score dependency types (e.g., analog-digital sharing = high conflict). Test conflict quantification can transform qualitative dependencies into comparable conflict weights, supporting optimization decisions. Channel conflict quantification data can be the numerical risk assessment result output by the test conflict quantification operation, including the conflict level or interference coefficient of each operation pair. Channel conflict quantification data can be used as constraints for collaborative allocation generation, suppressing high-risk channel combinations.

[0031] The test channel collaborative allocation generation can generate a channel allocation scheme that satisfies load balancing and low-conflict constraints by integrating load compensation estimation data and channel conflict quantification data. Furthermore, the test channel collaborative allocation generation can solve for the optimal or feasible solution of channel allocation under the constraints of conflict threshold and load balancing. In an exemplary embodiment, the test channel collaborative allocation generation can employ a constraint satisfaction problem (CSP) solver, using conflict data as a soft constraint; or it can use a genetic algorithm to search for low-conflict, high-balance solutions in the allocation space. The test channel collaborative allocation generation can output an executable dynamic allocation scheme, achieving high-concurrency, low-conflict, and load-balanced test execution. The test channel collaborative allocation data can be the final allocation scheme output by the test channel collaborative allocation generation operation, containing the mapping relationship between each test task and a specific physical channel. The test channel collaborative allocation data can be used to directly drive the test system to execute high-concurrency, low-conflict parallel tests.

[0032] Taking automated testing of high-density FPGA chips as an example, the multi-test channel allocation method for electronic component testing in this embodiment can be as follows: When mass-producing an FPGA with 2000 pins, the system first acquires the pin topology data of its BGA package and the I / O standards of each pin (such as LVDS, SSTL, GPIO, etc.); through pin functional domain division, it identifies 8 high-speed transceiver domains, 4 power domains, and several general-purpose I / O domains; the test task requirements include eye diagram testing, power integrity verification, and logic function scanning; the system decomposes the tasks into 12 channel topology segments, each corresponding to a different functional domain; real-time monitoring reveals that the load rate of the high-speed transceiver channel segment reaches 90%, while that of the general-purpose I / O segment is only 40%; dynamic load compensation estimation suggests migrating some low-speed scan tasks to the idle segment; based on this, an operation dependency graph is constructed, revealing strong coupling between the high-speed segment and the adjacent analog monitoring segment; a conflict quantification model gives a high interference score; finally, the collaborative allocation generator staggers the execution of high-interference tasks and balances the load, achieving conflict-free parallel testing of the entire chip.

[0033] In one embodiment, pin functional domains are divided based on pin topology data and I / O characteristic parameters to obtain pin functional domain data, including: Pin-channel coupling relationship analysis is performed based on pin topology data and I / O characteristic parameters to obtain pin-channel coupling matrix data; Obtain pin test timing data, and calculate the test coordination frequency based on the pin test timing data to obtain the test coordination frequency data; Digital twin connected domains are constructed based on pin-channel coupling matrix data and test coordination frequency data to obtain pin functional domain data.

[0034] Pin-channel coupling relationship resolution can be a process of modeling the electrical compatibility, signal driving capability, and physical connection possibilities between each pin of a multi-pin electronic component and its connectable test channels. This can be used to generate dynamic adaptation relationships between pins and channels, supporting many-to-many mappings rather than fixed bindings. In this embodiment, pin-channel coupling relationship resolution can combine pin electrical attributes (such as voltage domain and signal type) with channel capability parameters (such as bandwidth and drive current) to evaluate the fit of each pin-channel pair. Furthermore, pin-channel coupling relationship resolution can assign zero weights to mismatched combinations (such as mapping analog pins to digital channels) by constructing a compatibility rule base, or use a neural network model to learn from historical successful mapping cases to predict the coupling score of new pin-channel pairs, thereby generating fine-grained, quantifiable pin-channel adaptation relationships and supporting flexible mapping. For example, pin-channel coupling relationship resolution can include, but is not limited to, one or more of electrical compatibility resolution, drive capability matching resolution, and physical wiring reachability resolution.

[0035] Pin-channel coupling matrix data can be structured data expressing the coupling strength or compatibility between each pin and available test channels in matrix form. Element values ​​reflect connection feasibility or signal fidelity and can be used as one of the inputs for functional domain partitioning, reflecting the dynamic correlation between pin and channel resources. In an exemplary embodiment, pin-channel coupling matrix data can be input together with test coordination frequency data into the construction of a digital twin connected domain, providing constraints on the physical connection dimension. Pin test timing data can be a timing sequence recording the activation times, durations, and synchronization relationships of each pin in historical or preset test procedures. It can be used to reflect the behavior patterns of pins during testing and to evaluate functional coordination. In a specific embodiment, pin test timing data can be extracted from test program logs, ATE execution traces, or simulation waveforms.

[0036] Test coordination frequency calculation can be based on pin test timing data, statistically analyzing the frequency or co-occurrence probability of any two or more pins being synchronously activated during testing. This can be used to quantify the test coordination tendency between pins and identify high-frequency co-test pin groups. Furthermore, test coordination frequency calculation can employ a sliding time window to calculate local coordination frequency to capture coordination changes during dynamic testing phases, or use the Jaccard similarity coefficient to measure the overlap of pin activation sets as a coordination index, thereby quantifying the functional coordination strength between pins and identifying pin groups belonging to the same test domain. For example, test coordination frequency calculation can include, but is not limited to, one or more of the following: pin-to-pin co-activation frequency, multi-pin synchronous triggering frequency, and cross-functional domain coordination frequency. Test coordination frequency data can be the numerical result output by the test coordination frequency calculation, representing the strength of pin combinations co-occurring during testing. This can be used as a basis for functional domain partitioning, guiding the clustering of high-frequency co-conducting pins into the same domain. In an exemplary embodiment, test coordination frequency data can be jointly driven with pin-channel coupling matrix data to construct digital twin connected domains, providing clustering weights in the timing behavior dimension.

[0037] The construction of connected components in a digital twin can be a process of fusing physical coupling relationships and temporal coordination information to build a pin connectivity graph in a virtual space and perform connected component clustering. This can be used to generate functional domain partitioning results with both physical and behavioral semantics. Furthermore, the construction of connected components in a digital twin can be achieved by constructing a weighted graph (nodes are pins, and edge weights are the fusion values ​​of coupling strength and coordination frequency) and performing clustering using connected component analysis or community detection algorithms, or by using spectral clustering algorithms to segment pin groups in the fused feature space. Alternatively, graph convolutional networks can be used to learn pin embeddings and then K-means clustering can be used to generate connected components. This can generate functional domains that possess both physical feasibility and behavioral consistency, improving the rationality of subsequent allocation. A connected component in a digital twin can be a connected subgraph in the digital twin space composed of pins with high coupling strength and high coordination frequency, representing a virtual test unit with consistent functional semantics. It can be used as the basis for generating pin functional domain data, embedding both structural and behavioral features. For example, a digital twin connectivity domain may include, but is not limited to, one or more of the following: a power-ground co-connectivity domain, a high-speed transceiver timing connectivity domain, and an analog-digital isolation connectivity domain.

[0038] Pin functional domain partitioning can be achieved through pin clustering methods constructed using digital twin connected domains. By combining physical connectivity with test behavior synergy, it can output functional domains with richer semantics and stronger behavioral awareness, outperforming static partitioning based solely on I / O type or topology. In a specific embodiment, the output of pin functional domain partitioning is the pin functional domain data, directly replacing the partitioning results based on rules or simple clustering in the original scheme. The pin functional domain data can be a structured set of functional domains derived from digital twin connected domains. Each domain contains a pin list and its coupling-coordination feature labels, which can be used to provide high-fidelity logic units for subsequent channel topology decomposition, improving allocation accuracy.

[0039] Taking mixed-signal SoC chip testing as an example, the multi-test channel allocation method for electronic component testing in this embodiment can be as follows: When testing an SoC integrating ADC, DAC, CPU core, and high-speed SerDes, the system first analyzes the pin topology and I / O characteristics of its BGA package (such as 1.8V LVCMOS, 3.3V analog input, etc.), and evaluates the coupling capability of each pin with the ATE channel, generating a pin-channel coupling matrix; at the same time, the enable timing of each pin is extracted from the historical test vector, and it is found that the ADC sampling pin and the reference voltage pin are synchronously activated within 90% of the test cycles; the cooperative frequency calculation confirms that the combination has high cooperativeness; the digital twin connected domain construction clusters the two with the adjacent analog ground pin into the same connected domain; the finally generated pin functional domain data not only distinguishes the analog, digital, and power domains, but also further subdivides into a "high cooperative analog acquisition subdomain", so that the subsequent channel allocation can reserve a low-noise, synchronously triggered dedicated channel segment for it, avoiding conflicts with digital scanning tasks.

[0040] This embodiment provides a multi-test channel allocation method for electronic component testing. It analyzes the pin-channel coupling relationship based on pin topology data and I / O characteristic parameters to obtain pin-channel coupling matrix data. By modeling the electrical connectivity, signal compatibility, and driving capability between physical pins and their mappable test channels into a structured matrix, it achieves a many-to-many, dynamically adaptable association between pins and channels. Furthermore, by acquiring pin test timing data and calculating test coordination frequency based on this data, it obtains test coordination frequency data. By quantifying the frequency at which different pins are synchronously activated in historical or preset test processes, it reflects... Its functional synergy and resource competition tendency; by constructing a digital twin connected domain based on pin-channel coupling matrix data and test synergy frequency data, pin functional domain data is obtained. By integrating physical coupling and timing synergy information to construct a virtualized functional clustering model, highly coupled and highly synergistic pins are aggregated into the same functional domain. This can achieve the generation of functional domain division results that integrate structural, electrical, and timing information, enabling channel allocation to accurately match the differentiated needs of heterogeneous I / O, effectively alleviating signal crosstalk, timing conflicts, and uneven load problems. This lays the foundation for intelligent testing with high concurrency, low conflict, and load balancing, and significantly improves the technical effects of testing efficiency and system robustness.

[0041] In one embodiment, a digital twin connected domain is constructed based on pin-channel coupling matrix data and test coordination frequency data to obtain pin functional domain data, including: Based on the pin-channel coupling matrix data and test coordination frequency data, virtual test topology coverage features and dynamic signal transmission features are extracted, resulting in virtual topology coverage feature data and dynamic signal transmission feature data, respectively. Based on the virtual topology coverage feature data and dynamic signal transmission feature data, a twin coupling diagram is generated from the pin-channel coupling matrix data to obtain twin coupling diagram data; The virtual-real mismatch region detection is performed on the twin coupling graph data to obtain virtual-real calibration graph data. The virtual-real mismatch region detection includes signal delay mismatch detection, level anomaly tomography detection, and dynamic verification detection of test permissions. Test condition timing constraints are injected into the virtual and real calibration map data to obtain timing constraint map data; Functional connectivity subdomains are extracted from the timing constraint diagram data to obtain pin functional domain data.

[0042] Virtual test topology coverage feature extraction can be a process of abstracting the channel combinations and their connection integrity characteristics that pins can be effectively covered in the virtual test space from the pin-channel coupling matrix and test coordination frequency. This can be used to quantify the resource reachability and topology connectivity completeness of each pin in the virtual domain. In this embodiment, virtual test topology coverage feature extraction can analyze the completeness and path redundancy of pin-mappable channel combinations and extract coverage integrity indicators. For example, virtual test topology coverage feature extraction can include, but is not limited to, one or more of the following: channel combination coverage extraction, topology path redundancy extraction, and functional domain boundary integrity extraction. The virtual topology coverage feature data can be a structured feature set output by virtual test topology coverage feature extraction, describing which channel combinations can completely cover each pin or pin group in the virtual test environment. This can be used as structural input for generating a twin coupling graph, ensuring the virtual model has physical realizability.

[0043] Dynamic signal propagation feature extraction can be based on pin-channel coupling matrices and test co-activation frequencies to analyze the dynamic behavioral characteristics of signals propagating along different pin-channel paths, such as propagation delay, bandwidth limitations, and interference sensitivity. This can be used to capture the dynamic fidelity of signals in virtual mappings, providing a basis for behavioral consistency modeling. In one exemplary embodiment, dynamic signal propagation feature extraction can combine channel bandwidth, pin load, and co-activation modes to estimate the dynamic response characteristics of the signal along the path. Furthermore, dynamic signal propagation feature extraction can include, but is not limited to, one or more of the following: path propagation delay features, signal integrity attenuation features, and cross-domain crosstalk sensitivity features.

[0044] Dynamic signal transmission feature data can be a set of numerical behavioral features extracted from dynamic signal transmission features, characterizing the dynamic signal transmission quality of each pin-channel path. It can be used as behavioral input for generating twin coupling graphs to enhance the dynamic fidelity of virtual models.

[0045] Extracting virtual test topology coverage features based on pin-channel coupling matrix data and test coordination frequency data can analyze the completeness and path redundancy of pin-mappable channel combinations, extracting coverage integrity indices. Furthermore, this operation can calculate the pin coverage of the minimum channel set based on graph coverage theory, or verify whether functional domain boundaries can be fully driven by existing channels using the Boolean Satisfactionability (SAT) model, thus ensuring that each pin in the virtual model is physically accessible and avoiding unrealizable mapping assumptions. Extracting dynamic signal transmission features based on pin-channel coupling matrix data and test coordination frequency data can combine channel bandwidth, pin load, and coordination activation modes to estimate the dynamic response characteristics of the signal along the path. Furthermore, this operation can be achieved by quickly simulating the signal integrity of critical paths using SPICE sub-circuit models, or by training regression models based on historical ATE waveform data to predict delay and distortion, thereby extending static coupling relationships into dynamic behavior models and improving the realism of virtual mapping.

[0046] Based on virtual topology coverage feature data and dynamic signal transmission feature data, a twin coupling graph is generated from the pin-channel coupling matrix data. This can be achieved by using pins and channels as nodes and fusing coverage integrity scores and signal transmission quality scores to construct weighted edges. Furthermore, this operation can be implemented using multi-objective weighted fusion strategies, such as weighted geometric mean or Pareto front selection, or by introducing an attention mechanism to automatically learn the importance weights of the two types of features. This allows for the generation of a high-fidelity digital twin graph that uniformly represents structural accessibility and behavioral consistency.

[0047] Twin coupling graph generation can be a process of fusing virtual topology coverage features and dynamic signal transmission features to enhance the modeling of the original pin-channel coupling matrix and construct a high-fidelity digital twin graph structure. This structure can be used to generate virtual mapping models that possess both structural connectivity and consistent dynamic behavior. The twin coupling graph data can be a weighted directed graph output from the twin coupling graph generation operation, with nodes representing pins or channels and edge weights fusing coverage integrity and signal transmission quality. This can be used as a foundational model for virtual-physical mismatch detection, supporting subsequent calibration and constraint injection. Virtual-physical mismatch detection on the twin coupling graph data can be performed by executing small-scale probe tests or readback verification, comparing virtual predictions with physical measurement results. Furthermore, this operation can be achieved by inserting calibration vectors during test idle periods to measure the actual delay and level of the critical path, or by comparing expected and measured signal waveforms in real time through an online monitoring module. This allows for the identification and location of deviations between the model and the physical system, triggering a self-calibration process.

[0048] Virtual-real mismatch detection can compare the twin coupling diagram with the actual response of the physical test system to identify areas where the model deviates from reality. This can trigger a model self-correction mechanism, improving the accuracy of the digital twin. In a specific embodiment, virtual-real mismatch detection may include, but is not limited to, one or more of the following: signal delay mismatch detection, level anomaly discontinuity detection, and dynamic verification of test permissions. Signal delay mismatch detection can detect significant deviations between the signal propagation delay predicted by the virtual model and the physically measured delay, and can be used to identify timing modeling errors caused by miscalculations of wiring parasitic parameters or drive capabilities. Level anomaly discontinuity detection can detect discontinuities or abnormal jumps between the expected logic level or analog amplitude in the virtual model and the measured value, and can be used to detect level modeling distortions caused by power supply noise, ground bounce, or channel nonlinearity. Dynamic verification of test permissions can verify whether the operation permissions of each channel on a specific pin under the current test task comply with safety and functional constraints, and can be used to prevent hardware damage or test failures caused by permission conflicts (such as driving the same pin simultaneously). The virtual-real calibration graph data can be a calibrated graph structure obtained by correcting the twin coupling graph after detecting the virtual-real mismatch region. By marking the mismatch region and adjusting the edge weights or node attributes, it can be used to provide a highly reliable virtual model that has been corrected by physical feedback for subsequent constraint injection.

[0049] Injecting test-condition timing constraints into virtual-to-real calibration graph data can be achieved by attaching timing rules from the test program (such as setup / hold times, synchronization windows, and trigger phases) as graph constraints to relevant nodes or edges. Furthermore, this operation can be further refined by encoding timing constraints as edge attributes of a graph neural network for subsequent message passing, or by constructing a timing dependency hypergraph to explicitly express multi-pin synchronization triggering relationships. This allows the virtual model to possess the temporal semantics of a real test scenario, avoiding the generation of timing-violation allocation schemes. Test-condition timing constraint injection can embed timing rules from the actual test scenario (such as setup / hold times, synchronization windows, and trigger phases) into the calibrated virtual graph, enabling the virtual model to possess the temporal semantic constraints of a real test environment. The timing constraint graph data can be a graph structure after test-condition timing constraint injection, with constraint labels such as timing feasible windows and phase alignment requirements attached to nodes and edges. This can be used as a basis for timing compliance in the extraction of functionally connected subdomains.

[0050] Functional connectivity subdomain extraction based on timing constraint graph data can be achieved by finding maximal pin subgraphs that are structurally connected and behaviorally cooperative, while satisfying timing constraints. Furthermore, this operation can be implemented by employing a constrained community detection algorithm to maximize the cooperative frequency in the timing-compatible subgraph, or by modeling the problem as a constrained maximum clique search and using heuristic pruning to accelerate the solution. This can output functional domains that are electrically feasible, behaviorally consistent, and timing compliant, laying the foundation for high-concurrency, low-conflict testing. Functional connectivity subdomain extraction can identify maximal pin subsets that satisfy structural connectivity, behavioral consistency, and timing compatibility in the timing constraint graph. These subsets can be used to generate the final pin functional domains, ensuring that pins within the domain can be tested safely, efficiently, and synchronously. Functional connectivity subdomains can be pin clustering units output by the functional connectivity subdomain extraction operation. The internal pins are highly cooperative in structure, dynamic behavior, and timing, and can be used as concrete instances of pin functional domain data for direct use in subsequent channel topology decomposition. For example, functional connectivity subdomains can include, but are not limited to, one or more of synchronous sampling functional subdomains, asynchronous control functional subdomains, and mixed-signal isolation functional subdomains. Pin functional domain data can be a structured collection of functionally connected subdomains. Each subdomain is accompanied by coverage features, signal transmission characteristics, and timing constraint labels, which can be used to provide a high-fidelity, multi-dimensional constraint-aware logical unit for channel allocation.

[0051] Taking the mass production testing of 5G RF transceiver chips as an example, the multi-test channel allocation method for electronic component testing in this embodiment can be as follows: When testing an RFIC integrating millimeter-wave front-end and baseband processing, the system first extracts virtual topology coverage features (such as the LO pin must be synchronously covered with the IQ channel) and dynamic signal transmission features (such as high-frequency path delay <100ps) based on the pin-channel coupling matrix and historical test timing. After generating a twin coupling diagram, the system finds that the actual delay of a certain local oscillator pin is 15% higher than the model through probe calibration, triggering signal delay mismatch detection. At the same time, a power supply pin is detected to have a level collapse under high load, which is marked as a level abnormality fault. After calibration, strict timing constraints of 5G NR test waveforms (such as synchronous sampling window ±2ns) are injected. Finally, the functional connectivity subdomain extraction clusters the LO, I / Q, reference clock and other pins into a "RF synchronization subdomain" to ensure that they are mapped to the same low jitter and high synchronization accuracy channel segment in subsequent channel allocation, avoiding phase mismatch caused by scattered allocation.

[0052] In one embodiment, the test task requirement data and pin function domain data are decomposed into test channel topology segments to obtain channel topology decomposition data, including: The test channel segment topology is divided based on the test task requirement data and pin functional domain data to obtain channel topology division data. The test channel segment topology partitioning can be a process of jointly mapping test task requirement data with pin functional domain data to divide the test channel segment into several physical-logical channel segments with clear boundaries and functional consistency. This can be used to form preliminary resource grouping units, providing a structural foundation for subsequent electrical and timing characteristic extraction. In this embodiment, the test channel segment topology partitioning can cluster test tasks according to their required functional domains and physical pin locations, forming channel segment units with clear boundaries. For example, the test channel segment topology partitioning can use a graph partitioning algorithm based on connectivity constraints to ensure that pins are electrically adjacent within the same channel segment; or it can use a rule engine to perform hard boundary partitioning based on I / O type and voltage domain, and then optimize through spatial clustering. Furthermore, this operation can generate initial channel segments with reasonable structure and functional cohesion, laying the foundation for subsequent refined modeling. The channel topology partitioning data can be an intermediate data structure output by the test channel segment topology partitioning operation, containing the pin set covered by each channel segment, the corresponding test task, and functional domain labels. It can be used as a common input for signal transmission characteristic extraction and key test node extraction, carrying structured resource grouping information.

[0053] Based on the channel topology partitioning data, signal transmission characteristics and key test nodes are extracted to obtain signal transmission characteristic data and key test node data, respectively. Signal transmission characteristic extraction can be a process of parsing the electrical transmission behavior parameters of each channel segment from channel topology partitioning data. This can be used to identify key factors affecting signal integrity and provide an electrical basis for timing dependency modeling. In an exemplary embodiment, signal transmission characteristic extraction can call an electromagnetic simulation model or empirical parameter library to calculate the transmission line effect and coupling characteristics of each channel segment. Furthermore, this operation can be achieved by estimating crosstalk and delay based on IBIS models and PCB trace parameters, or by regressing and fitting signal integrity indices of each channel segment using historical test data. This quantifies the electrical interference potential between channel segments and provides a physical basis for timing dependency modeling. The signal transmission characteristic data can be a dataset output from the signal transmission characteristic extraction operation, containing parameters such as impedance matching characteristics, propagation delay, and crosstalk sensitivity of each channel segment. This data can be used to evaluate the electrical compatibility of different channel segments in parallel testing and support refined timing scheduling.

[0054] Critical test node extraction can be the process of identifying pins or nodes that have a decisive impact on system stability or test accuracy from channel topology partitioning data. It can be used to focus on high-risk or high-value test points, improving resource allocation priority and protection strategies. In one specific embodiment, critical test node extraction can filter pins sensitive to system performance from channel segments based on preset rules or machine learning models. For example, this operation can score based on rules such as fan-out, drive strength, and voltage sensitivity to select Top-K nodes; or use graph centrality algorithms (such as betweenness centrality) to identify key topology points, allowing high-influence nodes to be focused, improving test reliability and resource protection priority. Critical test node data can be the data set output by the critical test node extraction operation, identifying key locations such as high-fan-out pins, power / ground sensitive points, and high-speed differential pairs. This data can be used as constraints for timing dependency processing, ensuring that critical paths receive priority scheduling or isolation protection.

[0055] Based on signal transmission characteristic data and key test node data, the channel topology partitioning data is processed for test timing dependency to obtain timing dependency data. The test timing dependency processing can combine signal transmission characteristic data and key test node data to model the operation sequence and synchronization relationship of channel topology partitioning data in the time dimension. This can be used to explicitly express the sequential constraints, synchronization windows, and conflict time slots between test operations, generating quantifiable time dependencies. In this embodiment, the test timing dependency processing can integrate electrical delay, crosstalk window, and key node protection requirements to derive the time constraint relationship between test operations. Furthermore, this operation can be implemented by inserting an isolation time slot between test operations if strong crosstalk exists between two channel segments; or by setting exclusive time periods or synchronization trigger conditions for the channel segment where the key node is located. This transforms static resource grouping into an operation sequence with timing semantics, avoiding timing conflicts and signal pollution. The timing dependency data can be structured timing constraint information output by the test timing dependency processing operation, including the minimum interval, maximum tolerance offset, and synchronization trigger conditions between operation pairs. This can be used to provide time semantics for dynamic dependency graph construction, enabling channel allocation to have timing awareness capabilities.

[0056] Dynamic dependency graphs are constructed based on temporal dependency data to obtain channel topology decomposition data.

[0057] The dynamic dependency graph construction can be based on temporal dependency data, extending the static channel topology into a directed graph model that includes temporal dependencies. This model can be used to fuse structural, electrical, and temporal information to form a high-fidelity test operation interaction model. In an exemplary embodiment, the dynamic dependency graph construction can use channel segments or test operations as nodes and temporal dependency data as edge attributes to construct a weighted directed graph. Furthermore, this operation can use an attribute graph database to store the multidimensional features of nodes and edges, or encode the temporal window as the edge activation function, supporting queries by a dynamic scheduling engine. This allows the generation of a unified dependency model that fuses structural, electrical, and temporal information, serving as high-fidelity channel topology decomposition data output.

[0058] A dynamic dependency graph can be a graph structure output by a dynamic dependency graph construction operation. Nodes represent test operations or channel segments, and edges carry timing constraints and electrical interference weights. It can be used as the final form of channel topology decomposition data to support accurate decisions for subsequent load compensation and conflict quantification. The channel topology decomposition data can be the enhanced channel topology decomposition data output by the dynamic dependency graph in this embodiment, containing structural, electrical, and timing information. It can replace the coarse-grained decomposition results based solely on functional domain and task mapping in the original solution, providing high-fidelity input to support intelligent allocation.

[0059] For example, in the scenario of testing high-speed SerDes interface chips, the multi-test channel allocation method for electronic component testing in this embodiment can be as follows: When testing a communication chip with 16 10Gbps SerDes channels, the system first divides the tasks such as eye diagram testing and jitter tolerance verification with the pin functional domains (such as TX / RX differential pairs, reference clock, and power supply pins) into channel segment topologies, forming 18 channel segments; then, it extracts the transmission delay and crosstalk sensitivity of each differential pair, identifies 3 pairs of high crosstalk adjacent channels; at the same time, it marks the reference clock pin and the power supply decoupling point as key test nodes; based on this, the system stipulates that high crosstalk channels must not be transmitted simultaneously, and allocates independent test periods for the clock pin; the finally constructed dynamic dependency graph not only contains channel segments, but also embeds timing edges such as "channel B can only be started at least 5ns after channel A is tested"; this graph is used as channel topology decomposition data input to the subsequent load compensation module to ensure that high-speed testing is executed in parallel under interference-free and timing-compliant conditions.

[0060] In one embodiment, dynamic load compensation estimation is performed based on the current test channel load balancing data and channel topology decomposition data to obtain load compensation estimation data, including: Based on the current test channel load balancing data and channel topology decomposition data, multi-signal test timing overlay calculations are performed to obtain timing overlay data; Signal density kernel distribution is calculated based on time-series superimposed data to obtain local load clustering intensity data; Based on the current test channel load balancing data, the channel carrying capacity and test response cycle are calculated to obtain the carrying capacity data and response cycle data respectively. Based on the load capacity data and response cycle data, dynamic load compensation time extrapolation is performed on the local load concentration intensity data to obtain load compensation estimation data.

[0061] Multi-signal test timing overlay calculation can be a computational process that overlays and models the signal activities of multiple parallel test tasks in the time dimension. It can be used to reveal the overlap and competition relationships of different test signals on the time axis, providing a timing basis for load aggregation analysis. In this embodiment, multi-signal test timing overlay calculation can project the test tasks corresponding to each channel topology segment onto the time axis according to their trigger time and duration, and overlay the signal activity intensity. For example, multi-signal test timing overlay calculation can adopt an event-driven simulation method to accumulate signal activity event by event, or use a discrete-time grid to count the number of concurrent signals for each time slot. Furthermore, multi-signal test timing overlay calculation can explicitly model the time competition relationships under multi-task concurrency, providing structured input for density analysis. The timing overlay data can be the time series data output by multi-signal test timing overlay calculation, characterizing the overlay intensity of signal activities in each channel within the test period. It can be used as input for signal density analysis, reflecting the degree of concurrency density of test tasks in the time dimension.

[0062] Signal density kernel distribution calculation can be a process of smoothly modeling the distribution of signal activity in the spatiotemporal domain using kernel density estimation methods based on time-series overlay data. It can be used to quantify the density of test signals in local areas and identify potential overload hotspots. In an exemplary embodiment, signal density kernel distribution calculation can use time-series overlay data as sample points and apply a kernel function (such as a Gaussian kernel) to perform density estimation in the time-channel space. Furthermore, signal density kernel distribution calculation can set bandwidth parameters in both the channel and time dimensions to perform two-dimensional kernel density estimation, or adopt an adaptive bandwidth strategy to dynamically adjust the kernel scale according to the local signal sparsity. In a specific embodiment, signal density kernel distribution calculation can transform discrete signal events into a continuous load intensity field, improving the accuracy of hotspot identification. Local load aggregation intensity data can be the density field data output by signal density kernel distribution calculation, representing the load concentration of each channel or channel segment within a specific time window. This can be used to accurately locate resource bottleneck areas caused by high-concurrency test signals and support targeted compensation.

[0063] Channel capacity calculation can be a process of evaluating the maximum test signal throughput that each channel can handle per unit time based on the current test channel load balancing data. This can be used to determine the upper limit of the channel's physical and logical resources, serving as a capacity constraint basis for load compensation. In this embodiment, channel capacity calculation can comprehensively consider channel hardware specifications (such as drive current and switching frequency) and the current occupancy status to calculate the remaining available throughput capacity. For example, channel capacity calculation can estimate based on the channel type (digital / analog / power supply) by calling a preset capacity model, or it can infer the actual upper limit of capacity through online stress testing. Furthermore, channel capacity calculation can provide a quantitative basis for the upper limit of channel resources, avoiding overload allocation. The capacity data can be the maximum throughput capacity index of the channel output by the channel capacity calculation, including comprehensive parameters such as bandwidth, drive capability, and switching rate. This can be used to determine whether the local load exceeds the channel's processing capacity and guide the direction of compensation.

[0064] Test response cycle calculation can be an evaluation process based on current test channel load balancing data, calculating the minimum time interval required to complete a single test task. This can reflect the timeliness constraints of channel task scheduling and influence the time granularity of compensation strategies. In one specific embodiment, test response cycle calculation can measure or estimate the minimum time interval required for a channel to complete a typical test task, considering queue waiting and physical latency. Furthermore, test response cycle calculation can be based on statistically averaging response cycles from historical task execution logs, or by establishing a response time prediction model using channel topology and signal type. In one embodiment, test response cycle calculation can characterize the channel scheduling granularity, supporting time-dimensional compensation extrapolation. Response cycle data can be the channel task execution cycle index output by the test response cycle calculation, representing the latency characteristics of the channel from receiving an instruction to completing a response. This can be used as a time benchmark for dynamic extrapolation to predict future load evolution windows.

[0065] Dynamic load compensation time extrapolation can be a reasoning process that combines carrying capacity data, response cycle data, and local load aggregation intensity data to predict load change trends over a future time period and generate compensation suggestions. It can be used to achieve a leap from static snapshots to dynamic evolution prediction, supporting proactive resource scheduling. In this embodiment, dynamic load compensation time extrapolation can slide a prediction window on the time axis, combining load intensity, capacity limits, and response cycles to extrapolate whether the future load will exceed limits. For example, dynamic load compensation time extrapolation can construct a Markov chain model to predict the load state transition probability, or use difference equations to simulate the load accumulation and release process to identify critical overload points. Furthermore, dynamic load compensation time extrapolation can generate forward-looking load compensation suggestions, achieving proactive resource rebalancing.

[0066] Taking the parallel testing of a high-speed SerDes interface chip as an example, the multi-test channel allocation method for electronic component testing in this embodiment can be used when performing eye diagram and jitter testing on a SerDes chip with 48 high-speed transceiver channels. The system detects that multiple channels require high-frequency excitation signals within the same test cycle. Through multi-signal test timing superposition calculation, it is found that the signal activity of channels 12–15 is highly overlapping in the t=50–70μs interval; signal density kernel distribution calculation shows that the local load concentration intensity in this area is significantly higher than in other time periods; simultaneously, channel carrying capacity calculation indicates that the driving circuits of these channels are approaching their thermal limits, and response cycle data shows that their minimum test interval is 25μs. Dynamic load compensation time extrapolation predicts that if the current scheduling is maintained, signal distortion risk will occur at t=65μs. Based on this, the system proactively migrates some low-priority tasks to idle channel segments and inserts a small time offset, successfully avoiding crosstalk and response timeout, and ensuring the integrity of high-precision eye diagram acquisition.

[0067] In one embodiment, a test channel operation dependency graph is constructed based on load compensation estimation data to obtain channel operation dependency graph data, including: Based on the current test channel load balancing data and channel topology decomposition data, an operation dependency subgraph is constructed for the test channel segment to obtain the operation dependency subgraph data. Dynamic weighting is performed on the operation dependency subgraph data based on the load compensation estimation data to obtain dynamic weighted graph data. Directed acyclic allocation optimization is performed based on dynamic weight graph data to obtain channel operation dependency graph data.

[0068] The construction of the test channel segment operation dependency subgraph can be based on the current test channel load balancing data and channel topology decomposition data. For each channel topology segment, a local dependency graph is independently constructed, including its internal and cross-segment test operations. This allows for modularity and scalability in dependency modeling, avoiding excessive complexity in the global graph and supporting conflict analysis at the segment level. In this embodiment, the construction of the test channel segment operation dependency subgraph can be done on a per-channel topology segment basis, combining its load state and pin adjacency relationships to identify the dependencies and interference relationships between operations within and between segments, and constructing a local subgraph. For example, the construction of the test channel segment operation dependency subgraph can build a graph independently for each topology segment, adding cross-segment edges only when shared resources or electrical coupling exist between segments; alternatively, a sliding window mechanism can be used to construct a subgraph only for the currently active segment, reducing computational overhead. The operation dependency subgraph data can be the local dependency graph structure output by the test channel segment operation dependency subgraph construction operation, containing the test operation nodes within the segment and their dependent or interference edges. This can be used as the basic unit for dynamic weight assignment, preserving the semantics and coupling relationships of local operations.

[0069] Dynamic weight assignment can be based on load compensation estimation data, assigning numerical weights reflecting the real-time system state to edges or nodes in an operation dependency subgraph. This can be used to transform static dependencies into quantifiable dynamic risk or priority indicators, supporting subsequent optimization decisions. In an exemplary embodiment, dynamic weight assignment can map the direction and magnitude of deviations in the load compensation estimation data to the weight values ​​of edges or nodes in the subgraph. Furthermore, dynamic weight assignment can be achieved by assigning high conflict weights to operation edges in high-load segments to suppress concurrent execution, or by assigning high scheduling priority weights to task nodes requiring compensation migration. This enables the dependency graph to have runtime awareness, supporting risk quantification and priority adjustment based on real-time state. The dynamic weight graph data can be a weighted dependency graph generated after dynamic weight assignment. The weights reflect dimensions such as resource contention intensity, electrical interference risk, or timing urgency, and can be used to provide a quantitative basis for directed acyclic allocation optimization, enabling scheduling strategies to have runtime awareness.

[0070] Directed acyclic allocation optimization (DAG) can perform topological sorting and priority scheduling on a dynamic weight graph to ensure that the execution order of operations is free of circular dependencies and that high-weight tasks are prioritized. This can be used to eliminate deadlock risks, ensure causal consistency of test operations, and optimize the execution efficiency of critical paths. In one specific embodiment, DAG can perform priority-based topological sorting on the dynamic weight graph to generate an acyclic execution sequence with high-weight tasks preceding each other. Furthermore, DAG can employ a variant of the Kahn algorithm, prioritizing the task with the highest weight among nodes with zero in-degree; it can also be combined with Critical Path Method (CPM) to prioritize scheduling operations located on long, high-weight paths, thereby ensuring that the order of test operations satisfies causal constraints and optimizing the execution timing of high-risk or high-priority tasks, avoiding deadlocks and conflicts.

[0071] Taking the parallel functional verification of a multi-core SoC chip as an example, the multi-test channel allocation method for electronic component testing in this embodiment can be as follows: When performing parallel functional testing on a multi-core SoC with 1500 pins, the system has already obtained channel topology decomposition data (divided into 6 functional segments) and current load balancing data (where the high-speed SerDes segment has a load of 85%, while the GPIO segment has only 30%) through previous steps. First, an operation dependency subgraph is constructed for each segment: the eye diagram test and jitter injection in the SerDes segment have a timing dependency and are strongly coupled with the adjacent power monitoring segment; then, based on the load compensation estimation data (it is recommended to reduce the concurrency of the SerDes segment), high conflict weights (such as 0.9) are assigned to the dependency edges in the SerDes segment, while low weights (such as 0.2) are assigned to the GPIO segment tasks; finally, directed acyclic allocation optimization is performed on the dynamic weight graph, prioritizing the scheduling of high-weight but non-conflicting power monitoring tasks, suspending some SerDes concurrent tests, ensuring that the overall system is acyclic and that the critical path is not blocked, thus achieving stable high-throughput testing.

[0072] In one embodiment, test conflict quantization is performed based on channel operation dependency graph data to obtain channel conflict quantization data, including: Based on the channel operation dependency graph data, test resource usage mapping is performed to obtain resource usage data; Conflicting tuples are extracted from resource usage data to obtain conflicting tuple data. Based on the conflict tuple data, signal overlap tension quantization is performed to obtain channel conflict quantization data.

[0073] The test resource occupancy mapping can be a process of mapping operation nodes in the channel operation dependency graph to the occupancy status of specific physical or logical test resources (such as drivers, comparators, power supply units, clock sources, etc.). It can be used to transform abstract dependencies into an analyzable resource contention view, revealing potential sharing and conflict points. In this embodiment, the test resource occupancy mapping can traverse each operation node in the channel operation dependency graph, query its required test resource type and usage time period, and generate a three-dimensional resource-operation-time mapping table. Furthermore, the test resource occupancy mapping can be implemented by quickly matching operations with physical channel resources based on a resource type hash table, or by constructing a snapshot of the current occupancy status through resource scheduling log backtracking. This allows the dependencies in the graph structure to be grounded in specific resource contention scenarios, providing a physical basis for conflict identification. The resource occupancy data can be a data structure output from the test resource occupancy mapping operation, recording the specific resource type, quantity, and time series window occupied by each test operation. This data can be used as input for conflict tuple extraction, providing a basis for judging overlap in the resource dimension.

[0074] Conflict tuple extraction can be a process of identifying combinations of operations that overlap in time, space, or electrical path and may cause interference from resource occupancy data. It can be used to generate a structured set of conflict candidates, focusing on high-risk operation pairs that require further quantization. In an exemplary embodiment, conflict tuple extraction can scan resource occupancy data to identify combinations of operations that overlap in time or are electrically adjacent on the same resource, forming conflict tuples. For example, conflict tuple extraction can use a sliding time window to detect concurrent resource usage events, or identify spatially coupled operation pairs based on a cabling topology adjacency matrix, thereby filtering high-risk conflict candidates from massive resource occupancy information and narrowing the quantization range. Conflict tuple data can be structured data output from the conflict tuple extraction operation, containing several conflict tuples. Each tuple consists of two or more potentially interfering operations and their shared resources, which can be used to provide a clear evaluation object for signal overlap tension quantization and limit the quantization range. In a specific embodiment, conflict tuple data can include, but is not limited to, one or more of the following: time-overlapping conflict tuples, shared-power-domain conflict tuples, and adjacent cabling crosstalk conflict tuples.

[0075] Signal overlap tension quantization can be a process of multi-dimensionally modeling the waveform characteristics, coupling paths, and temporal overlap of each signal in a conflicting tuple, and calculating its comprehensive interference strength. It can be used to transform qualitative conflicts into comparable numerical indicators, supporting priority ranking and optimization decisions. Furthermore, signal overlap tension quantization can weight and fuse the signal waveform parameters, coupling path models, and temporal overlap ratios in each conflicting tuple to calculate the comprehensive tension value. For example, signal overlap tension quantization can use electromagnetic field simulation models to estimate parasitic coupling strength, combine signal edge rates to calculate transient interference, or substitute parameters such as rise time, voltage difference, and common-ground impedance into the tension function based on empirical formulas, thereby outputting a sortable and optimizable conflict strength indicator to support refined channel allocation decisions. Channel conflict quantization data can be the numerical result output by signal overlap tension quantization, representing the interference strength or conflict severity of each conflicting tuple. It can be used as a constraint input for collaborative allocation generation to suppress high-tension conflict combinations.

[0076] Taking mixed-signal SoC parallel functional testing as an example, the multi-test channel allocation method for electronic component testing in this embodiment can be implemented when testing an SoC integrating high-speed SerDes, audio ADC, and digital control logic, where the system has already constructed a channel operation dependency graph. First, a test resource occupancy mapping is performed, revealing that both the SerDes eye diagram test and audio ADC sampling occupy the same high-precision analog front-end resource, and their time windows partially overlap; simultaneously, the digital I / O scan task and the SerDes driver share the same power conditioning module. The conflict tuple extraction module generates two conflict tuples accordingly: (SerDes eye diagram, audio ADC) and (SerDes driver, digital scan). Subsequently, the signal overlap tension quantization module analyzes the former: the SerDes signal has a sub-nanosecond edge, while the audio signal is low-frequency and high-gain, resulting in strong coupling between the two at the analog front-end, leading to a high tension value; the latter, due to significant differences in power supply transient response, also yields a medium-to-high tension value. Finally, the coordinating allocator moves the audio test to a spare analog channel and staggers the digital scan timing, effectively avoiding high-tension conflicts.

[0077] In one embodiment, signal overlap tension quantization is performed based on the conflict tuple data to obtain channel conflict quantization data, including: The overlap of non-steady-state signals and the intersection of time-series occupancy are calculated based on the conflict tuple data, and the dynamic boundary overlap data and the intersection of time-series occupancy data are obtained respectively. The non-steady-state signal overlap can be used as an indicator to measure the degree of overlap of transient behaviors (such as edge transitions, ringing, and overshoot) of signals in conflicting tuples in the voltage-time domain. It can be used to capture potential interference of high-speed or precision signals in the non-steady-state stage, compensating for the neglect of transient crosstalk in traditional steady-state models. In an exemplary embodiment, the non-steady-state signal overlap can be obtained by extracting the transient waveform features of the signal and calculating its overlap area in the voltage-time domain.

[0078] The temporal occupancy intersection degree quantifies the overlap ratio of resource usage windows of multiple test tasks in the time dimension. It can be used to reflect the intensity of time competition between tasks, providing a temporal dimension basis for shared node resolution. For example, the temporal occupancy intersection degree can be obtained by comparing the scheduling time windows of each task and calculating their intersection length ratio. Dynamic boundary overlap data can be the output of non-steady-state signal overlap calculation, characterizing the overlapping area of ​​transient waveforms of signals in each conflicting tuple on the dynamic voltage boundary. It can be used as one of the inputs for shared test node competition resolution to identify high-risk transient coupling scenarios. The temporal occupancy intersection degree data can also be the output of temporal occupancy intersection degree calculation, recording the time window overlap ratio of the tasks corresponding to each conflicting tuple. It can be used in conjunction with dynamic boundary overlap degree data to jointly drive node competition resolution.

[0079] Calculating the overlap and temporal intersection of non-steady-state signals based on conflict tuple data can be achieved by extracting the transient waveform features of each pair of signals in the conflict tuple, calculating the voltage-time domain overlap area, and comparing it with their task scheduling time windows to determine the intersection ratio. Furthermore, this operation can be implemented by using wavelet transform to extract the transient features of the signals and then calculating the overlap integral, or by directly obtaining the time window from the task scheduler logs and calculating the intersection length ratio. This allows for the simultaneous capture of conflict triggers from both electrical transients and temporal concurrency dimensions, improving conflict identification accuracy.

[0080] Based on the dynamic boundary overlap data and the time sequence occupancy intersection data, the shared test node contention is analyzed to obtain node contention analysis data; The shared test node contention analysis can be a process of analyzing the contention behavior caused by multiple concurrent signals on shared physical nodes (such as ground planes, power rails, and multiplexed front-ends) based on dynamic boundary overlap and temporal occupancy intersection. This can be used to locate electrical coupling hotspots and identify potential conflict sources caused by resource sharing. In one specific embodiment, the shared test node contention analysis can combine circuit topology information to identify physical nodes shared by signal pairs that simultaneously satisfy high overlap and high temporal intersection, and evaluate their coupling strength. The node contention analysis data can be a structured result of the shared test node contention analysis operation, containing the contention strength, participating signals, and coupling paths of each shared node. This can be used to provide an initial excitation source for tension propagation modeling and identify the conflict initiation point that needs to be modeled. Furthermore, the node contention analysis data can include, but is not limited to, one or more of the following: common-ground impedance coupled nodes, multiplexed analog front-end contention nodes, and power rail transient load shared nodes.

[0081] Analyzing shared test node contention based on dynamic boundary overlap data and temporal occupancy intersection data can be achieved by combining circuit topology information to identify shared physical nodes for signal pairs with high overlap and high temporal intersection and to assess coupling strength. For example, this operation can be implemented by calculating the coupling gain of common-ground / common-power nodes based on the SPICE parasitic parameter model, or by using a wiring adjacency matrix and resource mapping table to infer shared nodes. This allows abstract signal pairs to be associated with specific physical contention points, enabling precise location of the conflict source.

[0082] Based on the node competition analysis data, signal tension propagation modeling is performed to obtain tension propagation matrix data; Signal tension propagation modeling can be a process of weighted diffusion modeling of the local conflict intensity in the node contention parsing data within the network through the channel topology. This can be used to characterize the propagation range and attenuation characteristics of the conflict impact in the test system, forming a global interference view. In this embodiment, signal tension propagation modeling can use the test channel topology as a graph structure, with the node contention intensity as the initial node weights, and propagate the tension through a graph diffusion algorithm.

[0083] Tension propagation matrix data can be a matrix structure output from signal tension propagation modeling, where element values ​​represent the interference influence of a node conflict on other nodes. It can be used to provide a quantitative expression of global conflict coupling relationships and support priority-aware control. Signal tension propagation modeling based on node competition analysis data can be performed using the test channel topology as a graph structure, with node competition intensity as the initial node weights, and propagating tension through a graph diffusion algorithm (such as a PageRank variant). Furthermore, this operation can be implemented by constructing a weighted directed graph (edge ​​weights determined by inter-channel parasitic capacitance / inductance) to perform iterative tension diffusion, or by using a graph neural network to learn tension propagation rules and generate a propagation matrix end-to-end. This allows local conflicts to be expanded into a system-level interference map, revealing hidden crosstalk paths.

[0084] Based on the tension propagation matrix data, gravity compensation control was performed on a high-priority test task to obtain channel conflict quantification data.

[0085] Among them, the gravity compensation control of high-priority test tasks can be a control mechanism that assigns higher weights to high-priority tasks during tension propagation, enhancing their repulsive force on neighboring low-priority tasks to protect signal integrity. This can be used to achieve task priority-driven dynamic conflict suppression, ensuring the execution quality of key test items. In a specific embodiment, the gravity compensation control of high-priority test tasks can apply gravity weights to the nodes containing high-priority tasks in the tension propagation matrix, amplifying their repulsive effect on neighboring nodes, and then re-normalizing to generate corrected conflict values.

[0086] Gravity compensation control for high-priority test tasks based on tension propagation matrix data can be achieved by applying a gravity weight to the node containing the high-priority task in the tension propagation matrix, amplifying its repulsive effect on neighboring nodes, and then renormalizing to generate a corrected conflict value. For example, this operation can be accomplished by introducing a task priority coefficient into the tension propagation equation to dynamically adjust the node update rules, or by multiplying the neighborhood tension value of a high-priority task by a decay factor to suppress the proximity of low-priority tasks. This allows for conflict control based on task value perception, prioritizing the quality of critical tests under resource constraints.

[0087] Taking the parallel calibration test of a 5G RF transceiver chip as an example, the multi-test channel allocation method for electronic component testing in this embodiment can be used when testing an RFIC integrating a millimeter-wave transceiver chain, baseband ADC, and digital calibration engine. The conflicting tuple includes high-speed local oscillator switching test and low-noise LNA gain calibration. The system first calculates the overlap of their non-steady-state signals: the local oscillator signal has nanosecond-level edges and significantly overlaps with the microvolt-level analog signal of the LNA in the voltage-time domain; simultaneously, the overlap rate of the two task scheduling windows reaches 70%. Shared node contention analysis identifies that the two share the same low-noise LDO power rail and their PCB traces are adjacent. Node contention analysis data marks this LDO as a high-contention node. Signal tension propagation modeling spreads this contention intensity along the power network and ground plane, generating a tension propagation matrix, showing that surrounding digital calibration tasks are also indirectly affected. Since the LNA calibration is marked as a high-priority task, the gravity compensation control mechanism enhances its "gravity," forcing the local oscillator switching task to be migrated to a spare time slot and isolating its power path in the final channel conflict quantization data, ensuring that the LNA test signal-to-noise ratio is not affected.

[0088] In one embodiment, test channel collaborative allocation is generated based on channel conflict quantification data to obtain test channel collaborative allocation data, thereby achieving real-time dynamic optimization allocation of multiple test channels, including: Conflict core clusters are identified based on channel conflict quantification data to obtain conflict core cluster data; The conflict core cluster data can be a structured set formed by clustering test channels or operation nodes with high conflict quantization values. This data can be used to focus resource optimization on high-risk areas, providing a priority basis for allocation sequence optimization. In this embodiment, the conflict core cluster data can characterize the critical areas in the system most prone to resource contention or signal interference. For example, the conflict core cluster data can include, but is not limited to, one or more of the following: power-analog coupling clusters, high-speed digital proximity crosstalk clusters, and timing-critical path contention clusters.

[0089] Identifying conflict core clusters based on channel conflict quantification data can be achieved by clustering high-weight edges or high-conflict nodes in the data to identify tightly coupled conflict subgraphs. Furthermore, this identification can be accomplished by employing community detection algorithms (such as the Louvain method) to extract highly cohesive subgroups from the conflict graph, or by setting a conflict threshold to merge adjacent operation nodes exceeding the threshold into clusters and iteratively expanding the boundaries. This allows global conflict information to be condensed into local key regions, improving the targeting and computational efficiency of subsequent optimizations.

[0090] Based on the conflict core cluster data, the test channel topology-level allocation sequence is optimized to obtain the allocation sequence optimization data; The optimized allocation sequence data can be a structured scheme of test operation execution order and channel mapping path generated after topology-level scheduling optimization. It can be used to reduce critical path latency and distribute load hotspots by rearranging the execution sequence, while meeting functional domain and task constraints. In an exemplary embodiment, the optimized allocation sequence data may include, but is not limited to, one or more of the following: time-driven allocation sequence, load-balanced allocation sequence, and interference-avoidance allocation sequence.

[0091] Optimizing the test channel topology-level allocation sequence based on conflicting core cluster data can involve rescheduling the operation execution order and channel mapping paths within the conflicting core cluster while maintaining the constraints of pin functional domains and channel topology decomposition. Furthermore, this optimization can be achieved by adjusting the execution sequence using a list scheduling algorithm with the goal of minimizing the maximum completion time within the cluster, or by introducing a time slot isolation mechanism to allocate highly conflicting operations to non-overlapping time slots, supplemented by physical channel isolation. This can reduce critical path latency, distribute load hotspots, and reduce concurrent interference in high-risk areas.

[0092] Based on the allocation sequence optimization data, test channel collaborative allocation data is generated to drive the digital twin test platform to perform real-time dynamic optimization allocation of multiple test channels.

[0093] The digital twin test platform can be a virtual simulation environment for high-fidelity modeling and real-time synchronization of the physical test system. It can receive collaborative allocation data and drive the physical test system to execute, while simultaneously providing feedback on the actual operating status for strategy iteration and optimization. In one specific embodiment, the digital twin test platform can maintain bidirectional data synchronization with the physical test system through sensor data and device status interfaces, constructing a virtual mapping. Generating collaborative allocation data for test channels based on allocation sequence optimization data can integrate the optimized execution sequence and channel mapping relationship into an executable allocation instruction set, thereby outputting a complete channel allocation scheme containing dynamic scheduling strategies, transcending the scope of static mapping. Driving the digital twin test platform to execute real-time dynamic optimization allocation of multiple test channels can involve sending collaborative allocation data for test channels to the digital twin test platform, which then synchronously controls the execution of the physical test system and monitors feedback. This enables closed-loop verification and dynamic optimization of the allocation strategy, enhancing the system's adaptability to runtime changes.

[0094] For example, in the scenario of parallel testing of 5G RF front-end modules, the multi-test channel allocation method for electronic component testing in this embodiment can be as follows: When testing an RF module integrating PA, LNA and switch, the conflict quantization model identifies strong coupling between multiple high-speed digital control lines and analog RF paths; the conflict core cluster identification clusters these high-interference operations into "digital-RF crosstalk clusters"; the system performs topology-level allocation sequence optimization on the cluster, delays the digital enable signal until after RF sampling is completed, and maps the relevant channels to physically isolated test resource segments; the generated collaborative allocation data contains timing scheduling instructions; the digital twin test platform receives the scheme, performs a conflict-free rehearsal in a virtual environment, drives the physical ATE to execute, and simultaneously transmits back the actual crosstalk level in real time for the next round of optimization.

[0095] Furthermore, to achieve the above objectives, the present invention also provides a multi-test channel allocation device for electronic component testing, the device comprising: a memory, a processor, and a multi-test channel allocation program for electronic component testing stored in the memory and executable on the processor, the multi-test channel allocation program for electronic component testing being configured to implement the steps of the multi-test channel allocation method for electronic component testing as described in any one of the above descriptions.

[0096] Other embodiments or specific implementations of the multi-test channel allocation device for electronic component testing described in this invention can be referred to the above-described method embodiments, and will not be repeated here.

[0097] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A method for allocating multiple test channels for testing electronic components, characterized in that, The method includes: Obtain the pin topology data and I / O characteristic parameters of multi-pin electronic components, and divide the pin functional domains according to the pin topology data and I / O characteristic parameters to obtain the pin functional domain data. Obtain test task requirement data; decompose the test channel topology segment into test task requirement data and pin function domain data to obtain channel topology decomposition data. Obtain the current test channel load balancing data, and perform dynamic load compensation estimation based on the current test channel load balancing data and channel topology decomposition data to obtain load compensation estimation data; Based on the load compensation estimation data, a test channel operation dependency graph is constructed to obtain channel operation dependency graph data; based on the channel operation dependency graph data, test conflict quantification is performed to obtain channel conflict quantification data; based on the channel conflict quantification data, test channel collaborative allocation is generated to obtain test channel collaborative allocation data, so as to realize real-time dynamic optimization allocation of multiple test channels.

2. The multi-test channel allocation method for electronic component testing as described in claim 1, characterized in that, The process of dividing pin functional domains based on pin topology data and I / O characteristic parameters to obtain pin functional domain data includes: Pin-channel coupling relationship analysis is performed based on pin topology data and I / O characteristic parameters to obtain pin-channel coupling matrix data; Obtain pin test timing data, and calculate the test coordination frequency based on the pin test timing data to obtain the test coordination frequency data; Digital twin connected domains are constructed based on pin-channel coupling matrix data and test coordination frequency data to obtain pin functional domain data.

3. The multi-test channel allocation method for electronic component testing as described in claim 2, characterized in that, The process of constructing a digital twin connected domain based on pin-channel coupling matrix data and test coordination frequency data yields pin functional domain data, including: Based on the pin-channel coupling matrix data and test coordination frequency data, virtual test topology coverage features and dynamic signal transmission features are extracted, resulting in virtual topology coverage feature data and dynamic signal transmission feature data, respectively. Based on the virtual topology coverage feature data and dynamic signal transmission feature data, a twin coupling diagram is generated from the pin-channel coupling matrix data to obtain twin coupling diagram data; The virtual-real mismatch region detection is performed on the twin coupling graph data to obtain virtual-real calibration graph data. The virtual-real mismatch region detection includes signal delay mismatch detection, level anomaly tomography detection, and dynamic verification detection of test permissions. Test condition timing constraints are injected into the virtual and real calibration map data to obtain timing constraint map data; Functional connectivity subdomains are extracted from the timing constraint diagram data to obtain pin functional domain data.

4. The multi-test channel allocation method for electronic component testing as described in claim 1, characterized in that, The test channel topology segment decomposition is performed on the test task requirement data and pin functional domain data to obtain channel topology decomposition data, including: The test channel segment topology is divided based on the test task requirement data and pin functional domain data to obtain channel topology division data. Based on the channel topology partitioning data, signal transmission characteristics and key test nodes are extracted to obtain signal transmission characteristic data and key test node data, respectively. Based on signal transmission characteristic data and key test node data, the channel topology partitioning data is processed for test timing dependency to obtain timing dependency data. Dynamic dependency graphs are constructed based on temporal dependency data to obtain channel topology decomposition data.

5. The multi-test channel allocation method for electronic component testing as described in claim 1, characterized in that, The dynamic load compensation estimation based on the current test channel load balancing data and channel topology decomposition data yields load compensation estimation data, including: Based on the current test channel load balancing data and channel topology decomposition data, multi-signal test timing overlay calculations are performed to obtain timing overlay data; Signal density kernel distribution is calculated based on time-series superimposed data to obtain local load clustering intensity data; Based on the current test channel load balancing data, the channel carrying capacity and test response cycle are calculated to obtain the carrying capacity data and response cycle data respectively. Based on the load capacity data and response cycle data, dynamic load compensation time extrapolation is performed on the local load concentration intensity data to obtain load compensation estimation data.

6. The multi-test channel allocation method for electronic component testing as described in claim 1, characterized in that, The step of constructing the test channel operation dependency graph based on load compensation estimation data to obtain channel operation dependency graph data includes: Based on the current test channel load balancing data and channel topology decomposition data, an operation dependency subgraph is constructed for the test channel segment to obtain the operation dependency subgraph data. Dynamic weighting is performed on the operation dependency subgraph data based on the load compensation estimation data to obtain dynamic weighted graph data. Directed acyclic allocation optimization is performed based on dynamic weight graph data to obtain channel operation dependency graph data.

7. The multi-test channel allocation method for electronic component testing as described in claim 1, characterized in that, The step of performing test conflict quantization based on channel operation dependency graph data to obtain channel conflict quantization data includes: Based on the channel operation dependency graph data, test resource usage mapping is performed to obtain resource usage data; Conflicting tuples are extracted from resource usage data to obtain conflicting tuple data. Based on the conflict tuple data, signal overlap tension quantization is performed to obtain channel conflict quantization data.

8. The multi-test channel allocation method for electronic component testing as described in claim 7, characterized in that, The step of performing signal overlap tension quantization based on conflict tuple data to obtain channel conflict quantization data includes: The overlap of non-steady-state signals and the intersection of time-series occupancy are calculated based on the conflict tuple data, and the dynamic boundary overlap data and the intersection of time-series occupancy data are obtained respectively. Based on the dynamic boundary overlap data and the time sequence occupancy intersection data, the shared test node contention is analyzed to obtain node contention analysis data; Based on the node competition analysis data, signal tension propagation modeling is performed to obtain tension propagation matrix data; Based on the tension propagation matrix data, gravity compensation control was performed on a high-priority test task to obtain channel conflict quantification data.

9. The multi-test channel allocation method for electronic component testing as described in claim 1, characterized in that, The step of generating test channel collaborative allocation data based on channel conflict quantification data to achieve real-time dynamic optimization allocation of multiple test channels includes: Conflict core clusters are identified based on channel conflict quantification data to obtain conflict core cluster data; Based on the conflict core cluster data, the test channel topology-level allocation sequence is optimized to obtain the allocation sequence optimization data; Based on the allocation sequence optimization data, test channel collaborative allocation data is generated to drive the digital twin test platform to perform real-time dynamic optimization allocation of multiple test channels.

10. A multi-test channel allocation device for testing electronic components, characterized in that, The device includes: a memory, a processor, and a multi-test channel allocation program for electronic component testing stored in the memory and executable on the processor, the multi-test channel allocation program for electronic component testing being configured to implement the steps of the multi-test channel allocation method for electronic component testing as claimed in any one of claims 1 to 9.

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