Multilayer electronic components

Abstract

We provide highly reliable stacked electronic components. [Solution] A stacked electronic component according to one embodiment of the present disclosure includes a body comprising a dielectric layer, and first and second internal electrodes arranged alternately with respect to the dielectric layer, and first and second external electrodes disposed on the body and connected to the first and second internal electrodes, respectively, wherein a Sn plating layer is disposed on the outermost part of the first external electrode, and an Au-Sn plating layer having a different color from the Sn plating layer is disposed on the outermost part of the second external electrode.

Description

Technical Field

[0001] The present disclosure relates to a stacked electronic component.

Background Art

[0002] A multilayer ceramic capacitor (MLCC), which is one of the stacked electronic components, is a chip-shaped capacitor that is mounted on a printed circuit board of various electronic products such as video devices such as liquid crystal display (LCD) devices and plasma display panel (PDP) panels, computers, smartphones, and mobile phones, and serves to charge or discharge electricity. The MLCC is used as a component of various electronic devices because of its advantages of being small while ensuring a high capacitance and being easy to mount.

[0003] On the other hand, in order to induce potential defects of the MLCC and pre-screen initial defects, screening tests such as a burn-in test are performed. During the screening test, a high voltage is applied to the MLCC several times, and the voltage is also applied to the MLCC after it is mounted on the printed circuit board after final screening. On the other hand, the MLCC mainly has two external electrodes, and it is common that the two external electrodes are not distinguishable from each other in appearance. Therefore, the voltage application direction may be changed several times in the screening test. In this case, it has been found that there is a problem that the insulation resistance (IR) and life characteristics of the dielectric decrease. Therefore, if the voltage application direction can be unified in the selection test and the final use process of the MLCC, the reliability of the MLCC can be improved.

Summary of the Invention

Problems to be Solved by the Invention

[0004] One of the various objects of the present disclosure is to provide a stacked electronic component with excellent reliability.

[0005] However, the purpose of this disclosure is not limited to what is described above, and this will become clearer in the course of describing specific embodiments of this disclosure. [Means for solving the problem]

[0006] A stacked electronic component according to one embodiment of the present disclosure includes a body comprising a dielectric layer, and first and second internal electrodes arranged alternately with respect to the dielectric layer, and first and second external electrodes disposed on the body and connected to the first and second internal electrodes, respectively, wherein a Sn plating layer is disposed on the outermost part of the first external electrode, and an Au-Sn plating layer having a different color from the Sn plating layer can be disposed on the outermost part of the second external electrode. [Effects of the Invention]

[0007] One of the various benefits of this disclosure is the ability to provide highly reliable stacked electronic components. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic perspective view of a stacked electronic component according to one embodiment of the present disclosure. [Figure 2] This is a schematic cross-sectional view showing a section along the line I-I' in Figure 1. [Figure 3] This is a schematic cross-sectional view showing a section along the line II-II' in Figure 1. [Figure 4] This is a schematic cross-sectional view showing a section along the line III-III' in Figure 1. [Figure 5] This is a schematic cross-sectional view of a stacked electronic component according to another embodiment of the present disclosure, and corresponds to Figure 2. [Figure 6] This is a schematic plan view showing a package for a stacked electronic component according to one embodiment of the present disclosure. [Figure 7a] This graph shows the lifetime Weibull distribution for Example 1 and Example 2. [Figure 7b]This graph shows the lifetime Weibull distribution for Examples 3 and 4. [Figure 7c] This graph shows the lifetime Weibull distribution for Examples 5 and 6. [Modes for carrying out the invention]

[0009] Embodiments of the present disclosure will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present disclosure can be modified into several other forms, and the scope of the present disclosure is not limited to the embodiments described below. Furthermore, embodiments of the present disclosure are provided to give a more complete explanation of the present disclosure to a person of the ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer explanation, and elements indicated by the same reference numeral in the drawings are the same element.

[0010] Furthermore, in order to clearly illustrate this disclosure, parts unrelated to the explanation have been omitted in the drawings, and the size and thickness of each illustrated component are shown arbitrarily for the convenience of explanation; therefore, this disclosure is not necessarily limited by the illustrations. Also, components with the same function within the scope of the same idea are described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a component, it does not mean that other components are excluded, but rather that other components may be included, unless otherwise stated to the contrary.

[0011] In drawings, the first direction X can be defined as the thickness (T) direction, the second direction Y as the length (L) direction, and the third direction Z as the width (W) direction.

[0012] Multilayer electronic components Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present disclosure; Figure 2 is a schematic cross-sectional view showing a section along line I-I' in Figure 1; Figure 3 is a schematic cross-sectional view showing a section along line II-II' in Figure 1; and Figure 4 is a schematic cross-sectional view showing a section along line III-III' in Figure 1.

[0013] Hereinafter, with reference to Figures 1 to 4, a multilayer electronic component 100 according to one embodiment of this disclosure will be described in detail. While a multilayer ceramic capacitor will be described as an example of a multilayer electronic component, this disclosure is not limited to this and can be applied to a variety of multilayer electronic components, such as inductors, piezoelectric elements, varistors, or thermistors.

[0014] An embodiment of the stacked electronic component 100 of this disclosure may include a main body 110 and external electrodes 131 and 132 disposed on the main body 110.

[0015] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process and the polishing process on the corners of the main body 110, the main body 110 may not be a perfectly straight hexahedron, but it can be substantially hexahedral.

[0016] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, a fifth surface 5 and a sixth surface 6 connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0017] The main body 110 can include a dielectric layer 111 and internal electrodes 121 and 122 that are alternately arranged with the dielectric layer 111. The plurality of dielectric layers 111 forming the main body 110 are in a fired state, and the boundary between adjacent dielectric layers 111 can be integrated to such an extent that it is difficult to confirm without using a scanning electron microscope (SEM).

[0018] The dielectric layer 111 can contain, for example, a perovskite-type compound represented by ABO3 as a main component. The perovskite-type compound represented by ABO3 can be, for example, BaTiO3, (Ba y , ,

[0021] Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3 (0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y )O3 (0 < x ≤ 0.5, 0 < y ≤ 0.5), and can contain one or more of them.

[0019] The average thickness td of the dielectric layer 111 is not particularly limited. The average thickness td of the dielectric layer 111 can be, for example, 0.1 μm to 20 μm, 0.1 μm to 10 μm, 0.1 μm to 5 μm, 0.1 μm to 2 μm, or 0.1 μm to 0.4 μm.

[0020] The internal electrodes 121 and 122 can include, for example, a first internal electrode 121 and a second internal electrode 122 that are alternately arranged in the first direction with the dielectric layer 111 interposed therebetween. The first internal electrode 121 and the second internal electrode 122, which are a pair of electrodes having different polarities, can be arranged so as to face each other with the dielectric layer 111 interposed therebetween.

[0021] The first internal electrode 121 is separated from the fourth surface and can be connected to the first external electrode 131 at the third surface 3. The second internal electrode 122 is separated from the third surface 3 and can be connected to the second external electrode 132 at the fourth surface 4.

[0022] The conductive metal contained in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, Sn, W, Ti, and alloys thereof, and more preferably may include Ni, but is not limited thereto.

[0023] The average thickness te of the internal electrodes 121 and 122 is not particularly limited. The average thickness te of the internal electrodes 121 and 122 may be, for example, 0.1 μm to 3.0 μm, 0.1 μm to 1.0 μm, or 0.1 μm to 0.4 μm.

[0024] The average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 refer to the average thickness of the dielectric layer 111 and the internal electrodes 121 and 122 in the first direction. The average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 can be measured by scanning the cross-sections of the main body 110 in the first and second directions with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the average thickness td of the dielectric layer 111 can be measured by measuring the thickness at multiple points on one dielectric layer 111, for example, five points equally spaced in the second direction, and then calculating the average value. Similarly, the average thickness te of the internal electrodes 121 and 122 can be measured by measuring the thickness at multiple points on one internal electrode 121 or 122, for example, five points equally spaced in the second direction, and then calculating the average value. The five equally spaced points can be specified in the capacitance forming section Ac. On the other hand, if such average values ​​are measured for 10 dielectric layers 111 and 10 internal electrodes 121 and 122, and then the average values ​​are measured, the average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 can be further generalized.

[0025] The main body 110 may include a capacitance forming section Ac disposed inside the main body 110 and comprising first internal electrodes 121 and second internal electrodes 122 arranged alternately with respect to the dielectric layer 111 in between, a cover section 112, 113 disposed on both sides of the capacitance forming section Ac facing a first direction, and margin sections 114, 115 disposed on both sides of the capacitance forming section Ac facing a third direction. The cover sections 112, 113 and the margin sections 114, 115 may have a configuration similar to the dielectric layer 111, except that they do not include internal electrodes.

[0026] The average thickness tc of the cover portions 112 and 113 may be, for example, 300 μm or less, 150 μm or less, 100 μm or less, 30 μm or less, or 20 μm or less. The average thickness tc of the cover portions 112 and 113 may be, for example, 5 μm or more, 10 μm or more, or 30 μm or more. Here, the average thickness tc of the cover portions 112 and 113 refers to the average thickness of the first cover portion 112 and the second cover portion 113, respectively.

[0027] The average thickness tc of the cover portions 112 and 113 can mean the average thickness of the cover portions 112 and 113 in the first direction, and can be the average value of the thickness in the first direction measured at five equally spaced points in the cross-section of the main body 110 in the first and second directions.

[0028] The average thickness of the margin portions 114 and 115 may be, for example, 150 μm or less, 100 μm or less, 20 μm or less, or 15 μm or less. The average thickness of the margin portions 114 and 115 may be, for example, 5 μm or more, 10 μm or more, or 20 μm or more. Here, the average thickness of the margin portions 114 and 115 refers to the average thickness of the first margin portion 114 and the second margin portion 115, respectively.

[0029] The average thickness wm of the margin portions 114 and 115 can represent the average thickness of the margin portions 114 and 115 in the third direction, and can be the average value of the thickness in the third direction measured at five equally spaced points in the cross-section of the main body 110 in the first and third directions.

[0030] The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 that are connected to a first internal electrode 121 and a second internal electrode 122, respectively. The first external electrode 131 is positioned on the third surface 3 and can contact the end of the first internal electrode 121, and the second external electrode 132 is positioned on the fourth surface 4 and can contact the end of the second internal electrode 122. The first external electrode 131 may extend from the third surface 3 onto the first surface 1, the second surface 2, the fifth surface 5, and a portion of the sixth surface 6, and the second external electrode 132 may extend from the fourth surface 4 onto the first surface 1, the second surface 2, the fifth surface 5, and a portion of the sixth surface 6.

[0031] According to one embodiment of the present disclosure, a Sn plating layer 131c can be placed on the outermost part of the first external electrode 131, and an Au-Sn plating layer 132c having a different color from the Sn plating layer 131c can be placed on the outermost part of the second external electrode 132.

[0032] As mentioned above, after manufacturing, multilayer electronic components undergo selection tests such as burn-in tests. During the selection testing process, high voltage must be applied to the multilayer electronic component several times. However, if the appearance of the first external electrode and the appearance of the second external electrode cannot be distinguished, the direction of the applied voltage to the multilayer electronic component can be changed multiple times during the selection process and subsequent use.

[0033] When a voltage is applied to a dielectric material, the domains within the dielectric can align in the direction of the applied voltage. After this, if the dielectric is heat-treated, the domains can be randomly aligned again, although some domains may remain aligned in their original direction even after heat treatment. If a voltage is applied to the dielectric in the opposite direction in this state, some domains may be damaged by the voltage applied in the opposite direction to their alignment, which can degrade the dielectric's insulation resistance.

[0034] On the other hand, in the case of a multilayer electronic component 100 according to one embodiment of the present disclosure, a Sn plating layer 131c is arranged on the outermost part of the first external electrode 131, and an Au-Sn plating layer 132c having a different color from the Sn plating layer 131c is arranged on the outermost part of the second external electrode 132, thereby allowing the first external electrode 131 and the second external electrode 132 to be distinguished during the sorting process and the use process. This makes it possible to unify the direction of voltage application applied to the multilayer electronic component 100 during the sorting process and the use process, thereby improving the reliability of the multilayer electronic component 100.

[0035] In this disclosure, the fact that the Sn plating layer 131c and the Au-Sn plating layer 132c have different colors means, for example, that the color difference (ΔE) between the Sn plating layer 131c and the Au-Sn plating layer 132c, as defined by the following mathematical formula 1, is 50 or more. [Mathematical formula 1] ΔE=[(ΔL * ) 2 +(Δa * ) 2 +(Δb * ) 2 ] 1 / 2

[0036] In the above [Mathematical Equation 1], ΔL * This is the CIE L measured on the Sn plating layer 131c. * a * b * L of the color system * The value and L measured in the Au-Sn plating layer 132c * It can mean the difference between the values, Δa * This is the CIE L measured on the Sn plating layer 131c. * a * b * a color system * The value and the a measured in the Au-Sn plating layer 132c * It can mean the difference between the values, Δb * This is the CIE L measured on the Sn plating layer 131c. * a * b * color system b *The value and the b measured in the Au-Sn plating layer 132c * It can mean the difference between the value and the given value. In this disclosure, "CIE L * a * b * The term "color system" can refer to the color system standardized and recommended by the CIE in 1976.

[0037] On the other hand, the Au-Sn plating layer 132c can contain an Au-Sn alloy that, despite being a colored metal, does not excessively reduce solderability to Sn, and falls between Au, which has excellent electrical conductivity, and Sn, which has excellent solderability. The Au-Sn plating layer 132c only needs to contain an Au-Sn alloy, but for example, the content of Au element (wt%) relative to the total elements of the Au-Sn plating layer 132c can be greater than the content of Sn element (wt%) relative to the total elements of the Au-Sn plating layer 132c. This allows for more reliable differentiation between the first external electrode 131 and the second external electrode 132. Because Au has excellent wettability to Sn, even if the content of Au element (wt%) in the Au-Sn plating layer 132c is greater than the content of Sn element (wt%), the mounting stability may not decrease significantly.

[0038] In one embodiment, the content of Au (wt%) relative to the total content of Au and Sn contained in the Au-Sn plating layer 132c may be 62.4% by weight or more and less than 100% by weight. When this range is met, the first external electrode 131 and the second external electrode 132 can be distinguished even more reliably. Referring to Table 1 below, when the content of Au (wt%) relative to the total content of Au and Sn is 62.4 wt% or more, AuSn and / or Au5Sn, in which the proportion of Au in the intermetallic compound between Au and Sn is high, can be formed, so a color difference between the Sn plating layer 131c and the Au-Sn plating layer 132c is reliably observed.

[0039] [Table 1]

[0040] For example, CIE L measured on Sn plated layer 131c * a * b * color system b * Value b1 * CIE L measured on Au-Sn plated layer 132c * a * b * color system b * Value b2 * In that case, b2 * -b1 * It is possible to satisfy the condition ≥ 50.

[0041] This allows multiple stacked electronic components 100 to be aligned in the same direction during the taping packaging process. In this case, when mounting the stacked electronic components 100 onto a printed circuit board, the polarity of the terminals on the printed circuit board and the polarity of the external electrodes 131 and 132 of the stacked electronic components 100 can be unified, thereby improving the expected lifespan of the stacked electronic components 100.

[0042] The content of Au (wt%) relative to the total content of Au and Sn in the Au-Sn plating layer 132c can be measured, for example, by analyzing the cross-sections in the first and second directions, polished to the center of the third direction of the multilayer electronic component 100, using SEM (scanning electron microscope)-EDS (energy-dispersive X-ray spectroscopy). However, this disclosure is not limited thereto, and other known measurement methods may also be used.

[0043] The Au-Sn plating layer 132c may contain one or more of Au5Sn, AuSn, AuSn2, and AuSn4. More preferably, the Au-Sn plating layer 132c may contain one or more of Au5Sn and AuSn, which have a high proportion of Au in the intermetallic compound between Au and Sn. This ensures that a color difference between the Sn plating layer 131c and the Au-Sn plating layer 132c is reliably observed.

[0044] The outermost surface of the first external electrode 131 is provided with a Sn plating layer 131c, and the outermost surface of the second external electrode 132 is provided with an Au-Sn plating layer 132c; the specific forms of the first external electrode 131 and the second external electrode 132 are not particularly limited.

[0045] The first external electrode 131 may include, for example, a first base electrode layer 131a in contact with the first internal electrode 121, and a first Ni plating layer 131b disposed on the first base electrode layer 131a. The second external electrode 132 may include, for example, a second base electrode layer 132a in contact with the second internal electrode 122, and a second Ni plating layer 132b disposed on the second base electrode layer 132a.

[0046] The first base electrode layer 131a and the second base electrode layer 132a may be fired electrode layers containing metal and glass, respectively. The first base electrode layer 131a and the second base electrode layer 132a may contain Cu, Ni, Pd, Pt, Au, Ag, Pb and / or alloys containing these. For example, the first base electrode layer 131a and the second base electrode layer 132a may each contain Cu. The glass contained in the base electrode layers 131a and 132a may contain one or more oxides from, for example, Ba, Ca, Zn, Al, B and Si.

[0047] The Sn plating layer 131c can be positioned in contact with the first Ni plating layer 131b, and the Au-Sn plating layer 132c can be positioned in contact with the second Ni plating layer 132b. In one embodiment, the Sn plating layer 131c can be positioned to completely cover the first Ni plating layer 131b, and the Au-Sn plating layer 132c can be positioned to completely cover the second Ni plating layer 132b.

[0048] The Sn plating layer 131c is positioned on the third surface 3 and can extend over parts of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6, while the Au-Sn plating layer 132c is positioned on the fourth surface 4 and can extend over parts of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6.

[0049] Figure 5 is a schematic cross-sectional view of a stacked electronic component 200 according to another embodiment of the present disclosure, and corresponds to Figure 2. Hereinafter, the stacked electronic component 200 according to another embodiment of the present disclosure will be described with reference to Figure 5, and the same / similar reference numerals will be used for components that are the same / similar as those of the stacked electronic component 100 described in Figures 1 to 4, and redundant explanations will be omitted.

[0050] The stacked electronic component 200 may include a main body 110 and external electrodes 231 and 232 disposed on the main body 110.

[0051] The first external electrode 231 may include a first base electrode layer 231a in contact with the first internal electrode 121, a first conductive resin layer 231d disposed on the first base electrode layer 231a, and a first Ni plating layer 231b disposed on the first conductive resin layer 231d.

[0052] The second external electrode 232 may include a second base electrode layer 232a in contact with the second internal electrode 122, a second conductive resin layer 232d disposed on the second base electrode layer 232a, and a second Ni plating layer 232b disposed on the second conductive resin layer 232d. The Sn plating layer 231c may be disposed in contact with the first Ni plating layer 231b, and the Au-Sn plating layer 232c may be disposed in contact with the second Ni plating layer 232b.

[0053] The first base electrode layer 231a and the second base electrode layer 232a may be fired electrode layers containing metal and glass, respectively. The first base electrode layer 231a and the second base electrode layer 232a may contain Cu, Ni, Pd, Pt, Au, Ag, Pb and / or alloys containing these. For example, the first base electrode layer 131a and the second base electrode layer 132a may each contain Cu.

[0054] The first conductive resin layer 231d and the second conductive resin layer 232d can each contain metal particles and a resin. The metal particles contained in the conductive resin layers 231d and 232d can include one or more of spherical particles and flaky particles. Here, the spherical particles can include forms that are not perfectly spherical, for example, forms with an aspect ratio (major axis / minor axis) of 1.45 or less. The flaky particles mean particles having a flat and elongated form and are not particularly limited, but for example, the aspect ratio (major axis / minor axis) may be 1.95 or more. The metal particles contained in the conductive resin layers 231d and 232d can include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, Sn, and / or an alloy containing these. The resin contained in the conductive resin layers 231d and 232d can include, for example, one or more of epoxy resin, acrylic resin, and ethyl cellulose.

[0055] Method for manufacturing a multilayer electronic component Hereinafter, an example of a method for forming the multilayer electronic component 100 will be described. However, the manufacturing method of the multilayer electronic component 100 is not limited thereto.

[0056] First, ceramic powder for forming the dielectric layer 111 is prepared. The ceramic powder is, for example, BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3 (0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y)One or more of O3 (0 < x ≤ 0.5, 0 < y ≤ 0.5) can be included. The BaTiO3 powder can be synthesized, for example, by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Examples of the method for synthesizing the ceramic powder include a solid-phase method, a sol-gel method, a hydrothermal synthesis method, etc., but the present disclosure is not limited thereto. Next, after drying and pulverizing the prepared ceramic powder, an organic solvent such as ethanol and a binder such as polyvinyl butyral are mixed to produce a ceramic slurry, and the ceramic slurry is applied and dried on a carrier film to prepare a ceramic green sheet.

[0057] Next, an internal electrode conductive paste containing a metal powder, a binder, an organic solvent, etc. is printed on the ceramic green sheet at a predetermined thickness using a screen printing method or a gravure printing method to form an internal electrode pattern.

[0058] After that, the ceramic green sheet with the internal electrode pattern printed thereon is peeled off from the carrier film, and then the ceramic green sheets with the internal electrode pattern printed thereon are laminated and pressure-bonded by a predetermined number of layers to form a ceramic laminate. On the upper and lower parts of the ceramic laminate, ceramic green sheets on which no internal electrode pattern is formed may be laminated by a predetermined number of layers in order to form the cover parts 112 and 113 after firing. After that, the ceramic laminate can be cut to have a predetermined chip size, and the cut chips can be fired to form the main body 110. The firing can be performed, for example, at a temperature of 1.0% H2 / 99.0% N2 to 3.5% H2 / 96.5% N2 (H2O / H2 / N2 atmosphere), 1000 °C or higher and 1400 °C or lower for 1 hour to 3 hours.

[0059] On the other hand, the margin portions 114 and 115 may be formed by applying a conductive paste for internal electrodes to the ceramic green sheet and firing it, except where the margin portions are formed. Alternatively, in order to suppress the step caused by the internal electrodes 121 and 122, the ceramic laminate may be cut so that the internal electrode pattern is exposed on both sides of the cut chip in the third direction, then a margin portion forming sheet may be attached to both sides of the cut chip in the third direction, and then fired to form the margin portions 114 and 115.

[0060] Next, external electrodes 131 and 132 are formed. For example, the base electrode layers 131a and 132a can be formed by dipping the main body 110 into a conductive paste containing metal powder, glass frit, a binder, and an organic solvent, and then firing the conductive paste at a temperature of 500°C to 900°C. The metal powder may include, for example, Cu powder.

[0061] Alternatively, Ni plating layers 131b and 132b may be formed on the underlay electrode layers 131a and 132a using electroplating and / or electroless plating.

[0062] Next, a Sn plating layer 131c can be formed on the first Ni plating layer 131b using an electrolytic plating method and / or an electroless plating method.

[0063] An Au-Sn plating layer 132c can be formed on the second Ni plating layer 132b. The Au-Sn plating layer 132c can be formed by an electroplating method using an Au-Sn alloy plating solution containing, for example, Na3Au(SO3)2, Sn(K2(OH)6), Na2SnO3 and / or NaOH. For example, by increasing the weight proportion of Na3Au(SO3)2 contained in the Au-Sn alloy plating solution, the Au content (wt%) relative to the total Au and Sn content in the Au-Sn plating layer 132c can be increased.

[0064] On the other hand, the method for manufacturing the stacked electronic component 200 is not particularly limited. For example, after forming base electrode layers 231a and 232a on the main body 110, the main body 110 can be dipped in a conductive resin composition containing metal powder, resin, binder, and organic solvent, and then subjected to heat treatment at a temperature of 250°C to 550°C to form conductive resin layers 231d and 232d.

[0065] Next, the Ni plating layers 231b and 232b, and the Sn plating layer 231c and Au-Sn plating layer 232c can be formed sequentially using the method described above.

[0066] Packaging for multilayer electronic components Figure 6 is a schematic plan view showing a packaging for a stacked electronic component according to one embodiment of the present disclosure. The packaging 300 for a stacked electronic component according to one embodiment of the present disclosure will now be described with reference to Figure 6.

[0067] A packaging 300 for a stacked electronic component according to one embodiment of the present disclosure may include a carrier tape 310 and a cover tape 320 attached to the carrier tape 310.

[0068] The carrier tape 310 may have, for example, a plurality of accommodating grooves 311. The plurality of accommodating grooves 311 can accommodate stacked electronic components 100, 200. The plurality of accommodating grooves 311 may be arranged along the length of the carrier tape 310.

[0069] Multiple sprocket grooves 312 may be provided on one side of the carrier tape 310. The multiple sprocket grooves 312 can be arranged along the length of the carrier tape 310. The sprocket grooves 312 can be used as a sawtooth-like configuration when moving the carrier tape 310.

[0070] As shown in Figure 6, the two external electrodes of the stacked electronic components 100 and 200 can be distinguished from each other through camera recognition during the taping packaging process, allowing multiple stacked electronic components 100 and 200 to be arranged in the same direction on the packaging 300. In this case, when mounting the stacked electronic components 100 and 200 on a printed circuit board, the polarity of the terminals of the printed circuit board and the polarity of the external electrodes 131 and 132 of the stacked electronic component 100 can be easily unified, improving the expected lifespan of the stacked electronic components 100 and 200.

[0071] (Experimental Example 1) A lifespan comparison evaluation was conducted by changing the voltage application direction during sorting tests and the final use process. First, a sample chip with a size of 3216 (length: approximately 3.2 mm, width: approximately 1.6 mm, thickness: approximately 1.6 mm) was prepared. The first external electrode of the sample chip included a first underlayer electrode layer containing Cu, a first Ni plating layer, and a Sn plating layer, which were formed sequentially. The second external electrode included a second underlayer electrode layer containing Cu, a second Ni plating layer, and an Au-Sn plating layer, which were formed sequentially.

[0072] Next, burn-in tests were performed on the sample chips. The burn-in tests were conducted four times under the conditions of 160°C, 75V, and 30 minutes of holding time. The direction of voltage application in each burn-in test is shown in Table 2 below. After the burn-in tests, each sample chip was heat-treated at 160°C for 1 hour.

[0073] Finally, each sample chip was mounted on a printed circuit board, and high-temperature accelerated lifetime evaluation (HALT) was performed under conditions of 160°C and 125V. The voltage application direction during the high-temperature accelerated lifetime evaluation is shown in Table 2 below, and the number of final voltage application direction changes for the sample chips after burn-in testing and high-temperature accelerated lifetime evaluation is also shown in Table 2.

[0074] Specifically, in Examples 1 and 2, the voltage application direction was standardized to + during the burn-in test. In Example 1, the voltage application direction was standardized to + during the high-temperature accelerated lifetime evaluation, while in Example 2, it was converted to -.

[0075] Examples 3 and 4 involved changing the voltage application direction three times during the burn-in test. In Example 3, the voltage application direction during the high-temperature accelerated life evaluation was set to the positive direction of the initial voltage application, while in Example 4, the voltage application direction during the high-temperature accelerated life evaluation was set to the negative direction opposite to the initial voltage application direction.

[0076] Examples 5 and 6 involved changing the voltage application direction once during the burn-in test. In Example 5, the voltage application direction during the high-temperature accelerated life evaluation was set to the positive direction of the initial voltage application, while in Example 6, the voltage application direction during the high-temperature accelerated life evaluation was set to the negative direction, opposite to the initial voltage application direction.

[0077] [Table 2]

[0078] Figure 7a is a graph showing the lifetime Weibull distribution for Examples 1 and 2, Figure 7b is a graph showing the lifetime Weibull distribution for Examples 3 and 4, and Figure 7c is a graph showing the lifetime Weibull distribution for Examples 5 and 6. Referring to Figures 7a to 7c, it can be confirmed that Example 1, in which the voltage application direction was not changed at all after burn-in testing and high-temperature accelerated lifetime evaluation, has superior lifetime characteristics compared to Examples 2 to 6.

[0079] This is presumably because some of the domains constituting the dielectric were damaged by a voltage applied in the opposite direction to the domain alignment, thereby degrading the dielectric's insulation resistance.

[0080] Furthermore, it can be confirmed that Example 3 has superior lifetime characteristics compared to Example 4, and Example 5 has superior lifetime characteristics compared to Example 6. This is presumably because, in Examples 3 and 5, the direction of the initially applied voltage and the direction of voltage application in the high-temperature accelerated lifetime evaluation were the same, while in Examples 4 and 6, the direction of the initially applied voltage and the direction of voltage application in the high-temperature accelerated lifetime evaluation were opposite. In other words, while the number of voltage application direction changes is important for maintaining the reliability of stacked electronic components, it can be confirmed that it is even more important to unify the direction of the initial voltage applied during the sorting process and the direction of the final voltage applied during the usage process.

[0081] (Experimental Example 2) A sample chip with size 3216 (length: approximately 3.2 mm, width: approximately 1.6 mm, thickness: approximately 1.6 mm) was prepared. The first external electrode of the sample chip included a first underlayer electrode layer containing Cu, a first Ni plating layer, and a Sn plating layer, which were formed sequentially. The second external electrode included a second underlayer electrode layer containing Cu, a second Ni plating layer, and an Au-Sn plating layer, which were formed sequentially.

[0082] Next, the taping and packaging process was carried out for each example, where the Au content (wt%) differed relative to the total Au and Sn content in the Au-Sn plating layer. In Example 7, the Au content (wt%) relative to the total Au and Sn content in the Au-Sn plating layer was 14.65 wt%. In Example 8, the Au content (wt%) relative to the total Au and Sn content in the Au-Sn plating layer was 37.3 wt%. In Example 9, the Au content (wt%) relative to the total Au and Sn content in the Au-Sn plating layer was 55.35 wt%. In Example 10, the Au content (wt%) relative to the total Au and Sn content in the Au-Sn plating layer was 62.4 wt%. In the comparative example, an Sn plating layer was formed on the outermost part of the second external electrode instead of an Au-Sn plating layer.

[0083] Next, the RGB of the second external electrode was measured and recorded in Table 3 below, and the CIE L measured on the Sn plating layer of the first external electrode was also measured. * a* b * color system b * Value (b1 * ) and the CIE L measured on the Au-Sn plating layer of the second external electrode * a * b * color system b * Value (b2 * The difference between (b2) * -b1 * The following measurements were taken and recorded in Table 3 below.

[0084] Next, the taping packaging process was carried out for the sample chips of the comparative examples and Examples 7-10. 300 sample chips were packaged, and the sample chips were arranged on the tape in the same direction by determining the color of the first and second external electrodes via a camera installed in the packaging equipment. The percentage of sample chips arranged in the same direction on the tape was defined as the "loading rate" and is shown in Table 3 below.

[0085] [Table 3]

[0086] In the comparative example, it was difficult to distinguish between the first and second external electrodes, and it was confirmed that the loading rate was approximately 50%, which can be interpreted as the sample chips being arranged in a random direction.

[0087] In Examples 7 and 8, the loading rate increased compared to the comparative example, but it was lower than in Examples 9 and 10.

[0088] In Example 9, it was confirmed that the distinction between the first and second external electrodes became easier, and the loading rate increased to 85.7%. In particular, in Example 10, by satisfying the requirement that the Au content (wt%) relative to the total Au and Sn content in the Au-Sn plating layer be 62.4 wt% or more, the distinction between the first and second external electrodes became reliable, resulting in a loading rate of 100%.

[0089] This disclosure is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims attached. Therefore, within the scope of the technical idea of ​​this disclosure as described in the claims, various forms of substitution, modification, and alteration are possible by a person with ordinary skill in the art, and these also fall within the scope of this disclosure.

[0090] Furthermore, the expression "one embodiment" does not mean that each embodiment is identical to the others, but is provided to highlight and explain the unique and distinct characteristics of each embodiment. However, the above-presented embodiments do not preclude their realization in combination with the characteristics of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, as long as there is no contradictory or contrary explanation of that matter in the other embodiment.

[0091] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and non-connected cases. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component. [Explanation of symbols]

[0092] 100, 200 Stacked Electronic Components 110 Main Unit 111 Dielectric layer 112, 113 Cover section 114, 115 Margin section 121, 122 Internal electrode 131, 132, 231, 232 external electrode 131a, 132a, 231a, 232a Base electrode layer 131b, 132b, 231b, 232b Ni plating layer 131c, 231c Sn plating layer 132c, 232c Au-Sn plating layer 231d, 232d Conductive resin layer

Claims

1. A body including a dielectric layer, and first and second internal electrodes arranged alternately on either side of the dielectric layer, The body includes a first external electrode and a second external electrode, which are arranged on the main body and connected to the first internal electrode and the second internal electrode, respectively. A multilayer electronic component in which a Sn plating layer is disposed on the outermost part of the first external electrode, and an Au-Sn plating layer having a different color from the Sn plating layer is disposed on the outermost part of the second external electrode.

2. The multilayer electronic component according to claim 1, wherein the content of Au element (wt%) relative to the total elements of the Au-Sn plating layer is greater than the content of Sn element (wt%) relative to the total elements of the Au-Sn plating layer.

3. The multilayer electronic component according to claim 1, wherein the content of Au (wt%) relative to the total content of Au and Sn contained in the Au-Sn plating layer is 62.4 wt% or more and less than 100 wt%.

4. The CIE L measured in the Sn plating layer ＊ , ＊ , ＊ , １ , ＊ , ２ , ＊ , ２ a ＊ b ＊ The b value of the colorimetric system ＊ is b １ <​​​​​​​​​​​​​​​​​​

5. The Au-Sn plating layer is made of Au ５ Sn, AuSn, AuSn ２ and AuSn ４ A stacked electronic component according to claim 1, comprising one or more of the above.

6. The Au-Sn plating layer is made of Au ５ A stacked electronic component according to claim 1, comprising one or more of Sn and AuSn.

7. The first external electrode includes a first base electrode layer in contact with the first internal electrode, and a first Ni plating layer disposed on the first base electrode layer. The stacked electronic component according to claim 1, wherein the second external electrode includes a second underlay electrode layer in contact with the second internal electrode, and a second Ni plating layer disposed on the second underlay electrode layer.

8. The Sn plating layer is arranged to completely cover the first Ni plating layer. The stacked electronic component according to claim 7, wherein the Au-Sn plating layer is arranged to completely cover the second Ni plating layer.

9. The main body has a first and second surface facing each other in a first direction, a third and fourth surface connected to the first and second surfaces and facing each other in a second direction, and a fifth and sixth surface connected to the first, second, third and fourth surfaces and facing each other in a third direction. The Sn plating layer is positioned on the third surface and extends over a portion of the first surface, the second surface, the fifth surface and the sixth surface, The stacked electronic component according to claim 1, wherein the Au-Sn plating layer is disposed on the fourth surface and extends over a portion of the first surface, the second surface, the fifth surface, and the sixth surface.

10. The laminated electronic component according to claim 7, wherein the first base electrode layer and the second base electrode layer each contain Cu and glass, respectively.

11. The first external electrode includes a first base electrode layer in contact with the first internal electrode, a first conductive resin layer disposed on the first base electrode layer, and a first Ni plating layer disposed on the first conductive resin layer. The laminated electronic component according to any one of claims 1 to 10, wherein the second external electrode includes a second base electrode layer in contact with the second internal electrode, a second conductive resin layer disposed on the second base electrode layer, and a second Ni plating layer disposed on the second conductive resin layer.

12. The first and second base electrode layers each contain Cu and glass, The laminated electronic component according to claim 11, wherein the first conductive resin layer and the second conductive resin layer each contain metal particles and resin, respectively.

13. The multilayer electronic component according to any one of claims 1 to 10, wherein the color difference (ΔE) between the Sn plating layer and the Au-Sn plating layer, as defined by the following mathematical formula 1, is 50 or more. [Mathematical formula 1] ΔE=[(ΔL ＊ ) ２ +(Δa ＊ ) ２ +(Δb ＊ ) ２ ] １／２ (In the above mathematical formula 1, ΔL ＊ This refers to the CIE L values ​​measured in the Sn plating layer and the Au-Sn plating layer, respectively. ＊ a ＊ b ＊ Color system L ＊ The difference between the values ​​is Δa ＊ This refers to the CIE L values ​​measured in the Sn plating layer and the Au-Sn plating layer, respectively. ＊ a ＊ b ＊ a color system ＊ The difference between the values ​​is Δb ＊ This refers to the CIE L values ​​measured in the Sn plating layer and the Au-Sn plating layer, respectively. ＊ a ＊ b ＊ color system b ＊ (The difference between the values)

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