METHOD FOR PROCESSING AN ELECTRONIC COMPONENT

Abstract

Method (100) for processing an electronic component comprising at least one electrically conductive contact area, wherein the method comprises: Forming a contact point comprising a self-segregating mixture over at least one electrically conductive contact area to electrically contact the electronic component (101); and Forming a segregation suppression structure between the contact point and the electronic component, wherein the segregation suppression structure comprises more nucleation-inducing topographic features than the at least one electrically conductive contact area, to disrupt chemical segregation of the self-segregating mixture by crystallographic interfaces of the contact point defined by the nucleation-inducing topographic features (103), wherein forming the segregation suppression structure (103) comprises forming a metallization over the at least one electrically conductive contact area and structuring the metallization to form the nucleation-inducing topographic features of the segregation suppression structure.

Description

[0001] Different embodiments generally refer to a method for processing an electronic component and an electronic component.

[0002] In general, a metal alloy (e.g., an aluminum-copper alloy) can be susceptible to pitting corrosion. Pitting corrosion can refer to extremely localized corrosion that damages the metal alloy, for example, by forming holes. Pitting corrosion can be induced by stoichiometric inhomogeneities leading to anode-cathode coupling, which induces localized contact corrosion on the spatial scale of the stoichiometric inhomogeneities. Therefore, pitting corrosion can occur even in otherwise corrosion-resistant alloys.

[0003] For example, in the case of grain boundary corrosion (also known as grain boundary attack), the boundaries of crystallites in a metal alloy can be more susceptible to corrosion than their interior, e.g., when the grain boundaries are depleted of corrosion-inhibiting elements such as chromium (also known as grain boundary depletion). In nickel alloys and austenitic steels, where chromium is added for corrosion resistance, the formation of chromium-depleted zones near the grain boundaries can be induced by chromium carbide precipitation at the grain boundaries. Grain boundary depletion can induce local galvanic coupling, which causes localized contact corrosion.

[0004] Alternatively or additionally, a chemically activating environment can induce or exacerbate pitting corrosion. For example, wet chemical treatment of an aluminum-copper alloy can lead to galvanic deposition of copper from the solution and aluminum corrosion. Alternatively or additionally, pitting corrosion can be induced or exacerbated by an electric current flowing through the metal alloy.

[0005] Traditionally, pitting corrosion can be reduced by artificial passivation (e.g., using a protective nitride) of the metal alloy. However, artificial passivation can impede the electrical contact of electronic components, for example, if the metal alloy provides a contact point. For electrical contacting, the artificial passivation can be locally removed by dry etching to expose the metal alloy, for example, for bonding the exposed area of ​​the contact point. In this case, dry etching can also attack the inherent passivation (e.g., aluminum oxide) of the metal alloy, thereby increasing the risk of pitting corrosion near the electrical contact. Alternatively, the bonding parameters can be adjusted through the artificial passivation, which can lead to a weakened electrical contact.Furthermore, if the artificial passivation contains a metal, the artificial passivation can form a galvanic cell with the metal alloy and thereby induce contact corrosion itself.

[0006] According to various embodiments, a method for processing an electronic component containing at least one electrically conductive contact area may include: forming a contact point containing a self-segregating mixture over the at least one electrically conductive contact area to electrically contact the electronic component; forming a segregation suppression structure between the contact point and the electronic component, wherein the segregation suppression structure contains more nucleation-inducing topographic features than the at least one electrically conductive contact area, to disrupt chemical segregation of the self-segregating mixture by crystallographic interfaces of the contact point defined by the nucleation-inducing topographic features. Prior art can be found, for example, in US 5,981,382 A, US 6,117,758 A, or US 6,120,844 A.

[0007] In the drawings, the same reference numerals generally refer to the same parts throughout the different views. The drawings are not necessarily to scale; instead, the illustration of the principles of the invention is generally emphasized. The following description details various embodiments of the invention with reference to the following drawings, in which: Fig. 1, Fig. 2 to Fig. 3. Each of the following methods is shown in a schematic flowchart according to different embodiments; Fig. Figures 4A to 4D each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. 5A and Fig. 5B each show a metallization process according to different embodiments in a schematic cross-sectional view or side view; Fig. 5C shows a schematic diagram in a method according to various embodiments; Fig. Figures 6A to 6D each show a segregation suppression structure in a method according to different embodiments in a schematic perspective view; Fig. 7A and Fig. 7B each show a segregation suppression structure in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. Figures 8A to 8C each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. Figures 9A to 9C each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. Figures 10A to 10C each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. Figures 11A to 11C each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. Figures 12A to 13 each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. Figures 14A to 15 each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. 16A and Fig. 16B each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. 17A and Fig. 17B each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. 18A and Fig. 18B each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; Fig. 19A and Fig. 19B each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view; and Fig. 20A and Fig. 20B each show an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view.

[0008] The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments in which the invention can be practiced.

[0009] The word "exemplary" is used here to mean "serving as an example, instance, or representation." Any embodiment or design described herein as "exemplary" should not necessarily be interpreted as preferred or advantageous over other embodiments or designs.

[0010] The word "over," used here in reference to an applied material formed "over" a side or surface, can be used to mean that the applied material may be formed "directly on," e.g., in direct contact with, the implied side or surface. The word "over," used here in reference to an applied material formed "over" a side or surface, can also be used to mean that the applied material is formed "indirectly on" the implied side or surface with one or more additional layers arranged between the implied side or surface and the applied material.

[0011] The term "lateral," used here in reference to the "lateral" extent of a structure (or substrate, wafer, or support) or "laterally beside," may be used to mean an extent or positional relationship along a surface of a substrate, wafer, or support. This means that a surface of a substrate (e.g., a surface of a support or a surface of a wafer) may serve as a reference, usually referred to as the primary processing surface of the substrate (or the primary processing surface of the support or wafer). Furthermore, the term "width," used here in reference to a "width" of a structure (or structural element), may be used to mean the lateral extent of a structure.Furthermore, the term "height," used here in relation to the height of a structure (or structural element), can be understood to mean an extent of the structure along a direction perpendicular to the surface of the substrate (e.g., perpendicular to the main working surface of a substrate). The term "thickness," used here in relation to the "thickness" of a layer, can be understood to mean the spatial extent of the layer perpendicular to the surface of the substrate (material) on which the layer is applied. If the surface of the substrate is parallel to the surface of the substrate (e.g., the main working surface), the "thickness" of the layer applied to the substrate can be the same as the height of the layer. Furthermore, a "vertical" structure can be defined as a structure that extends in a direction perpendicular to the lateral direction (e.g.,a “vertical” extension extends perpendicular to the main processing surface of a substrate), and a “vertical” extension can be defined as an extension along a direction perpendicular to the lateral direction (e.g., an extension perpendicular to the main processing surface of a substrate).

[0012] The phrase "at least one of" in relation to a group of elements can be used here to mean at least one element from the group consisting of those elements. For example, the phrase "at least one of" in relation to a group of elements can be used here to mean a selection from: one of the listed elements, several of one of the listed elements, several of individual listed elements, or several of several listed elements.

[0013] According to various embodiments, pitting corrosion (e.g., copper pitting) can be reduced. Intuitively, the stoichiometric inhomogeneities that lead to localized contact corrosion can be reduced. Therefore, the number of grain boundaries (also called crystallographic interfaces) can be increased to hinder stoichiometric depletion through migration (e.g., diffusion) of constituents. Alternatively or additionally, the spatially averaged grain size (also called crystallite size) can be reduced to minimize overall stoichiometric variation. Intuitively, the migration (e.g., diffusion) of constituents within a grain (also called a crystallite) can occur in such a way that stoichiometric variations can be reduced to the spatial scale of the grain size. This can reduce or prevent grain boundary depletion.In other words, contact corrosion (on the spatial scale of stoichiometric inhomogeneities) can be reduced by refining the microstructure.

[0014] According to various embodiments, pitting corrosion (e.g., copper pitting) at a contact point can be reduced by modifying the inherent grain size using a structured substrate. The substrate can be placed beneath the contact point. For example, the segregation suppression structure can contain or be formed from the substrate.

[0015] According to various embodiments, a diode (e.g., a Schottky diode) can be provided. After implantation and formation of an ohmic contact (e.g., a nickel-aluminum contact) on the front face of the diode, the substrate can be formed over the ohmic contact. The substrate (e.g., a substrate layer) can be structured using a mask to form the segregation suppression structure. The mask can contain or be formed from a resin mask. Structuring the substrate can involve the use of dry etching (e.g., plasma etching). The dry etching can provide a way to stop the etching within the substrate (e.g., to prevent etching through the substrate). After removing the mask, a metallization can be arranged over the segregation suppression structure. For example, the metallization can contain or be formed from an aluminum-copper alloy.The metallization can be patterned using a mask to form at least one contact point. Patterning the metallization can involve the use of wet processes (e.g., using a liquid etchant). After patterning the metallization, the remaining substrate (e.g., exposed by patterning the metallization) can optionally be removed using the same mask as used for patterning the metallization or a different mask. Furthermore, at least one passivation layer can be applied over the metallization (e.g., over the at least one contact point). Afterward, the back side of the diode can be processed (which includes, for example, thinning and / or forming a back-side metallization).

[0016] According to various embodiments, the formation of the segregation suppression structure can be provided within a front-end process. Machining the back side of the diode can be the final step of the front-end process. Other electronic components can be machined analogously.

[0017] According to various embodiments, a semiconductor device can contain one or more integrated circuit structures (also referred to as integrated electronic components, semiconductor chips, ICs, chips, or microchips) that are formed during the fabrication of the semiconductor device. An integrated circuit structure can be fabricated at least partially on or within a substrate in corresponding areas of the substrate (also referred to as active chip areas) using various semiconductor fabrication technologies. An integrated circuit structure can contain one or more (e.g., multiple) semiconductor circuit elements (also referred to as integrated electronic elements), which may include, for example, at least one diode, transistor, resistor, or capacitor that is electrically interconnected and configured to perform operations, such as at least one computational operation or switching operation.in power electronics), rectifier operations, or memory operations, e.g., in the fully machined integrated circuit structure. In the further fabrication of the semiconductor device, multiple semiconductor devices can be separated from the substrate (also called a wafer or carrier) by wafer sawing after semiconductor device machining to provide multiple individual semiconductor devices (also called semiconductor chips). Furthermore, a final stage of semiconductor device fabrication can involve packaging (also called assembling, encapsulating, or sealing) individual semiconductor devices, whereby an individual semiconductor device may be encased, e.g., in a support material (also called casting material or encapsulation material), to prevent physical damage and / or corrosion of the semiconductor device.The support material encases the semiconductor device (forming, figuratively, a package or shape) and can optionally accommodate the electrical contacts and / or a conductor to connect the semiconductor device to a peripheral device, e.g., a printed circuit board.

[0018] According to various embodiments, different types of materials can be processed during the manufacture of the electronic component to form at least one of the following: an integrated circuit structure, a semiconductor circuit element, a contact point, an electrical interconnection, which may be, among others, electrically insulating materials, electrically semiconducting materials (also referred to as semiconductor material) or electrically conductive materials (also referred to as electrically conductive materials).

[0019] According to various embodiments, a substrate and / or a semiconductor region can contain or be formed from a semiconductor material of various types, including a group IV semiconductor (e.g., silicon or germanium), a composite semiconductor, e.g., a group III-V composite semiconductor (e.g., gallium arsenide), or other types, including, for example, group III semiconductors, group V semiconductors, or polymers. In one embodiment, the substrate and / or the semiconductor region is made of silicon (doped or undoped); in an alternative embodiment, the substrate and / or the semiconductor region is a silicon-on-insulator (SOI) wafer. Alternatively, any other suitable semiconductor material can be used for the substrate and / or the semiconductor region, for example, a semiconductor composite such as...Gallium phosphide (GaP), indium phosphide (InP), silicon carbide (SiC) or gallium nitride (GaN), but also any suitable ternary semiconductor composite material or quaternary semiconductor composite material such as indium gallium arsenide (InGaAs).

[0020] According to various embodiments, a metallic material can contain or be formed from at least one chemical element from the following group of chemical elements (also referred to as metals): tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), magnesium (Mg), chromium (Cr), iron (Fe), zinc (Zn), tin (Sn), gold (Au), silver (Ag), iridium (Ir), platinum (Pt), indium (In), cadmium (Cd), bismuth (Bi), vanadium (V), titanium (Ti), palladium (Pd), or zirconium (Zr); or it can contain or be formed from a metal alloy containing at least one chemical element from this group. For example, a metal alloy can contain or be formed from at least two metals (e.g., two or more than two metals, such as in the case of an intermetallic compound) or at least one metal (e.g., one or more than one metal) and at least one other chemical element (e.g., a nonmetal or a metalloid).For example, a metal alloy can contain or be formed from at least one metal and at least one nonmetal (e.g., carbon (C) or nitrogen (N)), such as a carbide or a nitride in the case of steel. Alternatively, a metal alloy can contain or be formed from more than one metal (e.g., two or more metals), such as various compositions of gold with aluminum, various compositions of copper with aluminum (e.g., aluminum bronze), various compositions of copper and zinc (e.g., brass), or various compositions of copper and tin (e.g., bronze), which may contain, for example, various intermetallic compounds. According to various embodiments, a metallic material can be electrically conductive.

[0021] A semiconductor material, layer, region, or the like can be understood as having moderate electrical conductivity (also referred to as semiconducting), e.g., an electrical conductivity (measured at room temperature and constant electric field direction, e.g., constant electric field) in the range of about 10 -6 Siemens per meter (S / m) up to about 10 6 S / m.

[0022] According to various embodiments, an electrically conductive material, layer, region, or the like may contain or be composed of a metallic material (e.g., a metal or metal alloy), a silicide (e.g., titanium silicide, molybdenum silicide, tantalum silicide, or tungsten silicide), a conductive polymer, a polycrystalline semiconductor (e.g., polycrystalline silicon, also known as polysilicon), or a highly doped semiconductor (e.g., highly doped silicon). An electrically conductive material (e.g., a metallic material), layer, region, or the like may be understood to have high electrical conductivity (also referred to as electrically conductive), e.g., an electrical conductivity (measured at room temperature and constant electric field direction, e.g., a constant electric field) greater than approximately 10 6 S / m, e.g. larger than about 10 7 S / m.

[0023] An electrically insulating material, layer, area, or the like can be understood as having a low electrical conductivity (also referred to as electrically insulating), e.g., an electrical conductivity (measured at room temperature and constant electric field direction, e.g., constant electric field) of less than about 10 -6 S / m, e.g. smaller than about 10 -10 S / m.

[0024] Depending on the specific design, a transistor can be one of several types, including, for example, a bipolar junction transistor (BJT), a heterojunction BJP, a Schottky BJP, an insulated-gate BJP (also known as an IGBT), a field-effect transistor (FET), a junction field-effect transistor (JFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a dual-gate MOSFET, a fast-reversing or fast-recovering epitaxial diode FET, an insulated-gate heterostructure FET, a modulation-doped FET, a tunnel FET, or an insulated-gate bipolar transistor (IGBT). Depending on the specific semiconductor technology used to manufacture a transistor, different materials are processed to form the corresponding layers.For example, a transistor can be manufactured using complementary metal oxide semiconductor technology (CMOS technology) and / or double diffusion metal oxide semiconductor technology (DMOS technology).

[0025] Segregation (also known as chemical segregation) can be understood as the enrichment of one constituent of a mixture (e.g., a self-segregating mixture) at a surface, such as a free surface or an internal surface (e.g., a crystallographic interface) of the mixture (and the corresponding depletion of another constituent of the mixture at the surface). The constituent can migrate (e.g., diffuse) from a central region of the mixture or crystal to the surface of the mixture (e.g., a crystallographic interface). Migration can be activated by temperature, e.g., above room temperature, at or above a segregation temperature. Alternatively or additionally, migration can be activated during the adsorption of the mixture (e.g., during the growth of a layer or structure that the mixture possesses), e.g., by adsorption dynamics.

[0026] The structure of the segregation suppression structure can be used to influence the grain size of the self-segregating mixture (e.g., AlCu), thereby reducing mixture segregation. For example, the segregation suppression structure can contain or be composed of titanium.

[0027] The self-segregating mixture can contain at least one self-segregating alloying element (also referred to as at least one alloying element), e.g., the second metal, which is arranged in a base material, e.g., the first metal (e.g., mixed with it). The self-segregating mixture can be a metastable mixture, e.g., above an equilibrium solubility and / or within a miscibility gap. For example, the self-segregating alloying element can be soluble in the base material up to the equilibrium solubility, whereby the self-segregating mixture can contain a concentration of the at least one self-segregating alloying element greater than the equilibrium solubility (at a specific temperature). The self-segregating mixture can contain more base material than alloying element (in other words, a higher concentration of the base material than of the at least one alloying element) or be formed from it.

[0028] For example, the base material can contain or be composed of copper (Cu). Alternatively, the base material can contain or be composed of aluminum (Al). Optionally, the self-segregating mixture (e.g., its base material) can also contain at least one non-metal, e.g., silicon (Si). For example, the self-segregating mixture can contain or be composed of AlCu or AlCuSi.

[0029] For example, it can contain or be formed from at least one self-segregating alloying element, copper. Alternatively or additionally, it can contain or be formed from at least one self-segregating alloying element, aluminum.

[0030] The alloying element and the base material can differ from each other in at least one of the following: crystal structure (e.g., in the range from approximately room temperature to approximately the segregation temperature, e.g., up to approximately 400 °C), an atomic radius of more than approximately 15% (e.g., more than approximately 20%, 30%, or 40%), or an electronegativity of more than approximately 15% (e.g., more than approximately 20%, 30%, or 40%). Alternatively or additionally, the self-segregating mixture can contain at least one of the following: more than one phase, a eutectic, an intermetallic phase (e.g., CuAl₂), or a miscibility gap.

[0031] Fig. Figure 1 presents a method 100 according to various embodiments in a schematic flowchart. The method 100 can be configured for processing an electronic component that contains at least one electrically conductive contact area.

[0032] The method can include forming a contact point containing or formed from a self-segregating mixture. The contact point can be formed over at least one electrically conductive contact area to electrically contact the electronic component.

[0033] The method can further include forming a segregation suppression structure between the contact point and the electronic component. The segregation suppression structure can contain or be formed from more nucleation-inducing topographic features (e.g., a higher areal density of nucleation-inducing topographic features) than the at least one electrically conductive contact area. The nucleation-inducing topographic features can be configured to disrupt chemical segregation of the self-segregating mixture. The chemical segregation of the self-segregating mixture can be disrupted by crystallographic interfaces of the contact point defined by the nucleation-inducing topographic features. For example, the segregation suppression structure can contain or be formed from a segregation suppression layer (e.g., from a substrate), e.g., by structuring.

[0034] In other words, chemical segregation of the self-segregating mixture can be spatially limited to a crystallite size at the contact point. The crystallite size at the contact point can be defined by the areal density of the nucleation-inducing topographic features.

[0035] The method can optionally include 105 images of a passivation layer over the electronic component. The passivation layer can contain at least one opening that exposes the contact point.

[0036] The method can optionally include forming a metallization on one side of the electronic component (also referred to as the second side of the electronic component) opposite the contact point (located on the first side of the electronic component). The metallization can electrically contact the electronic component or provide an electrical contact for the electronic component.

[0037] According to various embodiments, each nucleation-inducing topographic feature of the segregation-suppression structure can be configured to induce crystallite nucleation. The crystallite nucleation induced therein can be configured such that at least one crystallographic interface is formed at the contact point. For example, each crystallographic interface can be formed between adjacent nucleation-inducing topographic features of the segregation-suppression structure. The crystallographic interface can be configured to disrupt segregation at the contact point through the crystallographic interface.

[0038] The method can optionally include 109 arranging at least one nucleation-inducing topographic feature of the segregation suppression structure between two electrically conductive contact areas from the at least one electrically conductive contact area. In other words, at least one nucleation-inducing topographic feature of the segregation suppression structure can be arranged between two electrically conductive contact areas from the at least one electrically conductive contact area. The at least one nucleation-inducing topographic feature of the segregation suppression structure can be arranged between the at least one electrically conductive contact area and the contact point.

[0039] Alternatively or additionally, the method can optionally include in 109 arranging at least one nucleation-inducing topography feature of the segregation suppression structure over an electrically conductive contact area from the at least one electrically conductive contact area.

[0040] According to various embodiments, forming the contact point can include forming a metallization and structuring the metallization. Structuring the metallization can include at least partial exposure of the segregation suppression structure.

[0041] Fig. 2 presents a method 200 according to various embodiments in a schematic flowchart.

[0042] Method 200 can be configured to process an electronic component that contains at least one electrically conductive contact area.

[0043] The method can include forming a metallization containing a self-segregating mixture. The metallization can be formed over at least one electrically conductive contact area to electrically contact the electronic component.

[0044] The method can further include 203 images of a segregation suppression structure between the metallization and the electronic component.

[0045] The segregation suppression structure can contain or be formed from more nucleation-inducing topographic features (e.g., a higher areal density of nucleation-inducing topographic features) than the at least one electrically conductive contact region. The nucleation-inducing topographic features can be configured to disrupt chemical segregation of the self-segregating mixture. The chemical segregation of the self-segregating mixture can be disrupted by crystallographic interfaces of the metallization defined by the nucleation-inducing topographic features. In other words, chemical segregation of the self-segregating mixture can be spatially confined to a crystallite size of the metallization. The crystallite size of the metallization can be defined by the areal density of the nucleation-inducing topographic features.

[0046] The process can optionally include forming a passivation layer over the electronic component. The passivation layer can contain at least one opening that exposes the metallization.

[0047] The method can optionally include forming a metallization on one side of the electronic component (also referred to as the second side of the electronic component) opposite the metallization (which is located on a first side of the electronic component). The metallization can electrically contact the electronic component or provide an electrical contact for the electronic component.

[0048] According to various embodiments, each nucleation-inducing topographic feature of the segregation-suppression structure can be configured to induce crystallite nucleation. The crystallite nucleation induced therein can be configured to form a crystallographic interface in the metallization. The crystallographic interface can be formed between adjacent nucleation-inducing topographic features of the segregation-suppression structure. The crystallographic interface can be configured to disrupt segregation of the metallization through the crystallographic interface.

[0049] The method can optionally include, in 209, the arrangement of at least one nucleation-inducing topographic feature of the segregation suppression structure between two electrically conductive contact areas from the at least one electrically conductive contact area. In other words, at least one nucleation-inducing topographic feature of the segregation suppression structure can be arranged between two electrically conductive contact areas from the at least one electrically conductive contact area. The at least one nucleation-inducing topographic feature of the segregation suppression structure can be arranged between the at least one electrically conductive contact area and the metallization.

[0050] Alternatively or additionally, the method can optionally include in 109 arranging at least one nucleation-inducing topography feature of the segregation suppression structure over an electrically conductive contact area from the at least one electrically conductive contact area.

[0051] Optionally, the process can include structuring the metallization to form at least one contact point. Structuring the metallization can include at least partial exposure of the segregation suppression structure.

[0052] Fig. Figure 3 presents a method 300 according to various embodiments in a schematic flowchart. The method 300 can be configured for processing an electronic component that contains at least one electrically conductive contact area.

[0053] The method can include forming a metallization in 301 that contains an aluminum bronze. The aluminum bronze can contain or be formed from aluminum and copper (e.g., an aluminum-copper alloy). The metallization can be formed over the at least one electrically conductive contact area to electrically contact the electronic component.

[0054] The method can further include 303 images of a segregation suppression structure between the metallization and the electronic component.

[0055] The segregation suppression structure can contain or be formed from more protrusions (e.g., a higher areal density of protrusions) than the at least one electrically conductive contact region. The protrusions (also called nucleation-inducing protrusions) can be configured to disrupt chemical segregation of the aluminum bronze. The chemical segregation of the aluminum bronze can be disrupted by crystallographic interfaces of the metallization induced by the protrusions. In other words, chemical segregation of the aluminum bronze can be spatially confined to a crystallite size of the metallization. The crystallite size of the metallization can be defined by the areal density of the protrusions.

[0056] The process can optionally include forming a passivation layer over the electronic component. The passivation layer can contain at least one opening that exposes the metallization.

[0057] The method can optionally include forming a metallization on one side of the electronic component (also referred to as the second side of the electronic component) opposite the metallization (which is located on a first side of the electronic component). The metallization can electrically contact the electronic component or provide an electrical contact for the electronic component.

[0058] According to various embodiments, each projection of the segregation suppression structure can be configured to induce crystallite nucleation. The induced crystallite nucleation can be configured to form a crystallographic interface in the metallization. The crystallographic interface can be formed between adjacent projections of the segregation suppression structure. The crystallographic interface can be configured to disrupt segregation of the metallization through the crystallographic interface.

[0059] The method can optionally include in 309 the application of at least one projection of the segregation suppression structure between two electrically conductive contact areas from the at least one electrically conductive contact area. In other words, at least one projection of the segregation suppression structure can be arranged between two electrically conductive contact areas from the at least one electrically conductive contact area. The at least one projection of the segregation suppression structure can be arranged between the at least one electrically conductive contact area and the metallization.

[0060] Alternatively or additionally, the method can optionally include in 109 arranging at least one projection of the segregation suppression structure over an electrically conductive contact area from the at least one electrically conductive contact area.

[0061] Optionally, the process can structure the metallization to form at least one contact point (in other words, one or more contact points). Structuring the metallization can include at least partial exposure of the segregation suppression structure.

[0062] Fig. 4A to 4D each represent an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0063] The electronic component 400a can contain at least one electrically conductive contact area 402. According to various embodiments, the electrically conductive contact area can contain a metal, e.g., nickel and / or aluminum, e.g., an alloy thereof. Alternatively or additionally, the electrically conductive contact area 402 can contain at least one doped semiconductor area (also referred to as a doped region), e.g., embedded in a less doped semiconductor region.

[0064] The electronic component can include a segregation suppression structure 404 in 400b. The segregation suppression structure 404 can be formed over the electrically conductive contact area 402.

[0065] The segregation suppression structure 404 can contain or be formed from at least one nucleation-inducing topographic feature 404f (also referred to as topographic feature 404f). Each nucleation-inducing topographic feature 404f of the segregation suppression structure 404 can contain or be formed from at least one type of the following nucleation-inducing topographic features 404p: a recess; a projection; an edge.

[0066] The segregation suppression structure 404 can contain or be formed from more nucleation-inducing topographic features 404p than the at least one electrically conductive contact area 402 (e.g., with respect to one type of nucleation-inducing topographic feature 404p). For example, the segregation suppression structure 404 can contain or be formed from more recesses than the at least one electrically conductive contact area 402. Alternatively or additionally, the segregation suppression structure 404 can contain or be formed from more projections than the at least one electrically conductive contact area 402. For example, at least one projection and each depression can contain at least one edge, so that the segregation suppression structure 404 can contain or be formed from more edges than the at least one electrically conductive contact area 402.

[0067] The electronic component in 400c can contain a metallization 406 (also referred to as a metallization layer) formed over the at least one electrically conductive contact area 402 to electrically contact the electronic component. For example, the metallization 406 can contain or be formed from a power metallization 406. The metallization 406 can contain or be formed from a self-segregating mixture. Physical vapor deposition (e.g., sputtering) can be used to form the metallization 406.

[0068] The self-segregating mixture can contain or be formed from a base material and an alloying element (self-segregating alloying element). The alloying element can contain or be formed from a first metal. Alternatively or additionally, the alloying element can contain or be formed from a second metal, e.g., a different metal than the first. The self-segregating mixture can contain at least two metals, e.g., an alloy containing at least two metals, the first metal and the second metal. For example, the at least two metals can contain or be formed from at least one of a semi-precious metal (e.g., copper) and one of a base metal (e.g., aluminum). The self-segregating mixture (also called a noble-base mixture) can be arranged stoichiometrically (e.g., in a homogeneous ratio of the first metal and the second metal), e.g., spatially homogeneously.

[0069] According to various embodiments, the at least two metals (e.g., the first metal and the second metal) can differ in the sign (positive or negative) of their standard potential. In other words, the first metal can be a noble metal (corresponding to a positive standard potential), and the second metal can be a base metal (corresponding to a negative standard potential), or vice versa. For example, the first metal can be one of the following group of noble metals: gold, platinum, iridium, palladium, osmium, silver, mercury, rhodium, copper, and / or bismuth. Alternatively or additionally, the second metal can be one of the following group of base metals: aluminum, zinc, tin, gallium, germanium, iron, cobalt, chromium, nickel, indium, titanium, tungsten, and / or magnesium.

[0070] According to various interpretations, the standard potential of a chemical element (such as a metal) can be understood in accordance with the galvanic series (also known as the electropotential series). The standard potential can be defined as the electrical potential difference between an electrode made of the chemical element and a reference electrode, for example, in a standard galvanic cell under normal conditions, such as standard temperature and pressure (298.15 K and 100 kilopascals). The standard galvanic cell can contain the electrode and the reference electrode (e.g., a hydrogen electrode). In other words, the standard potential is specified with respect to a reference potential (e.g., provided by the reference electrode, such as the hydrogen potential), which can be zero. Electricity is generated in the galvanic cell due to the electrical potential difference between the two electrodes.This potential difference is generated as a result of the difference between the individual potentials of the two electrodes with respect to the electrolyte of the galvanic cell. In the normal state of the galvanic cell, the electrolyte can have a pH of approximately 0 and an ion activity of approximately 1. The standard potential can also be referred to as the reduction standard potential.

[0071] Alternatively or additionally, the at least two metals (e.g., the first metal and the second metal) can differ from each other in their electronegativity (e.g., according to the Pauling scale), e.g., by more than or equal to about 0.1, e.g., by more than or equal to about 0.2, preferably by more than or equal to about 0.3, e.g., by more than or equal to about 0.4, e.g., by more than or equal to about 0.5, e.g., by more than or equal to about 0.6. For example, the first metal can have an electronegativity of more than or equal to about 1.8, e.g., more than or equal to about 1.9. Alternatively or additionally, the second metal can have an electronegativity of less than or equal to about 1.7, e.g., less than or equal to about 1.61.

[0072] During the formation of the metallization 406, several crystallites 406c can be formed (also referred to as nucleation). For example, crystallite nucleation can be enhanced (e.g., induced) by the nucleation-inducing topographic features 404f of the segregation suppression structure 404, e.g., in the recesses of the segregation suppression structure 404. Each nucleation-inducing topographic feature 404f of the segregation suppression structure 404 can be configured to index crystallite nucleation.

[0073] The density (e.g., areal density) of the nucleation-inducing topographic features 404f of the segregation-suppression structure 404 can define a density (e.g., an areal density) of crystallites 406c of the metallization 406. During growth, the adjacent crystallites 406c can abut each other by forming a crystallographic interface 406i of the metallization 406, as schematically illustrated in 400d. In other words, each nucleation-inducing topographic feature 404f of the segregation-suppression structure 404 can be configured to induce at least one crystallographic interface 406i of the metallization 406. The density (e.g. areal density) of the nucleation-inducing topography features 404f of the segregation-suppression structure 404 can define a density (e.g. an areal density) of crystallographic interfaces 406i of the metallization 406.The spacing of the crystallographic interfaces 406i of the metallization 406 can decrease with a higher surface density (number per surface) of the crystallographic interfaces 406i of the metallization 406. The crystallite size of the metallization 406 (in other words, the spacing of the crystallographic interfaces 406i) can be defined by the density of the nucleation-inducing topographic features 404f.

[0074] Each crystallographic interface 406i can be formed over each nucleation-inducing topographic feature and / or between adjacent nucleation-inducing topographic features 404f of the segregation-suppression structure 404. The crystallographic interfaces 406i of the metallization 406 can be configured to disrupt chemical segregation of the self-segregating mixture. In other words, the chemical segregation of the self-segregating mixture can be halted at the crystallographic interfaces 406i of the metallization 406.

[0075] According to various embodiments, the thickness 406t of the metallization 406 can be greater than the thickness 404t of the segregation suppression structure 404, e.g. greater than about ten times the thickness 404t of the segregation suppression structure 404, e.g. greater than about twenty times the thickness 404t of the segregation suppression structure 404, e.g. greater than about thirty times the thickness 404t of the segregation suppression structure 404, e.g. greater than about fifty times the thickness 404t of the segregation suppression structure 404, e.g. greater than about one hundred times the thickness 404t of the segregation suppression structure 404.

[0076] The crystallites 406c of the metallization 406 can grow in a columnar fashion. For example, the extent of each crystallite 406c of the metallization 406 in a direction perpendicular to a macroscopic surface plane 404p of the at least one electrically conductive contact region 402 can be greater than the distance between two other crystallites 406c of the metallization 406 that are adjacent to the crystallites 406c of the metallization 406. Alternatively or additionally, the extent of each crystallite 406c of the metallization 406 in a direction perpendicular to the macroscopic surface plane 404p can be greater than the extent of the crystallite 406c of the metallization 406 parallel to the macroscopic surface plane 404p. A macroscopic surface normal 404n of the electrically conductive contact area 402 can be perpendicular to the macroscopic surface plane 404p of the electrically conductive contact area 402.The macroscopic surface plane 404p can be arranged and oriented such that it contains a maximum number of points (or a corresponding maximum overlap with) a surface 402s of the electrically conductive contact area 402 above which the segregation suppression structure 404 is arranged.

[0077] Fig. Figure 5A represents a metallization 406 in a process according to various embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0078] The metallization 406 can contain or be formed from several crystallites 406c. Adjacent crystallites from the multiple crystallites 406c can border each other in a crystallographic interface 406i.

[0079] According to various embodiments, the metallization 406 can contain or be formed from at least one contact point. For example, the metallization 406 (e.g., the at least one contact point) can be configured to be contacted by bonding and / or soldering.

[0080] Fig. Figure 5B represents a metallization 406 in a process according to various embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0081] In a further process step, the metallized 406 can be heated. For example, the further process step can include or consist of at least one of the following: soldering, bonding, plasma cleaning, packaging, etc.

[0082] In a further process step, segregation of the metallization 406 (e.g., of its self-segregating mixture) can be activated, for example, by heating. Segregation of the metallization 406 (e.g., of its self-segregating mixture) can increase the concentration of the alloying element near the crystallographic interface 406i. For example, during segregation, the alloying element of the self-segregating mixture can migrate (e.g., diffuse) to the crystallographic interfaces 406i of the metallization 406. The alloying element can accumulate at the crystallographic interfaces 406i of the metallization 406. Due to the equilibrium established at the crystallographic interfaces 406i, the alloying element cannot pass through them. Therefore, chemical segregation of the self-segregating mixture (e.g.,the variations in its composition) are spatially limited to a crystallite size of metallization 406.

[0083] Activating segregation can involve activating the migration 401 of the alloying element to the crystallographic interface 406i. Through segregation of the metallization 406 (e.g., its self-segregating mixture), a first region 406a can be formed near the crystallographic interface 406i and a second region 406b away from the crystallographic interface 406i. For example, in each crystallite from the multiple crystallites 406c, at least one first region 406a and at least one second region 406b can be formed. The at least one first region 406a can at least partially surround the at least one second region 406b. Alternatively or additionally, the at least one first region 406a can be located between the at least one second region 406b and the crystallographic interface 406i.

[0084] Activating segregation can involve reducing the concentration (e.g., spatially averaged) of the alloying element in the second region 406b (e.g., in other words, depleting the alloying element in the second region 406b). Alternatively or additionally, activating segregation can involve enriching the alloying element in the first region 406a. In other words, the second region 406b can be a depletion region 406b for the alloying element. Alternatively or additionally, the first region 406a can be a depletion region 406b for the base material.

[0085] Activation of segregation can involve or result from heating the metallization 406 above the segregation temperature. Above the segregation temperature, the equilibrium solubility of the alloying element in the base material may be exceeded and / or the alloying element may enter a miscibility gap with the base material.

[0086] During and / or after segregation, the concentration of the alloying element in the at least one first region 406a may be greater than in the at least one second region 406b. The crystallographic interface 406i may be configured to reduce or prevent segregation of the metallization 406 through the crystallographic interface 406i.

[0087] Fig. Figure 5C presents a schematic diagram 500 in a method according to various embodiments.

[0088] In the schematic diagram 500, a concentration 503 (e.g., an atomic concentration) is shown across a vertical position 505 in the metallization 406 (e.g., along a macroscopic surface normal 404n of the electrically conductive contact region 402). The line 553 represents the spatially distributed concentration of the alloying element before the activation of segregation. The spatially distributed concentration 553 of the alloying element before the activation of segregation can be equal to a spatially averaged concentration 553 of the alloying element in the metallization layer 406. In other words, the spatial concentration 553 of the alloying element can be homogeneously distributed before the activation of segregation.

[0089] Line 551 represents a spatially distributed concentration of the alloying element during and / or after activation of the segregation. The concentration 503 of the alloying element in the first region 406a may be greater than the concentration 503 of the alloying element in the second region 406b. Alternatively or additionally, the concentration 503 of the alloying element in the first region 406a may be greater than the spatially averaged concentration 553 of the alloying element in the metallization layer 406.

[0090] A concentration (first concentration, e.g., spatially averaged) of the alloying element in the second region 406b (e.g., in the self-segregating mixture) before activation of the segregation may be higher than a concentration (second concentration, e.g., spatially averaged) of the alloying element in the second region 406b (e.g., in the self-segregating mixture) after activation of the segregation. Alternatively or additionally, the first concentration and / or the second concentration may be lower than a concentration (third concentration, e.g., spatially averaged) of the alloying element in the first region 406a after activation of the segregation.

[0091] The first concentration (e.g., spatially averaged) can be in the range of about 0.5 atomic percent (At%) to about 50 At%, e.g., in the range of about 1 At% to about 40 At%, e.g., in the range of about 2 At% to about 30 At%, e.g., in the range of about 5 At% to about 25 At%, e.g., in the range of about 5 At% to about 20 At%, e.g., about 10 At%.

[0092] Alternatively or additionally, the amount of the self-segregating mixture in the metallization layer 406 can be greater than approximately 70 at.%, e.g., greater than approximately 80 at.%, e.g., greater than approximately 90 at.%, e.g., greater than approximately 95 at.%, e.g., greater than approximately 99 at.%, e.g., approximately 100 at.%. In other words, the metallization layer 406 can be formed essentially from the self-segregating mixture.

[0093] The second concentration (e.g., spatially averaged) can be less than about 50 at%, e.g., less than about 40 at%, e.g., less than about 30 at%, e.g., less than about 20 at%, e.g., less than about 10 at%, e.g., less than about 5 at%, e.g., less than about 2 at%, e.g., less than about 0.5 at%, e.g., less than about 0.1 at%.

[0094] The third concentration (e.g., spatially averaged) can be greater than approximately 50 at.%, e.g., greater than approximately 60 at.%, e.g., greater than approximately 70 at.%, e.g., greater than approximately 80 at.%, e.g., greater than approximately 90 at.%, e.g., greater than approximately 95 at.%, e.g., greater than approximately 99 at.%, e.g., approximately 100 at.%. In other words, the first region 406a can be formed essentially from the alloying element after activation of the segregation.

[0095] Alternatively or additionally, the first region 406a can be formed essentially from a compound (also called an intermetallic phase) containing the alloying element and the base element. For example, the first region 406a can contain or be formed from a binary metal compound of the self-segregating mixture, e.g., CuAl2.

[0096] The alloying element may contain or be composed of at least one of the following: manganese, tantalum, chromium, tungsten, copper, and / or molybdenum. For example, the alloying element could be copper. Alternatively, the base material may contain or be composed of at least one of aluminum, silicon, and nickel.

[0097] According to various embodiments, activating the segregation can include forming a concentration gradient of the alloying element in each crystallite 406c of the metallization 406, pointing towards the crystallographic interface 406i.

[0098] According to various embodiments, the alloying element and / or the self-segregating mixture can be configured such that segregation of the alloying element from the metallization 406 (e.g., from the base material) begins at a lower temperature than a reaction of the metallization 406 (e.g., of the base material) with the at least one electrically conductive region 402, e.g., with a material (e.g., a metal and / or a semiconductor) of the at least one electrically conductive contact region 402. In other words, a temperature (also referred to as the segregation temperature) that activates segregation of the alloying element from the metallization 406 can be lower than a temperature (also referred to as the reaction temperature) that activates a reaction of the metallization 406 (e.g., of the base material) with the at least one electrically conductive contact region 402 (e.g., its material).

[0099] The segregation temperature can be lower than approximately 400 °C, e.g., lower than approximately 350 °C, e.g., lower than approximately 300 °C, e.g., lower than approximately 250 °C, e.g., lower than approximately 200 °C, e.g., lower than approximately 190 °C, e.g., lower than approximately 180 °C, e.g., lower than approximately 170 °C, e.g., lower than approximately 160 °C, e.g., lower than approximately 150 °C, or alternatively or additionally (and / or) higher than approximately room temperature, e.g., higher than approximately 100 °C.

[0100] According to various embodiments, the method can include heating the metallization 406 to a temperature higher than the segregation temperature in order to activate the segregation of the alloying element from the metallization 406 (e.g., from the base material).

[0101] The overall variation 511 of the concentration 551 of the alloying element in the metallization layer 406 (and the corresponding deviation 513 from the spatially averaged concentration 553 of the alloying element in the metallization layer 406) is smaller the smaller the grain size or the distance between the crystallographic interfaces. According to various embodiments, the deviation 513 from the spatially averaged concentration 553 of the alloying element in the metallization layer 406 (also referred to as the reference concentration 553) can be less than approximately 50 at.% of the reference concentration 553, e.g., less than approximately 40 at.% of the reference concentration 553, e.g., less than approximately 30 at.% of the reference concentration 553, e.g., less than approximately 20 at.% of the reference concentration 553, e.g., less than approximately 10 at.% of the reference concentration 553. B. less than about 5 at% of the reference concentration 553, e.g. less than about 2 at.-% of the reference concentration 553, e.g. less than about 0.5 at% of the reference concentration 553, e.g. less than about 0.1 at% of the reference concentration 553.

[0102] Fig. Figures 6A to 6D each represent a segregation suppression structure 404 in a method according to different embodiments in a schematic perspective view.

[0103] According to various embodiments, the segregation suppression structure 404 can include several nucleation-inducing topographic features 404f having different geometries. For example, the segregation suppression structure 404 can include a rough surface (e.g., formed by rough etching, e.g., using plasma etching). Alternatively or additionally, the segregation suppression structure 404 can include or be formed from at least one type selected from the following types of segregation suppression structures: a trench structure 1704r, a pyramid structure 1704p, a needle structure 1704n, and / or a hole structure 1704h.

[0104] The trench structure 1704r can contain or be formed from several projections 412p separated from one another by several recesses 412r. Each recess from the multiple recesses 412r can be in the form of a trench (or multiple trenches 412r). At least one from each projection from the multiple projections 412p and each recess from the multiple recesses 412r can provide a topographic feature. Each trench from the multiple trenches 412r can extend in a direction parallel to a macroscopic surface normal 404n of the electrically conductive contact area 402. The extent of the multiple trenches 412r in a direction parallel to the macroscopic surface normal 404n can be greater than the distance between them and / or their extent parallel to the macroscopic surface normal 404n. In other words, the ditches from the multiple ditches 412r can be elongated.Optionally, each projection from the multiple projections 412p can be conical. Alternatively or additionally, each projection from the multiple projections 412p can be faceted. The multiple grooves 412r can be formed using etching, ablation (e.g., by laser ablation), or sawing.

[0105] The pyramidal structure 1704p can contain or be formed from multiple pyramid-shaped projections, also referred to as multiple pyramids 412p. Each pyramid within the multiple pyramids 412p can be conical. Alternatively or additionally, each pyramid within the multiple pyramids 412p can be faceted. At least one pyramid from each set of multiple pyramids 412p, and each recess between them, can provide a topographic feature. The multiple pyramids 412p can be formed by anisotropic etching or ablation (e.g., by laser ablation).

[0106] The needle structure 1704n can contain or be formed from multiple needle-shaped projections 412p (multiple needles 412p) that are spaced apart from one another. For example, the needle structure 1704n can be formed by reactive ion etching. Each needle from the multiple needles 412p can extend in a direction perpendicular to the macroscopic surface normal 404n. The extent of the needles from the multiple needles 412p can be greater than a distance between them and / or their extent parallel to the macroscopic surface normal 404n. In other words, the needles from the multiple needles 412p can be elongated. Optionally, each needle from the multiple needles 412p can be conical. Alternatively or additionally, each needle from the multiple needles 412p can be faceted. At least one of each needle from the multiple needles 412p and each gap between them can provide a topographic feature.

[0107] The hole structure 1704h can contain or be formed from multiple recesses 412r in the form of holes, also referred to as multiple holes 412r. Each hole from the multiple holes 412r can extend into or through the segregation suppression structure 404, with the multiple holes 412r being separated from one another. The extent of the holes from the multiple holes 412r into the segregation suppression structure 404 can be greater than their extent parallel to the macroscopic surface normal 404n and / or their spacing from one another. Optionally, each hole from the multiple holes 412r can be conical. Alternatively or additionally, each hole from the multiple holes 412r can be faceted. Each hole from the multiple holes 412r can provide a topographic feature.

[0108] According to various embodiments, different types of the at least one nucleation-inducing topography feature 404f (in other words, one or more than one nucleation-inducing topography feature 404f) can be provided, for example, at least one of the following: an island, a line, and a hexagon. The more than one nucleation-inducing topography feature 404f can be arranged regularly, e.g., in a grid (which contains at least one nucleation-inducing topography feature 404f that is equidistant from all neighboring nucleation-inducing topography features 404f).

[0109] Optionally, each topographic feature can contain or be formed from an edge 602 and / or a peak 604.

[0110] Fig. 7A and Fig. Figure 7B each represents a segregation suppression structure 404 in a method according to various embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0111] According to various embodiments, the segregation suppression structure 404 can include a segregation suppression layer (e.g., a metallization) covering the electrically conductive contact area 402. The nucleation-inducing topographic features 404f (e.g., recesses 412r) can extend into the segregation suppression layer. Alternatively or additionally, the nucleation-inducing topographic features 404f can protrude from the segregation suppression layer, as shown in Fig. 7A is shown.

[0112] Alternatively or additionally, the segregation suppression structure 404 can include at least one recess 404r that partially exposes the electrically conductive contact area 402, as shown in Fig. Figure 7B shows that the nucleation-inducing topographic features 404f can extend through the segregation suppression layer and / or protrude from the at least one electrically conductive contact area 402, as shown in Fig. 7B is shown.

[0113] A thickness 404t of the segregation suppression structure 404 can be greater than or equal to a height 704t of each nucleation-inducing topography feature 404f (in other words, one or more than one of the nucleation-inducing topography features 404f). The height 704t of at least one nucleation-inducing topography feature 404f (e.g., to satisfy a nucleation-inducing height criterion) can be in the range of about 1 nanometer (nm) to about 100 nm, e.g., in the range of about 10 nm to about 50 nm. For example, the height 704t of the at least one nucleation-inducing topography feature 404f can be greater than about 25 nm, e.g., greater than about 50 nm, and / or less than about 100 nm. B. smaller than about 75 nm.

[0114] According to various embodiments, the thickness 404t of the segregation suppression structure 404 can be in the range of about 50 nm to about 500 micrometers (µm), e.g. greater than about 100 nm, e.g. greater than about 100 µm, and / or less than about 50 µm, e.g. in the range of about 10 µm to about 50 µm or less than about 10 µm.

[0115] Fig. 8A to 8C each represent an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0116] The electronic component 800a can contain or be formed from at least one semiconductor region 802, 804. The at least one semiconductor region 802, 804 can contain or be formed from a first semiconductor region 802 and optionally a second semiconductor region 804. The second semiconductor region 804 can optionally be formed by epitaxial growth on the first semiconductor region 802. The at least one semiconductor region 802, 804 can be doped, e.g., by a first doping type (e.g., n-type doped).

[0117] The first semiconductor region 802 may contain or be formed from a wafer (also referred to as a substrate). The first semiconductor region 802 may contain or be formed from a first semiconductor material, e.g., silicon and / or a silicon compound (e.g., silicon carbide). The thickness of the first semiconductor region 802 may be in the range of approximately 100 µm to approximately 500 µm, e.g., approximately 350 µm. The second semiconductor region 804 may contain or be formed from an epitaxial layer. The second semiconductor region 804 may contain or be formed from a second semiconductor material, e.g., the same as the first semiconductor material, e.g., silicon and / or a silicon compound (e.g., silicon carbide).

[0118] The first semiconductor region 802 or, if present, the second semiconductor region 804 may contain or be formed from an electrically conductive contact region 402 of the electronic component 800a.

[0119] The electronic component 800b can contain at least one further semiconductor region 806, 808. This at least one further semiconductor region 806, 808 can contain or be formed from a first further semiconductor region 806 and / or a second further semiconductor region 808. The at least one further semiconductor region 806, 808 can be doped, e.g., by a second type of doping (e.g., p-type doped). The second type of doping can be the opposite of the first type. The first further semiconductor region 806 can be less doped than the second further semiconductor region 808 (in other words, contain a lower doping concentration). As an example, the dopant of the second type of doping (also referred to as the second dopant) can contain or be formed from a metal, e.g., aluminum.

[0120] The at least one further semiconductor region 806, 808 can be formed by implanting (e.g., by ion implantation) a dopant of the second doping type into the first semiconductor region 802 or, if present, the second semiconductor region 804. Each further semiconductor region 806, 808 can contain or be formed from an electrically conductive contact region 402 of the electronic component 800a.

[0121] The electronic component 800c can contain at least one ohmic contact area 810. The at least one electrically conductive contact area 810 can have an ohmic property (e.g., an ohmic current-voltage property). The ohmic property can represent a linear correlation between the electric current and the electric voltage. The at least one ohmic contact area 810 can contain or be formed from a metal (e.g., aluminum), e.g., the same as the second dopant. Alternatively or additionally, the at least one ohmic contact area 810 can contain or be formed from a metal alloy containing at least two metals, e.g., nickel and aluminum.

[0122] Each ohmic contact area 810 can contain or be formed from an electrically conductive contact area 402 of the electronic component 800a. Each ohmic contact area 810 can be in electrical contact with the underlying semiconductor area 804, 802, 806, 808, e.g., the further semiconductor area 806, 808 and / or the at least one semiconductor area 804, 802. As an example, each ohmic contact area 810 can protrude from the underlying semiconductor area, e.g., the further semiconductor area 806, 808 and / or the semiconductor area 804, 802, 806, 808.

[0123] The material of the at least one ohmic contact region 810 can be alloyed at least partially (in other words, partially or completely) with the underlying semiconductor region 804, 802, 806, 808. For example, at least one metal of the ohmic contact region 810 can migrate (e.g., diffuse) into the underlying semiconductor region 804, 802, 806, 808, e.g., by thermal activation, to dope the underlying semiconductor region 804, 802, 806, 808.

[0124] For example, the electronic component 800b, 800c may contain or be formed from a Schottky diode.

[0125] Fig. Figures 9A to 9C each represent an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0126] The electronic component 900a can be similar to the electronic component 800a, wherein a segregation suppression structure 404 can be formed over the first semiconductor region 802 and, if present, over the second semiconductor region 804. The segregation suppression structure 404 can contain more nucleation-inducing topography features 404f than the underlying at least one semiconductor region 802, 804 (e.g., than the first semiconductor region 802 or, if present, than the second semiconductor region 804). For example, the segregation suppression structure 404 can contain more edges than the underlying semiconductor region 802, 804. Alternatively or additionally, the segregation suppression structure 404 can contain more notches than the underlying semiconductor region 802, 804. Alternatively or additionally, the segregation suppression structure 404 can contain more protrusions than the underlying semiconductor region 802, 804.

[0127] The electronic component 900b can be similar to the electronic component 800b, wherein a segregation suppression structure 404 can be formed over the at least one further semiconductor region 806, 808. The segregation suppression structure 404 can contain more nucleation-inducing topography features 404f than the underlying at least one further semiconductor region 806, 808 (e.g., than the first further semiconductor region 806 and / or, if present, than the second further semiconductor region 808). As an example, the segregation suppression structure 404 can contain more edges than the at least one further semiconductor region 806, 808. Alternatively or additionally, the segregation suppression structure 404 can contain more notches than the at least one further semiconductor region 806, 808. Alternatively or additionally, the segregation suppression structure 404 can contain more protrusions than at least one other semiconductor region 806, 808.

[0128] The electronic component 900c can be similar to the electronic component 800c, wherein a segregation suppression structure 404 can be formed over the at least one ohmic contact area 810. The segregation suppression structure 404 can contain more nucleation-inducing topographic features 404f than the underlying at least one ohmic contact area 810. For example, the segregation suppression structure 404 can contain more edges than the at least one ohmic contact area 810. Alternatively or additionally, the segregation suppression structure 404 can contain more recesses than the at least one ohmic contact area 810. Alternatively or additionally, the segregation suppression structure 404 can contain more protrusions than the at least one ohmic contact area 810.

[0129] Forming the segregation suppression structure 404 can involve forming a segregation suppression layer (which contains, for example, a metallic material, such as a metal or a metal alloy containing the metal). The segregation suppression layer can be provided by forming a substrate (which contains, for example, a Schottky metal or is formed from it).

[0130] The metal of the segregation suppression structure 404 can be different from the dopant of the underlying semiconductor region 802, 804, 806, 808. Alternatively or additionally, the metal of the segregation suppression structure 404 can be different from a metal of the underlying at least one ohmic contact region 810. For example, the metal layer can contain or be formed from titanium.

[0131] Forming the segregation suppression structure 404 can further include structuring the segregation suppression layer. By structuring the segregation suppression layer, at least one nucleation-inducing topographic feature 404f can be formed. As an example, the segregation suppression layer can be structured using photolithography and etching (e.g., wet etching and / or dry etching). Alternatively or additionally, another structuring method can be used, e.g., a lifting process, laser ablation, or the like. For example, dry etching can include or be formed from plasma etching.

[0132] For example, photolithography and the lift-off process can involve the formation of a mask layer. In this case, structuring the segregation suppression layer can further involve the removal of the mask layer. For example, in the lift-off process, the segregation suppression layer can be formed over the mask layer. In the case of photolithography, the mask layer can be formed over the segregation suppression layer. The mask layer can contain or be formed from a polymer, such as a resist, e.g., a photosensitive resist. Alternatively or additionally, the mask layer can contain or be formed from another polymer, e.g., an imide (e.g., a polyimide), a resin, an epoxy resin, or a casting compound.

[0133] For example, the electronic component 900a, 900b, 900c may contain or be formed from a Schottky diode. In this case, the segregation suppression structure 404 may contain or be formed from a Schottky contact layer.

[0134] Fig. 10A to 10C each represent an electronic component in a method according to various embodiments in a schematic cross-sectional view or side view (e.g., along a macroscopic surface normal 404n of the electrically conductive contact area 402). Electronic component 1000a can be similar to electronic component 900a. Electronic component 1000b can be similar to electronic component 900b. Electronic component 1000c can be similar to electronic component 900c.

[0135] According to various embodiments, the metallization 406 can be formed above the segregation suppression structure 404 of the electronic component 1000a, 1000b, 1000c. The metallization 406 can optionally include or be formed from a contact point. The metallization 406 can contain, or be formed from, a metallic self-segregating mixture or a metal alloy containing at least one metal, e.g., at least two metals. The metal of the metallization 406 can be the second dopant and / or the metal of the at least one ohmic contact area 810. Alternatively or additionally, the metal of the metallization 406 can be the base material and / or the alloying element of the self-segregating mixture. For example, the metal can be aluminum. Alternatively or additionally, the alloying element can be copper.

[0136] The formation of the metallization 406 can include arranging the self-segregating mixture (e.g., a layer thereof) over the segregation suppression structure 404. Optionally, the formation of the metallization 406 can include structuring the self-segregating mixture (e.g., the layer thereof), e.g., to form at least one contact point.

[0137] As an example, the self-segregating mixture (e.g., the layer thereof) can be structured using photolithography and etching. Alternatively or additionally, another structuring method can be used, such as a peeling process, laser ablation, or the like. For example, photolithography and the peeling process can involve the formation of a mask layer. In this case, structuring the self-segregating mixture can further involve the removal of the mask layer. As an example, in the case of the peeling process, the self-segregating mixture can be formed over the mask layer. In the case of photolithography, the mask layer can be formed over the self-segregating mixture. The mask layer can contain or be formed from a polymer, e.g., a resist, such as a photosensitive resist. Alternatively or additionally, the mask layer can contain another polymer, e.g., an imide (e.g., a cyanide).a polyimide), a resin, an epoxy resin, a casting compound, contain or be formed from it.

[0138] Arranging the self-segregating mixture (e.g., the layer thereof) can involve the use of a physical vapor deposition process, such as sputtering. Alternatively or additionally, the self-segregating mixture can be arranged using an electrochemical process, such as electroplating or metal deposition.

[0139] The at least one electrically conductive contact area 404, e.g., at least one from the first semiconductor area 802 (or, if present, the second semiconductor area 804), the at least one further semiconductor area 806, 808, and the at least one ohmic contact area 810, can be electrically connected to the metallization 406 via the segregation suppression structure 404. For example, the electronic component 1000a, 1000b, 1000c can contain or be formed from a Schottky diode. In this case, the segregation suppression structure 404 can contain or be formed from a front-facing metallization.

[0140] Fig. 11A to 11C each represent an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0141] The electronic component 1100a can be similar to the electronic components 1000a. According to various embodiments, the segregation suppression structure 404 can be partially removed, e.g., after the formation of the metallization 406. By partially removing the segregation suppression structure 404, the first semiconductor region 802 or, if present, the second semiconductor region 804 can be partially exposed.

[0142] The electronic component 1100b can be similar to the electronic components 1000b. According to various embodiments, the segregation suppression structure 404 can be partially removed, e.g., after the formation of the metallization 406. By partially removing the segregation suppression structure 404, at least one further semiconductor region 806, 808 can be partially exposed.

[0143] The electronic component 1100c can be similar to the electronic component 1000c. According to various embodiments, the segregation suppression structure 404 can be partially removed, e.g., after the formation of the metallization 406. By removing the segregation suppression structure 404, at least one further semiconductor region 806, 808 can be partially exposed. As an example, at least one ohmic contact region 810 can remain covered by the segregation suppression structure 404.

[0144] As an example, the segregation suppression structure 404 can be partially removed using photolithography and etching. Alternatively or additionally, other removal methods can be used, such as a peeling process, laser ablation, or the like. For example, photolithography and the peeling process can involve the formation of a mask layer. In this case, partial removal of the segregation suppression structure 404 can further involve the removal of the mask layer. As an example, in the case of the peeling process, the segregation suppression structure 404 can be formed over the mask layer. In the case of photolithography, the mask layer can be formed over the segregation suppression structure 404. The mask layer can contain or be formed from a polymer, such as a resist, e.g., a photosensitive resist. Alternatively or additionally, the mask layer can contain another polymer, e.g., an imide (e.g., a cyanoacrylate).a polyimide), a resin, an epoxy resin, a casting compound, contain or be formed from it.

[0145] Fig. 12A, Fig. 12B and Fig. Figure 13 each represents an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0146] The electronic component 1200a can be similar to the electronic components 1100a. According to various embodiments, at least one passivation layer 408 can be formed over the electronic component 1100a. The at least one passivation layer 408 can be formed over the first semiconductor region 802 or, if present, the second semiconductor region 804.

[0147] The electronic component 1200b can be similar to the electronic components 1100b. According to various embodiments, at least one passivation layer 408 can be formed over the electronic component 1100b. The at least one passivation layer 408 can be formed over the at least one further semiconductor region 806, 808.

[0148] The electronic component 1300 can be similar to the electronic components 1100c. According to various embodiments, at least one passivation layer 408 can be formed over the electronic component 1100c. The at least one passivation layer 408 can be formed over the at least one further semiconductor region 806, 808.

[0149] Furthermore, the at least one passivation layer 408 can optionally be formed partially over the metallization 406. The at least one passivation layer 408 can contain an opening 408o that at least partially exposes the metallization 406. If the metallization 406 contains more than one contact point, the at least one passivation layer 408 can contain more than one opening, each of which partially exposes a contact point of the metallization 406.

[0150] The at least one passivation layer 408 can contain or be formed from an electrically insulating material. According to various embodiments, an electrically insulating material can contain or be formed from a semiconductor oxide, a metal oxide, a ceramic, a semiconductor nitride, a semiconductor carbide, a glass, e.g., fluorosilicate glass (FSG), a polymer, e.g., a resin, an adhesive, a resist, benzocyclobutene (BCB) or polyimide (PI), a silicate, e.g., hafnium silicate or zirconium silicate, a transition metal oxide, e.g., hafnium dioxide or zirconium dioxide, an oxynitride, e.g., silicon oxynitride, or any other type of dielectric material. Alternatively or additionally, the at least one passivation layer 408 can contain or be formed from a hard passivation layer 408a and / or a polymer layer 408b.

[0151] The hard passivation layer 408a may contain or be formed from a nitride, an oxide, and / or a carbide. For example, the hard passivation layer 408a may contain or be formed from a semiconductor nitride, e.g., silicon nitride. Alternatively or additionally, the hard passivation layer 408a may contain or be formed from a semiconductor oxide, e.g., silicon oxide (also known as silicon glass). The semiconductor of the hard passivation layer 408a may be undoped. The polymer layer 408b may contain at least one of the following: an imide (e.g., a polyimide), a resin, an epoxy resin, or a cast compound.

[0152] According to various embodiments, the at least one passivation layer 408 can be structured, e.g., to form the opening 408o. For example, the at least one passivation layer 408 can be structured using photolithography and etching (e.g., using a fluorine-based etchant such as sulfur hexafluoride or phosphorus tetrafluoride). Alternatively or additionally, another structuring method can be used, e.g., a peeling process, laser ablation, or the like. For example, photolithography and the peeling process can involve forming a mask layer. In this case, structuring the at least one passivation layer 408 can further involve removing the mask layer. For example, in the case of the peeling process, the at least one passivation layer 408 can be formed over the mask layer.In the case of photolithography, the mask layer can be formed over at least one passivation layer 408. The mask layer can contain or be formed from a polymer, e.g., a resist, such as a photosensitive resist. Alternatively or additionally, the mask layer can contain or be formed from another polymer, e.g., an imide (e.g., a polyimide), a resin, an epoxy resin, or a casting compound.

[0153] Fig. 14A, Fig. 14B and Fig. Figure 15 each represents an electronic component in a method according to various embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0154] Electronic component 1400a can be similar to electronic component 1200a. Electronic component 1400b can be similar to electronic component 1200b. Electronic component 1500 can be similar to electronic component 1300.

[0155] According to various embodiments, the electronic component 1400a, 1400b, 1500 (e.g., its first semiconductor region 802) can be thinned, for example, by subtractive manufacturing (which may include, for example, sanding, grinding, sawing, sandblasting, milling). Thinning the electronic component 1400a, 1400b, 1500 can involve removing material from a second side of the electronic component 1400a, 1400b, 1500 opposite the segregation suppression structure 404 by subtractive manufacturing. Thinning the electronic component 1400a, 1400b, 1500 (e.g., its first semiconductor region 802) can reduce its thickness. For example, the thickness of the first semiconductor region 802 can be reduced to less than or equal to approximately 110 µm.

[0156] According to various embodiments, at least one electrically conductive layer 1402 can be formed. The at least one electrically conductive layer 1402 can contain or be formed from at least one electrically conductive material. By way of example, the at least one electrically conductive layer 1402 can contain or be formed from a compound layer 1402a and / or a further metallization 1402b.

[0157] For example, the compound layer 1402a can contain or be formed from a compound that includes a semiconductor, e.g., silicon, and / or a metal. For example, the compound can be a binary compound containing, for example, the semiconductor and the metal, e.g., silicon and nickel. Alternatively or additionally, the further metallization 1402b can contain a metallic material, e.g., a metal alloy. For example, the further metallization 1402b can contain or be formed from at least one of the following: titanium, nickel, silver.

[0158] Fig. 16A and Fig. 16B each represent an electronic component in a method according to various embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0159] In 1600a, the at least one electrically conductive contact region 402 (e.g., a semiconductor region and / or an ohmic contact region) can contain several projections 1602. For example, each projection from the multiple projections 1602 can contain or be formed from a first material that protrudes from a second material, which is different from the first. Alternatively or additionally, the first and second materials can be the same (visually, a monolithically formed at least one electrically conductive contact region 402). The multiple projections 1602 can define a first roughness of the at least one electrically conductive contact region 402.

[0160] In 1600b, the segregation suppression structure 404 can be formed over the at least one electrically conductive contact area 402. The segregation suppression structure 404 can contain or be formed from several topographic features 404f. Each feature from the several topographic features 404f can contain or be formed from a projection. The several topographic features 404f can define a second roughness of the segregation suppression structure 404.

[0161] The first roughness can be smaller than the second roughness (e.g., about 75%, 50%, or 25% of it). For example, a spatially averaged height variation 1604t of the at least one electrically conductive contact area 402 can be smaller than the spatially averaged height variation 704t of the segregation suppression structure 404 (e.g., about 75%, 50%, or 25% of it). Alternatively or additionally, a number of protrusions 1602 of the at least one electrically conductive contact area 402 can be smaller than a number of topographic features 404f of the segregation suppression structure 404 (e.g., per area) (e.g., about 75%, 50%, or 25% of it). Alternatively or additionally, a spatially averaged distance 714t of adjacent topographic features 404f of the segregation suppression structure 404 may be smaller than the (e.g. 75%, 50% or 25% of the) spatially averaged distance 1414t of adjacent projections 1602 of the at least one electrically conductive contact area 402.For example, at least one topographic feature of the segregation suppression structure 404 can be arranged over an area of ​​the at least one electrically conductive contact area 402 between two adjacent projections 1602 of the at least one electrically conductive contact area 402.

[0162] For example, the spatially averaged height variation 1604t of the at least one electrically conductive contact region 402 can be smaller than about 200 nm, e.g., smaller than about 100 nm, e.g., smaller than about 50 nm. Alternatively or additionally, a spatially averaged height variation 704t of the segregation suppression structure 404 can be larger than about 50 nm, e.g., larger than about 100 nm, e.g., larger than about 200 nm, e.g., larger than about 300 nm, e.g., larger than about 500 nm, e.g., larger than about 600 nm.

[0163] According to various embodiments, the spatially averaged distance 1414t of adjacent projections 1602 of the segregation suppression structure 404 can be greater than about 10 µm, e.g. greater than or equal to about 13 µm, e.g. greater than or equal to about 15 µm, e.g. greater than or equal to about 20 µm, e.g. greater than or equal to about 50 µm, e.g. greater than or equal to about 100 µm.

[0164] According to various embodiments, the average distance 714t between adjacent topographic features 404f of the segregation suppression structure 404 can be less than or equal to about 20 µm, e.g., less than or equal to about 15 µm, e.g., less than or equal to about 10 µm, e.g., less than or equal to about 5 µm, e.g., less than or equal to about 2 µm, e.g., less than or equal to about 1 µm, e.g., less than or equal to about 0.5 µm, e.g., in the range of about 0.1 µm to about 20 µm, e.g., in the range of about 0.1 µm to about 10 µm, or less than or less than or equal to about 0.1 µm.

[0165] According to various embodiments, the spatially averaged height variation 704t of the segregation suppression structure 404 can be greater than about 1 nm, e.g. greater than or equal to about 10 nm, e.g. greater than or equal to about 25 nm, e.g. greater than or equal to about 50 nm, e.g. greater than or equal to about 75 nm, e.g. greater than or equal to about 100 nm.

[0166] Fig. 17A and Fig. 17B each represent an electronic component in a method according to different embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0167] In 1700a, the electronic component can contain several electrically conductive contact areas 402. For example, each electrically conductive contact area among the several electrically conductive contact areas 402 can contain or be formed from an ohmic contact area. Alternatively or additionally, each electrically conductive contact area among the several electrically conductive contact areas 402 can protrude from a semiconductor region 1702 of the electronic component (e.g., the at least one semiconductor region 802, 804 and / or the at least one further semiconductor region 806, 808). The several electrically conductive contact areas 402 can define a first roughness of the electronic component.

[0168] In 1700b, the segregation suppression structure 404 can be formed over the multiple electrically conductive contact areas 402. The segregation suppression structure 404 can be configured as described above. The segregation suppression structure 404 can contain or be formed from multiple topographic features 404f. Each feature from the multiple topographic features 404f can contain or be formed from a projection. The multiple topographic features 404f can define a second roughness of the segregation suppression structure 404.

[0169] The first roughness may be smaller than the second roughness (e.g., about 75%, 50%, or 25% of it). For example, a spatially averaged protrusion 1704t of the multiple electrically conductive contact areas 402 may be smaller than a spatially averaged height variation 704t of the segregation suppression structure 404 (e.g., about 75%, 50%, or 25% of it). Alternatively or additionally, a number of electrically conductive contact areas 402 from the multiple electrically conductive contact areas 402 may be smaller than a number of topographic features 404f of the segregation suppression structure 404 (e.g., per area) (e.g., about 75%, 50%, or 25% of it). Alternatively or additionally, a spatially averaged distance 714t of adjacent topographic features 404f of the segregation suppression structure 404 can be smaller than the (e.g.75%, 50%, or 25% of the spatially averaged distance 1414t of adjacent electrically conductive contact areas 402 from the multiple electrically conductive contact areas 402. For example, at least one topographic feature of the segregation suppression structure 404 can be arranged over an area of ​​the electronic component between two adjacent electrically conductive contact areas from the multiple electrically conductive contact areas 402.

[0170] For example, the spatially averaged protrusion 1704t (or more generally, a corresponding height variation) of the multiple electrically conductive contact regions 402 can be smaller than approximately 200 nm, e.g., smaller than approximately 100 nm, e.g., smaller than approximately 50 nm. Alternatively or additionally, a spatially averaged height variation 704t of the segregation suppression structure 404 can be larger than approximately 50 nm, e.g., larger than approximately 100 nm, e.g., larger than approximately 200 nm, e.g., larger than approximately 300 nm, e.g., larger than approximately 500 nm, e.g., larger than approximately 600 nm.

[0171] According to various embodiments, the spatially averaged distance 1414t of adjacent electrically conductive contact areas 402 can be greater than about 10 µm, e.g. greater than or equal to about 13 µm, e.g. greater than or equal to about 15 µm, e.g. greater than or equal to about 20 µm, e.g. greater than or equal to about 50 µm, e.g. greater than or equal to about 100 µm.

[0172] Fig. 18A and Fig. 18B each represent an electronic component in a method according to various embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0173] In 1800a, the electronic component can contain several electrically conductive contact areas 402. For example, each electrically conductive contact area from the several electrically conductive contact areas 402 can contain or be formed from an ohmic contact area. Alternatively or additionally, each electrically conductive contact area from the several electrically conductive contact areas 402 can extend into the semiconductor region 1702 of the electronic component. A surface 1702s of the electronic component near the several electrically conductive contact areas 402 can define a first roughness of the electronic component.

[0174] In 1800b, the segregation suppression structure 404 can be formed over the surface 1702s. The segregation suppression structure 404 can be configured as described above. The segregation suppression structure 404 can contain or be formed from multiple topographic features 404f. Each feature from the multiple topographic features 404f can contain or be formed from a projection. The multiple topographic features 404f can define a second roughness of the segregation suppression structure 404.

[0175] The first roughness can be smaller than the second roughness (e.g., about 75%, 50%, or 25% of it). Alternatively or additionally, a spatially averaged extent 1804t of the multiple electrically conductive contact regions 402 into the semiconductor region 1702 can be smaller than a spatially averaged height variation 704t of the segregation suppression structure 404 (e.g., about 75%, 50%, or 25% of it). Alternatively or additionally, a number of electrically conductive contact regions 402 from the multiple electrically conductive contact regions 402 can be smaller than a number of topographic features 404f of the segregation suppression structure 404 (e.g., per area) (e.g., about 75%, 50%, or 25% of it). Alternatively or additionally, a spatially averaged distance 714t of adjacent topographic features 404f of the segregation suppression structure 404 can be smaller than a (e.g.75%, 50%, or 25% of a spatially averaged distance 1414t of adjacent electrically conductive contact areas 402 from the multiple electrically conductive contact areas 402. For example, at least one topographic feature of the segregation suppression structure 404 can be arranged over an area of ​​the electronic component between two adjacent electrically conductive contact areas from the multiple electrically conductive contact areas 402.

[0176] For example, the spatially averaged extent 1804t (or more generally, a corresponding height variation) of the multiple electrically conductive contact regions 402 can be smaller than approximately 200 nm, e.g., smaller than approximately 100 nm, e.g., smaller than approximately 50 nm. Alternatively or additionally, a spatially averaged height variation 704t of the segregation suppression structure 404 can be larger than approximately 50 nm, e.g., larger than approximately 100 nm, e.g., larger than approximately 200 nm, e.g., larger than approximately 300 nm, e.g., larger than approximately 500 nm, e.g., larger than approximately 600 nm.

[0177] According to various embodiments, the spatially averaged distance 1414t of adjacent electrically conductive contact areas 402 can be greater than about 10 µm, e.g. greater than or equal to about 13 µm, e.g. greater than or equal to about 15 µm, e.g. greater than or equal to about 20 µm, e.g. greater than or equal to about 50 µm, e.g. greater than or equal to about 100 µm.

[0178] Fig. 19A represents an electronic component 1900a (e.g. a semiconductor device 1900a) according to various embodiments in a method according to various embodiments in various embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402), e.g. a semiconductor circuit element, e.g. a power semiconductor circuit element.

[0179] The electronic component 1900a may contain a doped semiconductor layer 2010 formed on the second side 102b. The doped semiconductor layer 2010 may contain or be formed from a first doping type. The doped semiconductor layer 2010 may contain or be formed from an electrically conductive contact area 402, e.g., a collector area (an electrically conductive doped semiconductor area in the form of a collector area).

[0180] The electronic component 1900a can further include a first contact point 1706 in the form of a collector contact point 1706 (e.g., a drain contact point). The first contact point 1706 can electrically contact the doped semiconductor layer 2010, optionally via a segregation suppression structure 404 arranged between them.

[0181] Furthermore, the electronic component 1900a can contain a first doped region 2006. The first doped region 2006 can contain or be formed from an electrically conductive contact region 402, e.g., a base region. The first doped region 2006 can contain a doping type (e.g., a dopant having a doping type) identical to the doped semiconductor layer 2010 (in other words, the dopant of the doped semiconductor layer 2010), e.g., the first doping type. The electronic component 1900a can further contain a second contact point 1708a that electrically contacts the first doped region 2006, optionally via the segregation suppression structure 404 arranged between them. The second contact point 1708a can contain or be formed from an emitter contact point 1708a (e.g., a source contact point 1708a).

[0182] Furthermore, the electronic component 1900a can contain a second doped region 2004 formed between the first doped region 2006 and the doped semiconductor layer 2010. The second doped region 2004 can contain or be formed from a drift region. The second doped region 2004 can contain a doping type (second doping type) different from that of the doped layer 2010, e.g., a dopant exhibiting the second doping type. The second doped region 2004 can have an epitaxially formed layer (e.g., the second semiconductor region 804).

[0183] The electronic component 1900a may further include a second contact point 1708b. The second contact point 1708b may include or be formed from a gate contact point 1708b. The second contact point 1708b may be electrically isolated from the second doped region 2004, for example, by an electrically insulating material formed between the second contact point 1708b and the second doped region 2004.

[0184] Furthermore, the electronic component 1900a may contain a third doped region 2008. The third doped region 2008 may contain or be formed from an emitter region. The third doped region 2008 may contain a doping type (e.g., a dopant exhibiting a doping type) that differs from that of the doped semiconductor layer 2010, e.g., the second doping type. A dopant concentration of the third doped region 2008 may be greater than that of the second doped region 2004.

[0185] Optionally, the electronic component 1900a can include a fourth doped region 2002 between the second doped region 2004 and the doped semiconductor layer 2010. The fourth doped region 2002 can contain or be formed from a field-stop region. The fourth doped region 2002 can contain a dopant having a doping type different from that of the doped semiconductor layer 2010. The fourth doped region 2002 can have a dopant concentration higher than that of the second doped region 2004.

[0186] According to various embodiments, the first doping type can be an n-type doping type, and the second doping type can be a p-type doping type. Alternatively, the first doping type can be the p-type doping type, and the second doping type can be the n-type doping type.

[0187] The electronic component 1900a, e.g., a semiconductor circuit element 1702, may contain or be formed from a transistor structure (e.g., in an IGBT), e.g., a planar transistor structure (providing vertical current flow). A transistor structure may contain or be formed from several unipolar junctions (e.g., pn junctions) that, for example, form a bipolar junction. A unipolar junction may be formed by an interface between two doped regions having different doping types, e.g., an interface between at least one of the following: the first doped region 2006 and the second doped region 2004; the first doped region 2006 and the third doped region 2008; the second doped region 2004 and the doped semiconductor layer 2010; the doped semiconductor layer 2010 and the fourth doped region 2002.

[0188] According to various embodiments, the second doped region 2004 and the fourth doped region 2002 can contain the same doping type. As described above, the doped semiconductor layer 2010 can differ from the second doped region 2004 and the fourth doped region 2002 in the doping type. In this case, the doped semiconductor layer 2010 can provide a back-emitter region (e.g., for an IGBT). Alternatively, the doped semiconductor layer 2010 can have the same doping type as the second doped region 2004 and the fourth doped region 2002. In this case, the doped semiconductor layer 2010 can provide a contact reinforcement region (e.g., for a vertical metal-oxide-semiconductor field-effect transistor).

[0189] According to various embodiments, the electronic component 1900a, e.g. the semiconductor circuit element 1702, can contain or be formed from a bipolar transistor with an insulated gate.

[0190] Fig. 19B represents an electronic component 1900b, e.g. a semiconductor device 1900b, according to various embodiments in a method according to various embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402), e.g. a semiconductor circuit element, e.g. a power semiconductor circuit element.

[0191] The electronic component 1900b may contain the doped semiconductor layer 2010 formed on the second side 102b. The doped semiconductor layer 2010 (in other words, the activated dopant) may contain or be formed from a first doping type.

[0192] The electronic component 1900b can further include a first contact point 1706b that electrically contacts the doped semiconductor layer 210, optionally via the segregation suppression structure 404 arranged between them. The first contact point 1706 can contain or be formed from an electrode contact point. Illustratively, the first doped region 2006 can provide a thin doped region, and / or the second doped region 2004 can provide a thick drift zone. The first doped region 2006 can be electrically and / or physically connected to a second contact point 1708, optionally via the segregation suppression structure 404 arranged between them.

[0193] Furthermore, the electronic component 1900b can include a first doped region 2006. The first doped region 2006 can contain or be formed from a first transition region. The first doped region 2006 can contain a dopant having a doping type different from that of the doped semiconductor layer 2010 (in other words, the dopant of the doped semiconductor layer 2010), e.g., the second doping type. The electronic component 1900b can further include the second contact point 1708, which electrically contacts the first doped region 2006, optionally via the segregation suppression structure 404 arranged between them. The second contact point 1708 can contain or be formed from an electrode contact point. Furthermore, the electronic component 1900b can include a second doped region 2004 formed between the first doped region 2006 and the doped semiconductor layer 2010.The second doped region 2004 may contain or be formed from a second transition region. The second doped region 2004 may contain a doping type identical to a doping type of the doped semiconductor layer 2010, e.g., a dopant exhibiting the first doping type.

[0194] Optionally, the electronic component 1900b can include a third doped region 2002 between the second doped region 2004 and the doped semiconductor layer 2010. The third doped region 2002 can contain or be formed from a field-stop region. The third doped region 2002 can have a doping type identical to that of the doped semiconductor layer 2010 (e.g., a dopant with the same doping type). The third doped region 2002 can have a dopant concentration higher than that of the second doped region 2004.

[0195] The electronic component 1900b may contain or be formed from a diode structure, e.g., a planar diode structure (which provides a vertical current flow). A diode structure may contain or be formed from a pn junction, e.g., by an interface between two doped regions having different doping types, e.g., an interface between the first doped region 2006 and the second doped region 2004.

[0196] Optionally, the doped semiconductor layer 2010 can contain or be composed of multiple first segments containing the first doping type and multiple second segments containing the second doping type. The segments from the multiple first segments and the segments from the multiple second segments can be arranged in an alternating sequence. In this case, the doped semiconductor layer 2010 can be part of a reverse diode structure.

[0197] Fig. 20A and Fig. 20B each represent an electronic component in a method according to various embodiments in a schematic cross-sectional view or side view (e.g. along a macroscopic surface normal 404n of the electrically conductive contact area 402).

[0198] According to various embodiments, the electronic component may contain or be composed of an electromechanical component and / or an optoelectric component and / or an optoelectromechanical component. In general, the electronic component may be configured to transform between electrical energy (e.g., in the case of an electronic component) and / or mechanical energy (e.g., in the case of an electromechanical component) and / or optical energy (e.g., in the case of an optoelectric component), or both optical and mechanical energy (e.g., in the case of an optoelectromechanical component). Optical energy may contain or be composed of radiant energy.

[0199] According to various embodiments, an electronic component 2000a (e.g., a microelectromechanical device, also referred to as a microelectromechanical component) can include at least one semiconductor region 802, 804 and a microelectromechanical element 2204 arranged above the at least one semiconductor region 802, 804. The microelectromechanical element 2204 can be configured to generate or modify an electrical signal in response to a mechanical signal, and / or can be configured to generate or modify a mechanical signal in response to an electrical signal. Furthermore, the electronic component 2000a can include at least one contact point 2206 (e.g., two or more contact points 2206).The at least one contact point 2206 can be electrically connected to the microelectromechanical element 2204 via at least one electrically conductive contact area 402 for transmitting the electrical signal between the at least one contact point 2206 and the microelectromechanical element 2204.

[0200] According to various embodiments, the segregation suppression structure 404 can be arranged between the at least one electrically conductive contact area 402 and the at least one contact point 2206. The at least one electrically conductive contact area 402 can include or be formed from a via and / or a redistribution layer and / or an electrical interconnect. For example, the microelectromechanical element 2204 can include or be formed from a diaphragm, e.g., a microphone.

[0201] According to various embodiments, an electronic component 2000b (e.g., an optoelectronic device, also referred to as an optoelectronic component) can include at least one semiconductor region 802, 804 and an optoelectronic element 2214 arranged above the at least one semiconductor region 802, 804. The optoelectronic element 2214 can be configured to generate or modify an electrical signal in response to an optical signal, and / or can be configured to generate or modify an optical signal in response to an electrical signal. Furthermore, the electronic component 2000b can include at least one contact point 2206.The at least one contact point 2206 can be electrically connected to the optoelectronic element 2204 via at least one electrically conductive contact area 402 for transmitting the electrical signal between the at least one contact point 2206 and the optoelectronic element 2214. The segregation suppression structure 404 can be arranged between the at least one electrically conductive contact area 402 and the at least one contact point 2206. The at least one electrically conductive contact area 402 can include or be formed from a via and / or a redistribution layer and / or an electrical interconnect. For example, the optoelectronic element 2214 can include or be formed from a solid-state light source (SSL), e.g., a semiconductor light-emitting diode (SLED), an organic light-emitting diode (OLED), or a polymer light-emitting diode (PLED).

[0202] Furthermore, various embodiments are described below.

[0203] According to various embodiments, a method for processing an electronic component containing at least one electrically conductive contact area may include: forming a contact point containing a self-segregating mixture over the at least one electrically conductive contact area to electrically contact the electronic component; forming a segregation suppression structure between the contact point and the electronic component, wherein the segregation suppression structure may contain more nucleation-inducing topographic features than the at least one electrically conductive contact area, to disrupt chemical segregation of the self-segregating mixture through crystallographic interfaces of the contact point defined by the nucleation-inducing topographic features.Alternatively or additionally (for more nucleation-inducing topographic features), the segregation suppression structure can contain a greater areal density of nucleation-inducing topographic features than the at least one electrically conductive surface for spatially limiting chemical segregation of the self-segregating mixture to a crystallite size of the contact point defined by the areal density of the nucleation-inducing topographic features.

[0204] According to various embodiments, a method for processing an electronic component containing at least one electrically conductive surface may include: forming a metallization containing a self-segregating mixture over the at least one electrically conductive surface to electrically contact the electronic component; forming a segregation suppression structure between the metallization and the electronic component, wherein the segregation suppression structure may contain more nucleation-inducing topographic features than the at least one electrically conductive contact area, to disrupt chemical segregation of the self-segregating mixture through crystallographic interfaces of the metallization defined by the nucleation-inducing topographic features.Alternatively or additionally (for more nucleation-inducing topographic features), the segregation suppression structure can contain a greater areal density of nucleation-inducing topographic features than the at least one electrically conductive surface for spatially limiting chemical segregation of the self-segregating mixture to a crystallite size of the metallization defined by the areal density of the nucleation-inducing topographic features.

[0205] According to various embodiments, a method for processing an electronic component containing at least one electrically conductive surface may include: forming a metallization containing an aluminum bronze over the at least one electrically conductive surface to electrically contact the electronic component; forming a segregation suppression structure between the metallization and the electronic component, wherein the segregation suppression structure may contain more protrusions than the at least one electrically conductive contact area, to disrupt chemical segregation of the self-segregating mixture by crystallographic interfaces of the metallization induced by the protrusions.Alternatively or additionally (for more protrusions), the segregation suppression structure can contain a greater areal density of protrusions than the at least one electrically conductive surface for spatially limiting chemical segregation of the self-segregating mixture to a crystallite size of the metallization defined by the areal density of the protrusions.

[0206] According to various embodiments, the method can further include structuring the metallization to form at least one contact point. For example, the method can further include forming at least one contact point from the metallization.

[0207] According to various embodiments, each nucleation-inducing topographic feature of the segregation suppression structure can be configured to induce crystallite nucleation on it, such that a crystallographic interface is formed between adjacent nucleation-inducing topographic features of the segregation suppression structure.

[0208] According to various embodiments, at least one nucleation-inducing topography feature of the segregation suppression structure can be arranged between two electrically conductive contact areas from the at least one electrically conductive contact area.

[0209] According to various embodiments, at least one nucleation-inducing topographic feature of the segregation suppression structure can be arranged between the at least one electrically conductive contact area and the contact point.

[0210] According to various embodiments, at least one electrically conductive contact area can contain an ohmic property.

[0211] According to various embodiments, the method can further include forming a passivation layer over the electronic component, which has at least one opening that exposes the contact point.

[0212] According to various embodiments, the method can further include forming a metallization on one side of the electronic component opposite the contact point for electrically contacting the electronic component.

[0213] According to various embodiments, forming the contact point can include forming a metallization and structuring the metallization.

[0214] According to various embodiments, structuring the metallization can include at least partial exposure of the segregation suppression structure.

[0215] According to various embodiments, the electronic component can contain a semiconductor area (e.g., electrically semiconducting); and the at least one electrically conductive contact area can protrude from the semiconductor area.

[0216] According to various embodiments, forming the segregation suppression structure can include forming a metallization over the at least one electrically conductive contact area and structuring the metallization to form the nucleation-inducing topographic features of the segregation suppression structure.

[0217] According to various embodiments, forming the segregation suppression structure can include forming a substrate over the at least one electrically conductive contact area and structuring the substrate to form the nucleation-inducing topographic features of the segregation suppression structure.

[0218] According to various embodiments, the segregation suppression structure can contain or be formed from titanium.

[0219] According to various embodiments, the segregation suppression structure can contain a greater roughness than the at least one electrically conductive contact area.

[0220] According to various embodiments, the roughness of the segregation suppression structure can be greater than the roughness of a surface of the electronic component between two electrically conductive contact areas from the at least one electrically conductive contact area.

[0221] According to various embodiments, the areal density of crystallographic interfaces (of the metallization or the corresponding contact point) induced by the at least one electrically conductive contact area can be smaller than the areal density of the crystallographic interfaces induced by the segregation suppression structure.

[0222] According to various embodiments, the areal density of crystallites (of the metallization or the corresponding contact point) can be greater than the areal density of nucleation-inducing topographic features of the at least one conductive contact area.

[0223] According to various embodiments, the formation of the contact point can include the formation of more crystallites than the at least one electrically conductive contact area exhibiting nucleation-inducing topographic features.

[0224] According to various embodiments, the formation of the contact point can include the formation of a larger areal density of crystallites than an areal density of the nucleation-inducing topographic features of the at least one electrically conductive contact area.

[0225] According to various embodiments, an average crystallite size (of the metallization or the corresponding contact point) induced by the at least one electrically conductive contact area can be smaller than an average crystallite size induced by the segregation suppression structure.

[0226] According to various embodiments, each nucleation-inducing topographic feature of the segregation suppression structure can include or be formed from a projection and / or a recess.

[0227] According to various embodiments, each nucleation-inducing topographic feature of the segregation suppression structure can contain or be formed from at least one edge.

[0228] According to various embodiments, the segregation suppression structure can contain or be formed from several nucleation-inducing topographic features arranged between the at least one electrically conductive contact area and the metallization or the corresponding at least one contact point.

[0229] According to various embodiments, the distance between two topographic features of the segregation suppression structure can be smaller than the distance between two electrically conductive contact areas from the at least one electrically conductive contact area.

[0230] According to various embodiments, the distance between two topographic features of the segregation suppression structure can be smaller than the distance between two topographic features of the at least one electrically conductive contact area.

[0231] According to various embodiments, the distance between two topographic features of the segregation suppression structure can be smaller than the distance between two protrusions of the at least one electrically conductive contact area.

[0232] According to various embodiments, the self-segregating mixture can contain or be formed from at least two different metals, e.g. a metal alloy containing the at least two different metals.

[0233] According to various embodiments, the self-segregating mixture can contain or be formed from two metals that differ in the sign of their standard potential.

[0234] According to various embodiments, the self-segregating mixture can contain or be formed from a noble metal and a base metal.

[0235] According to various embodiments, the self-segregating mixture can contain or be formed from at least two metals that differ in their electronegativity by more than or equal to approximately 0.3.

[0236] According to various embodiments, the self-segregating mixture can contain or be formed from copper and / or aluminum.

[0237] According to various embodiments, at least one electrically conductive contact area can contain or be formed from nickel and / or aluminum.

[0238] According to various embodiments, at least one electrically conductive contact area can be in physical contact with a doped area of ​​the electronic component.

[0239] According to various embodiments, the at least one electrically conductive contact area can be in physical contact with an area of ​​the electronic component that is doped with a metal of the at least one electrically conductive contact area.

[0240] According to various embodiments, the segregation suppression structure can be in physical contact with the metallization or the corresponding at least one contact point.

[0241] According to various embodiments, the chemical segregation of the self-segregating mixture can be induced at least partially by heating the metallization or the corresponding at least one contact point (e.g. via a segregation temperature).

[0242] According to various embodiments, the method can further include heating the metallization or the corresponding at least one contact point, e.g., to a segregation temperature.

[0243] According to various embodiments, the electronic component can contain or be formed from at least one electronic power component.

[0244] According to various embodiments, the electronic component can contain or be formed from a diode and / or a transistor.

[0245] According to various embodiments, the electronic component can contain or be formed from a microelectromechanical system.

[0246] According to various embodiments, an electronic component may include or be formed from: at least one electrically conductive region; a contact point containing a self-segregating mixture, arranged above the at least one electrically conductive region; a segregation suppression structure arranged between the contact point and the electronic component, wherein the segregation suppression structure may contain more nucleation-inducing topographic features than the at least one electrically conductive contact region, for disrupting chemical segregation of the self-segregating mixture through crystallographic interfaces of the contact point defined by the nucleation-inducing topographic features.Alternatively or additionally (for more nucleation-inducing topographic features), the segregation suppression structure can contain a greater areal density of nucleation-inducing topographic features than the at least one electrically conductive surface for spatially limiting chemical segregation of the self-segregating mixture to a crystallite size of the contact point defined by the areal density of the nucleation-inducing topographic features.

[0247] According to various embodiments, an electronic component may include or be formed from: at least one electrically conductive surface; a metallization containing a self-segregating mixture arranged above the at least one electrically conductive surface; a segregation suppression structure arranged between the metallization and the electronic component, wherein the segregation suppression structure may contain more nucleation-inducing topographic features than the at least one electrically conductive contact area, for disrupting chemical segregation of the self-segregating mixture through crystallographic interfaces of the metallization defined by the nucleation-inducing topographic features.Alternatively or additionally (for more nucleation-inducing topographic features), the segregation suppression structure can contain a greater areal density of nucleation-inducing topographic features than the at least one electrically conductive surface for spatially limiting chemical segregation of the self-segregating mixture to a crystallite size of the metallization defined by the areal density of the nucleation-inducing topographic features.

[0248] According to various embodiments, an electronic component may include or be formed from: at least one electrically conductive surface; a metallization containing an aluminum bronze arranged over the at least one electrically conductive surface; a segregation suppression structure arranged between the metallization and the electronic component, wherein the segregation suppression structure may include more protrusions than the at least one electrically conductive contact area, for disrupting chemical segregation of the self-segregating mixture by crystallographic interfaces of the metallization induced by the protrusions. Alternatively or additionally (e.g.,(for more protrusions) the segregation suppression structure can contain a greater areal density of protrusions than the at least one electrically conductive surface for spatially limiting a chemical segregation of the self-segregating mixture to a crystallite size of the metallization defined by the areal density of the protrusions.

[0249] According to various embodiments, the projections of each of the metallization and of the at least one electrically conductive contact area can fulfill a nucleation-inducing height criterion.

[0250] According to various embodiments, the metallization can contain or be formed from at least one contact point.

[0251] According to various embodiments, each nucleation-inducing topographic feature of the segregation suppression structure can be configured to induce crystallite nucleation on it, such that a crystallographic interface is formed between adjacent nucleation-inducing topographic features of the segregation suppression structure.

[0252] According to various embodiments, each nucleation-inducing topographic feature of the segregation suppression structure can contact exactly one or exactly two crystallites of the metallization.

[0253] According to various embodiments, each nucleation-inducing topographic feature of the segregation suppression structure can contact exactly one crystallographic interface of the metallization.

[0254] According to various embodiments, at least one nucleation-inducing topography feature of the segregation suppression structure can be arranged between two electrically conductive contact areas from the at least one electrically conductive contact area.

[0255] According to various embodiments, at least one nucleation-inducing topographic feature of the segregation suppression structure can be arranged between the at least one electrically conductive contact area and the metallization or the corresponding at least one contact point.

[0256] According to various embodiments, at least one electrically conductive contact area can contain an ohmic property.

[0257] According to various embodiments, the electronic component may further include a passivation layer arranged above the electronic component and having at least one opening that exposes the metallization or the corresponding at least one contact point.

[0258] According to various embodiments, the electronic component may further include a metallization arranged on one side of the electronic component opposite the metallization or the corresponding at least one contact point for electrically contacting the electronic component.

[0259] According to various embodiments, at least one contact point can contain or be formed from a structured metallization.

[0260] According to various embodiments, the electronic component can further include a semiconductor area (e.g., electrically semiconducting); wherein at least one electrically conductive contact area can protrude from the semiconductor area.

[0261] According to various embodiments, the segregation suppression structure can contain, be formed from, or include a structured metallization that incorporates the nucleation-inducing topographic features of the segregation suppression structure.

[0262] According to various embodiments, the segregation suppression structure can contain or be formed from titanium.

[0263] According to various embodiments, the segregation suppression structure contains a greater roughness than the at least one electrically conductive contact area.

[0264] According to various embodiments, the roughness of the segregation suppression structure can be greater than the roughness of a surface of the electronic component between two electrically conductive contact areas from the at least one electrically conductive contact area.

[0265] According to various embodiments, each nucleation-inducing topographic feature of the segregation suppression structure can include or be formed from a projection and / or a recess.

[0266] According to various embodiments, each nucleation-inducing topographic feature of the segregation suppression structure can contain or be formed from at least one edge.

[0267] According to various embodiments, an area density of crystallographic interfaces (of the metallization or the corresponding contact point) induced by the at least one electrically conductive contact area can be smaller than an area density of the crystallographic interfaces induced by the segregation suppression structure.

[0268] According to various embodiments, the areal density of crystallites (of the metallization or the corresponding contact point) can be greater than the areal density of nucleation-inducing topographic features of the at least one conductive contact area.

[0269] According to various embodiments, an average crystallite size (of the metallization or the corresponding contact point) induced by the at least one electrically conductive contact area can be smaller than an average crystallite size induced by the segregation suppression structure.

[0270] According to various embodiments, the segregation suppression structure can contain or be formed from several nucleation-inducing topographic features arranged between the at least one electrically conductive contact area and the metallization or the corresponding at least one contact point.

[0271] According to various embodiments, the distance between two topographic features of the segregation suppression structure can be smaller than the distance between two electrically conductive contact areas from the at least one electrically conductive contact area.

[0272] According to various embodiments, the distance between two topographic features of the segregation suppression structure can be smaller than the distance between two topographic features of the at least one electrically conductive contact area.

[0273] According to various embodiments, the self-segregating mixture can contain or be formed from at least two (two or more) different metals, e.g. a metal alloy that contains or is formed from the at least two (two or more) different metals.

[0274] According to various embodiments, the self-segregating mixture can contain or be formed from two metals that differ in the sign of their standard potential.

[0275] According to various embodiments, the self-segregating mixture can contain or be formed from a noble metal and a base metal.

[0276] According to various embodiments, the self-segregating mixture can contain or be formed from at least two metals that differ in their electronegativity by more than or equal to approximately 0.3.

[0277] According to various embodiments, the self-segregating mixture can contain or be formed from copper and / or aluminum.

[0278] According to various embodiments, at least one electrically conductive contact area can contain or be formed from nickel and / or aluminum.

[0279] According to various embodiments, at least one electrically conductive contact area can be in physical contact with a doped area of ​​the electronic component.

[0280] According to various embodiments, the at least one electrically conductive contact area can be in physical contact with an area of ​​the electronic component that is doped with a metal of the at least one electrically conductive contact area.

[0281] According to various embodiments, the segregation suppression structure can be in physical contact with the metallization or the corresponding at least one contact point.

[0282] According to various embodiments, the self-segregating mixture can be configured to chemically segregate by heating the metallization or the corresponding at least one contact point.

[0283] According to various embodiments, the electronic component can contain or be formed from at least one electronic power component.

[0284] According to various embodiments, the electronic component can contain or be formed from a diode and / or a transistor.

[0285] According to various embodiments, the electronic component can contain or be formed from a microelectromechanical system.

[0286] According to various embodiments, at least one electrically conductive surface can be electrically contacted through the metallization via the segregation suppression structure.

[0287] According to various embodiments, the electronic component can contain or be formed from at least one electrical component (which, for example, has one or more unipolar junctions); an electromechanical component; an optoelectronic component; and / or an optoelectromechanical component. Key to symbols Fig. 1 101 Form a contact point that contains or is formed from a self-segregating mixture 103 Form a segregation suppression structure between the contact point and the electronic component 105 Form a passivation layer over the electronic component 107 Form a metallization on an opposite side of the electronic component 109 Arrange at least one nucleation-inducing topographic feature of the segregation suppression structure between two electrically conductive contact areas from at least one electrically conductive contact area Fig. 2 201 A metallization containing a self-segregating mixture forms 203 Form a segregation suppression structure between the metallization and the electronic component 205 Form a passivation layer over the electronic component 207 Form a metallization on an opposite side of the electronic component 209 Arrange at least one nucleation-inducing topographic feature of the segregation suppression structure between two electrically conductive contact areas from at least one electrically conductive contact area Fig. 3 301 A metallization containing an aluminium bronze form 303 Form a segregation suppression structure between the metallization and the electronic component 305 Form a passivation layer over the electronic component 307 Form a metallization on an opposite side of the electronic component 309 Arrange at least one protrusion of the segregation suppression structure between two electrically conductive contact areas from at least one electrically conductive contact area

Claims

[1] Method (100) for processing an electronic component comprising at least one electrically conductive contact area, the method comprising: Forming a contact point comprising a self-segregating mixture over at least one electrically conductive contact area to electrically contact the electronic component (101); and Forming a segregation suppression structure between the contact point and the electronic component, wherein the segregation suppression structure comprises more nucleation-inducing topographic features than the at least one electrically conductive contact area, to disrupt chemical segregation of the self-segregating mixture by crystallographic interfaces of the contact point defined by the nucleation-inducing topographic features (103), wherein forming the segregation suppression structure (103) comprises forming a metallization over the at least one electrically conductive contact area and structuring the metallization to form the nucleation-inducing topographic features of the segregation suppression structure. [2] Method (100) according to claim 1, wherein each nucleation-inducing topography feature of the segregation suppression structure is configured to induce crystallite nucleation such that a crystallographic interface is formed between adjacent nucleation-inducing topography features of the segregation suppression structure. [3] Method (100) according to claim 1 or 2, wherein at least one nucleation-inducing topographic feature of the segregation suppression structure is arranged between two electrically conductive contact areas from the at least one electrically conductive contact area. [4] Method (100) according to any one of claims 1 to 3, wherein the at least one electrically conductive contact area comprises an ohmic property. [5] Method (100) according to any one of claims 1 to 4, further comprising: Forming a passivation layer over the electronic component, which has at least one opening that exposes the contact point (105). [6] Method (100) according to any one of claims 1 to 5, further comprising: Formation of a metallization on one side of the electronic component opposite the contact point for electrical contacting of the electronic component (107). [7] Method (100) according to any one of claims 1 to 6, the formation of the contact point (101) includes forming a metallization and structuring the metallization; where optionally the structuring of the metallization includes at least a partial exposure of the segregation suppression structure. [8] Method (100) according to any one of claims 1 to 7, wherein the electronic component comprises a semiconductor region; and wherein the at least one electrically conductive contact region protrudes from the semiconductor region. [9] Method (100) according to any one of claims 1 to 8, wherein the segregation suppression structure comprises titanium. [10] Method (100) according to any one of claims 1 to 9, wherein the segregation suppression structure comprises a greater roughness than the at least one electrically conductive contact area. [11] Method (100) according to any one of claims 1 to 10, wherein forming the contact point (101) comprises forming more crystallites than the at least one electrically conductive contact area has nucleation-inducing topographic features. [12] Method (100) according to any one of claims 1 to 11, wherein each nucleation-inducing topography feature of the segregation suppression structure comprises a projection and / or a recess. [13] Method (100) according to any one of claims 1 to 12, wherein the distance between two topographic features of the segregation suppression structure is smaller than the distance between two electrically conductive contact areas from the at least one electrically conductive contact area. [14] Method (100) according to any one of claims 1 to 13, wherein the self-segregating mixture comprises a noble metal and a base metal. [15] Method (100) according to any one of claims 1 to 14, wherein the electronic component comprises at least one electronic power component. [16] Method (100) according to any one of claims 1 to 15, wherein the electronic component comprises at least one consisting of an electrical component; an electromechanical component; an optoelectronic component; and / or an optoelectromechanical component. [17] Method (200) for processing an electronic component comprising at least one electrically conductive surface, the method comprising: Forming a metallization comprising a self-segregating mixture over at least one electrically conductive surface to electrically contact the electronic component (201); and Forming a segregation suppression structure between the metallization and the electronic component, wherein the segregation suppression structure includes more nucleation-inducing topographic features than the at least one electrically conductive contact area, to disrupt chemical segregation of the self-segregating mixture by crystallographic interfaces of the metallization defined by the nucleation-inducing topographic features (203), wherein forming the segregation suppression structure (103) comprises forming a metallization over the at least one electrically conductive contact area and structuring the metallization to form the nucleation-inducing topographic features of the segregation suppression structure. [18] Method (300) for processing an electronic component comprising at least one electrically conductive surface, the method comprising: Forming a contact point comprising an aluminium bronze over at least one electrically conductive surface to electrically contact the electronic component (301); and Forming a segregation suppression structure between the metallization and the electronic component, wherein the segregation suppression structure includes more protrusions than the at least one electrically conductive contact area, to disrupt chemical segregation of the self-segregating mixture by crystallographic interfaces of the contact point induced by the protrusions (303), wherein the formation of the segregation suppression structure (103) comprises forming a metallization over the at least one electrically conductive contact area and structuring the metallization to form the nucleation-inducing topographic features of the segregation suppression structure.

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