Wiring delay compensation method based on TDR (time domain reflectometry) technology

Abstract

The invention relates to the technical field of routing delay compensation, and particularly discloses a TDR (time domain reflectometry) technology-based routing delay compensation method, which comprises the following steps of: S1, injecting a step signal into each signal channel and synchronously acquiring a reflection waveform to obtain a time domain voltage curve; s2, identifying a first characteristic jump point and a second characteristic jump point from the time domain voltage curve, and taking half of the time value of the second jump point as the actual transmission delay of the channel; s3, comparing the delay of each channel, and calculating the compensation delay amount required by each channel by taking the maximum value as a reference; s4, corresponding digital time delay is injected in the excitation signal generation process, so that all the signals synchronously reach pins of a target device after being transmitted; the transmission delay of each signal channel is accurately measured by using the TDR technology, the problem of signal asynchronization caused by the length difference of the wires is effectively eliminated through digital delay compensation, and the accuracy and the reliability of the test time sequence are obviously improved.

Description

Technical Field

[0001] This invention relates to the field of trace delay compensation technology, and specifically to a trace delay compensation method based on TDR technology. Background Technology

[0002] In integrated circuit testing, factors such as inconsistent trace lengths of signal channels on the test load board, cable differences, and delays introduced by connectors can cause signals from multiple pins to arrive at the device under test asynchronously, severely affecting the timing accuracy of test signals and the accuracy of test results.

[0003] Traditional methods typically employ equal-length wiring strategies to ensure that the physical lengths of each channel are consistent, thereby achieving signal synchronization. However, this method has significant limitations in practical applications: on the one hand, equal-length wiring design is complex and difficult to implement, especially in high-speed, high-density test boards; on the other hand, this method lacks flexibility and cannot cope with delay variations caused by factors such as cable aging, temperature changes, or replacement of connecting components, and it cannot compensate for delay differences in already manufactured boards in the later stages. Summary of the Invention

[0004] The purpose of this invention is to provide a trace delay compensation method based on TDR technology to solve the following technical problems.

[0005] The objective of this invention can be achieved through the following technical solutions: A trace delay compensation method based on TDR technology includes the following steps: Step S1: Generate a step signal with a preset voltage amplitude, acquire all signal channels, inject the step signal into each signal channel through the test interface; and simultaneously acquire the reflection waveform of each signal channel to obtain a time-domain voltage curve containing reflection characteristics of several impedance discontinuities. Step S2: Identify the first characteristic jump point in the time-domain voltage curve, and obtain the time when the signal is reflected after being transmitted to the common node, which is the first time value; and identify the second characteristic jump point in the time-domain voltage curve, and obtain the time when the signal is transmitted to the electrical endpoint and total reflection occurs and the voltage reaches a stable state, which is the second time value t2; obtain (1 / 2)t2 of the signal channel as the actual transmission delay of the signal channel; Step S3: Compare the actual transmission delay of each signal channel and select the actual transmission delay with the largest value as the reference delay; obtain the difference between the reference delay and the actual transmission delay of each signal channel, and record it as the compensation delay amount of each signal channel; Step S4: During the generation of excitation signals for each signal channel, a digital delay is injected according to the compensation delay amount, so that the excitation signals emitted by each signal channel arrive at the target device pin simultaneously after physical transmission.

[0006] As a further aspect of the present invention: the rise time of the step signal is less than 1 nanosecond, the voltage amplitude jumps from the initial 0 volts to a preset logic level value, and the logic level value is set according to the operating voltage range of the device under test, with a set range of [3.3, 5] volts.

[0007] As a further aspect of the present invention: the process of identifying the first feature transition point and the second feature transition point includes: The voltage change rate of the reflected waveform is monitored in real time. When the voltage change rate exceeds a preset voltage change threshold, it is determined that there is a voltage jump at the current moment, and the point corresponding to the current moment on the reflected waveform is recorded as the voltage jump point. The first voltage jump point identified in the reflected waveform is recorded as the first characteristic jump point, and the last voltage jump point in the reflected waveform when the voltage finally stabilizes at a preset voltage value is recorded as the second characteristic jump point.

[0008] As a further aspect of the present invention: the step signal generation process includes, beforehand, the following: Connect the standard short circuit breaker to the common node, and record the reflected waveform acquired during short circuit calibration as the first reference reflected waveform. Determine the inherent delay value of the test path based on the characteristic points of the falling edge of the first reference reflected waveform. Connect the standard open circuit device to the common node. The reflected waveform acquired during open circuit calibration is recorded as the second reference reflected waveform. The accuracy of the inherent delay value is verified by the second reference reflected waveform. If the inherent delay value is verified to be accurate, the inherent delay value is stored. In the process of obtaining the actual transmission delay of the signal channel, the inherent delay value is subtracted from the second time value in advance.

[0009] As a further aspect of the present invention: the digital delay injection is based on a high-precision digital delay chip, the adjustment accuracy of the high-precision digital delay chip is greater than or equal to 0.04 nanoseconds, the delay time of the high-precision digital delay chip is programmed and controlled through an SPI or I2C digital interface, and the minimum step value is 0.01 nanoseconds.

[0010] As a further aspect of the present invention: each signal channel includes a transmission line, a connector, and an impedance matching element.

[0011] As a further aspect of the present invention: the common node is made of copper material with gold plating on the surface, and the common node is located at the geometric center of the test load board, and is connected to each signal channel in a star topology.

[0012] As a further aspect of the present invention: obtaining the compensation delay amount further includes introducing a temperature compensation factor, specifically including: The temperature compensation factor dynamically corrects the compensation delay based on real-time monitored ambient temperature data, using the following formula: T comp =T original ×[1+α×(T current -T ref )], where T comp T represents the amount of compensation delay after compensation. original The compensation delay is the amount of time before compensation, α is the temperature coefficient of the material, and T is the temperature delay before compensation. current This indicates the real-time temperature of the test load board, T. ref This is the preset reference temperature.

[0013] The beneficial effects of this invention are: This invention utilizes TDR technology to accurately measure the transmission delay of each signal channel and effectively eliminates the signal asynchrony problem caused by differences in trace length through digital delay compensation, significantly improving the timing accuracy and reliability of the test. This invention does not rely on complex equal-length wiring, greatly improving the flexibility of PCB design and the adaptability of the test system, while possessing high compensation accuracy at the sub-nanosecond level, effectively ensuring the accuracy and efficiency of high-speed integrated circuit testing. Attached Figure Description

[0014] The invention will now be further described with reference to the accompanying drawings.

[0015] Figure 1 This is a schematic diagram of a trace delay compensation method based on TDR technology according to the present invention; Figure 2 This is a schematic diagram illustrating the signal time-domain changes during the actual operation of the trace delay compensation method based on TDR technology according to the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Please see Figure 1 As shown, this invention is a trace delay compensation method based on TDR technology, comprising the following steps: Step S1: Generate a step signal with a preset voltage amplitude, acquire all signal channels, inject the step signal into each signal channel through the test interface; and simultaneously acquire the reflection waveform of each signal channel to obtain a time-domain voltage curve containing reflection characteristics of several impedance discontinuities. Specifically, a step signal with an extremely short rise time and a preset voltage amplitude is generated by a high-precision pulse signal generator and injected into all signal channels on the load board under test through a high-speed interface between the test machine and the load board. The high-speed sampling module integrated into the test system is used to synchronously acquire the reflected signals of each channel at a sampling rate of not less than 20GS / s, and obtain the time-domain voltage curve of the reflection characteristics caused by multiple impedance discontinuities such as connectors, transmission line inflection points and terminal loads. In a preferred embodiment of the present invention, each signal channel includes a transmission line, a connector, and an impedance matching element; In a preferred embodiment of the present invention, the step signal generation process further includes: Connect the standard short circuit breaker to the common node, and record the reflected waveform acquired during short circuit calibration as the first reference reflected waveform. Determine the inherent delay value of the test path based on the characteristic points of the falling edge of the first reference reflected waveform. Connect the standard open circuit device to the common node. The reflected waveform acquired during open circuit calibration is recorded as the second reference reflected waveform. The accuracy of the inherent delay value is verified by the second reference reflected waveform. If the inherent delay value is verified to be accurate, the inherent delay value is stored. In the process of obtaining the actual transmission delay of the signal channel, the inherent delay value is subtracted from the second time value in advance. Specifically, a standard short circuit with extremely low impedance is reliably connected to the common node, and the reflected waveform generated at this time is acquired using a time-domain reflectometer and recorded as the first reference reflected waveform. The first reference reflected waveform exhibits typical negative total reflection characteristics. By accurately extracting specific feature points of its falling edge, such as the maximum negative slope point or the intersection with the reference voltage, the inherent delay value introduced by the test system itself, such as the delay caused by cables, connectors and internal circuits, is calculated. Remove the short circuit breaker and connect a standard open circuit breaker with extremely high impedance to the same common node. Acquire the reflected waveform generated at this time and record it as the second reference reflected waveform. The second reference reflected waveform should exhibit typical positive total internal reflection characteristics. By analyzing its rising edge shape, amplitude, and time information, and cross-validating it with the theoretical expectation and the analysis results of the first reference reflected waveform, it is determined whether the calculation of the inherent delay value is accurate and whether the measurement system is working properly. If the verification is successful, the calculated inherent delay value is stored in the non-volatile memory of the test instrument. When obtaining the actual transmission delay of each signal channel in subsequent formal measurements, the inherent delay value is subtracted from the measured original second time value in advance, and finally the net transmission delay that only reflects the characteristics of the load board trace itself is obtained, which greatly improves the accuracy and reliability of delay measurement and compensation. It should be noted that the standard short circuit breaker is an ideal load with an impedance close to 0 ohms. The first reference reflection waveform is acquired during short-circuit calibration, at which time the standard short circuit breaker is reliably connected to the common node. Since a short circuit causes almost 100% of the signal energy to be negatively reflected, the acquired waveform is a typical, sharply decreasing negative pulse. The first reference reflection waveform is mainly used to accurately measure and subtract the inherent signal transmission delay and distortion of the test system itself. The standard open circuit is an ideal load with near-infinite impedance. The second reference reflected waveform is acquired during open-circuit calibration. At this time, the standard open circuit is reliably connected to the same common node. The open circuit causes nearly 100% of the signal energy to be positively reflected. Therefore, the acquired waveform is a typical, sharply rising positive pulse that is superimposed on the incident wave. The two reference reflected waveforms are mainly used to verify whether the entire TDR measurement system is in normal condition, such as whether the amplitude is correct and whether the waveform is clear and oscillating, to help confirm the accuracy of the short-circuit calibration. In a preferred embodiment of the present invention, the rise time of the step signal is less than 1 nanosecond, and the voltage amplitude transitions from an initial 0 volt to a preset logic level value. The logic level value is set according to the operating voltage range of the device under test, and the set range is [3.3, 5] volts. Specifically, the step signal is generated by a high-speed pulse generator with a rise time of less than 1 nanosecond to ensure accurate differentiation of minute reflections caused by impedance discontinuities between adjacent points on the load board. The voltage amplitude of the step signal precisely transitions from an initial 0 volt to a preset logic level value, which is set according to the operating voltage range of the device under test (DUT), typically selected between 3.3 volts and 5 volts, to ensure compatibility with the DUT's input level, avoid overshoot or undershoot, and ensure sufficient signal-to-noise ratio for the reflected signal. The step signal is injected into the load board signal channel through a coaxial cable with a 50-ohm characteristic impedance and a high-frequency connector. Its signal quality is monitored in real time using a broadband oscilloscope to ensure signal integrity meets the requirements of high-precision time-domain reflectometry. Step S2: Identify the first characteristic jump point in the time-domain voltage curve, and obtain the time when the signal is reflected after being transmitted to the common node, which is the first time value; and identify the second characteristic jump point in the time-domain voltage curve, and obtain the time when the signal is transmitted to the electrical endpoint and total reflection occurs and the voltage reaches a stable state, which is the second time value t2; obtain (1 / 2)t2 of the signal channel as the actual transmission delay of the signal channel; Specifically, in the time-domain voltage curve, a digital signal processing algorithm is used to automatically identify characteristic jump points. By differentiating the voltage curve, the first obvious positive jump point where dV / dt exceeds a preset threshold is located. This point corresponds to the moment when the signal is transmitted to the common node and undergoes the first partial reflection due to impedance mismatch. Its time coordinate is marked as the first time value t1. Continuing to track voltage changes, the plateau point is identified when the voltage value first reaches and stabilizes within 90%-95% of the preset amplitude of the step signal and the maintenance time exceeds three times the signal rise time. This second characteristic jump point corresponds to the moment when the signal is transmitted to the electrical endpoint and undergoes total reflection and the energy reaches a stable equilibrium state. Its time coordinate is marked as the second time value t2. The electrical endpoint is the open circuit. According to the principle of electromagnetic wave transmission, the round-trip time of the signal on the transmission line is t2. Therefore, the one-way transmission delay is (1 / 2)t2. The actual transmission delay of the signal channel is calculated in this way. In a preferred embodiment of the present invention, the process of identifying the first feature transition point and the second feature transition point includes: The voltage change rate of the reflected waveform is monitored in real time. When the voltage change rate exceeds a preset voltage change threshold, it is determined that there is a voltage jump at the current moment, and the point corresponding to the current moment on the reflected waveform is recorded as the voltage jump point. The first voltage jump point identified in the reflected waveform is recorded as the first characteristic jump point, and the last voltage jump point in the reflected waveform when the voltage finally stabilizes at a preset voltage value is recorded as the second characteristic jump point. Step S3: Compare the actual transmission delay of each signal channel and select the actual transmission delay with the largest value as the reference delay; obtain the difference between the reference delay and the actual transmission delay of each signal channel, and record it as the compensation delay amount of each signal channel; In a preferred embodiment of the present invention, the step signal generation process further includes: Connect the standard short circuit breaker to the common node, and record the reflected waveform acquired during short circuit calibration as the first reference reflected waveform. Determine the inherent delay value of the test path based on the characteristic points of the falling edge of the first reference reflected waveform. Connect the standard open circuit device to the common node. The reflected waveform acquired during open circuit calibration is recorded as the second reference reflected waveform. The accuracy of the inherent delay value is verified by the second reference reflected waveform. If the inherent delay value is verified to be accurate, the inherent delay value is stored. In the process of obtaining the actual transmission delay of the signal channel, the inherent delay value is subtracted from the second time value in advance. Specifically, a digital signal processing algorithm is used to monitor the voltage change rate of the reflected waveform in real time. When the voltage change rate exceeds a preset voltage change threshold, a voltage jump is determined to exist at the current moment, and the point corresponding to the current moment on the reflected waveform is recorded as the voltage jump point. The entire waveform is scanned using a sliding time window algorithm, and the first voltage jump point identified in the reflected waveform is recorded as the first characteristic jump point. This point corresponds to the moment when the signal is first reflected due to impedance change after transmission to the common node. The waveform changes are continued to be tracked, and the last significant voltage jump point in the reflected waveform when the voltage finally stabilizes at a preset voltage value is recorded as the second characteristic jump point. This point corresponds to the moment when the signal undergoes total reflection at the electrical endpoint and the energy reaches a stable equilibrium state. To improve the recognition accuracy, an interpolation algorithm is used to refine the sampling points, so that the time resolution reaches the picosecond level, and random noise interference is eliminated by averaging multiple measurements. In a preferred embodiment of the present invention, the common node is made of copper and gold-plated. The common node is located at the geometric center of the test load board and is connected to each signal channel in a star topology. Step S4: During the generation of excitation signals for each signal channel, a digital delay is injected according to the compensation delay amount, so that the excitation signals emitted by each signal channel arrive at the target device pin simultaneously after physical transmission. Specifically, during the generation of excitation signals for each signal channel, the compensation delay amount calculated according to the aforementioned steps is injected with corresponding digital delay through a programmable digital delay chip or a high-precision delay unit inside the FPGA. The compensation delay value of each channel is written into the delay control register through an SPI or I2C digital interface. The delay unit precisely controls the output timing of the digital waveform data, with a delay adjustment accuracy of no less than 0.01 nanoseconds. For channels requiring longer delay compensation, a digital first-in-first-out (FIFO) memory is used to implement the basic delay. For channels requiring fine adjustment, digital clock phase interpolation technology is used to achieve sub-nanosecond level delay fine-tuning. After the delay parameters of each signal channel are configured, a synchronous trigger signal is used to ensure that each channel starts transmitting excitation signals simultaneously, so that after transmission over different physical lengths, all signals can arrive at the target device pins simultaneously, achieving strict timing synchronization. In a preferred embodiment of the present invention, the digital delay injection is based on a high-precision digital delay chip, the adjustment accuracy of which is greater than or equal to 0.04 nanoseconds, and the delay time of which is programmed and controlled through an SPI or I2C digital interface, with a minimum step value of 0.01 nanoseconds. In a preferred embodiment of the present invention, obtaining the compensation delay further includes introducing a temperature compensation factor, specifically including: The temperature compensation factor dynamically corrects the compensation delay based on real-time monitored ambient temperature data, using the following formula: T comp =T original ×[1+α×(T current -T ref )], where T comp T represents the amount of compensation delay after compensation. original The compensation delay is the amount of time before compensation, α is the temperature coefficient of the material, and T is the temperature delay before compensation. current This indicates the real-time temperature of the test load board, T. ref This is the preset reference temperature; It is understood that the correction formula is used to calculate the final delay T after temperature compensation. comp The signal propagation delay in a material changes with temperature; therefore, the delay T initially measured at the reference temperature will change. original Dynamic adjustments must be made based on the current actual temperature to ensure the accuracy of compensation under any ambient temperature; Compensated delay T comp This is the output of the formula, and also the temperature-corrected delay that will ultimately be applied to the corresponding signal channel, measured in nanoseconds. Using this value for compensation ensures precise signal synchronization under different temperature conditions; T originalIt is the raw delay difference calculated by TDR measurement at a reference temperature, before temperature compensation. ref Typically at room temperature, such as 25°C, the temperature coefficient α of a material represents the rate at which the delay of the printed circuit board (PCB) trace dielectric material changes with temperature. The unit is parts per million per degree Celsius, or ppm / °C, and it is used to determine the extent to which temperature changes affect the delay.

[0018] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the invention.

Claims

1. A trace delay compensation method based on TDR technology, characterized in that, Includes the following steps: Step S1: Generate a step signal with a preset voltage amplitude, acquire all signal channels, inject the step signal into each signal channel through the test interface; and simultaneously acquire the reflection waveform of each signal channel to obtain a time-domain voltage curve containing reflection characteristics of several impedance discontinuities. Step S2: Identify the first characteristic jump point in the time-domain voltage curve, and obtain the time when the signal is reflected after being transmitted to the common node, which is the first time value; and identify the second characteristic jump point in the time-domain voltage curve, and obtain the time when the signal is transmitted to the electrical endpoint and total reflection occurs and the voltage reaches a stable state, which is the second time value t2; obtain (1 / 2)t2 of the signal channel as the actual transmission delay of the signal channel; Step S3: Compare the actual transmission delay of each signal channel and select the actual transmission delay with the largest value as the reference delay; obtain the difference between the reference delay and the actual transmission delay of each signal channel, and record it as the compensation delay amount of each signal channel; Step S4: During the generation of excitation signals for each signal channel, a digital delay is injected according to the compensation delay amount, so that the excitation signals emitted by each signal channel arrive at the target device pin simultaneously after physical transmission.

2. The trace delay compensation method based on TDR technology according to claim 1, characterized in that, The rise time of the step signal is less than 1 nanosecond, and the voltage amplitude transitions from an initial 0 volt to a preset logic level value. The logic level value is set according to the operating voltage range of the device under test, and the set range is [3.3, 5] volts.

3. The trace delay compensation method based on TDR technology according to claim 1, characterized in that, The process of identifying the first feature transition point and the second feature transition point includes: The voltage change rate of the reflected waveform is monitored in real time. When the voltage change rate exceeds a preset voltage change threshold, it is determined that there is a voltage jump at the current moment, and the point corresponding to the current moment on the reflected waveform is recorded as the voltage jump point. The first voltage jump point identified in the reflected waveform is recorded as the first characteristic jump point, and the last voltage jump point in the reflected waveform when the voltage finally stabilizes at a preset voltage value is recorded as the second characteristic jump point.

4. The trace delay compensation method based on TDR technology according to claim 1, characterized in that, The step signal generation process also includes: Connect the standard short circuit breaker to the common node, and record the reflected waveform acquired during short circuit calibration as the first reference reflected waveform. Determine the inherent delay value of the test path based on the characteristic points of the falling edge of the first reference reflected waveform. Connect the standard open circuit device to the common node. The reflected waveform acquired during open circuit calibration is recorded as the second reference reflected waveform. The accuracy of the inherent delay value is verified by the second reference reflected waveform. If the inherent delay value is verified to be accurate, the inherent delay value is stored. In the process of obtaining the actual transmission delay of the signal channel, the inherent delay value is subtracted from the second time value in advance.

5. A trace delay compensation method based on TDR technology according to claim 1, characterized in that, The digital delay injection is based on a high-precision digital delay chip with an adjustment accuracy greater than or equal to 0.04 nanoseconds. The delay time of the high-precision digital delay chip is programmed and controlled through an SPI or I2C digital interface, and the minimum step value is 0.01 nanoseconds.

6. The trace delay compensation method based on TDR technology according to claim 1, characterized in that, Each signal channel includes a transmission line, connector, and impedance matching element.

7. The trace delay compensation method based on TDR technology according to claim 1, characterized in that, The common node is made of copper and gold-plated. It is located at the geometric center of the test load board and is connected to each signal channel in a star topology.

8. A trace delay compensation method based on TDR technology according to claim 1, characterized in that, Obtaining the compensation delay also includes introducing a temperature compensation factor, specifically including: The temperature compensation factor dynamically corrects the compensation delay based on real-time monitored ambient temperature data, using the following formula: T comp =T original ×[1+α×(T current -T ref )], where T comp T represents the amount of compensation delay after compensation. original The compensation delay is the amount of time before compensation, α is the temperature coefficient of the material, and T is the temperature delay before compensation. current This indicates the real-time temperature of the test load board, T. ref This is the preset reference temperature.

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