Method for detecting and analyzing defects of interconnection hole chain of micro bump bonding integrated chip
By combining a DC probe stage and a dicing device with optical and electron microscopes, this method rapidly detects and analyzes interconnect chain defects in microbump bonded integrated chips, solving the problem of low efficiency in existing technologies and achieving highly efficient defect analysis.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
- Filing Date
- 2026-01-12
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies are inefficient in detecting and analyzing interconnect chain defects in high-density microbump bonded integrated chips, failing to quickly locate the failure sites and impacting production efficiency.
DC electrical tests were performed using a DC probe stage. The cross-sections were then diced and polished using a dicing device. Batch analysis was conducted using optical and electron microscopes to determine the defects in the interconnected hole chain structure.
It enables efficient batch detection and analysis of defects in interconnect chain structures, improving the analysis efficiency of heterogeneous integration and advanced packaged integrated chips.
Smart Images
Figure CN122017667A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor process technology, specifically to a method for detecting and analyzing defects in interconnect hole chains of microbump bonded integrated chips. Background Technology
[0002] Heterogeneous integration of semiconductor chips and 3D packaging technology have become key pathways for the further miniaturization, weight reduction, multifunctionality, and intelligence of electronic components in the post-Moore's Law era. In the process of heterogeneous integration and advanced packaging, semiconductor chips typically require interconnection and integration via microbump bonding. Multiple semiconductor devices or chips are vertically stacked and integrated using interconnect chains formed by metal microbumps, which can reduce system size and weight while simultaneously improving overall performance.
[0003] In recent years, as integrated circuits (ICs) have shrunk in size and increased in functionality, the number of interconnect microbumps has increased while their area and pitch (interconnect spacing) have decreased. Interconnect via chains are achieved through high-precision alignment and bonding of microbumps. However, in actual alignment and bonding processes, alignment deviations caused by equipment or human error, or incorrect interconnections or poor bonding quality due to immature bonding process conditions, often lead to interconnect failure. In narrow-pitch interconnect via chains composed of numerous microbumps, the failure of a single microbump interconnect often results in the failure of the entire IC. Traditional analysis methods for this type of IC failure require analyzing each interconnect portion of every microbump in the bonded interconnect via chain structure individually to locate the failure point, leading to low efficiency in interconnect via chain structure failure analysis and thus affecting the production efficiency of chips with interconnect via chain structures.
[0004] Therefore, there is an urgent need for an efficient method to detect and analyze interconnect chain defects in high-density microbump bonded integrated chips. Summary of the Invention
[0005] The purpose of this application is to provide a method for detecting and analyzing defects in interconnect chain structures of micro-bump bonded integrated chips. Under the premise of completing the fabrication of the bonded integrated interconnect chain structure and confirming the abnormal electrical performance of the bonded integrated interconnect chain structure, the method can achieve the purpose of batch analysis of defects in the bonded integrated interconnect chain structure by dicing and polishing the cross-section. This effectively improves the analysis efficiency of bonding defects in the interconnect chain structure of heterogeneous integrated and advanced packaged integrated chips, thereby solving the problems mentioned in the background art.
[0006] To achieve the purpose of this application, the following technical solution is provided:
[0007] This application provides a method for detecting and analyzing interconnect chain defects in microbump bonded integrated chips. The microbump bonded integrated chip includes multiple sets of interconnect chain structures. Each set of interconnect chain structures is formed by bonding a first bump under metal and a first metal bump located on a first chip to be bonded to a second bump under metal and a second metal bump located on a second chip to be bonded. Interconnect chain test electrodes are formed at both ends of each set of interconnect chain structures. The method for detecting and analyzing interconnect chain defects includes:
[0008] S1, using a DC probe stage, DC electrical tests are performed on each group of interconnection structures via the interconnection chain test electrodes. Based on the DC electrical test data, the interconnection chain structures with short circuits or open circuits are identified and marked.
[0009] S2, using a dicing device that can locate the dicing position, the interconnection chain structure marked with short circuits or open circuits is diced vertically downward from the top of the microbump bonding integrated chip along the transverse center line of the interconnection chain structure to form the cross section of the interconnection chain structure.
[0010] S3, Polish the cross-section of the interconnect hole chain structure using a cross-section polishing device. Specifically, place the micro-bump bonding integrated chip with short circuit or open circuit of the interconnect hole chain structure after dicing into the cross-section polishing device, so that the cross-section of the interconnect hole chain structure exposed by dicing fits against the polishing pad for polishing until the cross-section of the interconnect hole chain structure is flat and smooth.
[0011] S4. After cleaning and polishing, the microbump bonded integrated chip is immersed in acetone and anhydrous ethanol to remove polishing particles and polishing liquid. After immersion, it is rinsed with deionized water and dried with nitrogen or oven.
[0012] S5. Use an optical microscope to examine the cross-section of the interconnect chain structure of the microbump bonded integrated chip after cleaning. Examine the cross-section of the bonding bump formed by the first metal bump and the second metal bump one by one, find the short circuit or open circuit point of the bonding bump and mark it.
[0013] S6. Using an electron microscope, the short circuit or open circuit point of the marked bonding bump is magnified, and a magnified defect photograph is taken. Based on the magnified defect photograph, the specific location and type of the defect in the interconnection chain structure are determined.
[0014] In one embodiment, the step S1 of determining and marking the interconnect chain structure with short circuits or open circuits based on DC electrical test data specifically involves:
[0015] The DC electrical test data includes the test current and test voltage of the interconnect chain structure. Based on the test current and test voltage, the test resistance value of the interconnect chain structure is calculated. The test resistance value is compared with the normal resistance value of the interconnect chain structure. If the test resistance value is more than one order of magnitude larger than the normal resistance value, it is determined that the interconnect chain structure has an open circuit abnormality. If the test resistance value is more than one order of magnitude smaller than the normal resistance value, it is determined that the interconnect chain structure has a short circuit abnormality. Interconnect chain structures with short circuits or open circuits are marked.
[0016] In one embodiment, in S2, the dicing device for locating the dicing position is a grinding wheel dicing machine or a laser dicing machine.
[0017] In one embodiment, in S3, the polishing is mechanical polishing or chemical polishing, and the polishing solution or abrasive used does not chemically react with the electroplated metal of the interconnected hole chain structure.
[0018] In one embodiment, in S4, the microbump bonding integrated chip is immersed in acetone for 5-20 minutes and in anhydrous ethanol for 3-20 minutes.
[0019] In one embodiment, in S6, the electron microscope is a scanning electron microscope, which can magnify the short circuit or open circuit point of the bonding bump to 1000 times or more.
[0020] In one embodiment, this application also provides a method for fabricating a microbump bonding integrated chip interconnect chain structure as follows:
[0021] S1', sputtering metal onto the surface of the first substrate to create the first electroplating seed layer;
[0022] S2', spin-coat photoresist on the first electroplating seed layer, and photolithographically print the metal under the first bump of the interconnection chain structure and the interconnection chain test electrode photolithographic pattern.
[0023] S3', using the photolithographic pattern of the first bump under metal and interconnection chain test electrode, the first bump under metal and interconnection chain test electrode of the interconnection chain structure are electroplated with an electroplating solution;
[0024] S4', the first substrate, after the preparation of the first bump under metal and the interconnection chain test electrode, is placed in acetone and anhydrous ethanol in turn to remove the photoresist and then cleaned and dried.
[0025] S5', spin-coat photoresist onto the surface of the first substrate after cleaning and drying, and photolithographically print the first metal bump pattern;
[0026] S 6', using the photolithographic pattern of the first metal bump, the first metal bump of the interconnecting hole chain structure is electroplated with an electroplating solution;
[0027] S 7', the first substrate of the first bump and the first metal bump of the first metal bump, after the interconnect hole connection structure has been fabricated, are placed in acetone and anhydrous ethanol respectively to remove the photoresist, and then cleaned and dried.
[0028] S8', the exposed first electroplating seed layer is removed sequentially by wet etching or dry etching, the removal order is the opposite of the sputtering order, and after etching is completed, the chip to be bonded is prepared.
[0029] S9', the second chip to be bonded is prepared using the same steps as S1' to S8'. Specifically, the second electroplating seed layer is fabricated on the second substrate using the same steps as S1' to S8', as well as the second under-bump metal and the second metal bump corresponding to the first under-bump metal and the first metal bump.
[0030] S10' After cleaning the first and second chips to be bonded, place them into a hot press bonding machine or flip bonding machine with alignment function, so that the first bump under metal and the first metal bump correspond to the second bump under metal and the second metal bump, respectively, to complete the bonding of the first and second chips to be bonded, and to prepare the microbump bonded integrated chip interconnect chain structure.
[0031] In one embodiment, the first substrate and the second substrate are semiconductor single-crystal substrates or epitaxial substrates, and the semiconductor material is any one or more of Si, GaAs, GaN, SiC or InP.
[0032] In one embodiment, the metal of the first electroplating seed layer and the second electroplating seed layer is any one or more of Au, Cu, and Ni, and the thickness of the first electroplating seed layer and the second electroplating seed layer is not less than 50 nm.
[0033] In one embodiment, the first bump under metal, the first metal bump, the second bump under metal and the second metal bump are electroplated using DC pulse or non-pulse electroplating. The electroplated metal is Au, Cu or Ni, and the bump thickness of the first bump under metal, the first metal bump, the second bump under metal and the second metal bump is not less than 500 nm.
[0034] Compared with the prior art, this application has the following significant technical advantages:
[0035] By performing DC electrical tests on the interconnect chain structure using a DC probe stage, the location of short-circuited or open-circuited interconnect chain structures on the chip can be quickly determined. Simultaneously, using a dicing device, dicing is performed along the transverse centerline of the interconnect chain structure with short circuits or open circuits, completely exposing the cross-sections of the bonding bumps throughout the interconnect chain structure. Combined with an optical microscope, the cross-sections of bonding bumps in the entire interconnect chain structure can be inspected in batches to locate the bonding bumps with short circuits or open circuits. Electron microscopy is then used to magnify and analyze the defects of these abnormal bonding bumps, thus achieving the goal of batch detection and analysis of interconnect chain structure defects. This effectively improves the analysis efficiency of bonding defects in interconnect chain structures of heterogeneous integrated and advanced packaged integrated chips. Attached Figure Description
[0036] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0037] Figure 1 This is a flowchart of a method for detecting and analyzing defects in interconnect links of microbump bonded integrated chips, provided in an embodiment of this application.
[0038] Figure 2 This is a schematic diagram of a microbump bonding integrated chip with interconnect chain structure having short circuits or open circuits after dicing, as provided in an embodiment of this application.
[0039] Figure 3 This is a schematic diagram showing the polishing of a microbump bonding integrated chip with short-circuited or open-circuited interconnect chain structure after dicing, as provided in an embodiment of this application, and the location of interconnect chain defects using SEM.
[0040] Figure 4 This is a schematic diagram of a first electroplating seed layer sputtered on the surface of a first substrate, provided as an embodiment of this application.
[0041] Figure 5 This is a schematic diagram of the photolithographic pattern of the metal under the first bump and the interconnection chain test electrode, which is photolithographically etched on the surface of the first electroplated seed layer according to an embodiment of this application.
[0042] Figure 6 This is a schematic diagram of the metal under the first bump of the interconnection chain structure electroplated on the surface of the first electroplating seed layer and the interconnection chain test electrode, provided in an embodiment of this application.
[0043] Figure 7 This is a schematic diagram of removing photoresist from the surface of a first electroplated seed layer, provided as an embodiment of this application.
[0044] Figure 8This is a schematic diagram of a first metal bump photolithography pattern for photolithographically forming an interconnection chain structure on the surface of a first substrate, provided in an embodiment of this application.
[0045] Figure 9 This is a schematic diagram of a first metal bump on a first substrate electroplated with an interconnecting hole chain structure, provided in an embodiment of this application.
[0046] Figure 10 This is a schematic diagram of a first chip to be bonded formed after removing photoresist and exposing the first electroplating seed layer on a first substrate, according to an embodiment of this application.
[0047] Figure 11 This is a schematic diagram of a second chip to be bonded, provided in an embodiment of this application.
[0048] Figure 12 This is a schematic diagram illustrating the bonding and integration of a first chip to be bonded and a second chip to be bonded after fabrication, according to an embodiment of this application.
[0049] In the figure: 1. First substrate; 2. First electroplating seed layer; 3. Photolithographic pattern of the metal under the first bump and the interconnect chain test electrode; 4. Metal under the first bump; 5. Photolithographic pattern of the first metal bump; 6. First metal bump; 7. Second metal bump; 8. Metal under the second bump; 9. Second electroplating seed layer; 10. Second substrate; 11. Cross-section of the interconnect chain structure; 12. Short circuit or open circuit point of the bonding bump; 13. Interconnect chain test electrode; 14. Interconnect chain structure; 15. First chip to be bonded; 16. Second chip to be bonded. Detailed Implementation
[0050] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.
[0051] It should also be noted that, for ease of description, the accompanying drawings show only the parts relevant to this application, not the entire structure. Throughout this specification, the same or similar reference numerals represent the same or similar structures, elements, or processes. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.
[0052] The terms “first” and “second” as used in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as “first” and “second” may explicitly or implicitly include one or more of that feature. Furthermore, the term “comprising” and any derivative thereof are intended to cover non-exclusive inclusion.
[0053] like Figure 1 and Figure 2 As shown, this application discloses a method for detecting and analyzing interconnect hole chain defects in a microbump bonded integrated chip. The microbump bonded integrated chip includes multiple sets of interconnect hole chain structures 14. Each set of interconnect hole chain structures 14 is formed by bonding a first bump under metal 4 and a first metal bump 6 located on a first chip to be bonded 15 with a second bump under metal 8 and a second metal bump 7 located on a second chip to be bonded 16. Interconnect hole chain test electrodes 13 are formed at both ends of each set of interconnect hole chain structures 14.
[0054] Specifically, the detection and analysis method for interconnect hole chain defects in this microbump bonded integrated chip includes the following steps:
[0055] Step 1: Perform DC electrical tests on each group of interconnect via structures 14 using a DC probe station. Based on the DC electrical test data, identify and mark interconnect via structures 14 with short circuits or open circuits. In one embodiment, the microbump bonding integrated chip with interconnect via structures 14 is subjected to on-chip DC electrical tests on the interconnect via structures 14 using a DC probe station. Record the test current and voltage values of the interconnect via structure 14. Calculate the test resistance value of the interconnect via structure 14 using the test current and voltage values. Compare the test resistance value with the normal resistance value of the interconnect via structure 14. If the test resistance value is more than one order of magnitude (10 times) larger than the normal resistance value, it can be determined that the interconnect via structure 14 has an open circuit abnormality. If the test resistance value is more than one order of magnitude (10 times) smaller than the normal resistance value, it can be determined that the interconnect via structure 14 has a short circuit abnormality. Locate and mark the interconnect via structures 14 with short circuits or open circuits. In one embodiment, the DC probe station can be a two-probe test station, a four-probe test station, or other probe station that can characterize the DC characteristics of the bonded interconnect chain.
[0056] Step two: Using a dicing device capable of dicing positions, the interconnect via chain structure 14 marked with short circuits or open circuits is diced vertically downwards from the top of the microbump bonding integrated chip, along the transverse centerline of the interconnect via chain structure 14, to form the interconnect via chain structure cross-section 11, as shown below. Figure 2As shown. In one embodiment, the bonded chip with the interconnect via chain structure 14 having a short circuit or an open circuit is placed in a dicing machine or laser dicing machine that can locate the dicing position. The short circuit or open circuit interconnect via chain structure 14 marked in step one is found. The dicing mark side is moved to the center of the bonding bump formed by the bonding of the first metal bump 6 and the second metal bump 7, and dicing is performed with a grinding wheel or laser. In order to ensure that the interconnect via chain structure can be polished and observed by SEM in the future, it is necessary to ensure that 1 / 3 of the interconnect via chain structure remains intact after dicing.
[0057] Step 3: Polish the cross-section 11 of the interconnect via chain structure using a cross-section polishing device. Specifically, after dicing, the bonded integrated chip with short-circuited or open-circuited interconnect via chain structure 14 is fixed to the cross-section polishing device by means of bonding or mechanical clamping, and the exposed cross-section 11 of the interconnect via chain structure is kept flush with the polishing pad for polishing until the cross-section 11 of the interconnect via chain structure is flat and smooth. In one embodiment, polishing can be selected from mechanical polishing or chemical mechanical polishing. The polishing solution or abrasive should not chemically react with the electroplated metal of the interconnect via chain structure 14. The polished cross-section of the bonded integrated chip with short-circuited or open-circuited interconnect via chain structure 14 is as follows: Figure 3 As shown.
[0058] Step four involves cleaning the polished microbump bonded integrated chip. Specifically, the polished chip is removed from the polishing fixture by heating or opening the clamping jig, and then immersed in acetone and anhydrous ethanol to remove polishing particles and polishing fluid. After immersion, it is rinsed with deionized water and then dried with nitrogen or by baking. In one embodiment, the immersion time in acetone is 5-20 minutes, and the immersion time in anhydrous ethanol is 3-20 minutes.
[0059] Step 5: Use an optical microscope to examine the cross-section 11 of the cleaned interconnection chain structure. Specifically, place the microbump bonded integrated chip with short-circuit or open-circuit interconnection chain structure 14 after polishing and cleaning on the optical microscope platform, and examine the cross-section of the bonding bumps formed by the first metal bump 6 and the second metal bump 7 one by one. Mark the short-circuit or open-circuit points 12 where there are bonding bumps.
[0060] Step six: Use an electron microscope to analyze the bonding defects of the entire interconnect chain structure cross section 11. Specifically, place the bonded integrated chip with short-circuited or open-circuited interconnect chain structure 14, which has been polished, into a scanning electron microscope and fix it in place. Locate the positioning marks of the short-circuit or open-circuit points 12 of the bonding bumps. Magnify the short-circuit or open-circuit points 12 of the bonding bumps more than 1000 times using an electron microscope and scan and take defect photos. Based on the magnified defect photos, determine the specific location and type of interconnect chain structure defects (mainly including bonding interface gaps, voids, or incorrect interconnection of bumps), thereby completing the efficient analysis of interconnect chain defects in the bonding integration process.
[0061] This application also proposes a method for fabricating interconnect chains of microbump bonding integrated chips, including the following steps:
[0062] Step A: Form a first electroplating seed layer 2 on the surface of the first substrate 1. Specifically, clean the first substrate 1 by immersing it in acetone and anhydrous ethanol for 5-20 minutes and 3-20 minutes respectively. After immersion, rinse with deionized water and then dry with nitrogen or oven. Then, sputter metal onto the surface of the first substrate 1 to form the first electroplating seed layer 2. The sputtered first electroplating seed layer metal is Ti / Au / Ti or WTi / Au / Ti. The first substrate 1 is a semiconductor single crystal substrate or an epitaxial substrate, and the semiconductor material is any one or more of Si, GaAs, GaN, SiC or InP.
[0063] In one embodiment, the sputtered first resistive seed layer metal is Au, and its thickness is not less than 50 nm, to ensure that the metal under the first bump and the interconnect chain test electrode can be electroplated, such as... Figure 4 As shown.
[0064] Step B: Photolithographically pattern 3 of the metal under the first bump and the interconnection chain test electrode of the interconnection chain structure 14 is formed on the first electroplating seed layer 2. Specifically, photoresist is spin-coated onto the front side of the first chip to be bonded 1. The spin-coating speed is set to 1000-5000 rpm and the spin-coating time is 30s-1min, depending on the required thickness. The first chip to be bonded 15 with the photoresist coated is placed face up on a clean hot plate for pre-baking. The hot plate temperature is set to 110-150℃ and the time is 1-4min. After baking, exposure is performed using a contact lithography machine or a stepper lithography machine. The specific exposure dose depends on the type and thickness of the photoresist. After exposure, development and post-baking are performed. The photolithographic pattern 3 of the metal under the first bump and the interconnection chain test electrode is observed under a microscope to confirm that the photolithographic pattern 3 of the metal under the first bump and the interconnection chain test electrode is intact. Figure 5As shown. Among them, the types of photoresists include, but are not limited to, AZ4562, AZ4620, AZ701, AZ7908, and 10XT.
[0065] Step C: Using the photolithographic pattern 3 of the first bump under-metal and interconnect chain test electrode, the first bump under-metal and interconnect chain test electrode 13 of the interconnect chain structure 14 are electroplated. Specifically, the first substrate 1 of the prepared first electroplating seed layer 2 and the photolithographic pattern 3 of the first bump under-metal and interconnect chain test electrode 13 is placed into the Au electroplating solution through a suitable electroplating fixture, and a constant DC current of 0.5-10mA is passed through. The magnitude of the current is determined according to the proportion of the required electroplating pattern to the entire chip seed layer area. Electroplating is performed for 10-100 minutes to electroplat the first bump under-metal and interconnect chain test electrode 13 of the interconnect chain structure. Figure 6 As shown.
[0066] Step D, Removing the front photoresist from the first substrate: The metal 4 under the first bump of the interconnect chain structure 14 and the first substrate 1, after the interconnect chain test electrode 13 structure has been fabricated, are successively immersed in acetone and anhydrous ethanol to remove the front photoresist. The acetone immersion time is 5-20 minutes, and the ethanol immersion time is 3-20 minutes. After immersion, rinse with deionized water, and then dry with nitrogen or by baking. Figure 7 As shown.
[0067] Step E: On the first substrate 1 where the structure of the first bump under the metal 4 and the interconnect chain test electrode 13 has been fabricated, a photolithographic pattern 5 of the first metal bump of the interconnect chain structure 14 is photolithographically etched. Specifically, photoresist is spin-coated onto the front side of the first substrate 1 where the structure of the first bump under the metal 4 and the interconnect chain test electrode 13 has been fabricated. The thickness of the spin-coated photoresist should be greater than the sum of the heights of the first metal bump under the first bump and the first metal bump. The spin-coating speed is set to 1000-5000 rpm, and the spin-coating time is 30s-1min, depending on the required thickness. The first substrate 1 to be bonded, with the photoresist coated, is placed face up on a clean hot plate for pre-baking. The hot plate temperature is set to 110-150℃, and the time is 1-4min. After baking, exposure is performed using a contact lithography machine or a stepper lithography machine. The specific exposure dose depends on the type and thickness of the photoresist. After exposure, development and post-baking are performed. The first metal bump photolithographic pattern 5 is observed under a microscope to confirm its integrity. Figure 8 As shown. Among them, the types of photoresists include, but are not limited to, AZ4562, AZ4620, AZ701, AZ7908, and 10XT.
[0068] Step F involves electroplating the first metal bump 6 using the photolithographic pattern 5 of the first metal bump. Specifically, the first substrate 1 with the photolithographic pattern 5 is placed into the Au electroplating solution using a suitable electroplating fixture. A constant DC current of 0.5-10mA is applied, with the current determined based on the proportion of the desired electroplating pattern to the entire seed layer area of the chip. Electroplating is performed for 10-100 minutes to electroplat the first metal bump 6. Figure 9 As shown.
[0069] Step G: Remove the photoresist on the front side of the first substrate 1. Specifically, the first substrate 1, after the first metal bump structure 6 of the interconnection chain structure 14 has been fabricated, is placed in acetone and anhydrous ethanol in turn to remove the photoresist on the front side. The acetone soaking time is 5-20 minutes and the ethanol soaking time is 3-20 minutes. After soaking, it is rinsed with deionized water and then dried with nitrogen or oven.
[0070] Step H involves removing the first electroplating seed layer 2 from the first substrate 1. Specifically, excess exposed first electroplating seed layer metal 2 is removed sequentially using a wet etching process or a dry etching process. The removal order is the reverse of the sputtering order. After etching, the substrate is cleaned to complete the fabrication of the first chip to be bonded 15. Figure 10 As shown.
[0071] Step I: Fabricate the second chip to be bonded 16. Specifically, using the same steps as in step AH, fabricate a second electroplating seed layer 9 on the second substrate 10, as well as a second under-bump metal 8 and a second metal bump 7 corresponding to the first under-bump metal 4 and the first metal bump 6, as shown below. Figure 11 As shown. In one embodiment, the first substrate 1 and the second substrate 10 are semiconductor single crystal substrates or epitaxial substrates, and the semiconductor material is any one or more of Si, GaAs, GaN, SiC, and InP.
[0072] Step J involves bonding the first integrated chip 15 and the second integrated chip 16 to be bonded, which have been prepared above. Specifically, after cleaning, the first chip 15 and the second chip 16 with the interconnect chain structure are placed in a hot press bonding machine or flip-chip bonding machine with alignment function, so that the metal under the first bump 4 and the first metal bump 6 correspond to the metal under the second bump 8 and the second metal bump 7, respectively, for alignment bonding. The bonding method can be any one of metal hot press bonding, metal eutectic bonding, or metal melt bonding, such as... Figure 12 As shown
[0073] In one embodiment, the thickness of the first bump under metal 4, the first metal bump 6, the second bump under metal 8, and the second metal bump 7 is not less than 500 nm, so as to allow for later observation of the bonding bumps.
[0074] To more clearly illustrate the technical solution of this application, the following detailed description is provided in conjunction with specific embodiments.
[0075] This embodiment provides a method for fabricating a microbump bonded integrated circuit interconnect chain structure and a method for detecting and analyzing defects in the microbump bonded integrated circuit interconnect chain fabricated by this method, as detailed below:
[0076] Step 1) Fabricate a first electroplating seed layer on the front side of the first substrate. Specifically, the material of the first substrate is Si. The first substrate is cleaned by immersing it in acetone and anhydrous ethanol successively, with the acetone immersion time being 5 minutes and the ethanol immersion time being 3 minutes. After immersion, the first substrate is rinsed with deionized water and then dried with nitrogen. Ti / Au / Ti is sputtered on the front side of the first substrate using a magnetron sputtering stage as a seed layer for the first electroplating of Au, wherein the thicknesses of the three metal layers are 20 / 50 / 20 nm, respectively.
[0077] Step 2) Spin-coat a 4μm layer of 10XT photoresist onto the front side of the first substrate after the first Au electroplating seed layer has been fabricated. The spin-coating speed is 2400 rpm, and the spin-coating time is 40 s. After spin-coating, place the chip face up on a hot plate protected with lint-free paper for pre-baking. The hot plate temperature is set to 110℃ for 3 minutes. After baking, expose the chip using a contact lithography machine with an exposure dose of 500 mJ / cm². 2 After exposure, the substrate was developed with 3038 developer for 200 seconds. Then, the substrate was baked with the front side facing up on a heat plate at 110°C for 120 seconds. The photolithographic pattern of the metal under the first bump and the interconnection chain test electrode was observed under a microscope, and it was confirmed that the photolithographic pattern of the metal under the first bump and the interconnection chain test electrode was intact.
[0078] Step 3) Place the first substrate with the photolithographic pattern of the first bump under metal and interconnect chain test electrode into the Au electroplating solution through a suitable electroplating fixture, pass a constant DC current of 10mA through it, monitor the electroplating rate, remove it after electroplating for 50 minutes, rinse the surface of the electroplating solution, measure the electroplating step using a step meter, and confirm that the first bump under metal and interconnect chain test electrode with a total height of 2μm have been electroplated.
[0079] Step 4) The first substrate with the first bump under metal and interconnect chain test electrode structure completed is placed in acetone and anhydrous ethanol to remove 10XT photoresist. The acetone soaking time is 5 min and the ethanol soaking time is 3 min. After soaking, it is rinsed with deionized water and then dried with nitrogen.
[0080] Step 5) Spin-coat a 4μm layer of 10XT photoresist onto the front side of the first substrate after the fabrication of the metal under the first bump and the interconnect chain test electrodes. The spin-coating speed is 2400 rpm, and the spin-coating time is 40 s. After spin-coating, place the chip face up on a hot plate protected with lint-free paper for pre-baking. The hot plate temperature is set to 110℃ for 3 minutes. After baking, expose the chip using a contact lithography machine with an exposure dose of 500 mJ / cm². 2 After exposure, the chip was developed with 3038 developer for 200 seconds. Then, the chip was baked with the front side facing up on a heat plate at a temperature of 110°C for 120 seconds. The photolithographic pattern of the first metal bump was observed under a microscope to confirm that the photolithographic pattern of the first metal bump was intact.
[0081] Step 6) Place the first substrate with the first metal bump photolithographic pattern into the Au electroplating solution through a suitable electroplating fixture, pass a constant DC current of 10mA through it, monitor the electroplating rate, take it out after electroplating for 50 minutes, rinse the surface electroplating solution clean, measure the electroplating steps with a step meter, and confirm that the first metal bump of the interconnect hole chain structure with a total height of 2μm has been electroplated.
[0082] Step 7) The first substrate with the first bump under the interconnect chain structure and the first metal bump structure is placed in acetone and anhydrous ethanol respectively to remove the 10XT photoresist. The acetone soaking time is 5 minutes and the ethanol soaking time is 3 minutes. After soaking, rinse with deionized water and then blow dry with nitrogen.
[0083] Step 8) Place the first substrate cleaned in step 7) into 10% HF acid to etch Ti. After it is completely discolored, take it out and clean it. Then place it into a mixed solution of I and KI to etch Au. After it is completely discolored, take it out and clean it. Finally, etch Ti again with 10% HF acid. After it is completely discolored, take it out and clean it. Then blow it dry with nitrogen to complete the fabrication of the first Si chip to be bonded.
[0084] Step 9) The second chip to be bonded is fabricated using the same steps as steps 1) to 8). Specifically, a second electroplating seed layer is fabricated on the second substrate, as well as the second bump under metal and the second metal bump corresponding to the interconnection hole chain structure of the first bump under metal and the second metal bump. The second chip to be bonded is a GaAs chip.
[0085] Step 10) After cleaning the Si chip and GaAs chip prepared above, place them into a hot press bonding machine with alignment function. Edit the hot press bonding machine recipe, set the bonding temperature to 200℃, the bonding pressure to 500N, and the holding time to 5min. Execute the hot press bonding recipe to complete the bonding of the Si chip and GaAs chip, and prepare the microbump bonded integrated chip interconnect chain structure.
[0086] Step 11) Place the bonded chip into a two-probe DC probe station and press the two probes onto the test electrodes on both sides of the interconnect chain structure. Apply a voltage of 0-20V to the bonded interconnect chain structure with a voltage step value of 100mV, and test and record the current results after applying the voltage.
[0087] Step 12) Calculate the resistance value of the interconnect chain structure based on the recorded current results, and compare the test resistance value with the normal resistance value to see if there is a difference of orders of magnitude. If the test value is more than one order of magnitude larger than the normal value, it is determined that the interconnect chain structure has an open circuit abnormality. If the test value is more than one order of magnitude smaller than the normal value, it is determined that the interconnect chain structure has a short circuit abnormality. Mark the location of the abnormal interconnect chain structure.
[0088] Step 13) After bonding Si with GaAs and the chip with short-circuited or open-circuited interconnect chain structure, place it into a dicing machine with a dicing wheel that can locate the dicing position. Locate the marked short-circuited or open-circuited interconnect chain structure using a dicing machine microscope. Starting from the top of the bonded chip, dicing is performed vertically downward along the transverse center line of the interconnect chain structure to form the cross-section of the interconnect chain structure.
[0089] Step 14) After bonding Si and GaAs with short-circuited or open-circuited interconnect chain structures, paraffin wax is applied to one side of the chip. After coating, the chip is placed on a cross-section polishing fixture and fixed by heating and cooling the paraffin wax. During fixation, the cross-section of the interconnect chain structure of the Si-GaAs bonded integrated chip is kept flush with the polishing pad.
[0090] Step 15) Place the Si and GaAs bonded integrated chip with short-circuited or open-circuited interconnect chain structure, which has been diced and mounted on the cross-section polishing fixture, into the cross-section polishing equipment so that the cross-section of the bonded interconnect chain exposed by dicing can fit with the polishing disk. Set the polishing speed to 1000 rpm and add diamond suspension polishing fluid with a particle diameter of 0.5 μm to polish the interconnect chain structure of the bonded integrated chip until the cross-section of the interconnect chain structure is flat and smooth.
[0091] Step 16) After polishing, remove the cross-section polishing fixture from the polishing machine and place it on a 100°C heating table for heating until the paraffin wax is completely melted. Remove the Si-GaAs bonded integrated chip that has been polished and place it in acetone and anhydrous ethanol to remove polishing particles and polishing liquid. The acetone soaking time is 5-20 minutes and the ethanol soaking time is 3-20 minutes. After soaking, rinse with deionized water and then blow dry with nitrogen or dry it.
[0092] Step 17) Place the Si-GaAs bonded integrated chip with short-circuit or open-circuit interconnect chain structure that has been polished on an optical microscope platform for cross-sectional inspection. Locate the bonding bumps formed by the first metal bump and the second metal bump in the interconnect chain structure and inspect them one by one. If any abnormalities such as gaps or misalignments of the bonding bumps are found under the microscope, mark the abnormalities with a marker to locate the short-circuit or open-circuit points.
[0093] Step 18) Fix the Si-GaAs bonded integrated chip with short-circuited or open-circuited interconnect chain structure, which has been polished, onto a conductive tape and place it in the vacuum chamber of a scanning electron microscope. Locate the abnormal points marked with a marker pen, magnify the short-circuited or open-circuited points 5000 times using an electron microscope, scan and take defect photos, and complete the analysis of interconnect chain defects in the bonding integration process based on the magnified defect photos.
[0094] As can be seen from the above embodiments, this application uses a DC probe stage to perform DC electrical testing on the interconnect chain structure, which can quickly determine the location of short-circuited or open-circuited interconnect chain structures on the chip. At the same time, by using a dicing device to dice along the transverse centerline of the interconnect chain structure with short circuits or open circuits, the cross-section of the bonding bumps in the entire interconnect chain structure can be completely exposed. Combined with an optical microscope, the cross-section of the bonding bumps in the entire interconnect chain structure can be inspected in batches to find the bonding bumps with short circuits or open circuits. The defects of the abnormal bonding bumps can be magnified and analyzed using an electron microscope, thereby achieving the purpose of batch detection and analysis of interconnect chain structure defects, effectively improving the analysis efficiency of bonding defects in interconnect chain structures of heterogeneous integrated and advanced packaged integrated chips.
[0095] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.
Claims
1. A method for detecting and analyzing defects in interconnect via chains of microbump bonded integrated circuits, characterized in that, The microbump bonding integrated chip includes multiple interconnection chain structures (14). Each interconnection chain structure (14) is formed by bonding a first bump under metal (4) and a first metal bump (6) on a first chip to be bonded (15) to a second bump under metal (8) and a second metal bump (7) on a second chip to be bonded (16). Interconnection chain test electrodes (13) are formed at both ends of each interconnection chain structure (14). The method for detecting and analyzing interconnection chain defects includes: S1. Using a DC probe stage, DC electrical tests are performed on each group of interconnection structures (14) via the interconnection chain test electrode (13). Based on the data from the DC electrical tests, the interconnection chain structures (14) that have short circuits or open circuits are identified and marked. S2, using a dicing device that can locate the dicing position, the interconnection chain structure (14) marked with short circuits or open circuits is diced vertically downward from the top of the microbump bonding integrated chip along the transverse center line of the interconnection chain structure (14) to form the interconnection chain structure cross section (11). S3, the cross section (11) of the interconnection hole chain structure is polished using a cross section polishing device. Specifically, the micro-bump bonding integrated chip with short circuit or open circuit of the interconnection hole chain structure (14) after dicing is placed into the cross section polishing device, so that the cross section (11) of the interconnection hole chain structure exposed by dicing is in contact with the polishing disk for polishing until the cross section (11) of the interconnection hole chain structure is flat and smooth. S4. After cleaning and polishing, the microbump bonded integrated chip is immersed in acetone and anhydrous ethanol to remove polishing particles and polishing liquid. After immersion, it is rinsed with deionized water and dried with nitrogen or oven. S5, use an optical microscope to examine the cross-section (11) of the interconnection chain structure of the microbump bonded integrated chip after cleaning, examine the cross-section of the bonding bump formed by the first metal bump (6) and the second metal bump (7) one by one, find the short circuit or open circuit point (12) of the bonding bump and mark it. S6. Using an electron microscope, the short circuit or open circuit point (12) of the marked bonding bump is magnified, and a magnified defect photograph is taken. Based on the magnified defect photograph, the specific location and type of the defect in the interconnection hole chain structure are determined.
2. A method for detecting and analyzing defects in interconnect via chains of microbump bonded integrated chips as described in claim 1, characterized in that, The process described in S1, which involves determining and marking interconnection chain structures (14) with short circuits or open circuits based on DC electrical test data, specifically includes: The DC electrical test data includes the test current and test voltage of the interconnection chain structure (14). Based on the test current and test voltage, the test resistance value of the interconnection chain structure (14) is calculated. The test resistance value is compared with the normal resistance value of the interconnection chain structure (14). If the test resistance value is more than one order of magnitude larger than the normal resistance value, it is determined that the interconnection chain structure (14) has an open circuit abnormality. If the test resistance value is more than one order of magnitude smaller than the normal resistance value, it is determined that the interconnection chain structure (14) has a short circuit abnormality. Interconnection chain structures (14) with short circuits or open circuits are marked.
3. A method for detecting and analyzing defects in interconnect via chains of microbump bonded integrated chips as described in claim 1, characterized in that, In S2, the dicing device that can locate the dicing position is a grinding wheel dicing machine or a laser dicing machine.
4. A method for detecting and analyzing defects in interconnect via chains of microbump bonded integrated chips as described in claim 1, characterized in that, In S3, the polishing is mechanical polishing or chemical polishing, and the polishing solution or abrasive used does not chemically react with the electroplated metal of the interconnected hole chain structure (14).
5. A method for detecting and analyzing defects in interconnect via chains of microbump bonded integrated chips as described in claim 1, characterized in that, In S4, the microbump bonding integrated chip is immersed in acetone for 5-20 minutes and in anhydrous ethanol for 3-20 minutes.
6. A method for detecting and analyzing defects in interconnect via chains of microbump bonded integrated chips as described in claim 1, characterized in that, In S6, the electron microscope is a scanning electron microscope, which can magnify the short circuit or open circuit point (12) of the bonding bump to 1000 times or more.
7. A method for detecting defects in interconnect via chains of microbump bonded integrated chips as described in claim 1, characterized in that, The fabrication method of the interconnect chain structure of the micro-bump bonding integrated chip is as follows: S1', sputter metal onto the surface of the first substrate (1) to form the first electroplating seed layer (2). S2', spin-coat photoresist on the first electroplating seed layer (2) and photolithographically print the first bump under metal and interconnection test electrode photolithographic pattern (3) of the interconnection chain structure (14). S3', using the photolithographic pattern (3) of the first bump under metal and interconnection chain test electrode, the first bump under metal (4) and interconnection chain test electrode (13) of the interconnection chain structure (14) are electroplated by electroplating solution. S4', the first substrate (1) that has completed the preparation of the first bump under metal (4) and the interconnection chain test electrode (13) is placed in acetone and anhydrous ethanol in turn to remove the photoresist and then clean and dry it. S5', spin-coat photoresist on the surface of the first substrate (1) after cleaning and drying, and photolithographically print the first metal bump pattern (5). S 6', using the first metal bump photolithography pattern (5), the first metal bump (6) of the interconnection hole chain structure (14) is electroplated with an electroplating solution. S 7', the first substrate (1) with the first bump under metal (4) and the first metal bump (6) of the interconnect hole connection structure (14) is placed in acetone and anhydrous ethanol to remove the photoresist, and then cleaned and dried. S8', the exposed first electroplating seed layer (2) is removed sequentially by wet etching or dry etching. The removal order is the opposite of the sputtering order. After etching, the chip is cleaned and dried to prepare the first chip to be bonded (15). S9', the second chip to be bonded (16) is prepared using the same steps as S1' to S8'. Specifically, the second electroplating seed layer (9) and the second bump under metal (8) and the second metal bump (7) corresponding to the first bump under metal (4) and the first metal bump (6) are prepared on the second substrate (10) using the same steps as S1' to S8'. S10' After cleaning the first chip to be bonded (15) and the second chip to be bonded (16) that have been prepared, place them into a hot press bonding machine or flip bonding machine with alignment function, so that the first bump under metal (4) and the first metal bump (6) correspond to the second bump under metal (8) and the second metal bump (7) respectively, and complete the bonding of the first chip to be bonded (15) and the second chip to be bonded (16), and prepare the microbump bonded integrated chip interconnect hole chain structure.
8. A method for detecting defects in interconnect via chains of microbump bonded integrated chips as described in claim 7, characterized in that, The first substrate (1) and the second substrate (10) are semiconductor single crystal substrates or epitaxial substrates, and the semiconductor material is any one or more of Si, GaAs, GaN, SiC or InP.
9. A method for detecting defects in interconnect via chains of microbump bonded integrated chips as described in claim 7, characterized in that, The electroplating seed layer metal of the first electroplating seed layer (2) and the second electroplating seed layer (9) is any one or more of Au, Cu, and Ni, and the thickness of the first electroplating seed layer (2) and the second electroplating seed layer (9) is not less than 50 nm.
10. A method for detecting interconnect chain defects in microbump bonded integrated chips as described in claim 7, characterized in that, The first bump under metal (4), the first metal bump (6), the second bump under metal (8) and the second metal bump (7) are electroplated using DC pulse or non-pulse electroplating. The electroplated metal is Au, Cu or Ni. The bump thickness of the first bump under metal (4), the first metal bump (6), the second bump under metal (8) and the second metal bump (7) is not less than 500 nm.