Complex modulation signal generation method based on multiphase fitting modeling

Abstract

The invention particularly relates to a complex modulation signal generation method based on multiphase fitting modeling, belongs to the field of radars, and is applied to a radar frequency synthesizer. The method comprises the following steps: by taking an FPGA (Field Programmable Gate Array) and a DAC (Digital-to-Analog Converter) as core hardware, generating an n-phase phase increment sequence through multi-phase fitting modeling according to the phase change characteristics of CW, LFM and NLFM signals and the phase-to-amplitude conversion IP instantiation number of the FPGA; amplitude codes are output through multiple paths of IPs, and after cross sorting is carried out according to the phase relation, the amplitude codes are transmitted to a DAC through an LVDS or JESD204B / C high-speed interface to generate a target signal. According to the method, signal phase characteristics are fitted in a targeted manner, phase increment can be calculated in real time through LFM signal generation, storage is not occupied additionally, the three types of signals are consistent in processing flow, high in universality and easy to transplant, and high-stability and high-precision complex modulation signals can be generated efficiently.

Description

Technical Field

[0001] This invention relates to the field of radar technology, and specifically to a method for generating complex modulation signals based on multiphase fitting modeling. Background Technology

[0002] In radar systems, the frequency synthesizer occupies a central position. Its core function is to generate highly stable, high-precision, and flexibly controllable radio frequency signals. The performance of these signals directly determines the overall performance of the radar system. The generation of complex modulation signals (such as linear frequency modulated signals (LFM), nonlinear frequency modulated signals (NLFM), and continuous wave (CW) signals) is one of the key tasks of the frequency synthesizer, and is crucial to the radar's detection accuracy and anti-jamming capabilities.

[0003] Currently, solutions based on hardware such as DACs (Digital-to-Analog Converters), DDS (Direct Digital Synthesizers), VCOs (Voltage-Controlled Oscillators), and PLLs (Phase-Locked Loops) have become the mainstream methods for generating complex modulation signals. With the rapid development of integrated semiconductor technology, FPGAs (Field-Programmable Gate Arrays) and DAC-type devices have made breakthroughs, possessing flexible IP cores, abundant high-speed interfaces (such as LVDS and JESD204B / C), and continuously improving data transmission rates. This provides ample space for innovation in complex modulation signal generation technology and promotes the continuous expansion of related technical routes. However, existing technologies still have some shortcomings in the process of generating complex modulation signals. For example, some solutions have poor adaptability to different types of signals, LFM signal generation requires additional storage space, and portability is poor, limiting their widespread application and performance improvement in radar systems.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned shortcomings of the prior art and provide a method for generating complex modulation signals based on multiphase fitting modeling. Using general-purpose hardware (FPGA, DAC) and its abundant resources (IP cores, high-speed interfaces, etc.) as a platform, this invention achieves efficient generation of various complex modulation signals such as CW, LFM, and NLFM through phase fitting modeling. At the same time, it solves the problems of poor versatility, high storage consumption, and difficulty in porting in the prior art.

[0006] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0007] According to a first aspect of the present invention, a method for generating complex modulation signals based on multiphase fitting modeling is provided. The main circuit components include an FPGA and a DAC. The specific implementation steps are as follows: Step 1: Based on the phase change characteristics of the signal form and the number n of phase-amplitude conversion IP instantiations in the FPGA, generate an n-phase phase increment sequence through multiphase fitting modeling; the signal form includes CW signal, LFM signal and NLFM signal; Step 2: Output amplitude codes from multiple IP channels; Step 3: Cross-sort the amplitude codes according to the phase change relationship to obtain the signal amplitude change sequence; Step 4: Send the sorted amplitude codes to the DAC, which generates a complex modulation signal of the desired frequency; the complex modulation signal includes continuous wave (CW), linear frequency modulation (LFM), and nonlinear frequency modulation (NLFM).

[0008] In some exemplary embodiments, the principle for determining the number of IP instantiations n is that the IP clock clk rate is ≤250MHz.

[0009] In some exemplary embodiments, the phase increment is quantized as follows:

[0010] in, Based on whether the signal is a constant or a sequence that changes over time.

[0011] In some exemplary embodiments, the CW signal generation is specifically implemented as follows: The initial phase of the first channel is 0, and the phase increment is a constant value, which is used as the input of IP1. The initial phase of the second channel is a specific value, and the phase increment is a constant value, which is used as the input of IP2. Similarly, the initial phase of the nth path corresponds to a specific value, the phase increment is a constant value, and it is used as the input of IPn. The time axis is based on a preset reference. After the output amplitude data of IP1 to IPn are sorted by corresponding phase and cross-sorted, they are output to the DAC at a data rate of n×clk. The DAC generates a CW signal with the corresponding output frequency.

[0012] In some exemplary embodiments, for LFM signal generation, since the phase increment change has a constant acceleration characteristic, the specific implementation method is as follows: Taking n-phase as an example, the initial phase of the first path is 0, and the phase increment is the corresponding change form, which is used as the input of IP1; The initial phase of the second path is a specific value, and the phase increment is the corresponding change form, which is used as the input of IP2; Similarly, the initial phase of the nth path corresponds to a specific value, and the phase increment corresponds to the change form, which is used as the input of IPn, with the time axis based on a preset reference; The output amplitude data of IP1 to IPn are sorted by corresponding phase and then cross-sorted. They are then output to the DAC at a data rate of n×clk, and the DAC generates an LFM signal with the corresponding output frequency.

[0013] In some exemplary embodiments, for NLFM signal generation, due to the nonlinear characteristics of phase change, the specific implementation method is as follows: The phase sequence is pre-calculated in MATLAB and then grouped. The first path uses the corresponding phase sequence after grouping as the input to IP1; The second path uses the corresponding phase sequence after grouping as the input to IP2; Similarly, the nth path uses the corresponding phase sequence after grouping as the input to IPn; The output amplitude data of IP1 to IPn are sorted by corresponding phase and then cross-sorted. They are then output to the DAC at a data rate of n×clk, and the DAC generates an NLFM signal with the corresponding output frequency.

[0014] In some exemplary embodiments, the sorted amplitude codes are sent to the DAC via an LVDS or JESD204B / C high-speed interface.

[0015] In some exemplary embodiments, the DAC includes a parallel DAC and a serial DAC, the parallel DAC being based on an LVDS interface and the serial DAC being based on a JESD204B / C interface.

[0016] In some exemplary embodiments, the expression for the desired frequency is:

[0017] in, This is the IP operating clock.

[0018] The complex modulation signal generation method based on multiphase fitting modeling provided by the embodiments of the present invention has the following advantages compared with the prior art: 1. This invention performs targeted phase fitting modeling on the phase change characteristics of complex modulation signals, which can accurately match the phase change patterns of different types of complex modulation signals and ensure the accuracy of signal generation. 2. During the LFM signal generation process, the phase increment can be calculated in real time based on the "constant acceleration" characteristic, eliminating the need to pre-store a large amount of phase data, which greatly saves storage space and improves the real-time performance of signal generation; 3. This method emphasizes software-based processing logic. The generation and processing flow of different types of signals such as CW, LFM, and NLFM remains consistent. Only the setting or source of the phase increment needs to be adjusted, which has strong versatility. Moreover, based on a general FPGA and DAC hardware platform, it is easy to port to different radar frequency synthesizer systems. 4. By leveraging the parallel processing capabilities and high-speed interface characteristics of FPGAs, combined with multiphase fitting modeling, the data rate and frequency accuracy of signal output can be effectively improved, meeting the high-performance requirements of radar systems for complex modulation signals.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 is a block diagram of the implementation scheme of the present invention, showing the connection relationship and signal transmission direction between the main circuit components FPGA and DAC; Figure 2(a) is a block diagram of the implementation principle of the present invention (4-phase example: CW), showing the multi-phase IP parallel processing and signal flow during CW signal generation; Figure 2(b) is a block diagram of the implementation principle of the present invention (4-phase example: LFM), showing the multi-phase IP parallel processing and signal flow during LFM signal generation; Figure 3 is a block diagram of the implementation of the present invention (4-phase example), showing the complete processing flow in two cases: parallel DAC (LVDS interface) and serial DAC (JESD204B / C interface).

[0022] Figure 4 This is a flowchart of the method of the present invention. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the invention will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0024] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0025] As shown in Figure 1, the main components of the circuit of this invention include an FPGA and a DAC. The FPGA, as the core processing unit, is responsible for generating phase increment sequences, parallel processing of multiple IPs, and sorting amplitude codes. The DAC is responsible for converting the sorted digital amplitude codes into analog radio frequency signals. The two achieve data transmission through LVDS or JESD204B / C high-speed interfaces.

[0026] As shown in Figure 2, the implementation principle of this invention is as follows: In the low-speed clock domain (clk), firstly generate... n The phase increment sequence is input to the respective inputs. n In the phase-to-amplitude conversion IP, n The IP channels perform phase-amplitude conversion in parallel and output the corresponding amplitude codes. Then, the amplitude codes are cross-sorted according to the phase change relationship to obtain a continuous amplitude change sequence. Finally, the signal is sent to the DAC through a high-speed interface at a data rate of n×clk to complete the generation of the complex modulation signal.

[0027] like Figure 4 As shown, the specific implementation steps are as follows: Step 1: Based on the phase change characteristics of the signal form and the number n of phase-amplitude conversion IP instantiations in the FPGA, generate an n-phase phase increment sequence through multiphase fitting modeling; the signal form includes CW signal, LFM signal and NLFM signal; Step 2: Output amplitude codes from multiple IP channels; Step 3: Cross-sort the amplitude codes according to the phase change relationship to obtain the signal amplitude change sequence; Step 4: Send the sorted amplitude codes to the DAC, which generates a complex modulation signal of the desired frequency; the complex modulation signal includes continuous wave (CW), linear frequency modulation (LFM), and nonlinear frequency modulation (NLFM).

[0028] Furthermore, in step 1, the principle for determining the number of IP instantiations n is that the IP clock clk rate is ≤250MHz, generated by multiphase fitting modeling. Phase increment sequence:

[0029] IP phase integrators are typically 32 bits, and the phase increment quantization is as follows:

[0030] in: Depending on the signal form, it may be a constant (CW) or a time-varying sequence (LFM, NLFM).

[0031] Furthermore, in step 2, the multiple IP output amplitude codes

[0032] Furthermore, in step 3, the signal amplitude change sequence is obtained by cross-sorting according to the phase change relationship. ); Furthermore, in step 4, the sorted amplitude code is sent to the DAC via LVDS or JESD204B / C high-speed interface to generate the desired frequency.

[0033]

[0034] in, This is the IP operating clock.

[0035] In practical implementation, the value of n must satisfy the IP clock clk rate ≤ 250MHz. For example, if n=4 and clk=100MHz are selected, the input data rate of the DAC is 400MHz, which can effectively improve the frequency accuracy and output bandwidth of the signal.

[0036] For CW signal generation (as shown in Figure 2(a)): The initial phase of IP channel 1 is 0, and the phase increment is a fixed value. , as input to IP1; The second IP address is initially... Phase increment setpoint , as input to IP2; ......; No. Lu Chuxiang Phase increment setpoint As IP n Input, timeline based .

[0037] IP1~IP n Output amplitude data cross-sorting (corresponding phase sorting) The data is output to the DAC at a data rate of n×clk, and the DAC generates an output frequency of... The CW signal.

[0038] For LFM signal generation (as shown in Figure 2(b)): the phase increment change has a "constant acceleration" characteristic. Taking 4 phases as an example, The initial phase of the first IP channel is 0, and the input phase increment is... , as input to IP1; The second IP address is initially... Input phase increment , as input to IP2; The third IP address is initially... Input phase increment As an IP3 input; First appearance of the 4th road Phase increment As IP4 input, Timeline based on .

[0039] IP1~IP n Output amplitude data cross-sorting (corresponding phase sorting) The data is output to the DAC at a data rate of 4×clk, and the DAC generates an output frequency of... .

[0040] For NLFM signal generation: Due to the nonlinear nature of phase changes, the phase sequence can be pre-calculated in MATLAB, and then grouped: Route 1 , as input to IP1; Route 2 , as input to IP2; ......; No. road As IP n enter.

[0041] IP1~IP n Output amplitude data cross-sorting (corresponding phase sorting) The data is output to the DAC at a data rate of n×clk, and the DAC generates an output frequency of... .

[0042] As shown in Figure 3, the implementation process of this invention covers the entire signal generation process: the FPGA completes the generation of phase increment sequence, multi-channel IP phase-amplitude conversion, and amplitude code cross-sorting. Then, according to the DAC type, the LVDS interface (parallel DAC) or JESD204B / C interface (serial DAC) is selected for data transmission, and finally the DAC outputs the desired complex modulation signal.

[0043] This invention achieves efficient and accurate generation of various complex modulation signals by combining multiphase fitting modeling with software processing. It has advantages such as strong versatility, good portability, and low storage requirements, and can be widely used in various radar frequency synthesizers, providing strong support for improving radar system performance.

[0044] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0045] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is defined only by the appended claims.

Claims

1. A method for generating complex modulated signals based on multiphase fitting modeling, characterized in that, The main components of the circuit include an FPGA and a DAC. The specific implementation steps are as follows: Step 1: Based on the phase change characteristics of the signal form and the number n of phase-amplitude conversion IP instantiations in the FPGA, generate an n-phase phase increment sequence through multiphase fitting modeling; the signal form includes CW signal, LFM signal and NLFM signal; Step 2: Output amplitude codes from multiple IP channels; Step 3: Cross-sort the amplitude codes according to the phase change relationship to obtain the signal amplitude change sequence; Step 4: Send the sorted amplitude codes to the DAC, which generates a complex modulation signal of the desired frequency; the complex modulation signal includes continuous wave (CW), linear frequency modulation (LFM), and nonlinear frequency modulation (NLFM).

2. The method for generating complex modulation signals based on multiphase fitting modeling according to claim 1, characterized in that, The principle for determining the number of IP instantiations n is that the IP clock clk rate is ≤250MHz.

3. The method for generating complex modulation signals based on multiphase fitting modeling according to claim 1, characterized in that, The phase increment is quantized as follows: in, Based on whether the signal is a constant or a sequence that changes over time.

4. The method for generating complex modulation signals based on multiphase fitting modeling according to claim 3, characterized in that, The specific implementation method for CW signal generation is as follows: The initial phase of the first channel is 0, and the phase increment is a constant value, which is used as the input of IP1. The initial phase of the second channel is a specific value, and the phase increment is a constant value, which is used as the input of IP2. Similarly, the initial phase of the nth path corresponds to a specific value, the phase increment is a constant value, and it is used as the input of IPn. The time axis is based on a preset reference. IP1~IP n After the output amplitude data is sorted by corresponding phase and cross-sorted, it is output to the DAC at a data rate of n×clk. The DAC generates a CW signal with the corresponding output frequency.

5. The method for generating complex modulation signals based on multiphase fitting modeling according to claim 3, characterized in that, For LFM signal generation, since the phase increment change has a constant acceleration characteristic, the specific implementation method is as follows: Taking n-phase as an example, the initial phase of the first path is 0, and the phase increment is the corresponding change form, which is used as the input of IP1; The initial phase of the second path is a specific value, and the phase increment is the corresponding change form, which is used as the input of IP2; Similarly, the initial phase of the nth path corresponds to a specific value, and the phase increment corresponds to the change form, which serves as the IP. n Input, the timeline is based on a preset baseline; IP1~IP n After the output amplitude data is sorted by corresponding phase and cross-sorted, it is output to the DAC at a data rate of n×clk. The DAC then generates an LFM signal with the corresponding output frequency.

6. The method for generating complex modulation signals based on multiphase fitting modeling according to claim 3, characterized in that, For NLFM signal generation, due to the nonlinear characteristics of phase changes, the specific implementation method is as follows: The phase sequence is pre-calculated in MATLAB and then grouped. The first path uses the corresponding phase sequence after grouping as the input to IP1; The second path uses the corresponding phase sequence after grouping as the input to IP2; Similarly, the nth path uses the corresponding phase sequence after grouping as the input to IPn; IP1~IP n After the output amplitude data is sorted by corresponding phase and cross-sorted, it is output to the DAC at a data rate of n×clk. The DAC generates an NLFM signal with the corresponding output frequency.

7. The method for generating complex modulation signals based on multiphase fitting modeling according to claim 1, characterized in that, The sorted amplitude codes are sent to the DAC via LVDS or JESD204B / C high-speed interface.

8. The method for generating complex modulation signals based on multiphase fitting modeling according to claim 7, characterized in that, The DAC includes a parallel DAC and a serial DAC. The parallel DAC is based on the LVDS interface, and the serial DAC is based on the JESD204B / C interface.

9. The method for generating complex modulation signals based on multiphase fitting modeling according to claim 1, characterized in that, The expression for the desired frequency is: in, This is the IP operating clock.

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