Array substrate, driving method and display device

Abstract

The embodiment of the invention discloses an array substrate, a driving method and a display device, a plurality of pixel units on the array substrate are provided with first sub-pixel units and second sub-pixel units, and data lines are arranged between the first sub-pixel units and the second sub-pixel units. One column of first sub-pixel units and one column of second sub-pixel units which are adjacent left and right of the data line are connected with the same data line; the two adjacent scanning lines are respectively a first scanning line and a second scanning line, and the two vertically adjacent pixel units are respectively connected with different scanning lines; two adjacent pixel units on the left and right sides of the data line are respectively connected with different scanning lines; the driving method comprises the steps that in each frame, a first scanning line is scanned in the first 1 / 2 frame time, a second scanning line is scanned in the latter 1 / 2 frame time, and the polarity of a driving signal on a data line is changed once every 1 / 2 frame, so that single-point inversion can be displayed when the polarity of the driving signal on the data line only needs to be changed once in the 1 / 2 frame, and the driving power consumption of single-point inversion is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, a driving method, and a display device. Background Technology

[0002] With the development of science and technology, LCD (Liquid Crystal Display) monitors have replaced bulky CRT monitors and are increasingly integrated into people's daily lives. In particular, LCD monitors have developed rapidly in recent years due to their small size, light weight, thinness, low power consumption, and no radiation. They occupy a dominant position in the current flat panel display market and are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, computers, mobile phones, PDAs, GPS, automotive displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] During image display, each liquid crystal pixel in an LCD flat panel display is driven by a thin-film transistor (TFT) integrated in a TFT thin-film transistor array substrate, and together with peripheral driving circuitry, the image is displayed. Dual-gate LCD architecture is a commonly used architecture because it reduces the number of data lines and increases the aperture ratio.

[0004] Figure 1 This is a schematic diagram of the waveforms of the scan signal and data signal during double-point inversion in existing technology 1; Figure 2 It corresponds to existing technology 1 Figure 1 A schematic diagram of the polarity of the array substrate during dual-point reversal; Figure 3 This is a schematic diagram corresponding to the R / G / B pixel arrangement structure in existing technology one. For example... Figures 1 to 3 As shown, for LCD products with a dual-gate architecture in the existing technology, the data signal only needs to switch once per frame when the two dots are reversed. Although this can save power consumption, the image quality of the two dots is poor. Figure 4 This is a waveform diagram of the scan signal and data signal during single-point inversion in existing technology 1; Figure 5 It corresponds to existing technology 1 Figure 4 A schematic diagram of the polarity of the array substrate during single-point reversal. (See diagram below.) Figure 4 and Figure 5As shown, to achieve better single-point inversion, the data signal needs to be inverted once for each scan line. Although this achieves a better single-point inversion effect, the switching frequency of the data signal is too fast, which increases the driving power consumption. Moreover, in this architecture of the existing technology, the source lines of some pixels need to be lengthened, resulting in larger resistance and parasitic capacitance, thus increasing the loading.

[0005] Figure 6 This is a schematic diagram of the waveforms of the scan signal and data signal during double-column inversion in the prior art 2; Figure 7 It corresponds to existing technology two Figure 6 A schematic diagram of the polarity of the array substrate during dual-row inversion; Figure 8 This is a schematic diagram corresponding to the R / G / B pixel arrangement structure in existing technology two. For example... Figures 6 to 8 As shown, in order to reduce the problem of large resistance and parasitic capacitance in the existing technology 1 architecture, the existing technology 2 adopts another dual-gate architecture. However, when the data signal only needs to switch once per frame, the existing technology 2 can only achieve double column inversion, which results in worse image quality compared to double-point inversion and single-point inversion. Figure 9 This is a schematic diagram of the waveforms of the scanning signal and the data signal during double-point inversion in the prior art 2; Figure 10 It corresponds to existing technology two Figure 9 A schematic diagram of the polarity of the array substrate during dual-point reversal. (See diagram below.) Figure 9 and Figure 10 As shown, in the second prior art, when performing double-point inversion, the data signal needs to be inverted once every two scan lines. Although the image quality is better than that of double-column inversion, the switching frequency of the data signal is too fast, resulting in high driving power consumption. Figure 11 This is a schematic diagram of the waveforms of the scanning signal and the data signal during single-point inversion in the prior art 2; Figure 12 It corresponds to existing technology two Figure 11 A schematic diagram of the polarity of the array substrate during single-point reversal. (See diagram below.) Figure 11 and Figure 12 As shown, in the second prior art, the data signal needs to be reversed once for each scan line during single-point reversal. Although it can achieve a single-point reversal effect with better image quality, the data signal switching frequency is faster and the driving power consumption is greater. Summary of the Invention

[0006] In order to overcome the shortcomings and deficiencies of the prior art, the present invention aims to provide an array substrate, a driving method, and a display device, so as to simultaneously solve the problems of large loading of dual-gate architecture and large power consumption of single-point inversion driving in the prior art.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] This invention provides a driving method for an array substrate. The array substrate has multiple scan lines, multiple data lines, and multiple pixel units arranged in an array. Each pixel unit includes a first sub-pixel unit and a second sub-pixel unit. A column of first sub-pixel units and a column of second sub-pixel units are arranged alternately in the row direction. Data lines are disposed between a column of first sub-pixel units and a column of second sub-pixel units. A column of first sub-pixel units and a column of second sub-pixel units are located between two adjacent data lines. A column of first sub-pixel units and a column of second sub-pixel units adjacent to the left and right sides of each data line are connected to the same data line.

[0009] The two adjacent scan lines are the first scan line and the second scan line, which are arranged alternately in the column direction. The first scan line and the second scan line are provided on the upper and lower sides of each row of sub-pixel units, and the first scan line and the second scan line are provided between adjacent rows of sub-pixel units.

[0010] In two adjacent pixel units, one pixel unit is connected to the first scan line and the other pixel unit is connected to the second scan line; in two adjacent pixel units on the left and right sides of the data line, one pixel unit is connected to the first scan line and the other pixel unit is connected to the second scan line.

[0011] The driving method includes: in each frame, the first scan line is scanned in the first half of the frame time, and the second scan line is scanned in the second half of the frame time, wherein the polarity of the driving signal on the data line changes once every half frame.

[0012] Furthermore, in each row of pixel units, all first sub-pixel units are connected to the same scan line, and all second sub-pixel units are connected to the same scan line. The driving method includes:

[0013] The drive signals on all the data lines have the same polarity at the same time.

[0014] Furthermore, the first sub-pixel unit in the odd-numbered rows of pixel units and the second sub-pixel unit in the even-numbered rows of pixel units are connected to the corresponding first scan line, and the second sub-pixel unit in the odd-numbered rows of pixel units and the first sub-pixel unit in the even-numbered rows of pixel units are connected to the corresponding second scan line;

[0015] Alternatively, the first sub-pixel unit in the odd-numbered rows of pixel units and the second sub-pixel unit in the even-numbered rows of pixel units are connected to the corresponding second scan line, and the second sub-pixel unit in the odd-numbered rows of pixel units and the first sub-pixel unit in the even-numbered rows of pixel units are connected to the corresponding first scan line.

[0016] Furthermore, in each row of pixel units, an odd number and an even number of the first sub-pixel units are respectively connected to different scan lines, and an odd number and an even number of the second sub-pixel units are respectively connected to different scan lines. The driving method includes:

[0017] The drive signals on two adjacent data lines have opposite polarities at the same time.

[0018] Furthermore, an odd number of first sub-pixel units in an odd-numbered row of pixel units, an even number of second sub-pixel units in an odd-numbered row of pixel units, an odd number of second sub-pixel units in an even-numbered row of pixel units, and an even number of first sub-pixel units in an even-numbered row of pixel units are connected to corresponding first scan lines, and an even number of first sub-pixel units in an odd-numbered row of pixel units, an odd number of second sub-pixel units in an odd-numbered row of pixel units, an even number of second sub-pixel units in an even-numbered row of pixel units, and an odd number of first sub-pixel units in an even-numbered row of pixel units are connected to corresponding second scan lines;

[0019] Alternatively, an even number of first sub-pixel units in an odd-numbered row of pixel units, an odd number of second sub-pixel units in an odd-numbered row of pixel units, an even number of second sub-pixel units in an even-numbered row of pixel units, and an odd number of first sub-pixel units in an even-numbered row of pixel units are connected to corresponding first scan lines, and an odd number of first sub-pixel units in an odd-numbered row of pixel units, an even number of second sub-pixel units in an odd-numbered row of pixel units, an odd number of second sub-pixel units in an even-numbered row of pixel units, and an even number of first sub-pixel units in an even-numbered row of pixel units are connected to corresponding second scan lines.

[0020] Furthermore, the array substrate is provided with a plurality of first thin-film transistors, a plurality of second thin-film transistors, a first control line, a second control line, and a plurality of scan signal lines. The first scan line is connected to the first control line and the scan signal line through the first thin-film transistor, and the second scan line is connected to the second control line and the scan signal line through the second thin-film transistor. The first scan line and the second scan line adjacent to each other in each row of pixel units are connected to the same scan signal line.

[0021] The driving method includes:

[0022] Within each frame, for the first half of the frame time, the first control line controls all the first thin-film transistors to turn on and scans the first scan line through the scan signal line; for the second half of the frame time, the second control line controls all the second thin-film transistors to turn on and scans the second scan line through the scan signal line.

[0023] This application also provides an array substrate for the driving method of the array substrate as described above. The array substrate is provided with multiple scan lines, multiple data lines, and multiple pixel units arranged in an array. Each pixel unit has a first sub-pixel unit and a second sub-pixel unit. A column of first sub-pixel units and a column of second sub-pixel units are arranged alternately in the row direction. The data lines are disposed between a column of first sub-pixel units and a column of second sub-pixel units. A column of first sub-pixel units and a column of second sub-pixel units are disposed between two adjacent data lines. The columns of first sub-pixel units and the columns of second sub-pixel units adjacent to the left and right sides of the data lines are all connected to the same data line.

[0024] The two adjacent scan lines are the first scan line and the second scan line, which are arranged alternately in the column direction. The first scan line and the second scan line are provided on the upper and lower sides of each row of sub-pixel units, and the first scan line and the second scan line are provided between adjacent rows of sub-pixel units.

[0025] In two adjacent pixel units, one pixel unit is connected to the first scan line and the other pixel unit is connected to the second scan line; in two adjacent pixel units on the left and right sides of the data line, one pixel unit is connected to the first scan line and the other pixel unit is connected to the second scan line.

[0026] Furthermore, in each row of pixel units, all first sub-pixel units are connected to the same scan line, and all second sub-pixel units are connected to the same scan line;

[0027] Alternatively, in each row of pixel units, odd and even numbers of the first sub-pixel units are connected to different scan lines, and odd and even numbers of the second sub-pixel units are connected to different scan lines.

[0028] Furthermore, the array substrate is provided with a plurality of first thin-film transistors, a plurality of second thin-film transistors, a first control line, a second control line, and a plurality of scan signal lines. The first scan line is connected to the first control line and the scan signal lines through the first thin-film transistors, and the second scan line is connected to the second control line and the scan signal lines through the second thin-film transistors. The first scan lines and second scan lines that are adjacent to each other in each row of pixel units are connected to the same scan signal line.

[0029] This application also provides a display device, including a color filter substrate and an array substrate as described above. The color filter substrate and the array substrate are disposed opposite to each other, and a liquid crystal layer is disposed between the color filter substrate and the array substrate. An upper polarizer is disposed on the color filter substrate, and a lower polarizer is disposed on the array substrate. The light transmission axes of the upper polarizer and the lower polarizer are perpendicular to each other.

[0030] The beneficial effects of this invention are as follows: By connecting the first and second sub-pixel units in adjacent columns to the same data line, connecting two adjacent pixel units vertically to different scan lines, and connecting two adjacent pixel units horizontally to different scan lines, and by scanning the first scan line in the first half-frame time and the second scan line in the second half-frame time, the driving signal on the data line only needs to change its polarity once every half-frame to display single-point inversion, thereby reducing the driving power consumption of single-point inversion and improving the image display effect. At the same time, it avoids the problem of increased resistance and parasitic capacitance due to the need to lengthen the source lines of some pixels, thus increasing the loading. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the waveforms of the scan signal and data signal during double-point inversion in existing technology 1;

[0032] Figure 2 It corresponds to existing technology 1 Figure 1 A schematic diagram of the polarity of the array substrate during dual-point reversal;

[0033] Figure 3 This is a schematic diagram of the arrangement structure of R / G / B pixels corresponding to the existing technology.

[0034] Figure 4 This is a waveform diagram of the scan signal and data signal during single-point inversion in existing technology 1;

[0035] Figure 5 It corresponds to existing technology 1 Figure 4 A schematic diagram of the polarity of the array substrate during single-point reversal;

[0036] Figure 6This is a schematic diagram of the waveforms of the scan signal and data signal during double-column inversion in the prior art 2;

[0037] Figure 7 It corresponds to existing technology two Figure 6 A schematic diagram of the polarity of the array substrate during dual-row inversion;

[0038] Figure 8 This is a schematic diagram of the arrangement structure of R / G / B pixels corresponding to the existing technology 2;

[0039] Figure 9 This is a schematic diagram of the waveforms of the scanning signal and the data signal during double-point inversion in the prior art 2;

[0040] Figure 10 It corresponds to existing technology two Figure 9 A schematic diagram of the polarity of the array substrate during dual-point reversal;

[0041] Figure 11 This is a schematic diagram of the waveforms of the scanning signal and the data signal during single-point inversion in the prior art 2;

[0042] Figure 12 It corresponds to existing technology two Figure 11 A schematic diagram of the polarity of the array substrate during single-point reversal;

[0043] Figure 13 This is a schematic diagram of the polarity structure of the array substrate during single-point reversal in Embodiment 1 of the present invention;

[0044] Figure 14 This is one of the schematic diagrams of the arrangement structure of R / G / B pixels in Embodiment 1 of the present invention;

[0045] Figure 15 This is the second schematic diagram of the arrangement structure of R / G / B pixels in Embodiment 1 of the present invention;

[0046] Figure 16 This is a schematic diagram of the waveforms of the scanning signal and data signal when the array substrate is reversed at a single point in Embodiment 1 of the present invention;

[0047] Figure 17 This is a schematic diagram of the polarity structure of the array substrate in the first half frame of Embodiment 1 of the present invention;

[0048] Figure 18 This is a schematic diagram of the polarity structure of the array substrate in the last half frame of Embodiment 1 of the present invention;

[0049] Figure 19 This is a schematic diagram of the gate driving circuit on the array substrate in Embodiment 1 of the present invention;

[0050] Figure 20 This is a schematic diagram of the gate driving circuit on the array substrate in Embodiment 2 of the present invention;

[0051] Figure 21 This is a schematic diagram of the polarity structure of the array substrate during single-point reversal in Embodiment 3 of the present invention;

[0052] Figure 22 This is a schematic diagram of the display device in the black state in this invention;

[0053] Figure 23 This is a schematic diagram of the display device in the white state in this invention. Detailed Implementation

[0054] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the array substrate and driving method, and display device proposed according to the present invention:

[0055] [Example 1]

[0056] Figure 13 This is a schematic diagram of the polarity structure of the array substrate during single-point reversal in Embodiment 1 of the present invention. Figure 13 As shown in Embodiment 1 of the present invention, an array substrate is provided, on which multiple scan lines, multiple data lines 2, and multiple pixel units P arranged in an array are provided. Each pixel unit P has a first sub-pixel unit P1 and a second sub-pixel unit P2, arranged alternately in a row direction. Data lines 2 are located between a column of first sub-pixel units P1 and a column of second sub-pixel units P2. The first sub-pixel units P1 and the second sub-pixel units P2 adjacent to each other on the left and right sides of a data line 2 are connected to the same data line 2, i.e., one data line 2 connects two adjacent columns of pixel units P, thus reducing the number of data lines 2 to only half the number of columns of pixel units P. Two columns of pixel units P are located between two adjacent data lines 2, namely a column of first sub-pixel units P1 and a column of second sub-pixel units P2. For example, the Nth data line 2 connects the (2N-1)th column of pixel units P and the 2Nth column of pixel units P, where N is an integer greater than or equal to 1.

[0057] Two adjacent scan lines are designated as first scan line 11 and second scan line 12. First scan line 11 and second scan line 12 are arranged alternately in the column direction. Each row of sub-pixel units P has first scan line 11 and second scan line 12 on both its upper and lower sides. Adjacent rows of sub-pixel units P also have first scan line 11 and second scan line 12 between them. For example, the 2N-1th (odd-numbered) scan line is first scan line 11, and the 2Nth (even-numbered) scan line is second scan line 12, where N is an integer greater than or equal to 1. Figure 19This is a schematic diagram of the gate driving circuit on the array substrate in Embodiment 1 of the present invention. Figure 19 As shown, the gate drive circuit adopts a double-ended counter-current architecture, that is, gate drive circuits are provided at both ends of the scan line. Each scan line is jointly applied a scan signal by the gate drive circuits at both ends, thereby improving the scanning effect. Moreover, it can still be used normally when there is an open circuit in the middle of the scan line.

[0058] In two adjacent pixel units P, one pixel unit P is connected to the first scan line 11, and the other pixel unit P is connected to the second scan line 12. In two adjacent pixel units P on the left and right sides of data line 2, one pixel unit P is connected to the first scan line 11, and the other pixel unit P is connected to the second scan line 12.

[0059] In this embodiment, in each row of pixel units P, all first sub-pixel units P1 are connected to the same scan line, and all second sub-pixel units P2 are connected to the same scan line. For example... Figure 13 As shown, the first sub-pixel unit P1 in the odd-numbered row pixel unit P and the second sub-pixel unit P2 in the even-numbered row pixel unit P are connected to the corresponding first scan line 11, and the second sub-pixel unit P2 in the odd-numbered row pixel unit P and the first sub-pixel unit P1 in the even-numbered row pixel unit P are connected to the corresponding second scan line 12. For example, in the 2N-1th row pixel unit P, the first sub-pixel unit P1 is connected to the 4N-3rd scan line, and the second sub-pixel unit P2 is connected to the 4N-2th scan line; in the 2Nth row pixel unit P, the second sub-pixel unit P2 is connected to the 4N-1th scan line, and the first sub-pixel unit P1 is connected to the 4Nth scan line, where N is an integer greater than or equal to 1. Of course, in other embodiments, the first sub-pixel unit P1 in the odd-numbered row pixel unit P and the second sub-pixel unit P2 in the even-numbered row pixel unit P can also be connected to the corresponding second scan line 12, and the second sub-pixel unit P2 in the odd-numbered row pixel unit P and the first sub-pixel unit P1 in the even-numbered row pixel unit P can be connected to the corresponding first scan line 11.

[0060] Furthermore, a plurality of third thin-film transistors 3 are provided on the array substrate, and each pixel unit P is electrically connected to the corresponding scan line and data line 2 through the corresponding third thin-film transistor 3, wherein the third thin-film transistor 3 is disposed in the display area.

[0061] Figure 14 This is one of the schematic diagrams of the arrangement structure of R / G / B pixels in Embodiment 1 of the present invention. Figure 15 This is a second schematic diagram of the R / G / B pixel arrangement structure in Embodiment 1 of the present invention. Pixel unit P includes red pixel units, green pixel units, and blue pixel units. For example... Figure 14As shown, pixel unit P in column 3M+1 is a red pixel unit, pixel unit P in column 3M+2 is a green pixel unit, pixel unit P in column 3M+3 is a blue pixel unit, and M is an integer greater than or equal to 0. Alternatively, as shown... Figure 15 As shown, in the odd-numbered rows of pixel units P, the 3M+1th pixel unit P is a red pixel unit, the 3M+2nd pixel unit P is a green pixel unit, and the 3M+3rd pixel unit P is a blue pixel unit; in the even-numbered rows of pixel units P, the 3M+1th pixel unit P is a green pixel unit, the 3M+2nd pixel unit P is a blue pixel unit, and the 3M+3rd pixel unit P is a red pixel unit. That is, the odd-numbered rows and even-numbered rows are staggered by one color of pixel unit P, thus making the color of the displayed image more uniform. Of course, the odd-numbered rows and even-numbered rows can also be staggered by two colors of pixel unit P.

[0062] Figure 16 This is a schematic diagram of the waveforms of the scanning signal and data signal when the array substrate is reversed at a single point in Embodiment 1 of the present invention; Figure 17 This is a schematic diagram of the polarity structure of the array substrate in the first half frame of Embodiment 1 of the present invention; Figure 18 This is a schematic diagram of the polarity structure of the array substrate in the latter half of the frame in Embodiment 1 of the present invention. Figures 16 to 18 As shown, this embodiment also provides a driving method for an array substrate, used to drive the array substrate as described above. The driving method includes:

[0063] Within each frame, the first scan line 11 is scanned in the first half of the frame time, and the second scan line 12 is scanned in the second half of the frame time. The drive signal on data line 2 changes polarity once every half frame. That is, in the first half of the frame time of each frame, only the scan lines of odd-numbered rows (first scan line 11) are scanned, so that the first sub-pixel unit P1 in the odd-numbered row pixel unit P and the second sub-pixel unit P2 in the even-numbered row pixel unit P are turned on and charged; in the second half of the frame time of each frame, only the scan lines of even-numbered rows (second scan line 12) are scanned, so that the second sub-pixel unit P2 in the odd-numbered row pixel unit P and the first sub-pixel unit P1 in the even-numbered row pixel unit P are turned on and charged.

[0064] In this embodiment, in each row of pixel units P, all first sub-pixel units P1 are connected to the same scan line, all second sub-pixel units P2 are connected to the same scan line, and the driving signals on all data lines 2 have the same polarity at the same time. For example... Figure 13As shown, the first sub-pixel unit P1 in the odd-numbered row pixel unit P and the second sub-pixel unit P2 in the even-numbered row pixel unit P are connected to the corresponding first scan line 11, and the second sub-pixel unit P2 in the odd-numbered row pixel unit P and the first sub-pixel unit P1 in the even-numbered row pixel unit P are connected to the corresponding second scan line 12. For example, in the 2N-1th row pixel unit P, the first sub-pixel unit P1 is connected to the 4N-3rd scan line, and the second sub-pixel unit P2 is connected to the 4N-2th scan line; in the 2Nth row pixel unit P, the second sub-pixel unit P2 is connected to the 4N-1th scan line, and the first sub-pixel unit P1 is connected to the 4Nth scan line, where N is an integer greater than or equal to 1.

[0065] Figure 16 and Figure 17 In the first half of each frame, a negative polarity drive signal is applied to all data lines 2, so that the first sub-pixel unit P1 in the odd-numbered row pixel unit P and the second sub-pixel unit P2 in the even-numbered row pixel unit P are turned on and charged with the negative polarity drive signal. Figure 16 and Figure 18 In the process, during the half-frame time after each frame, all data lines 2 are given positive driving signals, so that the second sub-pixel unit P2 in the odd-numbered row pixel unit P and the first sub-pixel unit P1 in the even-numbered row pixel unit P are turned on and charged with positive driving signals.

[0066] [Example 2]

[0067] Figure 20 This is a schematic diagram of the gate driving circuit on the array substrate in Embodiment 2 of the present invention. Figure 20 As shown, the array substrate and driving method provided in Embodiment 2 of the present invention are the same as those in Embodiment 1. Figures 13 to 19 The array substrate and driving method are basically the same as those in the previous embodiment, except that in this embodiment:

[0068] The array substrate is provided with multiple first thin-film transistors 4, multiple second thin-film transistors 5, a first control line 6, a second control line 7, and multiple scan signal lines 8. A first scan line 11 is connected to the first control line 6 and the scan signal line 8 via the first thin-film transistors 4. A second scan line 12 is connected to the second control line 7 and the scan signal line 8 via the second thin-film transistors 5. The adjacent first scan lines 11 and second scan lines 12 in each row of pixel units P are connected to the same scan signal line 8, which is then connected to the gate driver chip to scan the first scan lines 11 and 12. The first thin-film transistors 4, multiple second thin-film transistors 5, first control line 6, second control line 7, and multiple scan signal lines 8 are all located in the non-display area. In this embodiment, one end of the scan line is provided with the first thin-film transistor 4, second thin-film transistor 5, first control line 6, second control line 7, and scan signal line 8. Alternatively, the first thin-film transistor 4, second thin-film transistor 5, first control line 6, second control line 7, and scan signal line 8 can be provided at both ends of the scan line, thus forming a double-ended offset architecture.

[0069] The scanning signal line 8 is controlled by the first control line 6 and the second control line 7 to apply a scanning signal to the first scan line 11 or the second scan line 12, so that one first scan line 11 and one second scan line 12 can share one scanning signal line 8, thereby reducing the number of scanning signal lines 8 in the non-display area of ​​the array substrate, and also simplifying the driving logic of the gate driver chip.

[0070] This embodiment also provides a driving method for an array substrate, used to drive the array substrate as described above. The driving method includes:

[0071] Within each frame, the first scan line 11 is scanned in the first half of the frame time, and the second scan line 12 is scanned in the second half of the frame time. The drive signal on data line 2 changes polarity once every half frame. That is, in the first half of the frame time of each frame, only the scan lines of odd-numbered rows (first scan line 11) are scanned, so that the first sub-pixel unit P1 in the odd-numbered row pixel unit P and the second sub-pixel unit P2 in the even-numbered row pixel unit P are turned on and charged; in the second half of the frame time of each frame, only the scan lines of even-numbered rows (second scan line 12) are scanned, so that the second sub-pixel unit P2 in the odd-numbered row pixel unit P and the first sub-pixel unit P1 in the even-numbered row pixel unit P are turned on and charged.

[0072] Specifically, within each frame, during the first half-frame time, the first control line 6 controls all first thin-film transistors 4 to turn on and scans the first scan line 11 through the scan signal line 8, causing the first sub-pixel unit P1 in the odd-numbered row pixel unit P and the second sub-pixel unit P2 in the even-numbered row pixel unit P to turn on and be charged; during the last half-frame time of each frame, the second control line 7 controls all second thin-film transistors 5 to turn on and scans the second scan line 12 through the scan signal line 8, causing the second sub-pixel unit P2 in the odd-numbered row pixel unit P and the first sub-pixel unit P1 in the even-numbered row pixel unit P to turn on and be charged.

[0073] In this embodiment, in each row of pixel units P, all first sub-pixel units P1 are connected to the same scan line, all second sub-pixel units P2 are connected to the same scan line, and the driving signals on all data lines 2 have the same polarity at the same time. For example... Figure 20 As shown, the first sub-pixel unit P1 in the odd-numbered row pixel unit P and the second sub-pixel unit P2 in the even-numbered row pixel unit P are connected to the corresponding first scan line 11, and the second sub-pixel unit P2 in the odd-numbered row pixel unit P and the first sub-pixel unit P1 in the even-numbered row pixel unit P are connected to the corresponding second scan line 12. For example, in the 2N-1th row pixel unit P, the first sub-pixel unit P1 is connected to the 4N-3rd scan line, and the second sub-pixel unit P2 is connected to the 4N-2th scan line; in the 2Nth row pixel unit P, the second sub-pixel unit P2 is connected to the 4N-1th scan line, and the first sub-pixel unit P1 is connected to the 4Nth scan line, where N is an integer greater than or equal to 1.

[0074] During the first half of each frame, a negative driving signal is applied to all data lines 2, causing the first sub-pixel unit P1 in the odd-numbered row pixel unit P and the second sub-pixel unit P2 in the even-numbered row pixel unit P to open and be charged with a negative driving signal; during the last half of each frame, a positive driving signal is applied to all data lines 2, causing the second sub-pixel unit P2 in the odd-numbered row pixel unit P and the first sub-pixel unit P1 in the even-numbered row pixel unit P to open and be charged with a positive driving signal.

[0075] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0076] [Example 3]

[0077] Figure 21 This is a schematic diagram of the polarity structure of the array substrate during single-point reversal in Embodiment 3 of the present invention. Figure 21 As shown, the array substrate and driving method provided in Embodiment 3 of the present invention are the same as those in Embodiment 1. Figures 13 to 19 Example 2 Figure 20The array substrate and driving method are basically the same as those in the previous embodiment, except that in this embodiment:

[0078] In each row of pixel units P, the odd and even number of first sub-pixel units P1 are connected to different scan lines, and the odd and even number of second sub-pixel units P2 are connected to different scan lines. For example... Figure 21 As shown, the odd number of first sub-pixel units P1, the even number of second sub-pixel units P2, the odd number of second sub-pixel units P2, and the even number of first sub-pixel units P1 in the odd-numbered row pixel unit P are connected to the corresponding first scan line 11, and the even number of first sub-pixel units P1, the odd number of second sub-pixel units P2, the even number of second sub-pixel units P2, and the odd number of first sub-pixel units P1 in the odd-numbered row pixel unit P are connected to the corresponding second scan line 12. For example, in the 2N-1th row of pixel unit P, the 4N-3rd and 4Nth pixel units P are connected to the 4N-3rd scan line, and the 4N-2nd and 4N-1st pixel units P are connected to the 4N-2nd scan line; in the 2Nth row of pixel unit P, the 4N-2nd and 4N-1st pixel units P are connected to the 4N-1st scan line, and the 4N-3rd and 4Nth pixel units P are connected to the 4Nth scan line, where N is an integer greater than or equal to 1. Of course, in other embodiments, the even number of first sub-pixel units P1, the odd number of second sub-pixel units P2, the even number of second sub-pixel units P2, and the odd number of first sub-pixel units P1 in the odd-numbered row pixel unit P can be connected to the corresponding first scan line 11, and the odd number of first sub-pixel units P1, the even number of second sub-pixel units P2, the even number of second sub-pixel units P2, and the even number of first sub-pixel units P1 in the odd-numbered row pixel unit P can be connected to the corresponding second scan line 12.

[0079] In each row of pixel units P, the odd and even number of first sub-pixel units P1 only refer to the first sub-pixel unit P1. The second sub-pixel units P2 are not included. For example, if the 2N-1th pixel unit P in each row of pixel units P is the first sub-pixel unit P1, then the 4N-3th pixel unit P is the odd number of first sub-pixel units P1, and the 4N-1th pixel unit P is the even number of first sub-pixel units P1. The 4N-2nd and 4Nth pixel units P are not included. Similarly, the odd and even number of second sub-pixel units P2 in each row of pixel unit P only refer to the second sub-pixel units P2; the first sub-pixel units P1 are not included. For example, if the 2Nth pixel unit P in each row of pixel unit P is the second sub-pixel unit P2, then the 4N-2th pixel unit P is the odd number of second sub-pixel units P2, and the 4Nth pixel unit P is the even number of second sub-pixel units P2. The 4N-3th and 4N-1th pixel units P are not included.

[0080] This embodiment also provides a driving method for an array substrate, used to drive the array substrate as described above. The driving method includes:

[0081] Within each frame, the first half of the frame time is used to scan the first scan line 11, and the second half of the frame time is used to scan the second scan line 12. The polarity of the drive signal on the data line 2 changes once every half frame. That is, during the first half of each frame, only the scan lines of odd-numbered rows (first scan lines 11) are scanned, so that the odd number of first sub-pixel units P1, the even number of second sub-pixel units P2, the odd number of second sub-pixel units P2, and the even number of first sub-pixel units P1 in the odd-numbered row pixel unit P are turned on and charged; during the last half of each frame, only the scan lines of even-numbered rows (second scan lines 12) are scanned, so that the even number of first sub-pixel units P1, the odd number of second sub-pixel units P2, the even number of second sub-pixel units P2, and the odd number of first sub-pixel units P1 in the even-numbered row pixel unit P are turned on and charged.

[0082] In this embodiment, in each row of pixel units P, the odd and even number of first sub-pixel units P1 are connected to different scan lines, and the odd and even number of second sub-pixel units P2 are connected to different scan lines. The driving signals on adjacent data lines 2 have opposite polarities at the same time. Figure 21As shown, the odd number of first sub-pixel units P1, the even number of second sub-pixel units P2, the odd number of second sub-pixel units P2, and the even number of first sub-pixel units P1 in the odd-numbered row pixel unit P are connected to the corresponding first scan line 11, and the even number of first sub-pixel units P1, the odd number of second sub-pixel units P2, the even number of second sub-pixel units P2, and the odd number of first sub-pixel units P1 in the odd-numbered row pixel unit P are connected to the corresponding second scan line 12.

[0083] During the first half of each frame, odd-numbered data lines 2 are given negative drive signals, while even-numbered data lines 2 are given positive drive signals; during the last half of each frame, odd-numbered data lines 2 are given positive drive signals, while even-numbered data lines 2 are given negative drive signals.

[0084] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1 and Embodiment 2, and will not be repeated here.

[0085] Figure 22 This is a schematic diagram of the display device in the black state in this invention. Figure 23 This is a schematic diagram of the display device in the white state according to the present invention. Figures 22 to 23 As shown, the present invention also provides a display device, including a display panel 30 and a backlight module 40, wherein the backlight module 40 is located below the display panel 30 and is used to provide a backlight source for the display panel 30.

[0086] The backlight module 40 can be an edge-lit backlight module or a direct-lit backlight module. Preferably, the backlight module 40 adopts a collimated backlight (CBL) mode, which can collect light and ensure display effect.

[0087] The backlight module 40 includes a backlight source 41 and a privacy layer 43, which reduces the range of light emission angles. A brightness enhancement film 42 is also provided between the backlight source 41 and the privacy layer 43, increasing the brightness of the backlight module 40. The privacy layer 43 acts like a miniature venetian blind, blocking light with a large incident angle while allowing light with a smaller incident angle to pass through, thus reducing the range of light angles passing through the privacy layer 43. The privacy layer 43 includes multiple parallel light-blocking walls and light-transmitting holes located between adjacent light-blocking walls. Light-absorbing material is provided on both sides of the light-blocking walls. Alternatively, the backlight source 41 can be a light-collecting backlight, eliminating the need for a privacy layer 43; however, light-collecting backlights are more expensive than conventional backlights.

[0088] like Figures 22 to 23 As shown, this application also provides a display panel 30 for use in the display device described above. The display panel 30 includes a color filter substrate 31 and an array substrate 32 as described above. The color filter substrate 31 and the array substrate 32 are disposed opposite to each other, and a liquid crystal layer 33 is disposed between the color filter substrate 31 and the array substrate 32. The liquid crystal layer 33 preferably uses positive liquid crystal molecules, that is, liquid crystal molecules with positive dielectric anisotropy. In the initial state, the positive liquid crystal molecules in the liquid crystal layer 33 are aligned parallel to the color filter substrate 31 and the array substrate 32, and the alignment direction of the positive liquid crystal molecules on the side closer to the color filter substrate 31 is parallel or antiparallel to the alignment direction of the positive liquid crystal molecules on the side closer to the array substrate 32. Of course, in other embodiments, the liquid crystal layer 33 may also use negative liquid crystal molecules, and the negative liquid crystal molecules in the liquid crystal layer 33 may be aligned perpendicular to the color filter substrate 31 and the array substrate 32, that is, similar to the alignment method of VA display mode.

[0089] The color filter substrate 31 has color resist layers 312 arranged in an array and black matrix 311 separating the color resist layers 312. The color resist layers 312 include red (R), green (G) and blue (B) color resist materials, and correspondingly form red (R), green (G) and blue (B) pixel units P.

[0090] In this embodiment, a common electrode 321 is also provided on the side of the array substrate 32 facing the liquid crystal layer 33. The common electrode 321 and the pixel electrode 322 are located on different layers and are insulated from each other by an insulating layer. The common electrode 321 may be located above or below the pixel electrode 322. Figure 22 The diagram shows the common electrode 321 located below the pixel electrode 322. Preferably, the common electrode 321 is a planar electrode disposed across the entire surface, and the pixel electrode 322 is a block electrode disposed within each pixel unit or a slit electrode with multiple electrode strips, to form a fringe field switching (FFS) mode. Of course, in other embodiments, the pixel electrode 322 and the common electrode 321 may be located on the same layer, but they are insulated from each other. Both the pixel electrode 322 and the common electrode 321 may include multiple electrode strips, and the electrode strips of the pixel electrode 322 and the common electrode 321 are arranged alternately to form an in-plane switching (IPS) mode; or, in other embodiments, the array substrate 32 has a pixel electrode 322 on the side facing the liquid crystal layer 33, and the color filter substrate 31 has a common electrode 321 on the side facing the liquid crystal layer 33 to form a TN mode or a VA mode.

[0091] The color filter substrate 31 and the array substrate 32 can be made of materials such as glass, acrylic, and polycarbonate. The common electrode 321 and the pixel electrode 322 can be made of materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0092] The color filter substrate 31 is provided with an upper polarizer 51, and the array substrate 32 is provided with a lower polarizer 52. The light transmission axes of the upper polarizer 51 and the lower polarizer 52 are perpendicular to each other.

[0093] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0094] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. A driving method for an array substrate, characterized in that, An array substrate is provided, on which multiple scan lines, multiple data lines (2) and multiple pixel units (P) arranged in an array are provided. Each pixel unit (P) has a first sub-pixel unit (P1) and a second sub-pixel unit (P2). A column of the first sub-pixel units (P1) and a column of the second sub-pixel units (P2) are arranged alternately in the row direction. The data lines (2) are located between a column of the first sub-pixel units (P1) and a column of the second sub-pixel units (P2). A column of the first sub-pixel units (P1) and a column of the second sub-pixel units (P2) are located between two adjacent data lines (2). The columns of the first sub-pixel units (P1) and the columns of the second sub-pixel units (P2) adjacent to the left and right of the data lines (2) are all connected to the same data line (2). The two adjacent scan lines are a first scan line (11) and a second scan line (12), and the first scan line (11) and the second scan line (12) are arranged alternately in the column direction. The first scan line (11) and the second scan line (12) are provided on the upper and lower sides of each row of sub-pixel units (P), and the first scan line (11) and the second scan line (12) are provided between adjacent rows of sub-pixel units (P). Of the two adjacent pixel units (P) above and below, one pixel unit (P) is connected to the first scan line (11), and the other pixel unit (P) is connected to the second scan line (12); Of the two adjacent pixel units (P) on the left and right sides of the data line (2), one pixel unit (P) is connected to the first scan line (11), and the other pixel unit (P) is connected to the second scan line (12); The driving method includes: in each frame, the first scan line (11) is scanned in the first half frame time, and the second scan line (12) is scanned in the second half frame time, and the driving signal on the data line (2) changes polarity once every half frame.

2. The driving method for the array substrate according to claim 1, characterized in that, In each row of pixel units (P), all first sub-pixel units (P1) are connected to the same scan line, and all second sub-pixel units (P2) are connected to the same scan line. The driving method includes: The drive signals on all the data lines (2) have the same polarity at the same time.

3. The driving method for the array substrate according to claim 2, characterized in that, The first sub-pixel unit (P1) in the odd-numbered rows of pixel units (P) and the second sub-pixel unit (P2) in the even-numbered rows of pixel units (P) are connected to the corresponding first scan line (11), and the second sub-pixel unit (P2) in the odd-numbered rows of pixel units (P) and the first sub-pixel unit (P1) in the even-numbered rows of pixel units (P) are connected to the corresponding second scan line (12). Alternatively, the first sub-pixel unit (P1) in the odd-numbered row of pixel units (P) and the second sub-pixel unit (P2) in the even-numbered row of pixel units (P) are connected to the corresponding second scan line (12), and the second sub-pixel unit (P2) in the odd-numbered row of pixel units (P) and the first sub-pixel unit (P1) in the even-numbered row of pixel units (P) are connected to the corresponding first scan line (11).

4. The driving method for the array substrate according to claim 1, characterized in that, In each row of pixel units (P), an odd number and an even number of first sub-pixel units (P1) are connected to different scan lines, and an odd number and an even number of second sub-pixel units (P2) are connected to different scan lines. The driving method includes: The drive signals on two adjacent data lines (2) have opposite polarities at the same time.

5. The driving method for the array substrate according to claim 4, characterized in that, An odd number of first sub-pixel units (P1) in an odd-numbered row of pixel units (P), an even number of second sub-pixel units (P2) in an odd-numbered row of pixel units (P), an odd number of second sub-pixel units (P2) in an even-numbered row of pixel units (P), and an even number of first sub-pixel units (P1) in an even-numbered row of pixel units (P) are connected to the corresponding first scan line (11). An even number of first sub-pixel units (P1) in an odd-numbered row of pixel units (P), an odd number of second sub-pixel units (P2) in an odd-numbered row of pixel units (P), an even number of second sub-pixel units (P2) in an even-numbered row of pixel units (P), and an odd number of first sub-pixel units (P1) in an even-numbered row of pixel units (P) are connected to the corresponding second scan line (12). Alternatively, an even number of first sub-pixel units (P1) in an odd-numbered row of pixel units (P), an odd number of second sub-pixel units (P2) in an odd-numbered row of pixel units (P), an even number of second sub-pixel units (P2) in an even-numbered row of pixel units (P), and an odd number of first sub-pixel units (P1) in an even-numbered row of pixel units (P) are connected to the corresponding first scan line (11), and an odd number of first sub-pixel units (P1) in an odd-numbered row of pixel units (P), an even number of second sub-pixel units (P2) in an odd-numbered row of pixel units (P), an odd number of second sub-pixel units (P2) in an even-numbered row of pixel units (P), and an even number of first sub-pixel units (P1) in an even-numbered row of pixel units (P) are connected to the corresponding second scan line (12).

6. The driving method for the array substrate according to any one of claims 1-5, characterized in that, The array substrate is provided with a plurality of first thin film transistors (4), a plurality of second thin film transistors (5), a first control line (6), a second control line (7), and a plurality of scan signal lines (8). The first scan line (11) is connected to the first control line (6) and the scan signal line (8) through the first thin film transistor (4), and the second scan line (12) is connected to the second control line (7) and the scan signal line (8) through the second thin film transistor (5). The first scan line (11) and the second scan line (12) that are adjacent to each other in each row of pixel units (P) are connected to the same scan signal line (8). The driving method includes: Within each frame, for the first half of the frame time, the first control line (6) controls all the first thin film transistors (4) to turn on and scan the first scan line (11) through the scan signal line (8), and for the second half of the frame time, the second control line (7) controls all the second thin film transistors (5) to turn on and scan the second scan line (12) through the scan signal line (8).

7. An array substrate, characterized in that, The driving method for the array substrate as described in any one of claims 1-6, wherein the array substrate is provided with a plurality of scan lines, a plurality of data lines (2) and a plurality of pixel units (P) arranged in an array, wherein each pixel unit (P) has a first sub-pixel unit (P1) and a second sub-pixel unit (P2), a column of the first sub-pixel units (P1) and a column of the second sub-pixel units (P2) are arranged alternately in the row direction, the data lines (2) are disposed between a column of the first sub-pixel units (P1) and a column of the second sub-pixel units (P2), and a column of the first sub-pixel units (P1) and a column of the second sub-pixel units (P2) are disposed between two adjacent data lines (2), and a column of the first sub-pixel units (P1) and a column of the second sub-pixel units (P2) adjacent to the left and right of the data lines (2) are both connected to the same data line (2); The two adjacent scan lines are a first scan line (11) and a second scan line (12), and the first scan line (11) and the second scan line (12) are arranged alternately in the column direction. The first scan line (11) and the second scan line (12) are provided on the upper and lower sides of each row of sub-pixel units (P), and the first scan line (11) and the second scan line (12) are provided between adjacent rows of sub-pixel units (P). Of the two adjacent pixel units (P) above and below, one pixel unit (P) is connected to the first scan line (11), and the other pixel unit (P) is connected to the second scan line (12); of the two adjacent pixel units (P) on the left and right sides of the data line (2), one pixel unit (P) is connected to the first scan line (11), and the other pixel unit (P) is connected to the second scan line (12).

8. The array substrate according to claim 7, characterized in that, In each row of pixel units (P), all first sub-pixel units (P1) are connected to the same scan line, and all second sub-pixel units (P2) are connected to the same scan line; Alternatively, in each row of pixel units (P), odd and even numbers of the first sub-pixel units (P1) are connected to different scan lines, and odd and even numbers of the second sub-pixel units (P2) are connected to different scan lines.

9. The array substrate according to claim 7 or 8, characterized in that, The array substrate is provided with a plurality of first thin-film transistors (4), a plurality of second thin-film transistors (5), a first control line (6), a second control line (7), and a plurality of scan signal lines (8). The first scan line (11) is connected to the first control line (6) and the scan signal line (8) through the first thin-film transistor (4), and the second scan line (12) is connected to the second control line (7) and the scan signal line (8) through the second thin-film transistor (5). The first scan line (11) and the second scan line (12) that are adjacent to each other in each row of pixel units (P) are connected to the same scan signal line (8).

10. A display device, characterized in that, The system includes a color filter substrate (31) and an array substrate (32) as described in any one of claims 7-9. The color filter substrate (31) and the array substrate (32) are disposed opposite to each other. A liquid crystal layer (33) is disposed between the color filter substrate (31) and the array substrate (32). An upper polarizer (51) is disposed on the color filter substrate (31), and a lower polarizer (52) is disposed on the array substrate (32). The light transmission axes of the upper polarizer (51) and the lower polarizer (52) are perpendicular to each other.

Images