Reference current generator of non-volatile memory

Abstract

A reference current generator comprises two transistors, a resistor and a mirror image circuit. The source of the first transistor receives a power voltage, the drain is connected to a first node, and the gate is connected to a second node. The source of the second transistor receives the power voltage, and the drain and the gate are connected to the third node. The resistor is connected between the second node and the third node. The input end of the mirror image circuit receives an input current, the first mirror image end is connected to the second node, and the second mirror image end is connected to the first node. The first mirror end and the second mirror end respectively generate a first mirror current and a second mirror current. The first transistor generates a saturation current. In addition, the reference current is equal to the saturation current minus the second mirror current.

Description

Technical Field

[0001] The present invention relates to a current generator, and more particularly to a reference current generator for a non-volatile memory. Existing technology

[0002] As is well known, non-volatile memory includes a memory cell array, which consists of multiple memory cells, all of which are non-volatile. Furthermore, each non-volatile memory cell contains one storage cell. For example, a storage cell might be a floating gate transistor. The storage state of a non-volatile memory cell is determined by the number of carriers stored in the floating gate of the floating gate transistor.

[0003] For example, a floating-gate transistor is a P-type floating-gate transistor, and the carriers are electrons. When programming a memory cell, electrons can be injected into the floating gate of the floating-gate transistor, representing that the floating gate stores carriers. At this time, the memory cell is in the programmed state, or on state. When erasing a memory cell, electrons can be ejected from the floating gate of the floating-gate transistor, representing that the floating gate does not store carriers. At this time, the memory cell is in the erased state, or off state. The on and off states represent two different storage states of the memory cell.

[0004] Of course, the storage cell of a memory cell can also be an N-type floating gate transistor. Controlling the number of storage carriers in the floating gate of the floating gate transistor can also make the memory cell either open or closed.

[0005] Furthermore, when a memory cell is read, the cell in the on state generates a larger cell current, also known as the on current. The cell in the off state generates a smaller cell current, also known as the off current. In other words, the storage state of a memory cell can be determined based on the magnitude of the cell current generated during a read operation.

[0006] To determine the storage state of a memory cell, a reference current generator and a sensing circuit are designed into a non-volatile memory. The reference current generator produces a reference current, the magnitude of which is set between the turn-on current and the turn-off current. During a read operation, the sensing circuit receives the reference current and the memory cell current generated by the memory cell, and determines the storage state of the memory cell.

[0007] When the current in the memory cell is greater than the reference current, the sensing circuit determines that the memory cell is in a programming state or an on state. When the current in the memory cell is less than the reference current, the sensing circuit determines that the memory cell is in an erasing state or a off state.

[0008] Basically, only after the non-volatile memory is manufactured and tested can its manufacturing process corner be determined. Furthermore, the memory cells at different process corners, as well as the operating temperature, will affect the current draw of the memory cells.

[0009] Please refer to Figure 1 The diagram shows the cell current and reference current for various manufacturing process angles and operating temperatures in existing non-volatile memories.

[0010] Read operations were performed on all memory cells at the typical-typical corner (TT corner), and statistics were compiled. At an operating temperature of -40℃, the minimum turn-on current (Min.I.) among the memory cells in the active state was determined. ON The maximum shutdown current (Max. I) is approximately 18 μA. Among the memory cells in the off state, the maximum shutdown current is... OFF The minimum turn-on current is approximately 1 μA. At an operating temperature of 25°C, the minimum turn-on current in the powered-on state of the memory cell is approximately 16 μA. The maximum turn-off current in the powered-off state of the memory cell is approximately 1 μA. At an operating temperature of 150°C, the minimum turn-on current in the powered-on state of the memory cell is approximately 14 μA. The maximum turn-off current in the powered-off state of the memory cell is approximately 2 μA.

[0011] Read operations were performed and statistics were compiled for all memory cells at the fast-fast corner (FF) angle. At an operating temperature of -40°C, the minimum turn-on current for the memory cells in the on state was approximately 20 μA. The maximum turn-off current for the memory cells in the off state was approximately 1 μA. At an operating temperature of 25°C, the minimum turn-on current for the memory cells in the on state was approximately 18 μA. The maximum turn-off current for the memory cells in the off state was approximately 2 μA. At an operating temperature of 150°C, the minimum turn-on current for the memory cells in the on state was approximately 14 μA. The maximum turn-off current for the memory cells in the off state was approximately 3 μA.

[0012] Read operations were performed and statistics were compiled for all memory cells at the slow-slow corner (SS corner). At an operating temperature of -40°C, the minimum turn-on current for memory cells in the on state was approximately 16 μA. The maximum turn-off current for memory cells in the off state was approximately 1 μA. At an operating temperature of 25°C, the minimum turn-on current for memory cells in the on state was approximately 14 μA. The maximum turn-off current for memory cells in the off state was approximately 1 μA. At an operating temperature of 150°C, the minimum turn-on current for memory cells in the on state was approximately 12 μA. The maximum turn-off current for memory cells in the off state was approximately 1 μA.

[0013] like Figure 1 As shown, during read operations, in order to accurately determine the storage state of various manufacturing process corner memory cells under different operating temperatures, a reference current generator can be designed in the non-volatile memory, and the reference current I... REF The reference current generator is set at 8.5μA. Therefore, during the read operation, the reference current generator outputs a reference current I of 8.5μA. REF To the sensing circuit. The sensing circuit is based on the reference current I. REF The storage state of a memory cell is determined by the magnitude of the current generated by the memory cell. Specifically, when the memory cell current is greater than the reference current, the sensing circuit determines that the memory cell is in the ON state. When the memory cell current is less than the reference current, the sensing circuit determines that the memory cell is in the OFF state.

[0014] Basically, a reference current generator includes a bandgap reference circuit and a resistor R. POLY Among them, the resistance R POLY This is a polysilicon resistor. The bandgap reference circuit can generate a bandgap voltage (V) that remains almost unchanged with temperature.BG For example, bandgap voltage V BG The voltage is 1.2V. Additionally, a 141.2KΩ polysilicon resistor R is designed. POLY Therefore, the reference current generator can output a reference current I of approximately 8.5 μA. REF (I REF =V BG / R POLY ).

[0015] However, current semiconductor manufacturing processes cannot produce polycrystalline silicon resistors R with precise resistance values. POLY The polycrystalline silicon resistor R is fabricated using semiconductor manufacturing processes. POLY Its resistance value has an error range of approximately ±25%. That is to say, when the polysilicon resistor R... POLY After fabrication, its resistance will be between 105.9KΩ and 176.5KΩ, resulting in a reference current I. REF The magnitude is between 6.8 μA and 11.3 μA. That is, the reference current I... REF The error range is approximately between +33% and -20%.

[0016] For example, such as Figure 1 As shown, when performing a read operation on a memory cell at the SS angle at an operating temperature of 150°C, in the worst case, the reference current generator may output a reference current I of 11.3μA. REF The storage cell generates a storage cell current of 12μA. Clearly, the difference between these two currents is only about 0.7μA.

[0017] Because the difference between the two currents is very small, the sensing circuit will take a long time to determine the storage state, resulting in a decrease in the read speed of the non-volatile memory. Of course, there is also a high possibility of misjudgment by the sensing circuit. Summary of the Invention

[0018] This invention relates to a reference current generator for use in non-volatile memory. The reference current generator includes: a first transistor, the source of which receives a first power supply voltage, the drain of which is connected to a first node, and the gate of which is connected to a second node; a second transistor, the source of which receives the first power supply voltage, the drain of which is connected to a third node, and the gate of which is connected to the third node; a first resistor, a first terminal of which is connected to the third node, and a second terminal of which is connected to the second node; and a first mirror circuit, an input terminal of which receives an input current. A first mirror terminal of the first mirror circuit is connected to the second node, and a second mirror terminal of the first mirror circuit is connected to the first node; wherein the first mirror terminal of the first mirror circuit generates a first mirror current, the second mirror terminal of the first mirror circuit generates a second mirror current, and there is a first proportional relationship between the input current, the first mirror current, and the second mirror current; wherein the first transistor and the second transistor operate in a saturation mode, and the first transistor generates a saturation current; wherein the reference current generator outputs a first reference current, and the first reference current is equal to the saturation current minus the second mirror current.

[0019] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0020] Figure 1 This is a schematic diagram showing the cell current and reference current for various manufacturing process angles and operating temperatures in existing non-volatile memories.

[0021] Figure 2 This is the reference current generator for the present invention;

[0022] Figure 3A and Figure 3B Examples of various input current generators;

[0023] Figure 4A and Figure 4B This is a variety of examples of another mirror circuit;

[0024] Figure 5 A schematic diagram of a sensing circuit used in non-volatile memory; and

[0025] Figure 6 This is a schematic diagram showing the storage cell current and reference current for various manufacturing process angles and operating temperatures in the non-volatile memory of this invention.

[0026] [Symbol Explanation]

[0027] 200: Reference Current Generator

[0028] 210, 330, 400, 410: Mirror circuits

[0029] 305: Current Source

[0030] 310: Bandgap Reference Circuit

[0031] 320: Operational Amplifier

[0032] 420, 430: Current mirror

[0033] 500: Sensing Circuit

[0034] 510: Current comparator Detailed Implementation

[0035] This invention proposes a reference current generator for use in non-volatile memory. The reference current generator and the non-volatile memory are fabricated on the same IC chip. That is, the reference current generator and the transistors in the memory cell belong to the same manufacturing process corner. Therefore, the reference current output by the reference current generator is related to the manufacturing process corner of the memory cell. Furthermore, the reference current output by the reference current generator can also vary with the operating temperature.

[0036] Please refer to Figure 2 The diagram illustrates the reference current generator of this invention. The reference current generator 200 includes a mirror circuit 210 and a transistor M. A M B With resistance R POLY1 .

[0037] transistor M A The source receives the power supply voltage V DD transistor M A The drain of transistor M is connected to node a. A The gate of transistor M is connected to node b. B The source receives the power supply voltage V DD transistor M B The drain of transistor M is connected to node c. B The gate is connected to node c. Resistor R POLY1 The first end is connected to node c, and the resistor R POLY1 The second end is connected to node b. Here, the resistor R... POLY1 It is a polycrystalline silicon resistor.

[0038] The mirror circuit 210 includes an input terminal, a first mirror terminal, and a second mirror terminal. The input terminal of the mirror circuit 210 receives an input current I. IN The first mirror terminal of the mirror circuit 210 is connected to node b, and the first mirror terminal can generate a first mirror current I. M1 The second mirror terminal of the mirror circuit 210 is connected to node a, and the second mirror terminal can generate a second mirror current I. M2 Among them, the input current I IN First mirror current I M1 With the second mirror current I M2 There is a specific proportional relationship between them.

[0039] In this embodiment, the mirror circuit 210 includes three transistors M1, M2, and M3. The drain of transistor M1 serves as the input terminal to receive the input current I. IN The source of transistor M1 receives the power supply voltage V. SS The gate of transistor M1 is connected to the drain of transistor M1. The drain of transistor M2 serves as the first mirror terminal, and the drain of transistor M2 is connected to node b. The source of transistor M2 receives the power supply voltage V. SS The gate of transistor M2 is connected to the gate of transistor M1. The drain of transistor M3 serves as the second mirror terminal, and the drain of transistor M3 is connected to node a. The source of transistor M3 receives the power supply voltage V. SS The gate of transistor M3 is connected to the gate of transistor M1. The size of transistors M1, M2, and M3 determines the input current I. N First mirror current I M1 With the second mirror current I M2 The proportional relationship between them. Furthermore, the power supply voltage V... DD Greater than the power supply voltage V SS For example, the power supply voltage V DD It is 3.3V, power supply voltage V SS It is 0V.

[0040] According to an embodiment of the present invention, in the mirror circuit 210, the input current I N First mirror current I M1 With the second mirror current I M2 The ratio between them is 1:2:2. Furthermore, when the reference current generator 200 is operating normally, transistor M... A M B When operating in saturation mode, transistor M A A saturation current (I) is generated. AAnd the reference current generator 200 outputs a reference current I. REF Among them, the reference current I REF Equal to saturation current I A Subtract the second mirror current I M2 That is, (I) REF =I A -I M2 ).

[0041] Therefore, I M1 =I M2 =2×I IN I M1 = I M2 =K P ×(V ODB ) 2 I A =K P ×(V ODA ) 2 Among them, K P These are the device parameters of a p-type transistor. For example, transistor M... A M B They have the same size and the same component parameter K. P With the same threshold voltage (V) T ), and V T It is a negative value. Furthermore, V ODA For transistor M A The overdrive voltage, V ODA =(V SGA +V T V ODB For transistor M B overdrive voltage, V ODB =(V SGB +V T V SGA For transistor M A The source-gate voltage, V SGB For transistor M B The source-gate voltage.

[0042] Depend on Figure 2 It can be seen that V SGA =V SGB +ΔV. Where ΔV is the resistance R. POLY1 The voltage drop across. Therefore, I REF =I A -I M1= K P ×(V ODA 2 -V ODB 2 ) = K P ×(V ODA +V ODB )×(V ODA -V ODB Due to V ODB =( V ODA -ΔV), so I REF =K P ×(2V ODB -ΔV)×ΔV.

[0043] Additionally, when 2V ODA When it is much greater than ΔV, (2V) ODA -ΔV) is approximately equal to 2V ODA Additionally, due to I A =K P ×(V ODA ) 2 Therefore, use I A With K P To replace V ODA I can then be derived REF That is, I REF = 2×K P ×V ODA ×ΔV=2× ×ΔV. For example, when V ODA When it is at least greater than five times ΔV, it can be considered as 2V. ODA Much greater than ΔV.

[0044] In this embodiment, the component parameter K of the P-type transistor P =(1 / 2)×μ P ×C OX ×(W / L). Where, μ P C represents hole mobility. OX Here, W is the oxide capacitance, W is the channel width, and L is the channel length. Generally, a P-type transistor with an FF angle has the following component parameters K... P Maximum. The component parameter K of a P-type transistor with a TT angle. P Secondly, the component parameter K of a P-type transistor at the SS angle. P Minimum. That is, K P (FF)> K P (TT)>K P(SS). Due to the transistors in the memory cell and transistor M A M B They belong to the same manufacturing process angle. Based on the aforementioned reference current I... REF From the equation, it can be seen that under the same bias conditions, the P-type transistor M belonging to the FF angle... A M B The generated reference current I REF Larger, belonging to the SS angle P-type transistor M A M B The generated reference current I REF Smaller.

[0045] In addition, hole mobility μ P It decreases as temperature increases. For example, at an operating temperature of 150°C, the hole mobility μ... P Minimum. At an operating temperature of 25°C, the hole mobility μ is [missing value]. P Secondly, at an operating temperature of -40℃, the hole mobility μ P The highest. That is to say, μ P (150℃)<μ P (25℃)<μ P (-40℃). Based on the above reference current I REF From the equation, it can be seen that under the same bias conditions, the reference current I generated at an operating temperature of 150℃ is... REF The reference current I generated at an operating temperature of -40°C is relatively small. REF Larger.

[0046] Please refer to Figure 3A and Figure 3B The illustrations depict various examples of input current generators. This input current generator can produce an input current to the reference current generator of the present invention.

[0047] like Figure 3A As shown, the input current generator includes a current source 305. The current source 305 generates an input current I. IN And the input current I IN Input terminal of input mirror circuit 210.

[0048] like Figure 3B As shown, the input current generator includes a bandgap reference circuit 310, an operational amplifier 320, a mirror circuit 330, and a resistor R. POLY2 The bandgap reference circuit 310 generates the bandgap voltage V. BG For example, resistor R POLY2A polysilicon resistor is connected to node d. The input of mirror circuit 330 is connected to node d to receive a first current I. R The mirror terminal of the mirror circuit 330 can generate an input current I. IN Operational amplifier 320 receives bandgap voltage V. BG The operational amplifier 320 is connected to node d and the mirror circuit 330 to control the mirror circuit 330.

[0049] The mirror circuit 330 includes two transistors M. C M D Transistor M C M D The source receives the supply voltage V SS Transistor M C M D The gates of the transistors are interconnected and connected to the output of operational amplifier 320. Transistor M C The drain of transistor M serves as the input terminal of the mirror circuit 330. D The drain of the amplifier serves as the mirror terminal of the mirror circuit 330. The inverting input (-) of the operational amplifier 320 receives the bandgap voltage V. BG The non-inverting input (+) of operational amplifier 320 is connected to node d, and the output of operational amplifier 320 is connected to transistor M. C The gate. Furthermore, the resistor R POLY2 The first end is connected to node d, and the resistor R POLY2 The second terminal receives the supply voltage V SS .

[0050] In this embodiment, the first current I R With input current I N The ratio between them is 1:M, where M is a positive real number. When the input current generator is operating normally, the voltage at node d will be equal to the bandgap voltage V. BG First current I R Equal to (V) BG / R POLY2 Input current I N Equal to (M×I) R That is to say, the first current I R With input current I N There is a specific proportional relationship between them. For example, when M equals 1, the input current I... N Equal to the first current I R And the input current I N Equal to (V) BG / R POLY2 ).

[0051] exist Figure 3B In the input current generator, resistor R POLY2 It is a polysilicon resistor. That is, when the reference current generator 200 is fabricated on the IC chip, the resistor R... POLY1 R POLY2 There will be the same error, so the resistance R can be made... POLY1 The voltage drop ΔV on the plate remains constant and hardly changes.

[0052] Essentially, the non-volatile memory also includes a sensing circuit. During a read operation, the sensing circuit receives a reference current I generated by the reference current generator 200. REF It is used to determine the storage status of a storage unit.

[0053] In other embodiments, the reference current generator 200 may further include another mirror circuit for generating a mirrored reference current I. MREF During the read operation, the sensing circuit receives the mirrored reference current I. MREF This allows the sensing circuit to operate based on the mirror reference current I. MREF To determine the storage status of the storage unit. Please refer to... Figure 4A and Figure 4B The diagrams shown represent various examples of another mirror circuit.

[0054] like Figure 4A As shown, the input of the mirror circuit 400 is connected to node a to receive the reference current I. REF The mirror terminal of the mirror circuit 400 can output a mirrored reference current (I). MREF ), where the reference current I REF With mirror reference current I MREF There is a specific proportional relationship between them.

[0055] For example, the mirror circuit 400 includes transistors M4 and M5. The drain of transistor M4 is connected to node a to receive a reference current I. REF The source of transistor M4 receives the power supply voltage V. SS The gate of transistor M4 is connected to the drain of transistor M4. The drain of transistor M5 serves as a mirror terminal to receive the mirror reference current I. MREF The source of transistor M5 receives the power supply voltage V. SS The gate of transistor M5 is connected to the gate of transistor M4.

[0056] like Figure 4B As shown, the mirror circuit 410 includes two current mirrors 420 and 430. The input terminal of the mirror circuit 410 is connected to node a to receive the reference current I.REF The mirror terminal of the mirror circuit 410 can output a mirrored reference current (I). MREF ), where the reference current I REF With mirror reference current I MREF There is a specific proportional relationship between them.

[0057] For example, current mirror 420 includes transistors M4 and M5, and current mirror 430 includes transistors M6 and M7. The drain of transistor M4 is connected to node a to receive the reference current I. REF The source of transistor M4 receives the power supply voltage V. SS The gate of transistor M4 is connected to the drain of transistor M4. The source of transistor M5 receives the power supply voltage V. SS The gate of transistor M5 is connected to the gate of transistor M4. The drain of transistor M6 is connected to the drain of transistor M5, and the source of transistor M6 receives the power supply voltage V. DD The gate of transistor M6 is connected to the drain of transistor M6. The drain of transistor M7 can generate a mirror reference current I. MREF The source of transistor M7 receives the power supply voltage V. DD The gate of transistor M7 is connected to the gate of transistor M6.

[0058] Please refer to Figure 5 The diagram shown is a schematic of a sensing circuit used in non-volatile memory.

[0059] The sensing circuit 500 receives the mirror reference current I. MREF And the memory cell current I generated by the memory cell CELL And based on the mirror reference current I MREF and storage cell current I CELL This determines the storage state of the memory cell. Of course, the sensing circuit 500 can also receive a reference current I. REF and storage cell current I CELL And according to the reference current I REF and storage cell current I CELL This determines the storage status of the storage unit.

[0060] For example, the sensing circuit 500 is a current comparator 510. The first input terminal (e.g., the positive input terminal) of the current comparator 510 receives the memory cell current I. CELL The second input (e.g., the negative input) of the current comparator 510 receives the mirrored reference current I. MREF The output terminal of the current comparator 510 generates an output signal D. OUT .

[0061] When the storage cell current I CELL Greater than the mirror reference current I MREF At that time, the current comparator 510 generates an output signal D at a first logic level (e.g., logic high). OUT This indicates that the memory cell is in a programmed or enabled state. When the memory cell current I... CELL Less than the mirror reference current I MREF At that time, the current comparator 510 generates an output signal D at a second logic level (e.g., logic low). OUT This indicates that the memory cell is in an erased or off state. In other embodiments, a reference current I is used. REF To replace the mirror reference current I MREF When used to determine the storage state of a memory cell, the two current mirrors 420 and 430 can be omitted, and the reference current I is received at the second input terminal of the current comparator 520. REF That's all.

[0062] Please refer to Figure 6 The diagram illustrates the storage cell current and reference current at various manufacturing process angles and operating temperatures in the non-volatile memory of this invention.

[0063] As previously mentioned, existing non-volatile memories provide a reference current generator with a fixed reference current. The reference current generator of this invention outputs a reference current I. REF Or mirror reference current I MREF It can vary depending on the manufacturing process angle and operating temperature.

[0064] For example, the present invention uses a transistor with a TT angle to design the reference current generator 200, and at an operating temperature of 25°C, the reference current generator 200 can generate a mirror reference current I of approximately 8.5 μA. MREF .

[0065] like Figure 6 As shown, after the non-volatile memory is manufactured, when both the transistors of the memory cell and the reference current generator are at the TT angle, at an operating temperature of 25°C, the reference current generator 200 can generate a mirror reference current I of 8.5 μA. MREF Due to hole mobility μ P It decreases as temperature rises, that is, μ P (150℃)<μ P (25℃)<μ P (-40℃). Therefore, at an operating temperature of 150℃, the mirror reference current I... MREF It will decrease to approximately 6.9 μA. At an operating temperature of -40°C, the mirror reference current I...MREF It will rise to approximately 9.6 μA.

[0066] like Figure 6 As shown, after the non-volatile memory is manufactured, when both the transistors of the memory cell and the reference current generator are at the FF angle, due to the component parameter K... P (FF)> K P (TT). Therefore, compared to the reference current generator at angle TT, the mirrored reference current I generated by the reference current generator 200 at angle FF is less than that generated at an operating temperature of 25°C. MREF It will rise to approximately 9.3 μA. Additionally, due to the hole mobility μ... P It decreases as temperature rises, that is, μ P (150℃)<μ P (25℃)<μ P (-40℃). Therefore, at an operating temperature of 150℃, the mirror reference current I... MREF It will decrease to approximately 7.7 μA. At an operating temperature of -40°C, the mirror reference current I... MREF It will rise to approximately 10.8 μA.

[0067] like Figure 6 As shown, after the non-volatile memory is manufactured, when both the transistors of the memory cell and the reference current generator are at the SS angle, due to the component parameter K... P (TT)>K P (SS). Therefore, compared to the reference current generator at angle TT, the mirror reference current I generated by the reference current generator 200 at an operating temperature of 25°C is... MREF It will drop to approximately 7.8 μA. Additionally, due to the hole mobility μ... P It decreases as temperature rises, that is, μ P (150℃)<μ P (25℃)<μ P (-40℃). Therefore, at an operating temperature of 150℃, the mirror reference current I... MREF It will decrease to approximately 6.2 μA. At an operating temperature of -40°C, the mirror reference current I... MREF It will rise to approximately 9.9 μA.

[0068] In addition, due to the reference current I REF The change is proportional to the current I A The square root of the change, i.e., ΔI REF And the reference current I REF With mirror reference current I MREF There is a specific ratio relationship between them. This is due to the saturation current I... AThe reference current I varies depending on the manufacturing process and temperature conditions, so its square root is used to define the reference current. REF This helps reduce the impact of manufacturing processes and temperature conditions. Therefore, the reference current I REF It has low sensitivity to changes in manufacturing processes and temperature. In other words, compared to current I... A The error, the mirror reference current I MREF The error will also be smaller.

[0069] exist Figure 6 In the middle, the mirror reference current I MREF The error range is approximately +12.5% ​​to -9%. Therefore, when performing a read operation on a memory cell at the SS angle at an operating temperature of 150°C, in the worst case, the mirror reference current I... MREF The difference in current between the storage cell and the storage cell is approximately 4.7 μA. Because this current difference is large enough, the sensing circuit 500 can accurately determine the storage state of the storage cell.

[0070] Furthermore, when performing a read operation on a memory cell at the FF angle at an operating temperature of 150°C, in the worst-case scenario, the mirror reference current I... MREF The difference in current between the storage cell and the storage cell is approximately 3.4 μA. Because this current difference is large enough, the sensing circuit 500 can accurately determine the storage state of the storage cell.

[0071] As described above, the invention proposes a reference current generator for use in non-volatile memory. Since the reference current generator and the transistors in the memory cell belong to the same manufacturing process angle, the reference current output by the reference current generator is related to the manufacturing process angle of the memory cell. Furthermore, the reference current output by the reference current generator of the present invention can also vary with the operating temperature.

[0072] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A reference current generator for use in a non-volatile memory, the reference current generator comprising: A first transistor, wherein a source of the first transistor receives a first power supply voltage, a drain of the first transistor is connected to a first node, and a gate of the first transistor is connected to a second node; A second transistor, wherein a source of the second transistor receives the first power supply voltage, a drain of the second transistor is connected to a third node, and a gate of the second transistor is connected to the third node; A first resistor, a first end of which is connected to the third node, and a second end of which is connected to the second node; as well as A first mirror circuit, wherein an input terminal of the first mirror circuit receives an input current, a first mirror terminal of the first mirror circuit is connected to the second node, and a second mirror terminal of the first mirror circuit is connected to the first node; wherein the first mirror terminal of the first mirror circuit generates a first mirror current, the second mirror terminal of the first mirror circuit generates a second mirror current, and there is a first proportional relationship between the input current, the first mirror current and the second mirror current; The first transistor and the second transistor operate in a saturation mode, and the first transistor generates a saturation current. The reference current generator outputs a first reference current, which is equal to the saturation current minus the second mirror current.

2. The reference current generator of claim 1, wherein there is a voltage drop across the first resistor, an overdrive voltage of the first transistor is at least five times the voltage drop, and the overdrive voltage is equal to a source-gate voltage of the first transistor plus a threshold voltage of the first transistor.

3. The reference current generator as claimed in claim 1, wherein the first mirror circuit comprises: A third transistor, wherein a drain of the third transistor receives the input current, a gate of the third transistor is connected to the drain of the third transistor, and a source of the third transistor receives a second power supply voltage; A fourth transistor, the drain of which is connected to the second node, the gate of which is connected to the gate of the third transistor, and the source of which receives the second power supply voltage; as well as A fifth transistor, wherein a drain of the fifth transistor is connected to the first node, a gate of the fifth transistor is connected to the gate of the third transistor, and a source of the fifth transistor receives the second power supply voltage; The first power supply voltage is greater than the second power supply voltage.

4. The reference current generator as claimed in claim 1 further includes a current source that generates the input current and inputs it to the input terminal of the first mirror circuit.

5. The reference current generator as described in claim 1, further comprising: A bandgap reference circuit that generates a bandgap voltage; A second resistor, a first end of which is connected to a fourth node, and a second end of which receives a second supply voltage; A second mirror circuit, wherein an input terminal of the second mirror circuit is connected to the fourth node to receive a first current, and a mirror terminal of the second mirror circuit generates the input current; as well as An operational amplifier has an inverting input terminal receiving the bandgap voltage, a non-inverting input terminal connected to the fourth node, and an output terminal connected to the second mirror circuit for controlling the second mirror circuit.

6. The reference current generator as claimed in claim 5, wherein the first current is equal to the bandgap voltage divided by the resistance value of the second resistor, and there is a second proportional relationship between the first current and the input current.

7. The reference current generator as claimed in claim 5, wherein the first resistor and the second resistor are polysilicon resistors.

8. The reference current generator of claim 5, wherein the second mirror circuit comprises: A third transistor, the source of which receives the first supply voltage, the gate of which is connected to the output of the operational amplifier, and the drain of which is connected to the fourth node; as well as A fourth transistor, the source of which receives the first supply voltage, the gate of which is connected to the output of the operational amplifier, and the drain of which generates the input current; The first power supply voltage is greater than the second power supply voltage.

9. The reference current generator as claimed in claim 1 further includes a second mirror circuit, an input terminal of the second mirror circuit being connected to the first node to receive the first reference current, a mirror terminal of the second mirror circuit outputting a second reference current, and a second proportional relationship between the first reference current and the second reference current.

10. The reference current generator of claim 9, wherein the second mirror circuit comprises: A third transistor, wherein a drain of the third transistor is connected to the first node to receive the first reference current, a gate of the third transistor is connected to the drain of the third transistor, and a source of the third transistor receives a second power supply voltage; as well as A fourth transistor, one drain of which is the mirror terminal of the second mirror circuit to generate the second reference current, a gate of which is connected to the gate of the third transistor, and a source of which receives the second power supply voltage. The first power supply voltage is greater than the second power supply voltage.

11. The reference current generator of claim 9, wherein the second mirror circuit comprises: A third transistor, wherein a drain of the third transistor is connected to the first node to receive the first reference current, a gate of the third transistor is connected to the drain of the third transistor, and a source of the third transistor receives a second power supply voltage; A fourth transistor, a gate of which is connected to the gate of the third transistor, and a source of which receives the second power supply voltage; A fifth transistor, wherein a drain of the fifth transistor is connected to a drain of the fourth transistor, a gate of the fifth transistor is connected to the drain of the fifth transistor, and a source of the fifth transistor receives the first power supply voltage; A sixth transistor, one drain of which is the mirror terminal of the second mirror circuit to generate the second reference current, a gate of which is connected to the gate of the fifth transistor, and a source of which receives the first power supply voltage. The first power supply voltage is greater than the second power supply voltage.

12. The reference current generator of claim 9, wherein the non-volatile memory includes a storage cell and a sensing circuit; wherein, During a read operation, the sensing circuit receives a storage cell current generated by the storage cell and the second reference current, and determines a storage state of the storage cell based on the storage cell current and the second reference current.

13. The reference current generator of claim 12, wherein the memory cell is in a programming state when the memory cell current is greater than the second reference current; and the memory cell is in an erasure state when the memory cell current is less than the second reference current.

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