Chip system and calculation method

Abstract

The invention relates to the technical field of optical computing, in particular to a chip system and a computing method. A matrix input chip and a plurality of matrix multiplication chips are sequentially arranged on the glass substrate chip; two ends of the beam splitter are respectively connected with the light source and the matrix input chip, the matrix multiplication chip is provided with a first decoupling functional area, the first decoupling functional area comprises a plurality of row waveguides which are arranged at intervals, the row waveguides are provided with the beam splitters, the corresponding beam splitters are connected with calculation waveguides, and the calculation waveguides are provided with modulators; a second decoupling functional area is arranged on the glass substrate chip corresponding to the matrix multiplication chip, the second decoupling functional area comprises a plurality of column waveguides arranged at intervals, and the column waveguides are connected with the calculation waveguide through a coupler assembly. The invention provides a large-scale optical computing chip realized based on a decoupling concept, which can improve the computing scale on the basis of realizing process simplification.

Description

[0001] Divisional application This application is a divisional application of the patent application filed on December 3, 2025, with application number 2025118048874, entitled "An Optical Computing Chip System and Computing Method". Technical Field

[0002] This invention relates to the field of optical computing chip technology, specifically to a chip system and computing method. Background Technology

[0003] Artificial intelligence (AI) technology is a key driving force for the new round of technological revolution and industrial transformation. Its foundation is intelligent computing power, namely the computing system capabilities for training and running AI algorithm models. Currently, the scale of computing power and energy consumption are key challenges.

[0004] The computing power scale depends on the size and communication bandwidth of the interconnection network between AI accelerators, as well as the performance of the AI ​​accelerators. The main task of the neural network processor in an AI accelerator is matrix operation. Compared with traditional electrical matrix operation, optical matrix operation has the potential advantages of high-speed parallel processing, low latency, and low power consumption. However, the size of optical matrix multipliers is limited by the exposure size of the photolithography process. Currently, the exposure area size of stepper lithography machines used to fabricate optical chips is typically no more than 2.6cm × 3.3cm.

[0005] To further expand computing scale, one approach is to stitch together the exposed areas using a stepper lithography machine to increase chip size; however, this increases the complexity of the lithography process and reduces yield. Another approach is to package multiple optoelectronic chips on the same substrate using 2.5D / 3D packaging, interconnecting them via electrical signals to improve computing scale. However, electrical interconnects between chips increase chip area and power consumption. Optical interconnects, on the other hand, enable high-bandwidth parallel transmission, overcoming the limitations of electrical interconnect size and power consumption.

[0006] For example, patent application CN 117492142A discloses an on-chip optical interconnect structure and its fabrication method, in which inter-chip optical interconnects can bridge multiple optoelectronic chips through multiple discrete passive waveguide chips. As another example, patent application CN118732150A discloses a semiconductor structure and its manufacturing method, which connects multiple optoelectronic chips to a common waveguide substrate. However, as chip interconnects or chip size increase, the difficulty of chip design and fabrication processes significantly increases, making it difficult to achieve substantial breakthroughs in computing scale.

[0007] Therefore, there is an urgent need for a new type of optical computing chip with lower process complexity and larger computing scale. Summary of the Invention

[0008] The purpose of this invention is to provide an optical computing chip system and computing method, which partially solves or alleviates the above-mentioned shortcomings in the prior art, and can improve the computing scale and expand the computing performance of the optical computing chip to a certain extent.

[0009] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution: A first aspect of the present invention is to provide an optical computing chip system, comprising: PCB board; Glass substrate chip disposed on the PCB board; At least one set of matrix operation chips are sequentially disposed on the glass substrate chip, and the set of matrix operation chips includes: a matrix input chip with n rows and n columns of input, and a plurality of matrix multiplication chips corresponding to the matrix input chip; A first beam splitter is connected at both ends to a light source and a matrix input chip, respectively, to split the light source into at least n light signals and input the n light signals to the matrix input chip, which modulates the light signals to generate corresponding input signals; and the matrix input chip is connected to the matrix multiplication chip to input the input signals to the matrix multiplication chip. The matrix multiplication chip is provided with a first decoupling functional area, which includes: Multiple spaced-apart traveling waveguides are provided, each traveling waveguide is provided with at least one second beam splitter, and each second beam splitter is connected to a traveling branch waveguide, which is provided with a modulator. A second decoupling functional area is provided on the glass substrate chip corresponding to the matrix multiplication chip, and the second decoupling functional area includes: Multiple spaced column waveguides are connected to the row branch waveguides via coupler assemblies; The matrix multiplication chip is used to output the first incident light formed by the product of the input signal and the weight signal. The first incident light is transmitted to the column waveguide via the coupler assembly, and a total summation calculation is performed in the column waveguide. The calculation result is then output through the column waveguide.

[0010] In some embodiments, the modulator includes: a phase change modulation layer disposed above the row branch waveguide, and a heating layer disposed above the phase change modulation layer, and the heating layer being provided with pads; wherein the pads are used to transmit electrical signals to the heating layer, and the heat of the heating layer is controlled by the magnitude of the electrical signals.

[0011] In some embodiments, the first decoupling functional area further includes: a metal interconnect line for connection to a power source, the metal interconnect line being connected to the pad.

[0012] In some embodiments, the system further includes at least one first electrical chip, and at least one first electrical chip is connected to the matrix input chip and / or the matrix multiplication chip.

[0013] In some embodiments, when the first electrical chip is connected to the matrix multiplication chip, the first electrical chip includes or is connected to a power source.

[0014] In some embodiments, the device further includes at least one second electrical chip, and the at least one second electrical chip is connected to the glass substrate chip; the second electrical chip is used to receive the calculation result through the glass substrate chip and to process or store the calculation result.

[0015] In some embodiments, the coupler assembly includes: a first coupler and a second coupler; the row waveguide includes a plurality of row bus waveguides, the column waveguide includes a plurality of column bus waveguides, at least one row bus waveguide and at least one column bus waveguide are intersected on a plane projection and a computing unit is formed at the intersection, the computing unit is correspondingly provided with the second beam splitter, the modulator and the combiner; The computing unit includes a row branch waveguide and a column branch waveguide; the row branch waveguide is split from the row bus waveguide by the second beam splitter, and the column branch waveguide is merged into the column bus waveguide by the combiner; the first coupler is disposed at the output end of the row branch waveguide, and the second coupler is disposed at the output end of the column branch waveguide.

[0016] In some embodiments, the coupler assembly includes: a first coupler disposed on the matrix multiplication chip and a second coupler disposed on the glass substrate chip.

[0017] In some embodiments, the first coupler causes the incoming first incident light to deflect by a first angle and be converted into a second incident light, while the second coupler is used to receive the second incident light and cause the second incident light to deflect by a second angle and be converted into a third incident light, wherein the second angle is greater than or equal to the first angle, and the first angle is less than or equal to 90°.

[0018] The present invention also provides an optical computing method implemented by an optical computing chip system according to any embodiment, comprising the following steps: The input light source is split into n optical signals using the first beam splitter. The n optical signals are used to input into the n rows and columns of the matrix input chip, where each row of optical signals corresponds to one column of input signals; Multiple input signals are input into the glass substrate chip and then enter the matrix multiplication chip via the glass substrate chip; The weight signal is input into the matrix multiplication chip, which ultimately outputs the product obtained by multiplying the input signal and the weight signal.

[0019] Beneficial technical effects: It should be noted that, unlike conventional integrated computing approaches, this invention rationally allocates (i.e., decouples) optoelectronic computing tasks spatially on a novel optoelectronic computing chip system, thereby expanding the scale of matrix multiplication operations through the coupling of multiple independent chips. Furthermore, this spatial and functional synergistic distribution simplifies the fabrication of core chips, such as simplifying the structure of matrix multiplication chips and reducing their fabrication difficulty; it also facilitates the processing of phase change materials on glass substrate chips. On the other hand, this synergistic distribution actually helps to increase the density of computing units in the optoelectronic chip.

[0020] Preferably, the present invention uses an external substrate waveguide to achieve beam splitting in matrix multiplication, in order to expand the scale of matrix multiplication operations.

[0021] Specifically, this invention provides a scheme that uses a large-scale glass substrate chip as a connection layer to connect multiple small matrix input chips and multiple small matrix multiplication chips as a whole. By decoupling the matrix multiplication chip that performs the core multiplication operation, row waveguides and column waveguides are separated on the matrix multiplication chip and the glass substrate chip. This reduces the design complexity of each individual chip through the collaboration of the multi-chip system. Furthermore, for the decoupled chip system, it is preferable to place the metal interconnect lines on the matrix multiplication chip, which can further reduce the wiring difficulties between the downguides and metal interconnect lines in the original chip architecture. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0023] Figure 1 This is a schematic diagram of the packaging structure of an optical computing chip system in an exemplary embodiment of the present invention; Figure 2 This is a top view schematic diagram of an optical computing chip system in another exemplary embodiment of the present invention; Figure 3 This is a schematic diagram of an exemplary weighted modulator of the present invention; Figure 4 This is a schematic diagram of the structure of another exemplary weighted modulator of the present invention; Figure 5 This is a schematic diagram of the structure of another exemplary waveguide substrate chip of the present invention; Figure 6 This is a schematic diagram of the waveguide arrangement in an exemplary embodiment of the present invention; Figure 7 This is a schematic diagram of the transmission angle for inter-chip transmission in an exemplary embodiment of the present invention; Figure 8 This is a schematic diagram of the coupler architecture in an exemplary embodiment of the present invention; Figure 9 This is a partial structural diagram of the coupler in an exemplary embodiment of the present invention; Figure 10 This is a schematic diagram of the coupler architecture in another exemplary embodiment of the present invention.

[0024] Summary of attached image labels: 010, PCB board; 01, First beam splitter; 011, Sub-beam splitter; 02, Matrix input chip; 03, Matrix multiplication chip; 04, Light source; 05, Glass substrate chip; 501, Substrate layer; 502, First cladding layer; 503, Second cladding layer; 504, Via; 505, Grating coupler; 506, First waveguide; 508, Second waveguide; 509, Phase change modulation layer; 510, Heating layer; 511, Pad; 06, Third electrical chip; 07, First electrical chip; 08, Second electrical chip; 09, Optical fiber; 12. Second beam splitter; 13. Modulator; 14. Metal interconnect line; 15. Ground line; 111. Row bus waveguide; 211. Column bus waveguide; 212. Column branch waveguide; 1121. Row first-level branch waveguide; 1122. Row second-level branch waveguide; 1121. Row first-level branch waveguide; 22. Combiner; 3. Coupler; 9. Computation unit; 1. First chip; 2. Second chip; 1002. Front coupler; 1003. Back coupler; 10011, Transparent substrate layer; 100121, Upper cladding layer; 100122, Lower cladding layer; 1003a, Waveguide core layer; 10031, Input / output terminal; 10032, Beam expansion region; 10033, Diffraction region; 10035, Metal reflective layer; 10034, Microlens. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0026] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0027] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0030] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0031] As used in this specification, the term "about" typically means + / -5% of the value, more typically + / -4% of the value, more typically + / -3% of the value, more typically + / -2% of the value, even more typically + / -1% of the value, and even more typically + / -0.5% of the value.

[0032] In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within those ranges. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This rule applies regardless of the breadth of the range.

[0033] Optical chips (or photonic chips, referred to simply as chips in this article): A photonic chip is an integrated circuit chip based on photonics principles. It achieves optoelectronic integration by integrating photonic devices onto the chip. Photonic chips realize various complex functions through the generation, transmission, processing, modulation, and detection of light waves. The "scale" of an optical chip refers to the size of the photonic computing array on a mask within a conventional wafer area (such as an 8-inch or 12-inch wafer), typically expressed in the form X1*X2, where X1 represents the number of rows in the photonic computing array, and X2 represents the number of columns. X1 and X2 are primarily limited by: 1. the size of the computing unit; 2. the area of ​​a single mask exposure plate on an 8-inch or 12-inch wafer.

[0034] Coupler: A coupler in an optical chip is a key passive component used to achieve optical power redistribution and mode conversion. Its core function is to efficiently and controllably transmit optical signals between different optical waveguides on the chip through specific effects / structures (such as waveguide proximity effect, grating, etc.). It can distribute input optical energy to one or more output ports according to a predetermined ratio and predetermined deflection angle.

[0035] Translucent substrate layer: refers to a substrate (substrate) made of a material with high light transmittance. The term "translucent" in "translucent substrate layer / translucent substrate" indicates that the chip's supporting substrate material exhibits excellent optical transmittance properties with low absorption and low scattering within the target operating wavelength range (such as visible light and near-infrared). Specifically, the translucent substrate layer in this invention can be a glass substrate, and the corresponding chip can be referred to as a glass substrate chip (or simply a glass chip).

[0036] Transparent substrate waveguide chip: refers to an integrated photonic chip that uses a material with high light transmittance as a substrate, on which or inside an optical waveguide structure is built to guide and manipulate optical signals.

[0037] A blazed grating is a diffraction grating that uses a specially shaped groove (usually a sawtooth profile) to concentrate the energy of incident light onto a specific, predetermined order. Unlike ordinary gratings that disperse energy across multiple orders, it utilizes the "blaze effect." By controlling the tilt angle of the grooves, the specular reflection direction is aligned with the diffraction direction of the desired order, thereby maximizing the intensity of diffracted light at that order. This design significantly improves the diffraction efficiency of the grating in a specific wavelength band (i.e., the blaze wavelength).

[0038] The applicant noted that with the increasing demands on the computing scale of optical chips, optical chips also face multiple pressures during the computing design process: 1) If the spacing between different waveguides is too small, optical crosstalk will occur. As the computational scale increases, the difficulty of waveguide winding increases, and the crosstalk problem becomes difficult to solve.

[0039] 2) Waveguides are usually made of silicon nitride, while optical chips often require metal interconnects to connect active devices. Once the scale increases, the problems of waveguides and metal traces become difficult to solve.

[0040] In response, this invention proposes an optical computing chip system implemented through a decoupling concept, in order to alleviate or solve the aforementioned technical problems.

[0041] Figures 1-10 The overall architecture and partial structural diagrams of the optical chip computing system proposed in this invention are shown respectively.

[0042] Example 1 Traditional optical chips face multiple wiring challenges as they scale up, including row waveguides, column waveguides, and metal circuits.

[0043] In response, this embodiment employs a decoupling design for the optical computing chip system, re-layouting the chip architecture both functionally and spatially. From another perspective, this optical computing chip system achieves a decoupled spatial arrangement of the chips based on functional decoupling.

[0044] by Figure 1 For example, an exemplary decoupling scheme provided by the present invention, namely a multi-chip integrated optical computing chip system, will be described.

[0045] The optical computing chip system includes: Glass substrate chip 05; At least one set of matrix operation chips are sequentially disposed on the glass substrate chip 05, and the set of matrix operation chips includes: a matrix input chip 02 with n rows and n columns of input, and a plurality of matrix multiplication chips 03 corresponding to the matrix input chip; A first beam splitter 01 is connected at both ends to a light source 04 and a matrix input chip, respectively, to split the light source into at least n optical signals and input the n optical signals to the matrix input chip 02. The matrix input chip 02 is used to modulate the optical signals to generate corresponding input signals. The matrix input chip 02 is also connected to the matrix multiplication chip 03 to input the input signals to the matrix multiplication chip 03. The matrix multiplication chip 03 is provided with a first decoupling functional area, which includes: Multiple spaced-apart traveling waveguides are provided, each traveling waveguide is provided with at least one second beam splitter, and a computational waveguide (also known as a branch waveguide, such as a traveling branch waveguide) is connected to the second beam splitter. A modulator (such as an optical modulator, an electrical modulator, etc.) is provided on the computational waveguide. The modulator is used to modulate the optical signal passing through the computational waveguide (therefore it can also be called a weighted modulator); for example, the optical signal can be an input signal input by the matrix input chip (for example, the optical signal can be an input signal, or the optical signal can be a new input signal obtained after the input signal is split by the second beam splitter).

[0046] A second decoupling functional area is provided on the glass substrate chip 05 corresponding to the matrix multiplication chip 03, and the second decoupling functional area includes: Multiple spaced column waveguides are connected to the computational waveguide via coupler assemblies (or inter-chip coupler assemblies); In this embodiment, the matrix multiplication chip 03 outputs a first incident light formed by the product of the input signal and the weight signal. This first incident light is transmitted to the column waveguide via the coupler assembly, where it is summed. Specifically, in this embodiment, the matrix input chip modulates the input signal, and the matrix multiplication chip 03 modulates the weights and outputs the product of the input signal (e.g., the input signal after being split by the second beam splitter) and the weight signal. This product is transmitted to the column waveguide via the coupler, where it is summed.

[0047] Specifically, a combiner can be set at the output end of the waveguide to sum multiple product results (which can be in the form of optical signals).

[0048] In some embodiments, such as Figure 2 As shown, the first beam splitter 01 can be connected to multiple sub-beam splitters 011, and the sub-beam splitters 011 are respectively connected to the matrix input chip.

[0049] In some embodiments, the weighting signal can be carried by either an electrical signal or an optical signal itself. When an optical signal is used as the weight, its interaction with the input signal (e.g., through optical interference or nonlinear effects) directly achieves the required multiplication operation.

[0050] In some embodiments, the modulator can be an optical modulator or an electrical modulator, and the type of modulator can be selected according to the form of the weighted signal.

[0051] For example, in some embodiments, the weighting signal can be understood as a weight value. When the modulator is an optical modulator, the optical modulator can change the properties of the passing optical signal according to the electrical signal applied to it (equivalent to the weight value).

[0052] In some embodiments, the row waveguide is a silicon waveguide, and the column waveguide is a silicon nitride waveguide.

[0053] It should be noted that in the process of optical computing using traditional integrated matrix multiplication chips, electrical signals are still required, necessitating the installation of metal interconnects. However, because the metal interconnects and traveling waveguides must avoid interference, this places extremely high demands on the chip's circuit design. Especially as chip size increases, the design difficulty of the metal interconnects significantly increases.

[0054] In this embodiment, a decoupling approach is adopted to arrange the row and column waveguides in layers, that is, on the matrix multiplication chip and the glass substrate chip. Preferably, the metal interconnect lines for connecting with the active devices in the matrix multiplication chip are arranged in the matrix multiplication chip.

[0055] In some embodiments, the active device includes a modulator.

[0056] Preferably, in some embodiments, the matrix multiplication chip in this embodiment can be a silicon-based optical chip (or, in other words, a silicon-based optoelectronic chip).

[0057] In some embodiments, the matrix input chip is a modulation chip. Specifically, the input signal of the matrix input chip can be transmitted to the matrix multiplication chip 03 via the glass substrate chip 05. That is, an optical transmission channel (such as a waveguide) can be provided in the glass substrate chip 05 to complete the optical signal connection between the matrix input chip and the matrix multiplication chip.

[0058] It should be noted that the glass substrate chip in this embodiment is only a preferred implementation and can be replaced with other types of chips, such as silicon-based optical chips. These chips can be collectively referred to as substrate waveguide chips.

[0059] The following is an exemplary description of a specific decoupling scheme provided by the present invention: This application proposes a substrate waveguide structure for large-scale optical matrix multipliers and a corresponding optical computing chip system. The overall optical computing chip system consists of a substrate waveguide chip, a matrix operation optoelectronic chip (which can be a matrix input optoelectronic chip, a matrix multiplication optoelectronic chip), and other PCB board 010 and other electrical chips (such as...). Figure 1 (As shown). An optical waveguide and metal vias are fabricated on the substrate waveguide chip. The substrate waveguide chip is connected to an external light source, and the beam is split (and modulated) and then coupled to multiple matrix operation optoelectronic chips on the top. Each matrix operation optoelectronic chip performs a summation operation on a block matrix.

[0060] The combination of a substrate waveguide chip and a matrix operation optoelectronic chip enables the realization of large-scale computing chips. Simultaneously, the substrate waveguide chip can serve as a medium for vertical electrical interconnects, facilitating the electrical interconnection between the top optoelectronic chip and the bottom PCB board.

[0061] In some embodiments, the substrate waveguide chip is fabricated using a nanoimprint lithography process, and the diameter of its non-repeating exposure area is in the range of approximately 4 to 12 inches. The minimum feature size is approximately 90 to 200 nm. For example, if the substrate waveguide is fabricated using silicon nitride with a refractive index of 2, the refractive index difference between it and the cladding silicon oxide is approximately 0.5, resulting in a typical waveguide bending radius of 50 to 100 μm, which is significantly lower than that of ion-exchange based waveguides.

[0062] like Figure 2 As shown, the multiplication matrix optical computing chip layout consists of an M*N row and P*Q column, formed by the substrate waveguide chip, the matrix input optoelectronic chip, and the matrix multiplication chip 03 (i.e., the matrix multiplication optoelectronic chip).

[0063] The present invention also provides an optical computing method implemented by an optical computing chip system according to any embodiment, comprising the following steps: The input light source is split into n optical signals using the first beam splitter. The n optical signals are used to input into the n rows and columns of the matrix input chip, where each row of optical signals corresponds to one column of input signals; Multiple input signals are input into the glass substrate chip and then enter the matrix multiplication chip via the glass substrate chip; The weight signal is input into the matrix multiplication chip, which ultimately outputs the product obtained by multiplying the input signal and the weight signal.

[0064] See Figure 1 As shown, the present invention provides a substrate waveguide chip. The substrate waveguide chip can be connected to an optoelectronic chip for optical signal transmission.

[0065] When traveling waveguides are arranged on a matrix multiplication chip, each computational unit in the matrix multiplication chip can include: The substrate layer 501 (also known as the substrate or substrate layer), the first cladding layer 502, and the second cladding layer 503 are arranged sequentially from bottom to top (in some embodiments, the first cladding layer and the second cladding layer can also be regarded as the lower cladding layer and the upper cladding layer). Via 504 (usually a metal via) is disposed through substrate layer 501, first cladding layer 502 and second cladding layer 503; for example, the via is a vertical metal via, used to provide an electrical connection path between the substrate waveguide chip and the upper and lower chips; The first waveguide 506 (which can be considered as a row waveguide, or as a row bus waveguide, or as a row branch waveguide). The second waveguide 508 (also known as a computational waveguide or a row branch waveguide) has its input end connected to the first waveguide 506, and a power beamsplitter (i.e., the second beamsplitter) is provided at the connection point. A coupler (such as a grating coupler 505) is provided at the output end of the second waveguide. A modulator is provided between the input and output ends of the second waveguide; preferably, the modulator is a weighted modulator based on a phase-change material. The modulator is used to adjust the power of the input optical signal.

[0066] Furthermore, in some embodiments, see Figure 4 The diagram shows side and top views of the modulator architecture in a computing unit. The modulator includes a phase-change modulation layer 509 disposed above the computing waveguide, and a heating layer 510 disposed above the phase-change modulation layer 509, with pads 511 on the heating layer 510. The pads 511 are used to transmit electrical signals to the heating layer 510, and the heat of the heating layer is controlled by the magnitude of the electrical signals.

[0067] In some embodiments, the first decoupling functional area further includes: a metal interconnect line for connection to a power source, the metal interconnect line being connected to the pad.

[0068] In some embodiments, the system further includes at least one first electrical chip, and at least one of the electrical chips is connected to the matrix input chip and / or the matrix multiplication chip.

[0069] In some embodiments, when the first electrical chip is connected to the matrix multiplication chip, the first electrical chip includes or is connected to a power source.

[0070] In some embodiments, the device further includes: at least one second electrical chip, and the at least one second electrical chip is connected to the glass substrate chip; the second electrical chip is used to receive the calculation result of matrix multiplication (such as the result of summation) through the glass substrate chip, and to process or store the calculation result.

[0071] In some embodiments, the substrate material may be silicon, glass, or aluminum nitride; the waveguide cladding material may be silicon oxide; and the waveguide layer material may be silicon, silicon nitride, silicon oxynitride, or niobium oxide, etc.

[0072] In some embodiments, a windowing process can be used to fabricate a phase change material modulation layer on a glass substrate waveguide chip or a matrix multiplication chip. Specifically, the windowing process can refer to an optical waveguide and its fabrication method disclosed in patent application PCT / CN2024 / 126989. The above process includes a multi-step photolithography overlay process, while the typical overlay deviation of the nanoimprint lithography process is 1µm. Therefore, the structural design needs to be compatible with the overlay deviation, increasing the width of the phase change modulation layer by a certain amount (more than twice the overlay deviation) to ensure that there is no significant degradation in device performance under the presence of overlay deviation. Similarly, the subsequent heating electrode and metal lead pad layer need to be further widened to overcome the overlay deviation.

[0073] Taking the setting of a phase change material layer on a matrix multiplication chip as an example, the specific scheme of this embodiment is explained: In terms of layer structure, the heating layer and the phase change material layer are as close as possible (for example, a titanium nitride heating layer is directly used to cover the phase change material layer) to ensure heating efficiency.

[0074] In the horizontal layout, the metal pad layer, the phase change material layer and the grating diffraction region do not overlap. The metal pad layer and its electrical connection path must be kept at a sufficient distance from the electrical connection paths of the photodetectors of this unit and adjacent units, or shielding must be provided to avoid crosstalk between signals.

[0075] It should be noted that traditional optical computing chips (such as matrix multiplication optoelectronic chips) require integrated computing. Integrated computing refers to the inclusion of functional units such as row beam splitting, column beam splitting, weighted modulation, and optical or electrical summation on the optical chip. Correspondingly, the optical computing chip performs calculations on the entire process of optical signal splitting and modulation.

[0076] To address this, the present invention provides a novel optical chip (e.g., a matrix multiplication optoelectronic chip) adapted for coupling with a substrate waveguide chip. For example, each computing unit on the matrix multiplication optoelectronic chip requires the addition of an optical coupler to couple the corresponding unit beam on the substrate waveguide chip into the waveguide, and then perform column-to-column optical or electrical summation operations after weighted modulation.

[0077] Alternatively, each computing unit on the matrix multiplication chip can be equipped with a surface-receiving photodetector. For example, the surface-receiving photodetector can be a large photosensitive surface detector, used to convert the optical signal into an electrical signal and perform subsequent electrical summation operations.

[0078] In this type of photodetector, the photoelectric conversion layer can be Ge, Si, or InGaAs, and the diameter of the photosensitive surface can be large (>80µm) or small (10~80µm). When the photosensitive surface has a small diameter, the transit time of the detector is shorter, resulting in a higher bandwidth. However, the corresponding substrate waveguide optical coupler needs to adopt a focusing grating, microlens, or other structure that matches the mode field.

[0079] In some embodiments, when the weight modulator is disposed on the glass substrate chip, the row waveguide can also be disposed on the matrix multiplication chip accordingly. That is, the modulation is performed by the glass substrate chip, and the final summation calculation is performed by the matrix multiplication chip. In this case, by externalizing the weight modulator, the matrix multiplication chip reduces the number of row and column beam splitters (and weight modulators, if PCM weight modulators are disposed on the substrate waveguide), the cell size can be reduced, the cell density can be increased, and the wiring can be simplified (the pins are closer to the first driving electrical chip (such as the first electrical chip 07) and the second driving electrical chip (the second electrical chip 08), reducing the complexity of rewiring).

[0080] Furthermore, in some embodiments, it may also include at least one third electrical chip 06, and the third electrical chip 06 may be directly disposed in the substrate waveguide chip (such as the glass substrate chip described above) via a bonding structure. For example, the third electrical chip may be used to realize electrical communication with the substrate waveguide chip.

[0081] Furthermore, in some embodiments, a high-diffraction-efficiency grating is used on the substrate waveguide chip to redirect the beam from the waveguide to a vertical or near-vertical direction for emission. Simultaneously, another high-diffraction-efficiency grating is disposed on the matrix multiplication chip to couple the vertical beam to the waveguide. The high-diffraction-efficiency grating on the substrate waveguide can be a two- or multi-stage stepped blazed grating. The grating period and duty cycle can be uniform or gradually varying in the x and y directions. The equiphase surface of the emitted beam can be close to a plane (collimation) or a sphere (convergence), and the emission direction can be upward (away from the substrate) or downward (through the substrate). The matrix multiplication chip can employ blazed gratings with similar structures, grating couplers with a metal reflective layer on the bottom surface, dielectric grating reflective layers, edge couplers with steering structures, etc.

[0082] In some embodiments, microlenses (such as those formed by nanoimprint lithography) can also be fabricated on the substrate waveguide using a nanoimprint lithography process. Figure 10 The wavefront of the beam emitted from the grating is shaped and matched with the optical coupler on the matrix multiplication chip.

[0083] In some embodiments, a mode-spot conversion waveguide edge coupler can also be fabricated on the substrate waveguide, and a reflective surface can be fabricated and a metal reflective layer deposited at the end of the coupler to achieve efficient optical coupling.

[0084] The grating arrangement in the above embodiments can reduce the loss of the light beam when switching between the substrate waveguide chip and the matrix multiplication chip.

[0085] In particular, it should be noted that this invention breaks with the conventional approach of integrating computing into optical computing chips. Instead, it breaks down the computing tasks of optical computing chips into multiple sub-tasks and sets up an optimized spatial arrangement scheme for the multiple small chips that execute the sub-tasks.

[0086] Below, to more clearly illustrate the implementation scheme of the optical computing chip provided by the present invention, an optional computing flow of the optical computing chip is described by way of example: (1) First, the input external light source 04 is split for the first time using the first beam splitter to obtain the first optical signal. Taking an n*n matrix input chip as an example, n parts of the first optical signal need to be split; (2) Input a first optical signal into a matrix input chip 02 and use the matrix input chip to modulate the first optical signal. One first optical signal is divided into a column of second optical signals. Among them, one matrix input chip 02 is connected to a multi-matrix multiplication chip 03. In this embodiment, modulation can refer to intensity modulation of the DC optical signal, so that the light intensity is distributed in a step-shaped manner over time, so as to realize the assignment of the input vector for matrix multiplication.

[0087] (3) The second optical signal is input into the substrate waveguide chip, which is used to divide the second optical signal into the corresponding third optical signal. The divided third optical signal (which is equivalent to the input signal of the computing unit) is input into the P column of the optoelectronic computing unit of each matrix multiplication optoelectronic chip 3. (4) The photoelectric computing unit performs weight modulation on the third optical signal (i.e., assigns weight vector values) and outputs the calculation results of the computing unit. (5) The calculation results can be acquired through an electronic chip.

[0088] Specifically, in some embodiments, the computation flow of the optical computing chip system provided by the present invention is as follows: See Figure 1 As shown, the external light source beam is coupled to the substrate waveguide chip via optical fiber 09. After passing through the optical beam splitter on the substrate waveguide chip, it is divided into M*N beams, which are then connected one by one to the M*N rows of the optical multiplication matrix.

[0089] Each row of light beams is coupled to the matrix input optoelectronic chip (or simply the input chip) via a grating coupler. After passing through a high-speed optical modulator on the input chip, it is coupled to the substrate waveguide chip via another grating coupler, thus assigning the matrix input vector. The modulated beam is then split into P*Q columns by a beam splitter. Each beam exits perpendicularly / approximately perpendicularly via a grating coupler and is coupled to the matrix multiplication optoelectronic chip at the top of the substrate waveguide chip. In the matrix multiplication optoelectronic chip, the beam in the i-th row and j-th column is intensity modulated with a transmittance of Wij, multiplied by the matrix element weighting factor, summed, and then converted into an electrical signal, or converted into an electrical signal and then summed.

[0090] The top of the substrate waveguide chip has Q matrix input optoelectronic chips and M*Q matrix multiplication optoelectronic chips. Each matrix input optoelectronic chip realizes N rows of beam transmission and reception. Among them, each matrix multiplication optoelectronic chip receives N rows and P columns of beams, and sums the P columns of beams to output a column vector containing P array elements.

[0091] Furthermore, in some embodiments, the substrate of the matrix input optoelectronic chip may be silicon, aluminum nitride, quartz, glass, or a III-V compound, and the waveguide may be silicon, lithium niobate, lithium tantalate, barium titanate, polymer, III-V semiconductor compound, or heterogeneous integration of two or more of the above materials.

[0092] Furthermore, in some embodiments, the substrate of the matrix multiplication chip can be silicon, a group III-V compound, and the waveguide can be silicon, silicon nitride, a group III-V compound, or a heterogeneous integration of two or more of the above materials. When the substrate and waveguide materials of the matrix input optoelectronic chip and the matrix multiplication chip are the same, they can be located on the same chip or on different chips.

[0093] Furthermore, in some embodiments, the substrate waveguide material is glass, and the waveguide material is silicon nitride; the substrate of the matrix input optoelectronic chip is quartz or aluminum nitride, and the waveguide is lithium niobate; the substrate of the matrix multiplication chip is silicon, and the waveguide is silicon. Based on a lithium niobate chip with a lossless, low-dielectric-constant substrate, high-speed optical modulation can be achieved to reach high-speed input, thereby improving the computational bandwidth of the optoelectronic chip.

[0094] Furthermore, in some embodiments, the optical coupling between the substrate waveguide chip and the matrix input optoelectronic chip or matrix multiplication optoelectronic chip can be achieved through edge coupling, evanescent wave coupling, or vertical grating coupling. Since nanoimprint lithography can fabricate 3D structures, it is possible to fabricate blazed grating couplers with high diffraction efficiency in a single step without overlay deviation, thus achieving efficient optical coupling.

[0095] Furthermore, in some embodiments, windows can be opened on the substrate waveguide chip to fabricate a phase change material light intensity modulator. The structure is as follows: Figure 3 As shown, a heating layer (such as a heating electrode) and pads are disposed on top of the phase change material. The pads are electrically connected to the top matrix multiplication chip, so that the weight control electrical signal of the matrix multiplication chip is applied to the heating layer. Through reasonable structural design, the phase change material, heating layer and pad structure can have high overlay tolerance, matching the typical overlay deviation of 1µm in nanoimprint lithography.

[0096] In some embodiments, the operating wavelength of the overall computing chip (or computing chip) can be either near-infrared short wave (780~1100nm) or near-infrared long wave (1100~2526nm). When the operating wavelength is in the 780~1100nm range, the substrate waveguide material can be silicon nitride, the matrix input optoelectronic chip waveguide can be lithium niobate, the matrix multiplication optoelectronic chip waveguide can be silicon nitride, and the weight modulator and detector can be silicon (based on the FK effect) or III-V group materials.

[0097] In some embodiments, the input light source of the overall computing chip is an optical frequency comb (based on the Kerr effect of silicon nitride waveguide microrings, III-V quantum dot lasers, and high-speed electro-optic modulation of lithium niobate), and the beam splitter of the substrate waveguide realizes the wavelength separation of each comb tooth in the frequency comb. The matrix input chip can be fabricated based on III-V compound waveguides and integrates on-chip SOA and high-speed optical modulator.

[0098] Waveguide substrates can be fabricated on glass substrates using full-mask lithography, resulting in pattern sizes much larger than the exposure size of stepper lithography machines, approaching wafer dimensions. Furthermore, the glass substrates can employ through-hole glass via (TGV) technology as an electrical interposer, providing a high-bandwidth connection bridge between optoelectronic chips and underlying circuitry.

[0099] In some embodiments, the glass substrate waveguide can be fabricated using photolithography and ion exchange processes, with a small difference in refractive index between the core and cladding layers, and a typical bending radius of 10–30 mm. In this case, the optical connection between the substrate waveguide and the optoelectronic chip requires edge coupling or evanescent wave coupling. Edge coupling requires well-etched end faces. Evanescent wave coupling requires strict control of the spacing between the optoelectronic chip and the glass substrate, and the coupling tolerance is smaller compared to grating-based vertical coupling. Vertical coupling typically requires a mirror-based structure or a grating coupler based on high-precision photolithography.

[0100] It should be noted that in this invention, the input and multiplication functions can be integrated onto a single optical chip, or two separate chips can be used to implement the input and multiplication functions respectively.

[0101] When two relatively independent chips are used to implement input and multiplication functions, the main device for the input section is a high-speed optical intensity modulator, while the main devices for the multiplication function include a small-sized intensity modulator and a high-speed photodetector. The performance of various devices differs significantly across different material platforms. This invention employs a decoupled design, using multiple chips with different material systems to optimize the performance of different materials.

[0102] For example, traveling-wave Mach-Zehnder modulators based on lithium niobate waveguides can achieve modulation rates exceeding 140 Gbps with bit power consumption below 20 fJ, but it is difficult to realize compact intensity modulators and detectors in this material system. On the other hand, silicon modulators with similar structures typically have speeds below 70 Gbps and bit power consumption on the order of pJ, but small-sized intensity modulators and photodetectors are easily realized on the silicon waveguide platform.

[0103] Furthermore, the inventors noted that the different coefficients of thermal expansion of various chip substrate materials can lead to thermal stress. To address this, the substrate waveguide chip can be fabricated using an appropriate glass substrate material, ensuring its coefficient of thermal expansion matches that of other chips. The dimensions of the bonding surfaces between chips can also be appropriately adjusted to reduce structural stress.

[0104] It is understood that the remaining architecture or device configuration of the matrix input chip and matrix multiplication chip used in this embodiment can adopt the conventional settings in existing optoelectronic chips or optical chips.

[0105] For example, in some embodiments, taking an n*n matrix input chip as an example, it can refer to the cross arrangement of row waveguides and column waveguides in existing optical chips.

[0106] Specifically, the present invention differs from traditional optical computing chips in at least the following aspects in terms of structure and fabrication: 1. The computing system proposed in this scheme can realize large-scale matrix operations. The size of the non-repeating nanoimprint pattern is limited only by the size of the substrate, which is typically fabricated on a silicon substrate using electron beam lithography (EBL). Therefore, the theoretical upper limit of the exposure area diameter is 12 inches.

[0107] 2. Compared to glass substrate waveguides based on ion exchange technology, nanoimprint lithography offers higher patterning precision and greater freedom in waveguide material design, resulting in higher integration density and supporting various inter-chip optical coupling schemes such as edge coupling, evanescent wave coupling, and vertical grating coupling. Since nanoimprint lithography can fabricate 3D structures in a single step, it can achieve grating structures with high diffraction efficiency.

[0108] It is worth noting that the decoupling design provided by this invention can significantly simplify the structural complexity of the glass substrate chip. This simplified structure also makes it easier to mass-produce the glass substrate chip using nanoimprint lithography. In other words, the simplified structure of the glass substrate chip also reduces the difficulty of implementing the nanoimprint lithography process.

[0109] 3. In this scheme, a matrix of row and column beam splitters is set on the substrate waveguide, which can share the beam splitting task of the matrix multiplication chip and reduce the design difficulty of the matrix multiplication chip.

[0110] 4. In this solution, a non-volatile weighted modulation unit based on phase change materials can also be integrated on the substrate waveguide, thereby improving the overall energy efficiency of the chip. The matrix multiplication chip can be implemented using standard CMOS (Complementary Metal-Oxide-Semiconductor) technology, which has relatively low process difficulty.

[0111] Example 2 It should be noted that, because this invention solves the difficulty of metal wiring—namely, by decoupling to separate row and column waveguides on a plane—more precise beam-splitting paths for row or column waveguides can be used to improve the accuracy of optical signal splitting during the beam-splitting process. Figure 6 As shown. Among them, Figure 6 The diagram shows the architecture of row waveguides and column waveguides in the planar direction.

[0112] The following example uses the first chip and the second chip as illustrations: The first and second chips are stacked vertically. The waveguides and metal interconnects of the first chip, and the waveguides on the second chip, are arranged in a staggered pattern in the horizontal direction. (See [reference needed]). Figure 6 As shown.

[0113] The first chip can be a silicon-based optoelectronic chip, which integrates a row waveguide, a second beam splitter 12, a modulator 13, and a metal interconnect line 14 connected to the modulator 13 (specifically, it may include a modulator ground bus). The second chip is a light-transmitting substrate waveguide chip, which integrates a column waveguide and a combiner 22. A coupler 3 (also called an inter-chip optical coupler) is provided between the first chip 1 and the second chip 2. The inter-chip optical coupler is used to realize the vertical interconnection of optical signals between the first chip 1 and the second chip 2, coupling the modulated optical signal in the row waveguide to the column waveguide. Thus, the relevant devices of a computing unit 9 are distributed on different chips.

[0114] In some embodiments, one end of the modulator 13 is connected to the modulator ground bus via a ground line 15.

[0115] The second beam splitter 12 can be a multi-path equal-splitting beam splitter. The row waveguide can include: row bus waveguide and row branch waveguide.

[0116] For example, the row bus waveguide 111 and the row branch waveguide are distributed on the first chip 1 using a tree-like beam splitting network, while the column bus waveguide 211 and the column branch waveguide 212 are distributed on the second chip 2 using a parallel beam combining structure.

[0117] Specifically, the row branch waveguides include: N first-level row branch waveguides 1121 split from the row bus waveguide 111 by the second beamsplitter 12; N second-level row branch waveguides 1122 split from each first-level row branch waveguide 1121 by the second beamsplitter 12; and so on. The second beamsplitter 12 is used to evenly divide an upstream row waveguide to obtain N downstream row waveguides. The second beamsplitter 12 is used to perform X beam splits on the row bus waveguide 111 to obtain N... X A row of X-level branch waveguides is used to evenly distribute the input optical signal in the row bus waveguide 111 to N. X In the X-level branch waveguides described in the article, the number of X-level branch waveguides is equal to the number of column bus waveguides 211, and the X-level branch waveguides and column bus waveguides 211 are arranged in a one-to-one correspondence. Here, the upstream to downstream direction refers to the direction of light transmission.

[0118] In some embodiments, the optical path length from the input end to all output ends of the traveling waveguide is equal. Further, the traveling waveguide is bent on the first chip such that the optical path length of all beam-splitting paths of the traveling waveguide is equal.

[0119] Taking the second beamsplitter 12 as a 1×2 equal-splitting beamsplitter, and performing at least two beam splits on the row bus waveguide 111 as an example. Preferably, all row bus waveguides 111 are bent vertically downwards. One row bus waveguide 111 is split in two by the second beamsplitter 12 to obtain two row primary branch waveguides 1121. The row primary branch waveguides 1121 are symmetrically bent upwards in a U-shape. One row primary branch waveguide 1121 is split in two by the second beamsplitter 12 to obtain two row secondary branch waveguides 1122. The row secondary branch waveguides 1122 are then symmetrically bent downwards in a U-shape. All bends in the row waveguides are arc-shaped for ease of fabrication.

[0120] In this embodiment, the traveling waveguide is arranged on the first chip 1 using a tree-like beam splitting network, which has the following advantages: (1) Better optical power uniformity: The beam is split step by step using a multi-path equal-splitter, and the structure of each stage is symmetrical and consistent, resulting in high output light intensity consistency, reducing channel deviation and improving calculation accuracy. (2) Support for equal optical path design: By compensating for path differences through waveguide bending, the optical path of all beam splitting paths can be made equal, so that the optical signal delay is equal, which is beneficial to improving the optical calculation speed.

[0121] In some embodiments, the row bus waveguide 111 and the row branch waveguide are distributed on the first chip 1 using a parallel beam splitting structure or a tree-like beam splitting network, while the column bus waveguide 211 and the column branch waveguide 212 are distributed on the second chip 2 using a tree-like beam combining network.

[0122] In some embodiments, the column branch waveguide 212 includes: N column primary branch waveguides merged into the column bus waveguide 211 by a multiplexer 22; N column secondary branch waveguides merged into each column primary branch waveguide by a multiplexer 22; and so on, with the multiplexer 22 merging the N upstream column waveguides to obtain a downstream column waveguide. X X-order branch waveguides are combined X times to obtain a single-order bus waveguide 211, and N... X The optical signals in the X-level branch waveguides are merged into a single column bus waveguide 211. The number of X-level branch waveguides is equal to the number of row bus waveguides 111, and the X-level branch waveguides and row bus waveguides 111 are configured in a one-to-one correspondence.

[0123] In some embodiments, the optical path lengths from all inputs to the outputs of the waveguide are equal. Furthermore, the waveguide is bent on the second chip 2 such that the optical path lengths of all beam combining paths of the waveguide are equal.

[0124] In this embodiment, the waveguides are arranged on the second chip 2 using a tree-like optical combining network. Therefore, this embodiment has the following advantages: the symmetrical architecture can improve system consistency. Specifically, the tree-like optical combining network on the second chip 2 forms a symmetrical topology with the tree-like optical splitting network of the first chip 1, so that the path characteristics of the optical signal distribution in the row direction and the convergence in the column direction are consistent and the delay is equal, which is beneficial to improving the calculation speed.

[0125] It is important to understand that this embodiment decouples the original architecture of the row waveguides and column waveguides, allowing them to be distributed across different chips. For example, the row waveguides and column waveguides can be located on a first chip and a second chip, respectively.

[0126] Among them, the first chip and the second chip can be respectively referred to as the matrix multiplication chip and the glass substrate chip.

[0127] Alternatively, in some other embodiments, the first chip and the second chip may correspond to the glass substrate chip and the matrix multiplication chip, respectively. That is to say, the vertical arrangement of the row waveguide and the column waveguide can be reversed.

[0128] Example 3: Specifically, the present invention also provides a low-loss optical transmission scheme suitable for inter-chip communication, as described below. Figures 7-8 An illustrative example will be provided: An inter-chip coupling component is disposed at at least one end of at least one optical channel, the inter-chip coupling component comprising: A front coupler 1002 is disposed at the optical output end of one of the chips; The back coupler 1003 is disposed at the optical receiver end of another chip that is disposed opposite to it; that is, the front coupler and the back coupler will be used for light emission and reception, respectively.

[0129] It should be noted that in some other embodiments, the front coupler and the back coupler can also be used as the first coupler and the second coupler.

[0130] The preferred type of coupler is a grating coupler.

[0131] For example, taking a glass substrate chip and a modulation chip as examples, at least one front coupler can be provided on the glass substrate chip, while a corresponding back coupler is provided on the modulation chip to realize signal transmission.

[0132] For example, taking glass chips and computing chips (such as matrix multiplication chips) as examples, a front coupler can be set on the glass chip and a back coupler can be set on the computing chip, so that the input signal (or modulation signal) generated by the modulation chip can be transmitted to the computing chip.

[0133] Specifically, the two stacked chips can be staggered on the coupler to create a certain distance between adjacent front and back couplers in the horizontal direction (i.e., the direction where the chip surface is located), thereby achieving a difference in the deflection angle of the front and back couplers. Thus, the oppositely positioned front and back couplers effectively form a coupler assembly. Simultaneously, the light-transmitting substrate layer can further reduce potential light loss during transmission.

[0134] The deflection angle refers to the angle between the original direction of light propagation and the direction of light propagation after deflection.

[0135] See Figure 4 As shown, in this embodiment, the front coupler is used as the output end of the optical signal, that is, it is configured to carry the deflection function of light; the back coupler is used as the transmission end of the optical signal, that is, it is configured to have the functions of receiving, deflecting and transmitting (specifically, it needs to capture and collect the optical signal after it has been deflected by a chip, deflect the captured signal, and then continue to transmit the deflected signal to the waveguide in the next chip).

[0136] Preferably, this embodiment focuses on using a small deflection angle design (less than 90°) for the front coupler, which serves as the optical signal output end. This significantly reduces the design difficulty of the front coupler's deflection. It should be noted that because the deflection angle is small, the front coupler faces relatively less pressure in its deflection function, making it easier to complete the deflection task with relatively low loss. In other words, the deflection difficulty of the front coupler is lower, thus resulting in only a small amount of signal loss. Simultaneously, assigning the task of performing large-angle deflection to the back coupler allows for light transmission between different chips (i.e., inter-chip transmission) with relatively limited structural reinforcement.

[0137] In other words, this combination of large and small deflection angles reduces the design burden on the front and back couplers. Specifically, the front coupler uses a small deflection angle design to ensure that the light maintains high transmission efficiency during deflection (i.e., reducing potential losses during deflection); at the same time, a localized reinforcement structure (such as a diffraction direction reinforcement structure) is designed for the receiving function of the back coupler to enhance the light capture and redirection efficiency, further reducing light loss.

[0138] This local reinforcement design, achieved through the coordinated use of deflection angle and reinforcement structure between the front and back couplers, allows for local reinforcement of the coupler components at a lower cost (i.e., focusing the functionality on the back coupler). This significantly reduces the overall configuration difficulty and cost of couplers in multi-chip systems.

[0139] In addition, the applicant noted that during inter-chip transmission, since the back coupler has integrated receiving, deflection and transmission functions, only relatively simple structural reinforcement design is needed on the above structure to achieve more efficient light capture and transmission, thus achieving twice the result with half the effort.

[0140] Specifically, taking the multi-chip system provided in this embodiment as an example, considering one X1*X2 optical chip, to achieve optical communication connections with the upper and lower optical chips, at least X1 front couplers and X1 back couplers are required. Therefore, for large-scale optical chips, such as 128*128 or even 1024*1024 chips, the design and fabrication difficulties of the couplers pose extremely high challenges to the implementation of multi-chip systems.

[0141] The coupler component based on local reinforcement design provided in this application can simplify half of the coupler (i.e., the front coupler) into a basic structure, while only local reinforcement is performed on the back coupler, thereby greatly reducing the difficulty of coupler design and configuration.

[0142] Furthermore, in some embodiments, the first angle is greater than 70°.

[0143] Furthermore, in some embodiments, the first angle is greater than 75°.

[0144] Furthermore, in some embodiments, the first angle is greater than 80°.

[0145] In some embodiments, the substrate layer selected as the carrier platform chip in this embodiment can be a light-transmitting substrate layer.

[0146] Preferably, the light-transmitting substrate layer in this embodiment is a glass substrate layer (correspondingly, the optical chip can be a glass substrate chip). By combining the glass substrate layer with the optical waveguide, a computing matrix scale of ultra-large area can be achieved (such as a computing scale of 5000×5000 on a 12-inch wafer; or even beyond a 12-inch wafer, a larger matrix scale can be achieved).

[0147] In this embodiment, all optical chips can be glass substrate chips, thereby realizing a large-scale multi-chip overlapping system. However, such a large-scale multi-chip overlapping system will significantly increase the difficulty of inter-chip transmission.

[0148] This embodiment provides a scheme for differentiating the deflection angle at the output and input ports of optical signals. This differentiated design is beneficial to improving the transmission efficiency of optical signals between chips, and can also reduce the design difficulty of couplers to a certain extent.

[0149] Preferably, a transition layer (not shown in the figure) is provided between two adjacent glass chips, that is, a transition layer can be provided between the waveguide layer of one optical chip and the light-transmitting substrate layer of another waveguide.

[0150] Preferably, the transition layer material can be silicon oxynitride (Si-ON), and the specific silicon-nitrogen-oxygen ratio is usually around 4:2:4. The specific ratio can be adjusted according to process requirements. The thickness of the transition layer can usually be less than 100 nm, such as preferably 50 nm.

[0151] In this embodiment, a transition layer is used as a connection between adjacent chips, which is beneficial to achieve stable connection between large-scale optical chips, such as reducing defects and faults that may exist between adjacent chips due to stress problems (such as reducing cracks).

[0152] Specifically, the coupler assembly implements a local reinforcement design based on the difference in deflection angle. For example, the front coupler preferably adopts a conventional coupler, while the back coupler is provided with a local reinforcement structure, such as a diffraction direction reinforcement structure.

[0153] In some embodiments, such as Figures 8-10As shown, the back coupler is provided with a diffraction direction enhancement structure, and the type of the diffraction direction enhancement structure includes: a blazed grating, a metal reflective layer and / or a microlens.

[0154] Preferably, in some embodiments, the back coupler includes: A substrate layer (which may be a light-transmitting substrate layer 10011) is provided with a lower cladding layer 100122. A waveguide core layer 1003a is sequentially provided on the lower cladding layer 100122. The waveguide core layer 1003a includes an input / output terminal 10031, a beam expanding region 10032, and a diffraction region 10033 sequentially provided. An upper cladding layer 100121 is further provided on the waveguide core layer 1003a. The diffraction region and the beam expanding region are used to receive the second incident light and deflect the second incident light by a second angle to convert it into a third incident light. The third incident light is then transmitted to the next stage waveguide through the input / output terminal 10031.

[0155] In some embodiments, the waveguide core layer 1003a may be made of silicon or silicon nitride, the lower cladding may be made of silicon dioxide, and the upper cladding may be made of silicon dioxide, polymer / polyimide, or silicon nitride.

[0156] Preferably, the diffraction region can employ a blazed grating structure. In some embodiments, the type of the diffraction region includes at least one of the following: linear, fan-shaped, or a combination of dot-line and dot-line shapes.

[0157] For example, in some embodiments, the type of the diffraction region includes at least one of the following: second-order step, third-order step. Figure 10 A side view of a two-stage stepped blazed grating structure is shown.

[0158] For example, in some embodiments, the back coupler further includes a metal reflective layer 10035 disposed on the outer surface of the upper cladding, such as... Figure 10 As shown.

[0159] For example, in some embodiments, the diffraction direction enhancement structure is a microlens 10034 disposed on the outer surface of the light-transmitting substrate, such as... Figure 10 As shown.

[0160] In some embodiments, the type of the front coupler includes: a single-level diffraction grating coupler, a bidirectional grating coupler, and / or a symmetrical grating coupler.

[0161] In other words, in this embodiment, the front coupler preferably adopts a more conventional grating coupler to achieve local simplification of the coupler.

[0162] For example, a single-order diffraction grating coupler is a basic grating structure in optical chips. Its design goal is usually to concentrate light energy into a single diffraction order (such as the -1st order of vertical incident / outgoing light) to achieve efficient coupling between the chip and the optical fiber. Therefore, it can be called a standard grating coupler. If its structure allows light energy to radiate symmetrically in both directions of the substrate, it is called a bidirectional grating coupler.

[0163] For example, a symmetrical grating coupler is a special grating structure designed to produce symmetrical or approximately symmetrical diffraction of incident light energy in directions perpendicular to the grating plane (i.e., upward and downward).

[0164] In other embodiments, the front coupler can be a directional grating, meaning that within a 360° range, the grating can receive light signals from a specific direction and output them from that specific direction. Light from directions other than the two specific directions is attenuated to a greater extent possible through designs such as asymmetric designs or reflectors (mirrors).

[0165] As mentioned earlier, this invention addresses the functional differences between the front and back couplers by incorporating small and large deflection angles. Furthermore, it adapts the front and back couplers structurally and functionally to accommodate these different deflection angles. This type of coupler assembly with differentiated deflection angles and structural functions not only improves the optical signal transmission efficiency between chips (i.e., reduces energy consumption), but also reduces the overall design and fabrication complexity of the coupler through localized functional enhancements, making the large-scale chip system easier to implement.

[0166] Furthermore, based on this locally reinforced coupler assembly, the present invention can provide a multi-chip system that may include at least two optical chips stacked vertically.

[0167] In other words, based on this inter-chip communication system design, the present invention can not only achieve large-scale expansion in the horizontal direction, but also stack chips in the vertical direction.

[0168] For example, the computing chips can be multiple stacked in the vertical direction. This stacking scheme is preferably implemented with the computing chips as glass substrate chips, and the computing chips can be connected to each other using the aforementioned low-loss coupler components.

[0169] In some embodiments, the light-transmitting substrate waveguide chip is any one of a glass substrate waveguide chip, a sapphire substrate waveguide chip, an aluminum nitride substrate waveguide chip, and a polymer substrate waveguide chip.

[0170] In some embodiments, the light-transmitting substrate waveguide chip is a glass substrate waveguide chip, and the glass in the glass substrate is ordinary or microcrystalline glass based on a silicate system.

[0171] For example, in some embodiments, ordinary glass based on silicate systems is typically represented by sodium-calcium silicate glass (Na2O-CaO-SiO2 system). Microcrystalline glass based on silicate systems typically includes lithium aluminum silicate system (Li2O-Al2O3-SiO2, LAS) and magnesium aluminum silicate system (MgO-Al2O3-SiO2, MAS).

[0172] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0173] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0174] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A chip system, characterized in that, include: PCB board (010); Substrate waveguide chip disposed on the PCB board; At least one set of matrix operation chips are sequentially disposed on the substrate waveguide chip, and the set of matrix operation chips includes: a matrix input chip (02) with n rows and n columns of input, and a plurality of matrix multiplication chips (03) corresponding to the matrix input chip. The first beam splitter (01) is connected at both ends to a light source (04) and a matrix input chip (02) to split the light source into at least n light signals and input the n light signals to the matrix input chip (02). The matrix input chip (02) is used to modulate the light signals to generate corresponding input signals. The matrix input chip (02) is also connected to the matrix multiplication chip (03) to input the input signals to the matrix multiplication chip (03). The matrix multiplication chip (03) is provided with a first decoupling functional area, which includes: Multiple spaced-apart traveling waveguides are provided, each traveling waveguide is provided with at least one second beam splitter, and each second beam splitter is connected to a traveling branch waveguide, which is provided with a modulator. A second decoupling functional area is provided on the substrate waveguide chip corresponding to the matrix multiplication chip (03), and the second decoupling functional area includes: Multiple spaced column waveguides are connected to the row branch waveguides via coupler assemblies; The matrix multiplication chip (03) is used to output the first incident light formed by the product of the input signal and the weight signal. The first incident light is transmitted to the column waveguide via the coupler assembly, and the total summation calculation is performed in the column waveguide. The calculation result is output through the column waveguide.

2. The chip system according to claim 1, characterized in that, The matrix input chip and the matrix multiplication chip have the same substrate and waveguide material; And / or, the substrate waveguide chip is provided with an optical transmission channel to complete the optical signal connection between the matrix input chip and the matrix multiplication chip.

3. The chip system according to claim 1 or 2, characterized in that, The matrix input chip and the matrix multiplication chip are the same chip.

4. The chip system according to claim 1 or 2, characterized in that, The matrix input chip and the matrix multiplication chip are different chips.

5. The chip system according to claim 1, characterized in that, The modulator includes: a phase-change modulation layer disposed above the row branch waveguide, and a heating layer disposed above the phase-change modulation layer, wherein the heating layer is provided with pads; wherein the pads are used to transmit electrical signals to the heating layer, and the heat of the heating layer is controlled by the magnitude of the electrical signals; And / or, further comprising: at least one first electrical chip, wherein at least one first electrical chip is connected to the matrix input chip and / or the matrix multiplication chip.

6. The chip system according to claim 5, characterized in that, The first decoupling functional area further includes: a metal interconnect line for connection to a power source, the metal interconnect line being connected to the pad.

7. The chip system according to claim 5, characterized in that, When the first electrical chip is connected to the matrix multiplication chip, the first electrical chip includes or is connected to a power source.

8. The chip system according to claim 1, characterized in that, The substrate waveguide chip is a light-transmitting substrate waveguide chip.

9. The chip system according to claim 8, characterized in that, The transparent substrate waveguide chip can be any one of glass substrate waveguide chip, sapphire substrate waveguide chip, aluminum nitride substrate waveguide chip, or polymer substrate waveguide chip.

10. A method for optical computing implemented using a chip system according to any one of claims 1-9, characterized in that, Including the following steps: The input light source is split into n optical signals using the first beam splitter. The n optical signals are used to input into the n rows and columns of the matrix input chip, where each row of optical signals corresponds to one column of input signals; Multiple input signals are input into the substrate waveguide chip and then enter the matrix multiplication chip via the substrate waveguide chip. The weight signal is input into the matrix multiplication chip, which ultimately outputs the product obtained by multiplying the input signal and the weight signal.

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