High-resolution sequence pulse synthesizer

Abstract

The invention relates to the technical field of digital signal generation and high-frequency electronics, and particularly discloses a high-resolution sequence pulse synthesizer, which is characterized in that an upper computer configures and issues sequence pulse parameters, and a data reading control module generates ground state control data streams according to the parameters; the programmable edge fine adjustment module generates multiple paths of control data streams by adopting a multi-channel collaborative fine adjustment algorithm according to the edge offset step number; the data split-phase sending module converts the control data stream into a plurality of paths of phase-staggered high-speed serial signals by using a plurality of reference clock channels of which the phases are offset in sequence; finally, a high-speed sequence pulse signal with ultrahigh time resolution is synthesized through an OR gate. According to the invention, the resolution limit of a single clock domain is broken through, the independent and accurate programming of any edge in the pulse sequence is realized, the sequence pulse with large data volume, high output frequency and extremely high resolution can be generated, and the method is suitable for high-performance scenes such as communication and semiconductor testing.

Description

Technical Field

[0001] This invention relates to digital signal generation and high-frequency electronics technology, and particularly to a high-resolution sequence pulse synthesis device. Background Technology

[0002] Pulse signal generators are core devices in the field of electronic test and measurement, and their sequence pulse generation function is crucial in testing in fields such as communications, semiconductors, and particle physics. A sequence pulse is a digital signal sequence composed of a series of pulses following specific encoding rules. With the rapid development of semiconductor technology and integrated circuit scale, electronic testing scenarios have placed higher demands on the performance of sequence pulses, including larger data volumes, higher output frequencies, and time resolutions on the order of nanoseconds or even picoseconds.

[0003] Currently, Direct Digital Synthesis (DDS) is the mainstream approach for digitally generating sequence pulses, primarily divided into Direct Digital Waveform Synthesis (DDWS) and Direct Digital Frequency Synthesis (DDFS). DDWS pre-calculates and stores all sampling points of the waveform in memory, reading them sequentially during output; while DDFS generates the signal using a phase accumulator and a waveform lookup table. However, both methods exhibit inherent drawbacks when addressing the demands of high-performance sequence pulse generation:

[0004] First, in terms of storage depth and waveform flexibility, both DDWS and DDFS require storing massive amounts of sampling data when generating non-periodic, large-scale, or complex encoded pulse sequences. This greatly increases the storage burden and implementation difficulty of the system, lacking efficiency and economy.

[0005] Secondly, regarding real-time performance and output bandwidth, since each sampling point needs to be read from memory, the maximum output frequency of the sequence pulses is directly limited by the memory read speed. Achieving extremely high read frequencies presents significant challenges in terms of both technology and cost, becoming a bottleneck for improving output bandwidth.

[0006] Furthermore, regarding output control and resolution, DDWS requires either changing the system clock frequency or updating the entire waveform memory to alter the output frequency. Both of these operations result in output interruptions, lacking the flexibility for dynamic adjustment and offering limited fine-grained control over high resolution. While DDFS can achieve continuous changes in output frequency by altering the frequency control word, it adjusts the frequency of the entire waveform, making it difficult to rapidly and independently modulate the width of a single pulse or the position of a specific edge with precision.

[0007] Finally, regarding time resolution, traditional digital methods are limited by a single clock domain, and their minimum time step cannot exceed one reference clock cycle, making it difficult to overcome hardware limitations and achieve picosecond-level resolution. Although there are techniques that use analog delay lines for fine-tuning, they generally suffer from drawbacks such as low accuracy, large temperature drift, and difficulty in digital programming and control. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a sequence pulse generation scheme that can simultaneously meet the requirements of large data volume, high output frequency, and high time resolution, and can program the pulse edges in real time, independently and accurately.

[0009] The technical solution adopted by this invention to solve the above-mentioned technical problems is a high-resolution sequence pulse synthesis device, comprising a host computer, a pulse data memory, a frequency configuration register, a fine-tuning enable register, an edge offset memory, a data read control module, a programmable edge fine-tuning module, a data phase-splitting transmission module, and an OR gate:

[0010] It includes a host computer, pulse data memory, frequency configuration register, fine-tuning enable register, edge offset memory, data read control module, programmable edge fine-tuning module, data phase-splitting transmission module, and OR gates;

[0011] The host computer is used to configure and send out sequence pulse parameters, which include: sequence pulse data. Reference pulse frequency Edge fine-tuning enable signal and edge offset step set ;

[0012] The pulse data memory, frequency configuration register, fine-tuning enable register, and edge offset memory are used to receive and store the sequence pulse data sent by the host computer. Reference pulse frequency Edge fine-tuning enable signal and edge offset step set ;

[0013] The data read control module is used to read the sequence pulse data from the pulse data memory. And read the reference pulse frequency from the frequency configuration register. According to the reference pulse frequency Calculate the number of sampling points for each user pulse. And based on the number of sampling points Convert the sequence pulses into a ground-state control data stream in real time. The ground state control data stream With the number of sampling points Output to the programmable edge trimming module;

[0014] The programmable edge fine-tuning module is used to adjust the edge fine-tuning enable signal output from the fine-tuning enable register. The state determines whether to enable the edge trimming function; when the edge trimming function is enabled, the ground state control data stream is... For each edge detected, the corresponding edge offset step number is read from the edge offset memory, and a multi-channel collaborative fine-tuning algorithm is applied to generate... The control data stream is sent to the data phase-splitting transmission module;

[0015] Among them, the multi-channel collaborative fine-tuning algorithm uses pulse width units as the processing unit, and each pulse width unit corresponds to the ground state control data stream. The duration is A continuous data segment at each sampling point; based on the edge offset steps configured for the start and end edges of the current pulse width unit, a set of collaborative parameters for the coordinated control of multiple data channels is calculated; based on the collaborative parameters, the data stream is controlled in the ground state. Based on this, generate The path control data stream includes a main channel control data stream used to implement coarse adjustment of the reference clock cycle as an integer multiple, and Paths are used to achieve system time resolution The auxiliary channel controls the data flow with fine-tuning at different levels;

[0016] Data phase transmission module, including Several parallel data transmission channels; each channel uses a reference clock with the same frequency but a phase delay of a specific ratio, to transmit the received data. The corresponding path in the path control data stream is converted into a set. A high-speed serial signal with sequentially shifted phase;

[0017] OR gate, used to convert the said The high-speed serial signals with sequentially shifted phases are logically ORed and combined to output a high-resolution sequential pulse signal with a time resolution equal to the reference clock period. .

[0018] This invention provides a novel high-resolution sequence pulse synthesis device. Sequence pulse parameters are configured and sent by a host computer, and received and stored by a pulse data memory, a frequency configuration register, an edge fine-tuning enable register, and an edge offset memory. The data reading control module reads the reference pulse frequency from the frequency configuration register. Calculate the number of sampling points for each pulse. Then, sequential pulse data is read from the pulse data memory. And convert it into a ground-state control data stream in real time. If edge fine-tuning enables If valid, the programmable edge fine-tuning module will detect it in real time. The edge transitions in the memory are based on the set of corresponding edge offset steps read from memory. A multi-channel collaborative fine-tuning algorithm is applied to generate... Road control data stream The data phase-splitting transmission module includes... Each reference clock at the same frequency But different phase shifts The data transmission channel will receive... Road control data stream , respectively converted to High-speed serial signals with phase interleaving These signals are finally combined by an OR gate to generate a reference pulse frequency. Time resolution High-speed, high-resolution sequence pulse signals with finely tuned edges This invention utilizes a multi-channel collaborative fine-tuning algorithm and the phase-interleaved characteristics of the data transmission channel to achieve high-resolution sequence pulse synthesis that is not limited by memory bandwidth, and features large data volume, high output frequency, and programmable arbitrary edges.

[0019] This invention is based on multi-channel multi-phase output and digital edge fine-tuning technology. By generating ground-state control data stream in real time, programmable edge fine-tuning algorithm, multi-channel multi-phase data transmission output, and signal synthesis in the analog domain, the delay effect of multiple high-speed serial signals is superimposed on one channel. This achieves a time resolution far exceeding the reference clock period limit and independent and precise programmable control of any edge in the sequence pulse. Finally, it synthesizes a high-speed sequence pulse signal with ultra-high time resolution that is not limited by memory bandwidth.

[0020] The beneficial effects of this invention are:

[0021] (1) Breakthrough in resolution bottleneck of traditional digital synthesis technology: By adopting multiple phase-interleaved data transmission channels and using OR gates for signal synthesis in the analog domain, the delay effects of multiple signals are superimposed on one channel, thereby improving the time resolution of the final output of the system. Able to break through the single reference clock cycle This overcomes the limitations and enables time control with picosecond-level or even higher precision than the reference clock frequency.

[0022] (2) Independent and precise programming of the edges of the sequence pulse is realized: The proposed multi-channel collaborative fine-tuning algorithm can decompose the time offset set by the user for any edge into collaborative parameters that control different phase channels. This algorithm allows for independent, digital programming and fine-tuning of the position of each rising or falling edge in the sequence pulse, overcoming the limitations of traditional DDWS and DDFS technologies, which can only adjust the waveform frequency as a whole or require massive storage, and providing unprecedented waveform editing flexibility.

[0023] (3) A highly efficient control architecture with hardware and software collaboration has been formed: by first quantizing the physical time offset into the smallest step integer of the system, and then decomposing it to generate precise timing control instructions that can directly drive multi-phase hardware channels, a direct and precise mapping from high-level user intent to low-level hardware behavior has been achieved. This hardware and software collaborative architecture avoids the bandwidth bottleneck of large-capacity waveform storage and retrieval, and can generate and output complex pulse sequences with large data volume and high repetition frequency in real time.

[0024] (4) Excellent overall performance and broad application prospects: The high-speed sequence pulse signal finally synthesized by this invention has four major features: ultra-high time resolution, high output frequency, large sequence data volume and independent edge programming. It well meets the urgent needs of modern communication testing, semiconductor detection, particle physics experiments and other fields for high-performance pulse sources, and has significant technological progress and broad application prospects. Attached Figure Description

[0025] Figure 1 This is a structural block diagram of the pulse synthesis device of the present invention;

[0026] Figure 2 This is a schematic diagram of the control data stream edge fine-tuning method provided in the embodiment;

[0027] Figure 3 This is a schematic diagram of the multi-channel, multi-phase high-speed signal merging provided in the embodiment. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] First, let's explain the following core terms and their interrelationships:

[0030] A sequence pulse refers to a complete digital signal waveform that the user expects to generate, consisting of a series of pulses following specific encoding rules. Its overall logical form is defined by the sequence pulse data (a binary array).

[0031] User pulses: These refer to each independent logic pulse that constitutes the sequence of pulses. User pulses are components of the sequence of pulses; their level is determined by user pulse data (a binary number), and their nominal width is determined by the reference pulse frequency. Users can independently configure the time offset for any edge of any user pulse.

[0032] Pulse Width Unit: In the digital processing flow of this invention, especially in the multi-channel collaborative fine-tuning algorithm, it refers to a data block that is used as a basic processing unit. Each pulse width unit strictly corresponds to a continuous sampling point in the ground-state data stream, and its duration is equal to the nominal width of a user pulse (i.e., (Sampling points). The pulse width unit is the operational object within the multi-channel collaborative fine-tuning.

[0033] Figure 1 It is a high-resolution sequence pulse synthesis device, comprising: a host computer, a pulse data memory, a frequency configuration register, a fine-tuning enable register, an edge offset memory, a data read control module, a programmable edge fine-tuning module, a data phase-splitting transmission module, and OR gates;

[0034] 1. Host computer, used to provide a graphical user interface, configure and send sequence pulse parameters; sequence pulse parameters include A single-bit sequence pulse data defining a pulse sequence logic waveform. The reference pulse frequency of the ground state width of each user pulse in a configuration sequence pulse. Edge fine-tuning enable of one control edge fine-tuning function switch ,as well as A set of edge offset steps for each user's pulse edge adjustment time. Edge offset step set The number of edge offset steps is calculated by dividing the edge offset of each user-configured edge adjustment time by the system resolution. The unit of the offset steps for each edge is the minimum time resolution of the system.

[0035] The reference pulse frequency configured by the host computer It should meet the following requirements: , It is a set of positive integers. This is the reference clock frequency.

[0036] 2. The pulse data memory, frequency configuration register, fine-tuning enable register, and edge offset memory all receive and store the corresponding sequence pulse parameters sent by the host computer, and use these parameters to... , , , To achieve high-speed, high-resolution sequential pulse waveform output.

[0037] 3. Data readout control module, used to read single-bit sequence pulse data from the pulse data memory and the frequency configuration register respectively. Reference pulse frequency ,Depend on calculate Number of sampling points for each user pulse , ,in, Use the reference clock frequency; then from Will Real-time conversion to ground state control data stream Then, the output is sent to the programmable edge fine-tuning module.

[0038] 4. Programmable edge fine-tuning module, used to read the edge fine-tuning enable from the fine-tuning enable register. ,like This enables edge fine-tuning functionality, controlling the ground-state data flow. For each edge detected, the set of edge offset steps is read from the edge offset memory. Then apply the multi-channel collaborative edge fine-tuning algorithm in Generate based on Road control data stream ;like Then the edge fine-tuning function will not be enabled. The value of is related to the inherent number of parallel channels in the hardware.

[0039] Each edge is configured with an independent offset step number, forming a set of edge offset steps. In the multi-channel collaborative edge fine-tuning algorithm, each user pulse and its corresponding preceding and following edge offset steps are processed as a pulse width unit. The processing of each pulse width unit is based on the number of offset steps of its starting edge. (i.e., the number of offset steps of the end edge of the previous pulse width unit) and the number of offset steps of its end edge. .

[0040] Specifically, in the multi-channel collaborative edge fine-tuning algorithm, for the set of edge offset steps... The process involves two steps: offset decomposition and control data stream generation.

[0041] 4.1 Offset Decomposition:

[0042] The purpose of this process is to determine the edge offset steps set by the user for each edge. The required coordination parameters for driving each data channel are calculated.

[0043] Specifically, the multi-channel collaborative edge fine-tuning algorithm processes data in units of pulse width units. For the first... Each pulse width unit (PWM) has a waveform that is simultaneously affected by its starting edge (corresponding to the number of edge offset steps). ) and the ending edge (corresponding to the edge offset step number) The effect of ). Then adjust the edge offset steps. and The decomposition yields a set of coordinated parameters for controlling multiple data channels. , , .

[0044] It determines the overall shift of the pulse width unit on the main data channel, representing the control command for driving the main channel (coarse adjustment). At that time, the first The data for each pulse width unit requires a coarse adjustment offset step for overall translation, in units of the reference clock cycle. . A positive value indicates a delay, while a negative value indicates a lead.

[0045] This indicates the index of auxiliary channels that need to be fine-tuned, in addition to the main channel. It indicates which auxiliary channel with an inherent phase offset will be activated to complete edge fine-tuning at the system resolution level.

[0046] Indicates data stream in the auxiliary channel In the middle, the fine-tuning narrow pulse should be inserted in the first... The sampling point position index within each pulse width unit. This parameter is related to... Together, they achieve system time resolution. Defined precision:

[0047] ;

[0048] ;

[0049] ;

[0050] in, Indicates the integer operation; express Medium pulse width unit The number of offset steps required for coarse adjustment of the corresponding sampling point is determined by the number of edge offset steps. Divide by the number of channels And rounded down to the nearest integer; This indicates the index of the auxiliary channel participating in the fine-tuning. According to the remainder theorem, the number of edge offset steps minus the number of offset steps in the coarse-tuning part is the number of offset steps for the remaining fine-tuning part. This number of offset steps will be divided by... External control data flow supply; Indicates in Pulse width unit The sampling point location index that needs fine-tuning is introduced. The term is used to ensure that the numerator is always positive, which facilitates calculation.

[0051] 4.2 Control Data Stream Generation: Based on the calculated offset parameters, multi-channel control data streams are generated according to the following rules. Based on the decomposed calculation of the coordination parameters... , , Generate the drive according to the following rules. One control data stream ,in, Use the main channel (coarse adjustment) to control the data flow. For auxiliary channel (fine-tuning) control of data flow:

[0052] (1) Main channel control data flow Used to drive channel 0 (main channel) to perform coarse adjustments. The first in Each pulse width unit, the value of which is indexed by the auxiliary channel. and Joint decision:

[0053] ;

[0054] This is the index of the sampling point within the pulse width unit. ; Indicates the main channel control data flow The Middle The pulse width unit of the first Sampling point No. This is for ground state control data flow.

[0055] When the start edge is delayed Current pulse width unit The beginning part ( The data will be from the previous pulse width unit. starting level This is equivalent to extending the tail of the previous pulse backward, thus delaying the start edge of the current pulse.

[0056] When the end edge is brought forward Current pulse width unit The end part ( The data will be transferred to the next pulse width unit. starting level This is equivalent to extending the head of the next pulse forward, thus advancing the end edge of the current pulse.

[0057] Other cases: Maintain the original value of the ground-state data stream S.

[0058] Based on the above rules, the offset step number is coarsely adjusted. This is converted into a direct modification of the pulse width unit data boundary, thereby controlling the data flow in the main channel. The method implements a reference clock period for the pulse edge. Coarse adjustment for integer multiples.

[0059] (2) For the auxiliary fine-tuning control data stream, i.e. the fine-tuning control data stream Fine-tuning the control data flow index Using the Kronecker function Perform location assignment:

[0060] ;

[0061] in, Indicates when The value is 1 if the condition is met, and 0 otherwise. This formula indicates that the value is only set to 1 for a specific control data flow. Pulse width unit Internal position index A fine-tuned narrow pulse is generated at this point. The fine-tuned narrow pulse is a micro-correction signal injected internally by the system to shape the edge of the user pulse.

[0062] The programmable edge trimming module generates timing control commands for directly controlling each phase data transmission channel, including both the main and auxiliary channels. Road control data stream It is then output to the data phase transmission module.

[0063] 5. Data phase transmission module, including: Same frequency But different phase shifts Reference clock data transmission channels; reference clock on each data transmission channel The phase shift is ,in, For the index of the data transmission channel, The corresponding time delay is Each data transmission channel will receive the corresponding control data stream from the programmable edge tuning module. Convert to High-speed serial signals with phase interleaving And output to an OR gate, Indicates the current time.

[0064] 6. High-speed logic OR gate, receiving data from the data phase-splitting transmission module. High-speed serial signals with phase interleaving They are then combined into one channel to obtain a reference pulse frequency of... High-speed, high-resolution sequence pulse signals The time resolution of this signal is This means that the system's time resolution is improved compared to the reference clock cycle. times.

[0065] Figure 2 This is a schematic diagram of the control data stream edge fine-tuning method provided in the sampling point embodiment.

[0066] like Figure 2 As shown, in this embodiment, the reference clock frequency Then, the reference clock period (the time resolution corresponding to the reference clock frequency) is used. If the system time resolution is required According to The required number of data transmission channels can be obtained. The generated control data stream is If the user configures the reference pulse frequency The data value of a certain segment in the sequence pulse data is , , , , , , Edge fine-tuning enables The edge offset corresponding to the above sequence pulse data is , , , , , ,in, For pulse width unit index, Then by The number of sampling points for each pulse width unit can be calculated. That is, one sequence of pulse data corresponds to four data points in the ground state control data stream, and the ground state control data stream corresponding to the sequence of pulses can be obtained accordingly. Data values, The edge fine-tuning function was enabled, and then according to exist Based on this, a multi-channel collaborative edge fine-tuning algorithm is applied to generate the fine-tuning control data stream. The corresponding data value;

[0067] Main channel control data flow The default value of each data item and Consistent, auxiliary channel control data flow The default value for each data point is 0. For pulses... and The rising edge offset that exists in between Therefore, there is no need to adjust the position of the edge; for pulses and Since there are no physical edges in between, the position of the edges cannot be adjusted using multi-channel collaborative edge fine-tuning algorithms, thus requiring a fixed offset. For pulses and The falling edge offset that exists in between This indicates that the edge needs to lag behind by six system resolutions. Then, the control data flow is obtained by the multi-channel collaborative edge fine-tuning algorithm. Data in and The value should be changed from 0 to 1; for pulses and The rising edge offset that exists in between This indicates that the edge needs to be ahead of four system resolutions. Then, using a multi-channel collaborative edge fine-tuning algorithm, only the coarse-tuning control data flow is obtained. Data in Changing the value from 0 to 1 will satisfy the requirement; for pulses and The falling edge offset that exists in between This indicates that the edge needs to be ahead of three system resolutions. Then, the control data flow is obtained by the multi-channel collaborative edge fine-tuning algorithm. Data in The value should be changed from 1 to 0. Data and The value should be changed from 0 to 1; for pulses and The rising edge offset that exists in between This indicates that the edge needs to lag behind by three system resolutions. Then, the control data flow is obtained by the multi-channel collaborative edge fine-tuning algorithm. Data in The value should be changed from 1 to 0. Data and The value should be changed from 0 to 1;

[0068] For ease of demonstration, Figure 2 It was also noted in the text. and The continuous waveforms corresponding to each data value.

[0069] Figure 3 This is a schematic diagram of the principle of multi-channel multiphase high-speed signal merging provided in the embodiment of the present invention.

[0070] like Figure 3 As shown, in this embodiment, the various settings and parameters are the same as... Figure 2 Consistent, the data input to each data transmission channel of the data phase-splitting transmission module is the same. Figure 2 Control data flow Each channel will Real-time conversion to analog waveforms The output is then sent to an OR gate, where a logical OR operation is performed. , OR operation, converting 4 high-speed serial signals The time delay effects are superimposed, thus overcoming the limitation of reference clock resolution and obtaining high-speed, high-resolution sequential pulse signals. And finally output to the system.

[0071] Output All the "spoofed" edges in the waveform are determined by the rising edge of the channel that first goes high and the falling edge of the channel that last goes low. In the waveform, The first waveform segment is a negative pulse, followed by a positive pulse, with its rising edge originating from the output of data transmission channel 0. The falling edge originates from the output of data transmission channel 2. The third segment is a negative pulse, and the fourth segment is a positive pulse, with its rising edge originating from the output of data transmission channel 0. The falling edge originates from the output of data transmission channel 1. The fifth waveform is a negative pulse, and the sixth waveform is a positive pulse, with its rising edge originating from the output of data transmission channel 3. .

[0072] In this invention, the variable related to the sequence pulse waveform is single-bit sequence pulse data. Reference pulse frequency The configuration is handled by the host computer, and the data is then sent to RAM and registers respectively. and After being read from RAM and registers respectively, the data enters the data read control module, controlled by variables. Calculate the number of sampling points for each synthesized pulse. Then by variables Convert to ground state control data stream This is to achieve the function of generating basic sequence pulse waveforms.

[0073] In this invention, the variable related to edge fine-tuning is the edge fine-tuning enable. Edge offset The configuration is handled by the host computer, and the data is then sent to registers and RAM respectively. and After being read from registers and RAM respectively, the data enters the programmable edge tuning module, where it is controlled by variables. The function of enabling or disabling edge fine-tuning, in After enabling the edge fine-tuning function, based on the variable Control data stream in the ground state Based on this, generate fine-tuning control data stream. This enables the programmable offset of arbitrary edges.

[0074] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A high-resolution sequence pulse synthesis device, characterized in that, It includes a host computer, pulse data memory, frequency configuration register, fine-tuning enable register, edge offset memory, data read control module, programmable edge fine-tuning module, data phase-splitting transmission module, and OR gates; The host computer is used to configure and send out sequence pulse parameters, which include: sequence pulse data. Reference pulse frequency Edge fine-tuning enable signal and edge offset step set ; The pulse data memory, frequency configuration register, fine-tuning enable register, and edge offset memory are used to receive and store the sequence pulse data sent by the host computer. Reference pulse frequency Edge fine-tuning enable signal and edge offset step set ; The data read control module is used to read the sequence pulse data from the pulse data memory. And read the reference pulse frequency from the frequency configuration register. According to the reference pulse frequency Calculate the number of sampling points for each user pulse. And based on the number of sampling points Convert the sequence pulses into a ground-state control data stream in real time. The ground state control data stream With the number of sampling points Output to the programmable edge trimming module; The programmable edge fine-tuning module is used to adjust the edge fine-tuning enable signal output from the fine-tuning enable register. The state determines whether to enable the edge trimming function; when the edge trimming function is enabled, the ground state control data stream is... For each edge detected, the corresponding edge offset step number is read from the edge offset memory, and a multi-channel collaborative fine-tuning algorithm is applied to generate... The control data stream is sent to the data phase-splitting transmission module; Among them, the multi-channel collaborative fine-tuning algorithm uses pulse width units as the processing unit, and each pulse width unit corresponds to the ground state control data stream. The duration is A continuous data segment at each sampling point; based on the edge offset steps configured for the start and end edges of the current pulse width unit, a set of collaborative parameters for the coordinated control of multiple data channels is calculated; based on the collaborative parameters, the data stream is controlled in the ground state. Based on this, generate The path control data stream includes a main channel control data stream used to implement coarse adjustment of the reference clock cycle as an integer multiple, and Paths are used to achieve system time resolution The auxiliary channel controls the data flow with fine-tuning at different levels; Data phase transmission module, including Several parallel data transmission channels; each channel uses a reference clock with the same frequency but a phase delay of a specific ratio, to transmit the received data. The corresponding path in the path control data stream is converted into a set. A high-speed serial signal with sequentially shifted phase; OR gate, used to convert the said The high-speed serial signals with sequentially shifted phases are logically ORed and combined to output a high-resolution sequential pulse signal with a time resolution equal to the reference clock period. .

2. The high-resolution sequence pulse synthesis apparatus as described in claim 1, characterized in that, The multi-channel collaborative fine-tuning algorithm partially includes an offset decomposition step and a control data stream generation step: Offset decomposition steps: For the Each pulse width unit, based on the number of offset steps of its starting edge. and the number of offset steps at the end edge A set of calculations is obtained for generating the above. Coordination parameters for path control data streams include: the number of offset steps used for coarse adjustment of the main channel. Used to indicate the auxiliary channel index involved in fine-tuning And a sampling point position index for indicating the insertion position of the fine-tuning narrow pulse in the auxiliary channel data stream. ; Control data stream generation steps: Based on the aforementioned coordination parameters , , , generate the Road control data stream ,in, The main channel controls the data flow. The auxiliary channel controls the data flow; the main channel controls the data flow. Used to achieve coarse edge adjustment of integer multiples of the reference clock period, its first The data value within each pulse width unit is based on and The value is modified to delay or advance the edge by overwriting the ground state data; Auxiliary channel control data stream Only when the channel index is satisfied Equal to the auxiliary channel index Under the condition that the auxiliary channel controls the data flow in the first... The index within each pulse width unit is At the sampling point, the data value is set to generate a fine-tuned narrow pulse; otherwise, the control data stream retains the default data value at that position; the fine-tuned narrow pulse is used to achieve the system time resolution. Fine-tuning of the level's edges.

3. The high-resolution sequence pulse synthesis apparatus as described in claim 2, characterized in that, Cooperative parameters , and The specific calculation method is as follows: ； ； ； in, This indicates the integer division operation.

4. The high-resolution sequence pulse synthesis apparatus according to claim 3, characterized in that, Main channel control data flow Used to achieve coarse edge adjustment of integer multiples of the reference clock period, its first The data value within each pulse width unit is based on and The specific method for modifying the value is as follows: ； This is the index of the sampling point within the pulse width unit. ; Indicates the main channel control data flow The Middle The index of each pulse width unit is sampling points, This is for ground state control data flow.

5. The high-resolution sequence pulse synthesis apparatus according to claim 4, characterized in that, Auxiliary channel control data stream Only when the channel index is satisfied Equal to the auxiliary channel index Under the condition that the auxiliary channel controls the data flow in the first... The index within each pulse width unit is At the sampling point, the specific method for setting the data value to generate a fine-tuned narrow pulse is as follows: For auxiliary channel control data stream Fine-tuning the control data flow index Using the Kronecker function Perform location assignment: ； in, Indicates when The value is 1 if it is true, and 0 otherwise.

6. The high-resolution sequence pulse synthesis apparatus according to claim 1, characterized in that, The set of edge offset steps Number of offset steps for each edge in By the user for the first The physical time offset configured at each edge divided by the system time resolution. And then rounded down to the nearest integer.

7. The high-resolution sequence pulse synthesis apparatus according to claim 1, characterized in that, In the data phase-splitting transmission module, the index is... The phase offset on the data transmission channel is ,in, For the index of the data transmission channel, The corresponding time delay is , For reference clock period, This is the reference clock frequency.

8. The high-resolution sequence pulse synthesis apparatus as described in claim 1, characterized in that, The OR gate is a high-speed logic OR gate, which, through the... The high-speed serial signals with sequentially shifted phases are logically ORed and combined, so that the edge time of the final output high-resolution sequence pulse signal is determined by the rising edge of the channel that goes high earliest and the falling edge of the channel that goes low latest, thereby superimposing the delay effect of multiple signals into one.

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