Quantum measurement and control multi-layer synchronization method, device and equipment oriented to heterogeneous fusion architecture

Abstract

The embodiment of the invention discloses a quantum measurement and control multi-layer synchronization method, device and equipment oriented to heterogeneous fusion architecture. A specific implementation mode of the method comprises the following steps: after responding to system starting, distributing a reference clock signal to each quantum measurement and control board card through a main clock source, so that each quantum measurement and control board card performs cross-board card clock phase alignment; configuring a board card trigger unit for each quantum measurement and control board card; the computing node performs waveform data issuing and transmission synchronization according to the quantum circuit; in response to determining that each node completes synchronization in the set timeout window, the main node issues a global trigger instruction, so that each quantum measurement and control board card simultaneously sends out a hardware trigger pulse at a unified clock edge; each quantum measurement and control board card executes a corresponding quantum operation based on the synchronous trigger signal; and dynamically and adaptively adjusting the synchronization parameter according to the coherence time of the current quantum bit. According to the embodiment, cross-node and cross-board multi-layer synchronization from a hardware bottom layer to a software upper layer can be realized.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of computer technology, and more specifically to a quantum measurement and control multilayer synchronization method, apparatus, and device for heterogeneous fusion architectures. Background Technology

[0002] As superconducting quantum computing systems gradually scale up, their measurement and control system architectures are becoming increasingly distributed and heterogeneous, making collaborative measurement and control across multiple nodes and boards essential. In such hybrid "classical + quantum" systems, classical computing nodes coordinate and control multiple quantum measurement and control boards, which in turn drive the quantum processor to execute complex computational tasks. However, due to the high time sensitivity of quantum operations and the inherent uncertainties in communication and scheduling within classical computing architectures, the system faces multiple synchronization challenges in actual operation—clock skew jitter between boards, data transmission delays, and the asynchronicity between the classical and quantum unit hardware and software execution processes. These factors severely restrict the fidelity of quantum gate operations and the real-time performance of feedback control, hindering the improvement of system reliability and scalability. Summary of the Invention

[0003] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0004] Some embodiments of this disclosure propose a quantum measurement and control multilayer synchronization method, apparatus, and device for heterogeneous fusion architectures to solve the technical problems mentioned in the background section above.

[0005] In a first aspect, some embodiments of this disclosure provide a multi-layer synchronization method for quantum measurement and control in a heterogeneous fusion architecture. The method includes: in response to system startup, distributing a reference clock signal to each quantum measurement and control board via a master clock source for cross-board clock phase alignment; configuring a board trigger unit for each quantum measurement and control board, wherein the configured board trigger unit enables the corresponding measurement and control board to respond to a synchronization trigger command within a unified clock cycle; synchronizing waveform data transmission and distribution according to the quantum circuit; in response to determining that all nodes have completed synchronization within a set timeout window, the master node issues a global trigger command for each quantum measurement and control board to simultaneously emit hardware trigger pulses at a unified clock edge; each quantum measurement and control board performs corresponding quantum operations based on the synchronization trigger signal; and dynamically adjusting synchronization parameters according to the coherence time of the current qubit.

[0006] Secondly, some embodiments of this disclosure provide a multi-layer synchronization device for quantum measurement and control oriented towards a heterogeneous fusion architecture. The device includes: a distribution unit configured to distribute a reference clock signal to each quantum measurement and control board via a master clock source after system startup, so as to enable cross-board clock phase alignment among the quantum measurement and control boards; a configuration unit configured to configure a board trigger unit for each quantum measurement and control board, wherein the configured board trigger unit is used to enable the corresponding measurement and control board to respond to a synchronization trigger command within a unified clock cycle; a data distribution unit configured to enable computing nodes to distribute and transmit waveform data synchronously according to the quantum circuit; a command distribution unit configured to, in response to determining that all nodes have completed synchronization within a set timeout window, the master node issues a global trigger command so that each quantum measurement and control board can simultaneously emit a hardware trigger pulse at a unified clock edge; an execution unit configured to enable each quantum measurement and control board to execute a corresponding quantum operation based on the synchronization trigger signal; and a parameter adjustment unit configured to dynamically and adaptively adjust the synchronization parameters according to the coherence time of the current quantum bit.

[0007] Thirdly, some embodiments of this disclosure provide an electronic device, including: one or more processors; and a storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0008] Fourthly, some embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method described in any of the implementations of the first aspect above.

[0009] The various embodiments disclosed herein have the following beneficial effects: The multi-layer synchronization method for quantum measurement and control oriented towards heterogeneous fusion architecture, through some embodiments of this disclosure, constructs a synchronization framework supporting multi-board hardware clock synchronization, data transmission and interrupt response, cross-node task global synchronization, and dynamic timeout handling and error recovery at the hardware, software, and full hardware global coordination levels. First, at the hardware synchronization level, by distributing reference clock signals from the master clock source and configuring board trigger units, control pulse deviations caused by clock jitter and drift are effectively suppressed, minimizing timing errors in multi-qubit collaborative operations and significantly improving the fidelity of quantum gate operations and the success rate of entangled state preparation. Then, at the transmission synchronization level, a pre-allocated locked memory page and DMA transmission mechanism, combined with event-driven feedback from interrupt service routines, construct a deterministic, low-latency data path, controlling the latency fluctuations of waveform data transmission and acquisition feedback within a controllable range, providing reliable communication guarantees for real-time quantum feedback control and error correction tasks. Secondly, at the software synchronization level, by introducing the CQMPI_Barrier synchronization function with timeout interrupt and fault tolerance mechanisms, deep awareness and adaptive synchronization judgment of the quantum hardware state are achieved. This effectively avoids the system deadlock problem caused by traditional barrier operations and significantly enhances the system's robustness and task scheduling flexibility in noisy environments. Finally, at the dynamic adaptation level, based on the quantum bit coherence time and real-time system load, the synchronization timeout parameters, DMA transfer strategy, and interrupt response mechanism are dynamically adjusted. This achieves a deep integration of system parameters and quantum physical characteristics, improving the long-term stability and execution efficiency of large-scale heterogeneous architectures in variable environments. Attached Figure Description

[0010] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0011] Figure 1 This is a schematic diagram of the communication process in the "classical + quantum" architecture; Figure 2 This is a flowchart of some embodiments of the quantum measurement and control multilayer synchronization method for heterogeneous fusion architecture according to the present disclosure; Figure 3 This is a schematic diagram of global synchronization of CQMPI_barrier in the “classical + quantum” architecture in the quantum measurement and control multilayer synchronization method for heterogeneous fusion architecture disclosed herein; Figure 4 This is a schematic diagram of the HI-HCQC measurement and control board system architecture in the quantum measurement and control multilayer synchronization method for heterogeneous fusion architecture disclosed herein; Figure 5 This is a schematic diagram of the local synchronization of CQMPI_barrier in the "classical + quantum" architecture in the quantum measurement and control multilayer synchronization method for heterogeneous fusion architecture disclosed in this paper; Figure 6 This is a schematic diagram of some embodiments of a quantum measurement and control multilayer synchronization device for heterogeneous fusion architecture according to the present disclosure; Figure 7 This is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present disclosure. Detailed Implementation

[0012] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0013] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0014] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0015] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0016] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0017] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0018] Figure 1 The communication process in the "classical + quantum" architecture is shown.

[0019] In practical large-scale quantum computing tasks, a typical "classical + quantum" hybrid process can be summarized as a cyclical iteration of "classical preprocessing—waveform delivery—quantum state evolution—result reading—classical postprocessing," as follows: Figure 1As shown. In this process, system performance and computational fidelity are severely constrained by key synchronization bottlenecks. These bottlenecks stem from the fundamental differences between the physical characteristics of quantum systems and classical computing architectures, and can be mainly divided into the following three types.

[0020] In the first type, regarding hardware timing, the operation of qubits relies on highly precise microwave pulses. The accuracy of their phase, frequency, and timing directly determines the fidelity of the quantum gate. In a distributed measurement and control system, multiple quantum control boards control different subsets of qubits. Because each control board has an independent clock source, even with excellent board performance, unavoidable clock jitter and drift will still be introduced, resulting in minute differences and phase deviations between control pulses. For quantum gates that require multiple qubits to operate collaboratively, this asynchrony directly disrupts the synchronization of operations, introduces severe coherence errors, causes the failure of entangled state preparation, and consequently leads to a sharp decline in the reliability of the computational results. Therefore, ensuring the clock synchronization accuracy of all control channels is a prerequisite for achieving high-fidelity large-scale quantum computing.

[0021] The second type, in terms of data transmission, suffers from latency uncertainty bottlenecks in the data interaction path between the classical computing layer and the quantum device layer. The transmission of waveform data from the PCIe interface to the board's local memory is affected by multiple factors, including operating system scheduling policies, PCIe controller load, and memory access conflicts. Similarly, the raw data generated after quantum state reading, such as IQ data, is transmitted back to the classical layer for processing, also exhibiting similar latency fluctuations. In control loops requiring rapid feedback, this transmission latency uncertainty makes it difficult for the feedback control loop to complete within a defined time window, thus affecting the effectiveness of quantum error correction and real-time control.

[0022] The third type, in terms of hardware and software collaboration, currently distributed quantum computing systems use traditional high-performance computing communication libraries for task coordination. Their standard barrier synchronization operation can only synchronize software processes between computing nodes, i.e., "waiting for all processes to reach the barrier point." However, it lacks the ability to interact with the underlying quantum hardware state and cannot perceive: 1. whether each board has completed waveform loading; 2. whether the hardware trigger signal has been actually issued and taken effect; 3. whether the quantum chip has completed its evolution and is ready to be read. Furthermore, if a quantum device fails to respond for any reason, the traditional barrier will wait indefinitely, causing the entire system to deadlock. The lack of effective timeout interrupt and error recovery mechanisms severely limits the system's fault tolerance and execution efficiency in noisy environments.

[0023] The aforementioned problems stem from the inherent differences between quantum physics systems and classical computing architectures: 1. Quantum operations rely on highly precise timing control, often requiring accuracy at the nanosecond or even picosecond level, while classical computing systems mostly operate asynchronously and in a time-sharing manner, lacking global timing determinism. 2. Quantum states are susceptible to environmental noise and have finite coherence time, requiring the measurement and control system to have rapid response and dynamic adjustment capabilities. 3. The distributed nature brought about by large-scale expansion further increases the complexity of cross-node and cross-board coordination. Therefore, relying solely on local optimization or single-level synchronization methods is insufficient to fundamentally solve the system synchronization problem. A multi-layered, cross-platform collaborative framework covering hardware clocks, data transmission, software scheduling, and error recovery mechanisms must be constructed to achieve true end-to-end synchronization.

[0024] To address the aforementioned technical issues, the quantum measurement and control multi-layer synchronization method for heterogeneous fusion architecture disclosed herein systematically improves synchronization accuracy and system robustness through collaborative innovation and deep integration of hardware, transmission, and software, thereby alleviating the synchronization bottleneck in large-scale quantum computing.

[0025] Figure 2 A flow 200 is shown illustrating some embodiments of a multi-layer synchronization method for quantum measurement and control of heterogeneous fusion architectures according to this disclosure. This multi-layer synchronization method for quantum measurement and control of heterogeneous fusion architectures includes the following steps: Step 201: In response to the startup of the quantum measurement and control system for heterogeneous fusion architecture, the quantum measurement and control system distributes reference clock signals to each quantum measurement and control board through the master clock source so that the above-mentioned quantum measurement and control boards can perform cross-board clock phase alignment.

[0026] In some embodiments, the execution entity (e.g., a computing device) of the multi-layer synchronization method for quantum measurement and control in a heterogeneous fusion architecture can, in response to the startup of the quantum measurement and control system for a heterogeneous fusion architecture, distribute reference clock signals to each quantum measurement and control board through an external high-stability master clock source. Each quantum measurement and control board can be locked to the master clock through a low-jitter phase-locked loop circuit to achieve cross-board clock phase alignment. The aforementioned external high-stability master clock source can be, but is not limited to, a temperature-controlled crystal oscillator or a rubidium atomic clock. The aforementioned reference clock signal can be a clock signal distributed by a global hardware counter (i.e., the external high-stability master clock source). The hardware counter automatically increments by 1 in each system clock cycle, and each digital increment represents the elapsed time of one clock cycle. As a high-precision, globally synchronized "clock," it provides a unified timestamp for all operations (CPU, signal generation, signal decoding) on ​​the entire chip. In traditional CPU-centric systems, time is usually defined by the execution of software instructions, which introduces huge and uncertain delays. The hardware counter turns time itself into a globally readable hardware resource, achieving time decoupling and precise timing control.

[0027] It should be noted that the aforementioned computing devices can be either hardware or software. When the computing device is hardware, it can be implemented as a distributed cluster consisting of multiple servers or terminal devices, or as a single server or a single terminal device. When the computing device is software, it can be installed on the hardware devices listed above. It can be implemented as, for example, multiple software programs or software modules used to provide distributed services, or as a single software program or software module. No specific limitations are made here. It should be understood that the number of the aforementioned computing devices can be arbitrary, depending on the implementation requirements.

[0028] The heterogeneous fusion architecture in the quantum measurement and control multilayer synchronization method for heterogeneous fusion architecture disclosed herein includes a hardware-software collaboration layer, a hardware synchronization layer, a transmission synchronization layer, and a software synchronization layer.

[0029] It should be noted that steps 201 and 202 primarily involve the hardware synchronization layer, which forms the physical foundation for the synchronization of the quantum measurement and control system. By distributing the reference clock from the master clock source and configuring the board-level trigger unit, a unified time base and trigger response capability are established directly at the hardware circuit level, providing high-precision timing guarantees for the entire system. Step 203 primarily involves the transmission synchronization layer, the core of which is to solve the problem of transmitting waveform data from the classical computing side to the quantum measurement and control board side. Through pre-allocated locked memory, DMA mechanism, and interrupt service routines, a deterministic low-latency data path is constructed, ensuring the timeliness and reliability of data transmission. Step 204 primarily involves the software-hardware collaboration layer, which is the hub of software-hardware collaboration. After confirming the synchronization of the software synchronization layer (implemented through CQMPI_Barrier), the master node issues instructions, which are ultimately executed by the hardware synchronization layer (board trigger unit) at the unified clock edge, realizing precise conversion and global synchronization from software commands to hardware actions. Step 205 primarily involves the hardware synchronization layer and the transmission synchronization layer. The quantum control board executes quantum operations based on the synchronization trigger signal (hardware synchronization layer) and outputs waveforms through the RF-DAC. After the operation is completed, data is acquired through the ADC and a data return is initiated (transmission synchronization layer). This step is the specific implementation of hardware control and data interaction. Step 206 primarily involves the software synchronization layer and influences the strategies of the transmission synchronization layer and the hardware synchronization layer across layers. This step reflects the system's intelligence and adaptability. Based on the physical characteristics of quantum bits (such as coherence time) and the real-time operating status of the system, the synchronization timeout parameters are dynamically adjusted in the software synchronization layer, and the DMA and interrupt strategies of the transmission synchronization layer are optimized, thereby indirectly improving the efficiency and robustness of the entire hardware execution process. Figure 3 As shown, a global synchronization protocol is further designed at the hardware-software collaboration layer to organically integrate the mechanisms of the above layers. During task execution, classical nodes distribute quantum circuits to each computing node via CQMPI_Send. After real-time compilation by the compiler, only the required waveform data is transmitted, reducing the bus load. Subsequently, software layer synchronization is achieved through CQMPI_Barrier to confirm that all board data has been loaded. The master node issues a global hardware trigger command to enable all boards to start operations synchronously within a unified clock cycle. Finally, data acquisition and feedback are completed through the reverse process, and multiple iterations are achieved on this basis. This protocol fully combines the flexibility of software scheduling with the high precision of hardware triggering, realizing end-to-end synchronization from task allocation to physical execution, laying a key technical foundation for large-scale, scalable quantum computing systems. The aforementioned classical nodes can refer to computer units, such as servers, responsible for performing traditional digital computing and task coordination in a "classical + quantum" heterogeneous fusion architecture. The aforementioned computing nodes can be other classical computing nodes participating in the computation, which receive subtasks from the master classical node.

[0030] The CQMPI_Send function described above is the core communication primitive in the CQMPI protocol. Its core function is to enable precise and efficient data transmission from one process to another in a heterogeneous "classical + quantum" fusion architecture. The key improvement of the CQMPI_Send function lies in its unification and abstraction of four different communication scenarios, which are separated in traditional MPI: 1. Classical computing node → Classical computing node; 2. Classical computing node → Quantum control board; 3. Quantum control board → Classical computing node; 4. Quantum control board → Quantum control board. Through a unified interface, the CQMPI_Send function shields the complex heterogeneity between underlying classical computing resources and quantum hardware resources, providing programmers with a consistent programming view and simplifying the development of distributed "classical + quantum" hybrid applications. The specific implementation of the CQMPI_Send function is as follows: The implementation of the CQMPI_Send function is the key to its innovation; it completes communication across heterogeneous environments in the following way: (a) Parameter parsing and routing decision: The function first parses the key parameters flag, node_id, and card_id. flag: determines which of the four scenarios this communication belongs to (e.g., C_Q indicates from a classical node to a quantum board). node_id and card_id: together constitute the "hardware address" of the data packet. It not only indicates which classical server the target is on, but also specifies which quantum control board on that server.

[0031] (b) Data Transmission Path Optimization: The implementation of the CQMPI_Send function greatly simplifies and optimizes the communication process. Traditional MPI scheme: Classic process → Host computer (line data) → (Host computer converts waveform) → Measurement and control equipment (waveform data). This is a complex, serial, multi-stage process. The CQMPI_Send scheme merges and simplifies the above process. When CQMPI_Send is used to send quantum lines, its implementation is as follows: 1. Inter-node transmission: Call the optimized classical MPI function at the lower level to send the line data directly from the source computing node to the target computing node. 2. Intra-node transmission and compilation: After the data arrives at the target computing node, it is directly delivered to the designated quantum measurement and control board by the service process on that node. Subsequently, the board itself (or its tightly coupled driver) completes the "line to waveform conversion". This avoids the centralized bottleneck of the host computer in the traditional scheme.

[0032] (c) Deep integration with hardware drivers: The function implementation is tightly coupled with the driver program of the quantum measurement and control board. When the target address is the quantum measurement and control board, the internal implementation of CQMPI_Send will call the corresponding board driver API to write the data directly to the specified memory area of ​​the board through the PCIe bus and using DMA and other technologies, thereby ensuring low latency and high throughput.

[0033] (d) Error checking and retransmission: At the protocol level, the implementation also includes an error checking mechanism for quantum computing environments. If data is corrupted during transmission due to noise interference or other reasons, the sending or receiving end can detect it and trigger a retransmission mechanism to ensure the accuracy of quantum operation instructions.

[0034] The primary function of the CQMPI_Barrier function is to synchronize all processes within a communication domain. Similar to traditional barrier functions, it ensures that all processes reach the same point in their programs before allowing them to continue executing subsequent code. However, in a hybrid "classical + quantum" system, its role takes on new and crucial meanings: 1. Software-level synchronization: Confirming that all software processes on all computing nodes have reached the synchronization point. 2. Hardware state awareness: Implicitly confirming that all quantum measurement and control boards have completed their preparatory tasks (such as waveform data loading) and entered a "ready" state. 3. Triggering global operations: Its successful completion is usually a prerequisite for the master node to issue a global hardware trigger command, thereby initiating all boards to simultaneously emit pulses at a unified clock edge. Improvements to the CQMPI_Barrier function: The CQMPI_Barrier function introduces a timeout interrupt mechanism and fault tolerance capabilities, making it a non-blocking or soft-blocking synchronization primitive, adaptable to unstable quantum computing environments. Its specific implementation is as follows: (a) Function parameter explanation: CQMPI_Barrier(CQMPI_Comm comm, int T_timeout). comm: Specifies the process group (communication domain) to be synchronized. T_timeout: Core improvement parameter. Specifies the timeout for synchronization wait. This parameter can be dynamically calculated.

[0035] (b) Initialization and Status Collection: 1. When a process calls the CQMPI_Barrier function, it reports to a designated coordinator (usually the master node of rank 0) that it has reached the barrier point. 2. The master node begins collecting the "arrival" status of all processes.

[0036] (c) Timeout Timer and Dynamic Waiting Loop: 1. When the master node starts collecting status, it starts a timeout timer with a duration of T_timeout. 2. The master node enters a waiting loop, in which it checks whether all processes have reported and whether the timeout timer has expired.

[0037] (d) Decision and Return (Core Fault Tolerance Logic): 1. Success Scenario: If all processes successfully report before the timer expires, the master node broadcasts a "synchronization successful" message. After all processes receive the message, the function returns a success code, and the program continues execution. 2. Failure / Timeout Scenario: If any process has not reported after the timer expires (e.g., processes 2 and 3 are not ready), the function will immediately interrupt and wait. The master node broadcasts a "synchronization failed" message, along with an error code and a list of unsynchronized process IDs (e.g., [2, 3]). The function returns instead of blocking indefinitely.

[0038] (e) Deep integration with quantum physics properties (dynamic timeout): T_timeout can be a dynamically adjustable parameter. Specifically, the system can dynamically set the value of T_timeout based on the coherence time (T1, T2) of the currently operated qubit. For example, T_timeout can be set to a value shorter than T2*(decoherence time) to ensure synchronization is completed before the quantum state fails or error recovery is triggered in time, thereby avoiding meaningless quantum operations and conserving valuable quantum resources.

[0039] (f) Upper-layer interaction and error recovery: The error codes and unsynchronized node information returned by the function provide a basis for decision-making in the upper-layer scheduling algorithm. The upper-layer system can perform the following based on this information: 1. Error mitigation: Ignore the results of the failed node and continue computation using the remaining nodes (degraded operation). 2. Task rescheduling: Reassign the subtasks on the failed node to other healthy nodes. 3. System reset: Trigger the error recovery process for the entire system.

[0040] The aforementioned global hardware trigger command is a low-latency, broadcast hardware-level instruction signal issued by the master node at a specific moment. Its core characteristics are global reach and direct hardware responsiveness. It possesses the following characteristics: 1. Global reach: The command is simultaneously sent to all quantum measurement and control boards in the system, ensuring that all boards receive and respond to the command within the same reference clock cycle. 2. Direct hardware responsiveness: It is not a data message that requires the operating system or upper-level software to slowly parse, but rather an electrical pulse or digital signal directly recognized by the trigger unit on the board. Its goal is to trigger a precise, predefined hardware action.

[0041] The core function of the global hardware trigger command is to achieve absolute synchronous startup of all quantum measurement and control boards on the timeline, thereby ensuring the timing consistency of multi-qubit operations. Its specific functions include: 1. Unifying the execution starting point: Ensuring that microwave pulse playback from all control channels and signal acquisition from all read channels begin at the same moment. 2. Eliminating accumulated errors: Even after clock synchronization and data transmission synchronization are completed, minor timing differences or software scheduling delays still exist within each board. The global hardware trigger command provides a unified, high-precision absolute time starting point, resetting all these potential minor deviations. 3. Connecting hardware and software: It is the critical point from the "classical computing domain" to the "quantum operation domain." Before this is software coordination and data preparation; after this is deterministic hardware execution. 4. Ensuring operational fidelity: Through nanosecond or even picosecond-level synchronization precision, it minimizes quantum gate errors introduced by control pulse asynchrony, directly improving the fidelity of quantum computing and the reliability of results. The direct target of the global hardware trigger command is all quantum measurement and control boards in the system.

[0042] Quantum measurement and control board: Commands are sent to each hardware board that controls the qubit.

[0043] Board Trigger Unit: This is the final unit for receiving and executing commands. This unit is configured during system initialization, and its logic circuitry continuously listens for this global trigger signal. Once the signal is detected on a uniform clock edge (such as a rising edge), it immediately initiates two core operations: 1. Trigger Waveform Playback: The command board's digital signal processor or direct memory access controller begins reading waveform data from memory and sends precise microwave pulses via an RF digital-to-analog converter to drive the qubits. 2. Trigger Data Acquisition: After quantum evolution is complete, the same or another trigger signal can activate the analog-to-digital converter to begin acquiring the read signal returned from the quantum chip.

[0044] The hardware synchronization layer is the physical foundation for the synchronization of the entire system, aiming to eliminate the inherent clock skew between control units. At the hardware synchronization layer, the system employs a highly stable external reference clock, distributed to each measurement and control board via differential signals and impedance-matched cables. This significantly reduces clock jitter and cross-node phase errors, precisely aligning the timing start points of all control commands on the time axis. This establishes a unified, high-precision reference for subsequent synchronous triggering, effectively suppressing noise interference and reflections during signal transmission, thereby ensuring the integrity of the clock waveform. The board integrates a programmable trigger unit, generating synchronization pulse signals based on a unified clock. This ensures that all boards can start waveform playback or data acquisition at the same time, physically guaranteeing the timing consistency of multi-qubit operations. The aforementioned programmable trigger unit refers to a software-configurable digital logic hardware integrated on the quantum measurement and control board. Its core function is to receive instructions from the software and generate one or more highly synchronized hardware trigger signals under a unified and precise clock reference. Because the triggering is absolutely synchronized, the microwave pulses driving the two qubits are perfectly aligned on the time axis. This ensures that two-qubit gates (such as CZ gates) can be executed with high fidelity, thus successfully preparing entangled states. Without this programmable trigger unit, even a slight delay in the software instructions would cause the two pulses to become asynchronous, disrupting the entanglement operation and leading to computational errors. The aforementioned synchronization pulse signal is a short, digital electrical pulse signal generated by the programmable trigger unit. Its core characteristics lie in its precise timing and global synchronization. The role of the aforementioned synchronization pulse signal is: 1. Unifying the execution starting point of multi-channel operations. In large-scale quantum computing, a quantum gate operation (such as a two-qubit gate) often requires multiple control channels to simultaneously emit microwave pulses. Without a synchronization pulse, even if data has been sent to each board in advance, due to minute clock drifts and software scheduling delays, the time when each board starts playing the waveform will have random and uncontrollable slight differences. This nanosecond-level difference is enough to disrupt quantum entanglement, causing the quantum gate operation to fail and the fidelity to drop sharply. With a synchronization pulse, the synchronization pulse provides an absolutely unified starting point for all control channels. All hardware on the boards (such as RF-DACs) begins to act the instant this pulse is received, ensuring perfect alignment of all control pulses on the timeline. This directly affects the RF-DACs on each quantum measurement and control board, triggering them to begin playing waveforms. 2. Coordinated control and readout sequence: In more complex quantum experiments, the operation sequence may contain multiple steps, such as: "first apply a control pulse, then wait for a period of time, and then perform a readout," affecting the analog-to-digital converters (ADCs) on each board, triggering them to begin signal acquisition. Synchronous trigger readout: Synchronization pulses can trigger not only pulse playback but also data acquisition.After the quantum state evolution is complete, another synchronization pulse can simultaneously activate the analog-to-digital converters (ADCs) on all boards to begin acquiring the quantum state readout signal. This ensures that the measurement results are time-aligned, which is crucial for subsequent data correlation and analysis. Constructing complex timing sequences: Through programming, a series of synchronization pulses with specific time relationships can be generated, thereby constructing complex control-readout timing logic to achieve advanced operations such as dynamic decoupling and quantum feedback control.

[0045] The aforementioned hardware synchronization layer consists of a master clock source, a clock distribution network, and synchronization hardware on the quantum measurement and control boards. The master clock source is a highly stable, low-jitter external reference clock generator that produces an extremely accurate and stable reference clock signal. The clock distribution network is a physical transmission line composed of differential signal lines and impedance-matched cables. It distributes the reference clock signal generated by the master clock source to all quantum measurement and control boards in the system with minimal signal distortion and jitter. Differential signals and impedance matching are used to suppress noise interference and signal reflection during transmission, ensuring the integrity of the clock waveform. The synchronization hardware on the quantum measurement and control boards is the core carrier for the hardware synchronization layer's functionality. Each board integrates the following key hardware units: 1. A phase-locked loop (PLL) circuit, an integrated circuit located on each quantum measurement and control board. It receives the reference clock signal from the master clock source and locks the board's internal clock to this master clock using PLL technology. This eliminates long-term drift caused by crystal oscillator differences between boards and significantly reduces clock jitter, achieving phase alignment of all board clocks. 2. The programmable trigger unit is a configurable digital logic circuit or dedicated processor (such as a logic block in an FPGA). This is the final receiving and execution unit for the "global hardware trigger command." Based on an aligned unified clock, it generates a highly accurate synchronization pulse signal at a preset, unified clock edge after receiving the trigger command from the master node. 3. Waveform playback and acquisition hardware includes a radio frequency digital-to-analog converter (RF-DAC) and an analog-to-digital converter (ADC). Upon receiving the synchronization pulse from the trigger unit, the RF-DAC simultaneously begins reading waveform data and converting it into analog microwave pulses to control the qubits. The ADC, upon reading the arrival of the trigger signal, simultaneously begins acquiring the quantum state signal. The aforementioned transmission synchronization layer focuses on solving the latency uncertainty problem of data interaction between the classical computing layer and the quantum device layer. In the transmission synchronization layer, the quantum measurement and control system optimizes the DMA transfer path by pre-allocating locked memory pages, avoiding memory paging and copying overhead during transmission. Furthermore, an event-driven mechanism based on Interrupt Service Routines (ISRs) is introduced. A hardware interrupt is triggered immediately upon DMA transfer completion, and a lightweight ISR quickly updates the status flags (e.g., setting `dma_transfer_complete` from 0 to 1) and notifies the upper-layer communication environment. This allows the data transfer completion event to be fed back to the software layer with extremely low latency, establishing a deterministic low-latency data path. This provides reliable guarantees for real-time feedback control, making the prediction and planning of feedback control loops possible. The upper-layer communication environment can refer to user-space applications or other threads within the kernel.

[0046] In practice, the specific implementation steps of the quantum measurement and control system to optimize the DMA transfer path by pre-allocating locked memory pages are as follows: Step 1: Pre-allocate a physically contiguous memory buffer. 1. Allocation during driver load: When the kernel driver for the quantum measurement and control board is loaded, a large contiguous DMA buffer with a fixed physical address is requested. 2. Alternative: Use large pages. For situations requiring a very large buffer, Linux's large page feature can be used to pre-allocate large pages of memory. This reduces page table entries and further improves access efficiency.

[0047] Step 2: Lock memory pages. For allocated memory, the "locking" is implicit; the operating system will not swap these pages out. If the memory is ordinary memory locked in user space using `mlock()`, it needs to be mapped to kernel space using the driver's `mmap()` operation to obtain its physical address before it can be used for DMA. This method is more complex and does not necessarily guarantee physical contiguity.

[0048] Step 3: Establish a mapping between user space and the DMA buffer. To allow user-space applications to directly fill waveform data into the DMA buffer, the driver needs to provide the mmap() interface. By calling mmap(), the application maps the kernel virtual address of the pre-allocated DMA buffer in the driver to its own user virtual address space. This allows the application to write waveform data directly to this buffer as if it were operating on ordinary memory.

[0049] Step 4: Configure DMA transfer and fill data: The application writes the compiled quantum circuit waveform data to the user space address mapped via mmap. Initiate transfer: The application notifies the driver to initiate DMA transfer via system calls such as IOCTL. The driver writes parameters such as the DMA buffer bus address and data length to the board's DMA controller register. Board executes DMA: The DMA controller on the board gains bus control and directly reads the waveform data from main memory according to the set bus address and length, writing it to the board's local memory (such as the FPGA's internal BRAM or onboard DDR memory). The entire process requires no CPU involvement in data copying.

[0050] Step 5: Transfer Completion and Notification. When the DMA transfer is complete, the board's DMA controller will trigger a hardware interrupt. The driver's interrupt service routine is called, which performs necessary cleanup work and immediately notifies the application that "waveform data is ready" by sending signals or events to the upper layer.

[0051] In practice, the event-driven mechanism based on interrupt service routines (ISRs) triggers a hardware interrupt immediately upon DMA transfer completion. A lightweight ISR quickly updates the status flags and notifies the upper-layer communication environment, thus feeding back the data transfer completion event to the software with extremely low latency. The specific implementation is as follows: Step 1: The DMA controller immediately triggers a hardware interrupt signal when the data transfer is complete.

[0052] Step 2: The CPU's interrupt controller receives the hardware interrupt, suspends the currently executing task, and jumps to the corresponding interrupt service routine according to the interrupt vector table.

[0053] Step 3: The Lightweight Interrupt Service Routine (ISR) begins execution and quickly completes the following key operations: First, the ISR clears the hardware interrupt flag to allow subsequent interrupt reception. Next, the ISR updates a predefined memory status flag. Then, the ISR sends a wake-up signal to a wait queue or an event notification to a task notification structure.

[0054] Step 4: After performing the above minimization operation, the ISR immediately exits and restores the interrupted CPU context.

[0055] Step 5: The upper-layer communication environment (such as user-space applications or other threads in the kernel) detects the status change of DMA transfer completion in real time by polling status flags or waiting for event notifications.

[0056] Step 6: After confirming the completion of the transmission, the upper-layer communication environment continues to execute the subsequent quantum computing process (such as calling CQMPI_Barrier for synchronization).

[0057] At the software synchronization layer, this invention extends the CQMPI (Classical-Quantum Message Passing Interfac) communication protocol with a barrier synchronization function CQMPI_Barrier, which incorporates timeout and fault tolerance mechanisms. Traditional MPI_Barrier (e.g., the MPI_Barrier function in the C language's MPI library) blocks the calling process until all processes in the communication domain have called the function. In distributed computing, this is an "all-or-nothing" blocking operation; therefore, if any process fails or experiences excessive latency, it can lead to a deadlock in the entire application, which is unacceptable in the noise-sensitive and unstable NISQ (Noisy Intermediate-Scale Quantum) quantum device environment. To address this, we innovatively designed the CQMPI_Barrier(comm, T_timeout) function with a timeout interrupt mechanism. This function allows setting a dynamically adjustable timeout T_timeout; synchronization is considered successful only if all processes in the communication domain successfully reach the barrier point within the specified time. If a timeout occurs, the function will return immediately, carrying a specific error code and the process ID information that failed to synchronize in time, thereby avoiding a global deadlock. The upper-level scheduling algorithm can use this information to mitigate the error or trigger task rescheduling.

[0058] For example, in a quantum error correction task requiring rapid feedback, the system has three computing nodes (node ​​0 is the master node, and nodes 1 and 2 are slave nodes), each controlling a batch of qubits. The task requires all nodes to complete waveform transmission and execute synchronously before the qubits decohere.

[0059] Scenario A: Synchronization Successful. 1. Parameter Setting: The master node sets T_timeout=80μs (to allow for computation and triggering) based on the current T2* (decoherence time) of the qubits, which is 100μs. 2. Command Issuance: The master node distributes the compiled quantum circuit waveform data to nodes 1 and 2 via CQMPI_Send. 3. Barrier Invocation: All nodes (0,1,2) call CQMPI_Barrier(comm,80). 4. Waiting and Confirmation: Node 0 (master node) completes data verification within 10μs and reaches the barrier point. Node 1 completes DMA transfer within 25μs and reaches the barrier point. Node 2 completes DMA transfer within 30μs and reaches the barrier point. 5. Successful Return: All processes report ready before the 80μs timeout. The barrier function returns the success code CQMPI_SUCCESS. 6. Subsequent Operations: The master node then issues a global hardware trigger command, and all boards synchronously execute quantum operations.

[0060] Case B: Synchronization timeout (fault tolerance mechanism takes effect). 1. Parameter setting: Same as case A above, T_timeout=80μs. 2. Issuing instructions: Same as case A above. 3. Calling the barrier: All nodes call CQMPI_Barrier(comm, 80). 4. Waiting and problems: Node 0 and Node 1 reach the barrier point within 30μs. The PCIe bus of Node 2 experiences temporary congestion, DMA transfer is slow, and it still does not reach the barrier point after the 80μs timeout. 5. Timeout return: At the timeout, the CQMPI_Barrier function immediately terminates the wait and returns the error code CQMPI_ERR_TIMEOUT. At the same time, it returns a list of unsynchronized node information[2]. 6. Error recovery: After the upper-layer scheduling algorithm receives the error code and the node list, it triggers the fault tolerance process: 6.1 Task rescheduling, the master node records the current state, cancels the current task, and reassigns the subtasks on Node 2 to Node 0 and 1 (degraded operation), and then restarts the entire process. 6.2 System Diagnosis: Simultaneously, report a potential hardware failure in node 2 to the system administrator, triggering the diagnostic program. 7. Deadlock Avoidance: The system did not experience indefinite waiting and deadlock due to the failure of one node; other healthy nodes continued to operate, and valuable quantum computing resources (the coherence time of other qubits) were not wasted.

[0061] Furthermore, T_timeout can be made a dynamically adjustable parameter, adaptively adjusting its value based on the coherence time (T1, T2) of the currently operated qubit. This optimizes system execution efficiency, demonstrates the software's deep understanding of quantum physics characteristics, and significantly enhances the system's adaptability to noisy environments. "Dynamically adjustable" means that the value of T_timeout is not a hard-coded constant, but rather dynamically calculated based on the system's real-time state during program execution. Its implementation logic is a typical closed-loop feedback control system.

[0062] In practice, the specific implementation of adaptively adjusting the value of T_timeout based on the coherence time (T1, T2) of the currently operated qubit is as follows: 1. Data Sensing Layer, Quantum Physics Sensing: The quantum measurement and control system maintains a database of qubit parameters. Before executing a quantum circuit, the scheduler queries the coherence time (T1, T2*) of all qubits involved in the circuit and takes the shortest one as the benchmark. System Load Sensing: The system monitors the global status in real time, such as average network latency, DMA transfer queue length, node CPU load, etc., and calculates a system load factor K_load (e.g., 1.0 indicates normal, >1.0 indicates high load).

[0063] 2. Decision Computation Layer: Define a basic security coefficient α (e.g., 0.2~0.5). This coefficient represents the proportion of qubit coherence time that is willing to be spent waiting for synchronization. The smaller α is, the more "impatient" the system is, and the lower its fault tolerance; the larger α is, the more "patient" the system is, but the risk of quantum state failure increases.

[0064] The formula for calculating dynamic timeout is: T_timeout = α * T_physical * K_load.

[0065] For example: The current task's shortest coherence time, T_physical, is 100 μs. The system load is normal, with K_load = 1.0. A safety factor α is set to 0.3. Therefore, T_timeout = 0.3 * 100 * 1.0 = 30 μs. If the system detects network congestion, K_load becomes 1.5, and T_timeout automatically adjusts to 0.3 * 100 * 1.5 = 45 μs, giving the system more synchronization time.

[0066] 3. Execution layer: Before calling CQMPI_Barrier, the master node or each node dynamically performs the above calculations and passes the calculation result T_timeout as a parameter to the function.

[0067] 4. Feedback optimization layer: The system can record the actual time T_actual of each synchronization and success / failure records. If multiple instances occur where T_actual is very close to T_timeout but the synchronization succeeds, α can be appropriately increased to reduce unnecessary timeout errors. If synchronization frequently fails, and it is found that an excessively long T_timeout setting is causing quantum state invalidation, α can be decreased.

[0068] Figure 3 The paper also describes the entire process of a quantum computing task under a heterogeneous "classical + quantum" fusion architecture, from the classical layer's issuance of the task, through execution by quantum hardware, to the return of the result. It highlights the fault-tolerance mechanism of the software synchronization layer (CQMPI_Barrier). This demonstrates how this patent achieves software-hardware collaboration and system fault tolerance by sensing hardware status and timeout interrupts, avoiding global deadlock caused by single-point failures.

[0069] Left side of the diagram: Classic node (control and decision layer) 1. Waveform Configuration. Function: The preparation phase for task execution. Terminology and process explanations are as follows: Demodulation Configuration: In a frequency-reused readout system, this configures how to separate the mixed readout signal onto each individual qubit. Multiple Shot Configuration: Refers to configuring the parameters for multiple measurements (Shots). To combat quantum noise and obtain statistically reliable results, the same quantum circuit needs to be repeated hundreds or thousands of times. Trigger Command: Generates and prepares to issue a global hardware trigger command. This command will be issued after all conditions are ready.

[0070] 2. Task Generation → Data Distribution. Function: Converts the configured quantum task into specific control commands and distributes them. The process is as follows: 2.1 Classical computing nodes compile the quantum circuit into specific waveform data. 2.2 Through communication functions such as CQMPI_Send, the waveform data is distributed to the computing nodes responsible for controlling each subset of qubits. 2.3 Each computing node efficiently transfers the waveform data from the host memory to the local memory of the quantum measurement and control board via DMA.

[0071] 3. Data Processing → Synchronization Judgment. Function: Perform barrier synchronization with timeout and fault tolerance mechanisms to confirm that all hardware units are ready. Synchronization Principle and Process: 3.1 All computing nodes call the CQMPI_Barrier function. 3.2 The function starts a timer and waits for all nodes to report "waveform data loading complete". 3.3 Key Judgment Nodes: Case A: All nodes complete: Within the timeout period T_timeout, all nodes successfully report. The process continues to the "data upload" stage to initiate hardware triggering. Case B: Some nodes / boards are not complete: Within T_timeout, some nodes do not respond (possibly due to network latency, board failure, etc.). The function immediately interrupts and returns with an error code and a list of unsynchronized node / board IDs. Fault Tolerance: When it is determined that "some nodes are not complete", the upper-level scheduler will trigger error recovery steps, such as task rescheduling (assigning the tasks of the faulty node to healthy nodes), node isolation, or system alarms, thereby avoiding global deadlock.

[0072] 4. Data Upload. Function: Initiates quantum operations and retrieves computation results. The process is as follows: 4.1 After confirming successful synchronization of all nodes, the master node sends a global hardware trigger command to all boards via the PCIe interface. 4.2 After the quantum operation is completed, each board transmits the collected raw data (such as IQ data) back to its corresponding classical computing node via the PCIe interface. 4.3 The classical nodes perform post-processing on the data (such as signal demodulation, state discrimination, averaging, etc.), and finally summarize the results of the quantum computing operation to obtain the final result.

[0073] Right side of the image: Measurement and control equipment and quantum chip (execution layer) 1. Measurement and Control Equipment (Board). Function: The board receives commands and executes specific quantum control and readout operations. The process and terminology are as follows: Data Preprocessing: The FPGA (PL) on the board performs final digital signal processing on the received waveform data, such as interpolation and modulation. Relaxation Waiting: A crucial physical waiting process. Sufficient time must be reserved between two consecutive measurements to allow the qubit to relax from the excited state back to the ground state to reset the quantum state. This time is determined by the T1 relaxation time of the qubit. Signal Playback: When the board's trigger unit receives a global hardware trigger command, it starts the RF-DAC at the edge of a unified clock to convert the digital waveform into analog microwave pulses and transmit them. Signal Acquisition: After the quantum state evolution is complete, the RF-ADC is started to acquire the readout signal returned from the quantum chip.

[0074] 2. Quantum Chip. Function: The physical carrier for performing quantum computing. The process is as follows: Quantum State Evolution: Under the drive of control pulses, the state of a qubit changes according to the laws of quantum mechanics, executing quantum gate operations and algorithms.

[0075] Furthermore, the accompanying diagram illustrates how the multi-layered synchronization framework of this patent works collaboratively: 1. Software Synchronization Layer (CQMPI_Barrier): At the judgment point in the middle of the diagram, task synchronization and fault tolerance judgment between computing nodes are implemented.

[0076] 2. Hardware Synchronization Layer (Global Trigger Command + Unified Clock): During the "data upload" phase, a unified hardware command is used to trigger all boards to start up physically in sync, based on the unified timing established previously through an external clock source.

[0077] 3. Data Transmission Synchronization Layer (DMA): During the "data download" and "data upload" phases, DMA and locked memory pages ensure the efficiency and determinism of data transmission. Step 202: The quantum measurement and control system configures the trigger units for each quantum measurement and control board.

[0078] In some embodiments, the quantum measurement and control system described above can configure board trigger units for each quantum measurement and control board. The configured board trigger units are used to enable the corresponding measurement and control board to respond to synchronization trigger commands within a unified clock cycle.

[0079] Step 203: The computing node synchronizes the waveform data distribution and transmission according to the quantum circuit.

[0080] In some embodiments, the aforementioned computing nodes can synchronize waveform data delivery and transmission based on quantum circuits.

[0081] In some optional implementations of certain embodiments, the aforementioned computing node can synchronize waveform data distribution and transmission based on the quantum circuit through the following steps: The first step is for the aforementioned computing nodes to compile the quantum circuits into waveform data and distribute the waveform data to each node.

[0082] In the second step, the aforementioned quantum measurement and control system uses pre-allocated locked memory pages and a DMA mechanism to transfer the waveform data from the classical computer to each quantum measurement and control board. The aforementioned classical computer is the classical node or classical computing node.

[0083] Third, in response to the completion of DMA transfer, each of the aforementioned quantum measurement and control boards immediately updates its status flag through the interrupt service routine and sends an event notification to the aforementioned master node to complete the synchronous data transmission.

[0084] Step 204: In response to confirming that all nodes have completed synchronization within the set timeout window, the master node issues a global trigger command, so that all the aforementioned quantum measurement and control boards can simultaneously emit hardware trigger pulses at a unified clock edge. The aforementioned global trigger command is the same as the aforementioned global hardware trigger command, and will not be described again here.

[0085] In some embodiments, in response to determining that all nodes have completed synchronization within a set timeout window, the master node can issue a global trigger command so that all the aforementioned quantum measurement and control boards can simultaneously emit hardware trigger pulses at a unified clock edge.

[0086] Optionally, the above method may further include the following steps: In response to determining that a node has not synchronized within the timeout window, the master node receives an error code, information about the unsynchronized node, and triggers task rescheduling or error recovery steps. Specifically, Step 1: Within the set timeout window, the master node continuously monitors the synchronization status of all nodes in the communication domain. The master node determines whether there are any unsynchronized nodes by checking whether each node has called the barrier function within the specified time. Step 2: Once a timeout occurs, the CQMPI_Barrier function immediately terminates the waiting state and returns a specific error code (such as CQMPI_ERR_TIMEOUT). At the same time, the function returns a list containing the IDs of all unsynchronized nodes (such as [2,5,7]). Step 3: After receiving the error code and information about the unsynchronized node, the upper-level scheduler (or fault tolerance manager) triggers the corresponding error recovery process according to the preset strategy. The scheduler assesses the severity of the error and the current system state, and chooses to perform task rescheduling or initiate other error recovery steps. Step 4: According to the decision, the quantum measurement and control system will perform specific recovery operations (such as reassigning tasks, isolating faulty nodes, or resetting the system state).

[0087] Step 205: Each quantum measurement and control board executes the corresponding quantum operation based on the synchronization trigger signal.

[0088] In some embodiments, the aforementioned quantum measurement and control boards perform corresponding quantum operations based on synchronization trigger signals.

[0089] In some optional implementations of certain embodiments, the aforementioned quantum measurement and control boards can perform corresponding quantum operations based on a synchronization trigger signal through the following steps: The first step involves each of the aforementioned quantum measurement and control boards reading waveform data in parallel based on a synchronization trigger signal and outputting the data through a radio frequency digital-to-analog converter (RF-DAC) to control the quantum chip to perform computational operations. Specifically, each of the aforementioned quantum measurement and control boards reads waveform data after receiving the synchronization trigger signal.

[0090] The second step is that, in response to the completion of quantum evolution, each of the aforementioned quantum measurement and control boards activates its analog-to-digital converter (ADC) to acquire signals and transmits the data back to the classical computer via a reverse transmission path.

[0091] Step 206: The quantum measurement and control system dynamically and adaptively adjusts the synchronization parameters based on the current coherence time of the qubit.

[0092] In some embodiments, the quantum measurement and control system described above can dynamically and adaptively adjust synchronization parameters based on the coherence time of the current qubit. The coherence time of the current qubit refers to the longest duration for which the quantum state of a specific qubit being operated can remain stable and unaffected by environmental noise under the current experimental environment; it is a key physical parameter for measuring the "lifetime" or "shelf life" of a qubit. Because the quantum states of a qubit (superposition state, entangled state) are extremely fragile, they can interact with the surrounding environment (such as lattice vibrations, electromagnetic noise, etc.) leading to the loss of their quantum properties; this process is called decoherence. The coherence time is the timescale on which the decoherence process occurs.

[0093] In some optional implementations of certain embodiments, the aforementioned execution entity can dynamically and adaptively adjust the synchronization parameters based on the current coherence time of the qubit through the following steps: The first step is for the quantum measurement and control system to dynamically adjust the timeout parameter based on the coherence time of the current qubit.

[0094] The second step, in the feedback control task, is to dynamically optimize the DMA transfer strategy and interrupt response mechanism based on the real-time system load and latency.

[0095] Third, during multiple rounds of task iteration, the aforementioned quantum measurement and control system optimizes the synchronization parameters (i.e., the T_timeout parameter) in real time.

[0096] Figure 4The core system architecture of the quantum measurement and control board was demonstrated. Built on the Xilinx Zynq UltraScale+ RFSoC chip, this board is a key hardware execution unit in the "classical + quantum" heterogeneous computing system, responsible for generating high-precision quantum bit control signals and acquiring readout signals. Its design enables the collaborative operation of the processing system (PS) and programmable logic (PL), and achieves system-level integration and synchronization through a high-speed external interface. It includes the following core modules: 1. Processing System (PS): The board's "classical computing brain" and control center. This is a multi-core processor based on the ARM architecture, running the Linux operating system. Its functions are as follows: running upper-layer software; receiving and parsing quantum circuit instructions from classical computing nodes via the PCIe interface (issued through the CQMPI protocol); task management and scheduling, coordinating various hardware logic modules on the PL side; and data preprocessing and post-processing, performing necessary format conversions or simple calculations before data is transmitted to the PL or after it is received from the PL.

[0097] 2. Programmable Logic (PL): The board's real-time signal processing unit and quantum operation execution unit. Its parallel processing and reconfigurable characteristics are well-suited for implementing timed digital signal processing. Its functions include: waveform generation, executing digital signal processing algorithms to convert command data from the PS into specific digital waveforms; direct digital synthesis, integrating a digital mixer and a numerically controlled oscillator to achieve waveform modulation; data acquisition and processing, performing real-time processing such as digital down-conversion and filtering on the raw data acquired by the ADC; and implementing synchronization logic. The board's trigger unit is a programmable digital logic implemented in the PL, used to respond to global trigger commands.

[0098] 3. DDR Memory (DDR): A high-speed data cache on the board. Serving as shared memory between the PS and PL, it stores large amounts of waveform data, acquired raw data, and intermediate data required for program execution. Its connection to synchronization: By pre-allocating and locking memory pages to optimize the DMA transfer path, waveform data is pre-loaded into DDR before execution, ensuring it can be read immediately upon receiving a trigger signal.

[0099] 4. Radio Frequency Data Converters (RF-DAC / RF-ADC): Connecting classical and quantum computing. RF-DAC: Directly converts the digital waveform generated by the PL (Programmable Logic Controller) into high-frequency microwave analog pulse signals for controlling qubits. RF-ADC: Converts the weak microwave analog signals returned from the resonant cavity into digital signals for further processing by the PL. They are the final executors of synchronous operations, and the synchronization accuracy of their sampling clocks directly determines the time consistency of multi-board collaborative operations.

[0100] 5. PCIe interface: A high-speed data channel between the board and the classic server host. Its functions include: data transmission, handling waveform data distribution and result feedback; its high bandwidth is fundamental for achieving low-latency data synchronization. Control command channel: Control commands such as global trigger instructions are also distributed from the master node to the PS of each board through this interface.

[0101] 6. Clock Input: Receives a reference clock signal from an external, highly stable master clock source. Synchronization Principle: The board uses its low-jitter phase-locked loop circuit to lock all internal clocks (including the sampling clock of the RF-DAC / ADC) to this external reference clock. This mechanism is the core of the hardware synchronization layer, achieving cross-board clock phase alignment across all boards on the time axis and establishing a unified timing reference for all asynchronous signals.

[0102] 7. Trigger Input / Output: Receives and distributes hardware synchronization trigger pulses. Synchronization Principle: Trigger Input: Used to receive global hardware trigger commands. When the board's trigger unit detects this signal at a unified clock edge, it immediately sends a start pulse to the RF-DAC / ADC. Trigger Output: Can be used for cascade synchronization between boards, or to indicate its own status to other devices, enabling more complex synchronization sequences.

[0103] Based on the synchronization method described in this application, the workflow of this board is as follows: 1. Initialization and Data Loading: The PS receives waveform data from the compute node via the PCIe interface. The PS stores the data in the locked memory area of ​​the DDR memory via the DMA controller. The PS configures the trigger unit, waveform generation IP core, etc., in the PL.

[0104] 2. Waiting for Synchronization: After the board completes local configuration, its PS reports "ready" via the CQMPI protocol. All nodes synchronize at the software layer via CQMPI_Barrier.

[0105] 3. Global Triggering and Execution: The master node issues a global hardware trigger command via PCIe. The PS of each board transmits the command to the trigger unit in the PL. The trigger units of all boards simultaneously generate a synchronization pulse at the next unified reference clock edge. This pulse triggers the RF-DAC in parallel to read waveform data and output microwave pulses, thereby controlling the quantum chip to perform calculations.

[0106] 4. Data Feedback: After quantum evolution is complete, a trigger signal starts the RF-ADC to acquire signals. The acquired data is preprocessed by the PL and then fed back to the classical layer for post-processing via DMA and PCIe interfaces.

[0107] Further reference Figure 6As an implementation of the methods shown in the above figures, this disclosure provides some embodiments of a quantum measurement and control multilayer synchronization device for heterogeneous fusion architecture. These device embodiments are similar to... Figure 1 Corresponding to the method embodiments shown, this quantum measurement and control multilayer synchronization device for heterogeneous fusion architecture can be specifically applied to various electronic devices.

[0108] like Figure 6 As shown, a quantum measurement and control multilayer synchronization device 600 for heterogeneous fusion architecture in some embodiments includes: a distribution unit 601, a configuration unit 602, a data distribution unit 603, an instruction distribution unit 604, an execution unit 605, and a parameter adjustment unit 606. The distribution unit 601 is configured to distribute a reference clock signal to each quantum measurement and control board via a master clock source after system startup, so that the quantum measurement and control boards can perform cross-board clock phase alignment; the configuration unit 602 is configured to configure a board trigger unit for each quantum measurement and control board, wherein the configured board trigger unit is used to enable the corresponding measurement and control board to respond to the synchronization trigger command within a unified clock cycle; the data sending unit 603 is configured to enable the computing node to send and transmit waveform data synchronously according to the quantum circuit; the command sending unit 604 is configured to, in response to determining that all nodes have completed synchronization within a set timeout window, the master node sends a global trigger command so that the quantum measurement and control boards can simultaneously emit hardware trigger pulses at a unified clock edge; the execution unit 605 is configured to enable the quantum measurement and control boards to execute corresponding quantum operations based on the synchronization trigger signal; and the parameter adjustment unit 606 is configured to dynamically and adaptively adjust the synchronization parameters according to the coherence time of the current quantum bit.

[0109] It is understandable that the units described in the web page generation device 600 are related to the reference. Figure 1 The steps in the described method correspond to each other. Therefore, the operations, features, and beneficial effects described above for the method also apply to the web page generation apparatus 600 and the units contained therein, and will not be repeated here.

[0110] The following is for reference. Figure 7 It shows a schematic diagram of the structure of an electronic device 700 (e.g., a computing device) suitable for implementing some embodiments of the present disclosure. Figure 7 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this disclosure.

[0111] like Figure 7As shown, the electronic device 700 may include a processing unit 701 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 708 into a random access memory (RAM) 703. The RAM 703 also stores various programs and data required for the operation of the electronic device 700. The processing unit 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0112] Typically, the following devices can be connected to I / O interface 705: input devices 706 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 707 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 708 including, for example, magnetic tapes, hard disks, etc.; and communication devices 709. Communication device 709 allows electronic device 700 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 7 An electronic device 700 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 7 Each box shown can represent a device or multiple devices as needed.

[0113] In particular, according to some embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 709, or installed from storage device 708, or installed from ROM 702. When the computer program is executed by processing device 701, it performs the functions defined in the methods of some embodiments of this disclosure.

[0114] It should be noted that, in some embodiments of this disclosure, the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In some embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0115] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0116] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to: upon system startup, distribute reference clock signals to each quantum measurement and control board via a master clock source for cross-board clock phase alignment; configure board trigger units for each quantum measurement and control board, wherein the configured board trigger units are used to enable the corresponding measurement and control board to respond to synchronization trigger commands within a unified clock cycle; the computing nodes synchronize waveform data transmission and distribution according to the quantum circuit; upon determining that all nodes have completed synchronization within a set timeout window, the master node issues a global trigger command so that each quantum measurement and control board simultaneously emits hardware trigger pulses at a unified clock edge; each quantum measurement and control board performs corresponding quantum operations based on the synchronization trigger signal; and dynamically and adaptively adjust synchronization parameters according to the current coherence time of the qubit.

[0117] Computer program code for performing operations of some embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0118] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0119] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0120] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A multi-layer synchronization method for quantum measurement and control oriented towards heterogeneous fusion architecture, characterized in that, include: In response to the startup of the quantum measurement and control system for heterogeneous fusion architecture, the quantum measurement and control system distributes reference clock signals to each quantum measurement and control board through the master clock source so that each quantum measurement and control board can perform cross-board clock phase alignment. The quantum measurement and control system configures a board trigger unit for each quantum measurement and control board. The configured board trigger unit is used to enable the corresponding measurement and control board to respond to the synchronous trigger command within a unified clock cycle. The computing nodes synchronize waveform data delivery and transmission based on the quantum circuitry. In response to the determination that all nodes have completed synchronization within the set timeout window, the master node issues a global trigger command so that all quantum measurement and control boards can simultaneously emit hardware trigger pulses at the same clock edge; Each quantum measurement and control board executes a corresponding quantum operation based on a synchronization trigger signal; The quantum measurement and control system dynamically and adaptively adjusts the synchronization parameters based on the current coherence time of the qubit.

2. The method according to claim 1, characterized in that, The computing node performs waveform data distribution and transmission synchronization based on the quantum circuit and distribution function, including: The computing nodes compile quantum circuits into waveform data and distribute the waveform data to each node; The quantum measurement and control system transmits the waveform data from the classical computer to each quantum measurement and control board through pre-allocated locked memory pages and DMA mechanism; In response to the completion of DMA transfer, each quantum measurement and control board immediately updates its status flag through an interrupt service routine and sends an event notification to the master node to complete the synchronization data transmission.

3. The method according to claim 1, characterized in that, The method further includes: In response to the determination that a node has not responded synchronously within the timeout window, the master node receives an error code, information on the unsynchronized node, and triggers a task rescheduling or error recovery step.

4. The method according to claim 1, characterized in that, Each of the quantum measurement and control boards executes corresponding quantum operations based on a synchronization trigger signal, including: Each quantum measurement and control board reads waveform data in parallel based on a synchronous trigger signal and outputs it through an RF digital-to-analog converter to control the quantum chip to perform computational operations. In response to the completion of quantum evolution, each quantum measurement and control board activates its analog-to-digital converter to acquire signals and transmits the data back to the classical computer via a reverse transmission path.

5. The method according to claim 4, characterized in that, The dynamic adaptive adjustment of synchronization parameters based on the current coherence time of the qubit includes: The quantum measurement and control system dynamically adjusts the timeout parameter based on the coherence time of the current quantum bit; In feedback control tasks, the DMA transfer strategy and interrupt response mechanism are dynamically optimized based on real-time system load and latency. During multiple rounds of mission iteration, the quantum measurement and control system optimizes the synchronization parameters in real time.

6. A quantum measurement and control multilayer synchronization device for heterogeneous fusion architecture, characterized in that, include: The distribution unit is configured to distribute a reference clock signal to each quantum measurement and control board via a master clock source in response to system startup, so that the quantum measurement and control boards can perform cross-board clock phase alignment. The configuration unit is configured to configure the board triggering unit for each quantum measurement and control board, wherein the configured board triggering unit is used to enable the corresponding measurement and control board to respond to the synchronization triggering command within a unified clock cycle; The data delivery unit is configured to enable computing nodes to synchronize waveform data delivery and transmission based on the quantum circuit. The instruction issuing unit is configured to respond to the determination that all nodes have completed synchronization within the set timeout window, and the master node issues a global trigger instruction so that all quantum measurement and control boards can simultaneously emit hardware trigger pulses at the same clock edge. The execution unit is configured such that each quantum measurement and control board performs a corresponding quantum operation based on a synchronization trigger signal; The parameter adjustment unit is configured to dynamically and adaptively adjust the synchronization parameters based on the coherence time of the current qubit.

7. An electronic device, characterized in that, include: One or more processors; A storage device on which one or more programs are stored; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 5.

8. A computer-readable medium, characterized in that, It stores a computer program thereon, wherein the computer program, when executed by a processor, implements the method as described in any one of claims 1 to 5.

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