Chip low-power-consumption intelligent control method and system based on proportion threshold value

Abstract

The invention discloses a chip low-power-consumption intelligent control method and system based on a proportion threshold value, and relates to the technical field of chip power consumption control. A proportion threshold reference model of each module of the chip is established, a proportion threshold sensing unit is designed to collect chip operation data in real time and identify proportion stress points influencing chip power consumption, and on this basis, chip power supply, clock and load scheduling are dynamically optimized through an intelligent control unit, so that the chip always works in an optimal proportion threshold interval. According to the method, the overall power consumption of the chip can be greatly reduced, the energy efficiency ratio is improved, the core task performance is guaranteed, the chip operation stability is improved, and the method is suitable for power consumption optimization of hardware such as various AI chips, processors and SoC.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design, chip power consumption control, and smart hardware energy efficiency optimization. Specifically, it relates to a low-power intelligent control method and system for chips based on a proportional threshold, which is applicable to the dynamic optimization of power consumption and energy efficiency improvement of various AI chips, processors, SoCs, and other hardware. Background Technology

[0002] Current chip power consumption control mostly adopts fixed threshold, fixed clock frequency reduction, or fixed power supply voltage regulation modes, which have the following core problems in complex multi-tasking scenarios: 1. The power consumption control threshold is fixed, which cannot adapt to the dynamic requirements of different chip loads and different operating scenarios, and is prone to performance loss or power waste. 2. Lack of dynamic perception of the power consumption ratio and load ratio of each module of the chip, making it impossible to identify the key power consumption stress nodes in chip operation, which can easily lead to local overheating and timing violations; 3. Traditional control methods focus on "passive power reduction" and do not utilize the global optimality of the proportional threshold, making it difficult to achieve a dynamic balance between chip performance, power consumption, and stability. 4. The control strategy is disconnected from the chip's operating status, making it impossible to dynamically adjust the power consumption control threshold according to task priority and computing power requirements, thus limiting the energy efficiency optimization effect.

[0003] Existing technologies fail to address the fundamental principle of proportionality in building a low-power intelligent control system for chips based on proportional thresholds, thus failing to fully unleash the energy efficiency potential of chips. Summary of the Invention

[0004] Based on the philosophy of proportionality and the principle of proportional threshold control, this invention proposes a low-power intelligent control method and system for chips based on proportional threshold. By constructing a proportional threshold benchmark model for chip operation, the power consumption ratio stress points during chip operation are dynamically identified, enabling adaptive optimization of chip power supply, clock, and load, thereby significantly reducing chip power consumption and improving energy efficiency.

[0005] This invention includes the following core steps: 1. Establish a proportional threshold benchmark model for each module of the chip, including the proportional relationship between parameters such as load rate, power consumption ratio, clock frequency, supply voltage, and temperature of each module, and define the safe proportional threshold range, the warning proportional threshold range, and the critical proportional threshold. 2. Design a proportional threshold sensing unit to collect real-time operating data such as load, power consumption, frequency, voltage, and temperature of each module of the chip, and form a real-time proportional vector after normalization processing; 3. Compare the real-time scaling vector with the benchmark model, calculate the scaling deviation, and identify the power consumption scaling stress points, i.e., the key module nodes that have a decisive impact on the chip's power consumption, performance, and stability; 4. Design a proportional threshold intelligent control unit to dynamically optimize chip operation based on stress point type: balance computing power scheduling for high-load, high-power modules, and reduce clock frequency and adjust power supply voltage for low-load, idle modules; 5. Design a proportional threshold dynamic calibration unit to periodically update the proportional threshold benchmark model based on chip operating data, adapt to different tasks, different ambient temperatures, and different aging levels, and maintain optimal control performance in the long term. 6. Construct a proportional threshold priority scheduling mechanism to dynamically adjust the proportional threshold of each module according to the task priority, so as to ensure the performance of core tasks while minimizing overall power consumption.

[0006] The system of the present invention includes: a proportional threshold sensing unit, a proportional threshold reference model unit, a proportional stress point identification unit, a proportional threshold intelligent control unit, a proportional threshold dynamic calibration unit, and a priority scheduling unit.

[0007] The beneficial effects of this invention are as follows: 1. Using proportional threshold as the core control basis, dynamic adaptive optimization of chip power consumption is achieved, significantly reducing the overall power consumption of the chip and improving the energy efficiency ratio; 2. Dynamically identify power consumption ratio stress points to avoid localized overheating and timing violations in the chip, thereby improving chip operational stability and lifespan; 3. Achieve a dynamic balance between performance and power consumption based on a proportional threshold, maximizing power consumption reduction while ensuring the performance of core tasks; 4. Adaptable to various chip architectures (AI chips, processors, SoCs, etc.), and can be directly integrated into existing chip design processes without significant hardware modifications; 5. It can be optimized in conjunction with the chip task scheduling system to achieve linkage between task priority and power consumption control, and adapt to complex multi-task operation scenarios. Detailed Implementation

[0008] 1. Power on the chip and initialize it, read the preset proportional threshold benchmark, establish the initial proportional model, and define the safe proportional threshold range, warning proportional threshold range and critical proportional threshold of each module; 2. During chip operation, the proportional threshold sensing unit collects the load rate, power consumption ratio, clock frequency, power supply voltage, and temperature data of each module every fixed clock cycle, and forms a real-time proportional vector after normalization processing. 3. The proportional stress point identification unit compares the real-time proportional vector with the benchmark model, calculates the proportional deviation, and locates the current power consumption proportional stress point: - If the power consumption ratio of a certain module exceeds the safe proportional threshold, it is determined to be a power consumption over-limit stress point; - If the load rate and power consumption ratio of a certain module are severely unbalanced, it is determined to be an energy efficiency imbalance stress point; - If the overall power consumption ratio of the chip exceeds the critical threshold, it is determined to be a global power consumption stress point; 4. The proportional threshold intelligent control unit executes optimization strategies based on the stress point type: - For stress points with excessive power consumption, the clock frequency and supply voltage of the module are reduced proportionally to bring the power consumption back to the safe proportional threshold; - For stress points with energy efficiency imbalance, perform task migration and computing power scheduling to balance the load ratio of each module and improve overall energy efficiency; - For global power consumption stress points, reduce the power consumption threshold of non-core modules proportionally to reduce overall power consumption and ensure the performance of core modules; 5. The proportional threshold dynamic calibration unit updates the proportional threshold benchmark model periodically based on real-time operating data to adapt to scenarios such as chip aging and changes in ambient temperature. 6. The priority scheduling unit dynamically adjusts the proportional threshold of each module according to the task priority to ensure the performance requirements of high-priority tasks while minimizing the power consumption of low-priority tasks.

Claims

1. A chip low-power intelligent control method based on a proportional threshold, characterized in that, Summarize load, temperature, and latency requirements It is converted into a continuous proportional value of [0,1], and the power consumption mode is continuously adjusted according to the multi-level proportional threshold.

2. The method according to claim 1, characterized in that, The multi-level proportional thresholds correspond to deep sleep, shallow sleep, and average sleep. It offers multiple power consumption modes, including balanced operation and high-performance operation.

3. The method according to claim 1, characterized in that, The adjustable parameters include core voltage, clock frequency, and arithmetic units. Power supply strategy for switches and peripherals.

4. The method according to claim 1, characterized in that, Smooth and continuous power consumption mode switching, without step jumps or current fluctuations. glitch.

5. A low-power intelligent control system for chips, characterized in that, The method described in any one of claims 1-4 is based on a proportional threshold. Low-power control methods for values.