Data writing method, data writing system, equipment and storage medium

Abstract

The invention provides a data writing method, a data writing system, equipment and a storage medium, and relates to the technical field of data processing. The first data writing request of the first-level cache unit is received through the first data distribution unit, and the first-level cache data corresponding to the first data writing request is written into the on-chip storage unit through the first data distribution unit; and receiving a second data writing request of the non-first-level cache unit through the second data distribution unit, and writing non-first-level cache data corresponding to the second data writing request into the on-chip storage unit through the second data distribution unit. Therefore, the writing paths of the first-level cache data and the non-first-level cache data are separated, the writing competition between the first-level cache data and the non-first-level cache data is reduced, the delay of writing the first-level cache data into the on-chip storage unit is reduced, the writing efficiency of the first-level cache data is improved, and the writing efficiency of the first-level cache data is improved. Therefore, the data writing performance of the on-chip storage unit is improved.

Description

Technical Field

[0001] This disclosure relates to the field of data processing technology, and in particular to a data writing method, data writing system, device and storage medium. Background Technology

[0002] Cache memory is a temporary storage unit located between the processor and main memory. Although the capacity of a cache unit is smaller than that of main memory, the data transfer speed of a cache unit is much faster than that of main memory. The Level 1 cache unit is directly connected to the processor's data bus, and its data transfer speed is close to that of the processor's data processing speed. The data in the Level 1 cache unit is called Level 1 cache data.

[0003] On-chip memory units are high-speed memory units integrated inside the processor chip, used to store data that is directly accessed by the processor.

[0004] In related technologies, both the L1 cache unit and non-L1 cache units need to write data to the on-chip memory unit in the processor for data processing. The data in the L1 cache unit is called L1 cache data, and the data in the non-L1 cache unit is called non-L1 cache data. The L1 cache data and non-L1 cache data are written to the on-chip memory unit in the processor through a target data distribution unit (e.g., a demultiplexer). The target data distribution unit performs write arbitration processing on the L1 cache data and non-L1 cache data, and then writes the L1 cache data and non-L1 cache data to the on-chip memory unit according to the data writing order after the write arbitration processing. This data writing method increases the write contention of L1 cache data, resulting in increased latency in writing L1 cache data to the on-chip memory unit, reduced write efficiency of L1 cache data, and consequently reduced data write performance of the on-chip memory unit. Summary of the Invention

[0005] To address the problems existing in the aforementioned related technologies, this disclosure provides a data writing method, a data writing system, a device, and a storage medium.

[0006] The first aspect of this disclosure provides a data writing method applied to a data writing system. The data writing system includes a first data distribution unit and a second data distribution unit. The first data distribution unit is a dedicated distribution unit for processing first-level cache data, and the second data distribution unit is a general-purpose distribution unit for processing non-first-level cache data. The method includes: The first data distribution unit receives the first data write request from the first-level cache unit and writes the first-level cache data corresponding to the first data write request into the on-chip storage unit. The second data distribution unit receives a second data write request from a non-Level 1 cache unit and writes the non-Level 1 cache data corresponding to the second data write request into the on-chip storage unit.

[0007] Optionally, the first data distribution unit is configured to bypass the preset arbitration process and write the first-level cache data into the on-chip storage unit; The second data distribution unit is configured to write the non-Level 1 cache data into the on-chip storage unit through the preset arbitration process.

[0008] Optionally, the above-mentioned writing of the first data write request corresponding to the first data cache data to the on-chip storage unit through the first data distribution unit includes: First-level cache data is obtained through the first data distribution unit, and the first-level cache data includes multiple target data. Through the first data distribution unit, multiple target data are sequentially stored into the data buffer in the first data distribution unit according to the acquisition order of the multiple target data; The first data distribution unit writes multiple target data from the data buffer into the on-chip storage unit.

[0009] Optionally, obtaining the first-level cache data through the first data distribution unit includes: The remaining buffer depth of the data buffer is obtained through the first data distribution unit; When the remaining buffer depth is greater than or equal to a preset depth threshold, the first data distribution unit obtains the number of first-level cache data corresponding to the remaining buffer depth. When the remaining buffer depth is less than a preset depth threshold, the first data distribution unit is controlled to stop acquiring level 1 cache data.

[0010] Optionally, writing multiple target data items from the data buffer to on-chip storage includes: For each target data in the data buffer, a target storage block corresponding to the target data is determined in the on-chip storage unit. The on-chip storage unit includes multiple storage blocks for storing data, and the target storage block is the storage block in the on-chip storage unit used to store the target data. Determine at least one target data to be stored for each target storage block. The target data to be stored is the target data in the data buffer that is requested to be written to the target storage block. For each target storage block, according to the storage order of each target data to be stored in the data buffer, each target data to be stored corresponding to the target storage block is written into the target storage block in the on-chip storage unit in sequence.

[0011] Optionally, determining the target storage block corresponding to the target data in the on-chip storage unit includes: Obtain the target storage address of the target data in the on-chip storage unit from the first data write request; Based on the mapping relationship between the target storage address and the storage block in the on-chip storage unit, the storage block corresponding to the target storage address is determined, and the storage block corresponding to the target storage address in the on-chip storage unit is determined as the target storage block corresponding to the target data.

[0012] Optionally, for each target storage block, the above-mentioned method involves sequentially writing the target data to be stored corresponding to the target storage block into the target storage block in the on-chip storage unit according to the storage order of each target data to be stored in the data buffer, including: For each target storage block, a pointer queue corresponding to the target storage block is constructed based on each target data to be stored corresponding to the target storage block; Based on the pointer queue corresponding to each target storage block, for each target storage block, according to the storage order of each target data to be stored in the data buffer, the target data to be stored corresponding to the target storage block is written into the target storage block in the on-chip storage unit in sequence. The pointer queue includes pointer data for each target data to be stored corresponding to the target storage block. The pointer data in the pointer queue is arranged in the same order as the target data to be stored in the data buffer. The pointer data includes the storage address and storage sequence number of the target data to be stored in the data buffer. The size of the storage sequence number is negatively correlated with the storage duration of the target data to be stored in the data buffer.

[0013] Optionally, the above-mentioned construction of a pointer queue corresponding to the target storage block based on each target data to be stored includes: Obtain the storage address and storage sequence number of each target data to be stored in the data buffer; For each target data to be stored, construct pointer data for the target data to be stored based on its storage address and storage sequence number in the data buffer; According to the storage order of each target data to be stored in the data buffer, the pointer data of each target data to be stored is sorted to obtain the pointer queue corresponding to the target storage block.

[0014] Optionally, based on the pointer queues corresponding to each target storage block, for each target storage block, according to the storage order of each target data to be stored in the data buffer, the target data to be stored corresponding to the target storage block is sequentially written into the target storage block in the on-chip storage unit, including: Read the first pointer data in each pointer queue, sort the storage sequence number in each first pointer data in ascending order, and obtain the target sequence; Starting from the first storage index of the target sequence, use the first storage index as the target storage index; Write the target data to be stored corresponding to the target storage sequence number into the target storage block corresponding to the target storage sequence number; In response to the successful writing of the target data to be stored corresponding to the target storage number into the target storage block corresponding to the target storage number, the storage number greater than the target storage number is used as the storage number to be processed. The storage address of the target data to be stored corresponding to the storage number to be processed in the data buffer is shifted one bit in the target direction to obtain the updated target data to be stored corresponding to each target storage block. The target direction is the direction of the storage address of the target data to be stored corresponding to the target storage number. Delete the pointer data corresponding to the target storage sequence number, and decrement the unprocessed storage sequence number in each pointer queue by one to obtain the updated pointer queue. Based on the updated target data to be stored and the updated pointer queue, re-execute the steps of reading the first pointer data in each pointer queue and subsequent data.

[0015] Optionally, the above-described step of writing the target data to be stored corresponding to the target storage sequence number into the target storage block corresponding to the target storage sequence number includes: Identify whether the target storage block corresponding to the target storage sequence number meets the one-time write condition of the target data to be stored corresponding to the target storage sequence number; When the target storage block corresponding to the target storage sequence number does not meet the one-time write condition, the processing of the data to be stored corresponding to the target storage sequence number is paused, and the next storage sequence number of the first storage sequence number in the target sequence is taken as the target storage sequence number. The steps of identifying whether the target storage block corresponding to the target storage sequence number meets the one-time write condition of the target data to be stored corresponding to the target storage sequence number and subsequent steps are re-executed. When the target storage block corresponding to the target storage sequence number meets the one-time write condition, the target data to be stored corresponding to the target storage sequence number is written into the target storage block corresponding to the target storage sequence number.

[0016] Optionally, the above methods also include: When none of the target storage blocks corresponding to each storage sequence number in the target sequence meet the one-time write condition corresponding to each storage sequence number, the writing of data to the on-chip storage unit is stopped.

[0017] Optionally, whether the target storage block corresponding to the storage sequence number meets the one-time write condition for the target data to be stored corresponding to the storage sequence number includes: Get the current write status of the target memory block corresponding to the memory sequence number in the on-chip memory unit; When the current write state of the target storage block is writable, identify whether there is a target number of target storage units in the target storage block. The target number is the number of target storage units requested by the storage sequence number for the target data to be stored. The target storage unit is the storage unit in the target storage block that is currently allowed to write data. When the target number of target storage units exists in the target storage block, determine that the target storage block corresponding to the storage sequence number meets the one-write condition; If the current write state of the target storage block is unwriteable or the target number of target storage cells does not exist in the target storage block, the target storage block corresponding to the storage sequence number is determined to not meet the one-time write condition.

[0018] Optionally, obtaining the current write status of the target memory block corresponding to the memory sequence number in the on-chip memory unit includes: Obtain the write enable signal of the target memory block corresponding to the memory sequence number from the on-chip memory cell; When the write enable signal of the target storage block is the first target enable signal, the current write state of the target storage block is determined to be a writable state, and the first target enable signal is an enable signal that indicates that the target storage block is currently allowed to write data. When the write enable signal of the target storage block is not the first target enable signal, the current write state of the target storage block corresponding to the storage sequence number is determined to be an unwriteable state.

[0019] Optionally, identifying whether the target number of target storage units exists in the target storage block includes: Obtain the write enable signal of each memory cell in the target memory block; When there is a target number of second target enable signals in the write enable signals of each memory cell, it is determined that there is a target number of target memory cells in the target memory block. The second target enable signal is an enable signal that represents the memory cell that is currently allowed to write data. If the target number of second target enable signals are not present in the write enable signals of each memory cell, it is determined that the target number of target memory cells are not present in the target memory block.

[0020] The second aspect of this disclosure provides a data writing system, which includes a first data distribution unit and a second data distribution unit. The first data distribution unit is a dedicated distribution unit for processing first-level cache data, and the second data distribution unit is a general distribution unit for processing non-first-level cache data. The first data distribution unit is used to receive the first data write request from the first-level cache unit and write the first-level cache data corresponding to the first data write request into the on-chip storage unit. The second data distribution unit is used to receive the second data write request from the non-Level 1 cache unit and write the non-Level 1 cache data corresponding to the second data write request into the on-chip storage unit.

[0021] A third aspect of this disclosure provides a computer device comprising: The memory and processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the data writing method described in the first aspect can be implemented.

[0022] A fourth aspect of this disclosure provides a computer-readable storage medium, characterized in that the storage medium stores a computer program, which, when executed by a processor, can implement the data writing method of the first aspect described above.

[0023] The technical solution provided in this disclosure has the following advantages compared with the prior art: In this embodiment, data writing is implemented through a data writing system. The data writing system includes a first data distribution unit for L1 cache data and a second data distribution unit for non-L1 cache data. The first data distribution unit receives a first data write request from the L1 cache unit and writes the L1 cache data corresponding to the first data write request to the on-chip storage unit. The second data distribution unit receives a second data write request from a non-L1 cache unit and writes the non-L1 cache data corresponding to the second data write request to the on-chip storage unit. Therefore, L1 cache data can be written to the on-chip storage unit through the first data distribution unit, and non-L1 cache data can be written to the on-chip storage unit through the second data distribution unit. L1 cache data and non-L1 cache data can be written to the on-chip storage unit through different data distribution units, thus separating the write paths for L1 cache data and non-L1 cache data. L1 cache data can be written to the on-chip storage unit without write arbitration with non-L1 cache data, thereby reducing write contention for L1 cache data, reducing latency in writing L1 cache data to the on-chip storage unit, shortening the time for writing L1 cache data to the on-chip storage unit, improving the write efficiency of L1 cache data, and thus improving the data write performance of the on-chip storage unit.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0026] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a flowchart of a data writing method provided in an embodiment of this disclosure; Figure 2 This is a flowchart of a data writing method provided in an embodiment of this disclosure; Figure 3 This is a flowchart of a data writing method provided in an embodiment of this disclosure; Figure 4 This is a flowchart of a data writing method provided in an embodiment of this disclosure; Figure 5a This is a schematic diagram of the target data to be stored corresponding to a target storage block provided in an embodiment of this disclosure; Figure 5b This is a schematic diagram of the target data to be stored corresponding to another target storage block provided in this embodiment of the disclosure; Figure 6 This is a flowchart of a data writing method provided in an embodiment of this disclosure; Figure 7a This is a schematic diagram of a pointer queue provided in an embodiment of this disclosure; Figure 7b This is a schematic diagram of another pointer queue provided in an embodiment of this disclosure; Figure 8 This is a flowchart of a data writing method provided in an embodiment of this disclosure; Figure 9 This is a flowchart of a data writing method provided in an embodiment of this disclosure; Figure 10 This is a flowchart of a data writing method provided in an embodiment of this disclosure; Figure 11 This is a schematic diagram of the structure of a data writing system provided in an embodiment of this disclosure; Figure 12 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure. Detailed Implementation

[0028] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0029] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0030] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0032] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0033] In related technologies, both the L1 cache unit and non-L1 cache units need to write data to the on-chip memory unit in the processor for data processing. The data in the L1 cache unit is called L1 cache data, and the data in the non-L1 cache unit is called non-L1 cache data. The L1 cache data and non-L1 cache data are written to the on-chip memory unit in the processor through a target data distribution unit (e.g., a demultiplexer). This target data distribution unit performs write arbitration processing on the L1 cache data and non-L1 cache data. For example, the write arbitration process may include steps such as allocating a cache region in Static Random-Access Memory (SRAM), multiplex data arbitration, SRAM data reading, and SRAM region release. Then, according to the data writing order after the write arbitration processing, the L1 cache data and non-L1 cache data are written to the on-chip memory unit. This data writing method increases the write contention of L1 cache data, resulting in increased latency in writing L1 cache data to the on-chip memory unit, reduced write efficiency of L1 cache data, and consequently, reduced data write performance of the on-chip memory unit.

[0034] To better understand the inventive concept of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure will be described below in conjunction with exemplary embodiments.

[0035] The data writing method provided in this disclosure can be applied to a data writing system, which may include a first data distribution unit and a second data distribution unit. The first data distribution unit is a dedicated distribution unit for processing first-level cache data, that is, a data distribution unit specifically for processing first-level cache data. The second data distribution unit is a general distribution unit used to process non-first-level cache data, that is, a data distribution unit specifically used to process non-first-level cache data.

[0036] The Level 1 cache unit can be understood as the L1 cache unit. The L1 cache unit is directly connected to the processor's data bus, and its data transfer speed is close to the processor's data processing speed. The data in the L1 cache unit is called L1 cache data. L1 cache data can be understood as the data that the processor urgently needs.

[0037] Processors can include central processing units (CPUs), graphics processing units (GPUs), and so on.

[0038] Non-L1 cache units can be understood as data processing units (data masters) outside of L1 cache units. Data in non-L1 cache units is called non-L1 cache data. Data transfer rates in non-L1 cache units are lower than those in L1 cache units. Non-L1 cache data can be understood as general data currently needed by the processor.

[0039] For example, non-Level 1 cache units may include Program Data Sequencer (PDS), Program Side Buffer (PSB), Image Signal Processor (ISP), Tiler Frontend (TF), Render Task Unit (RTU), etc.

[0040] On-chip memory can be understood as a high-speed memory unit integrated inside the processor chip, used to store data that the processor can directly access.

[0041] For example, on-chip storage units can be memory execution blocks (MEBs). Figure 1 This is a flowchart of a data writing method provided in an embodiment of this disclosure. This method can be executed by the aforementioned data writing system, which can be installed in a computer device, such as... Figure 1 As shown, the data writing method provided in this embodiment includes the following steps: Step 110: Receive the first data write request from the first-level cache unit through the first data distribution unit, and write the first-level cache data corresponding to the first data write request into the on-chip storage unit through the first data distribution unit.

[0042] In this embodiment of the disclosure, the first data write request can be understood as a request instruction to write the L1 cache data in the L1 cache unit to the on-chip storage unit.

[0043] When a Level 1 cache unit needs to write Level 1 cache data to an on-chip storage unit, the Level 1 cache unit can generate a first data write request and then send the first data write request to the data writing system. The data writing system can receive the first data write request from the Level 1 cache unit through the first data distribution unit, and write the Level 1 cache data corresponding to the first data write request to the on-chip storage unit through the first data distribution unit.

[0044] Step 120: Receive the second data write request from the non-Level 1 cache unit through the second data distribution unit, and write the non-Level 1 cache data corresponding to the second data write request into the on-chip storage unit through the second data distribution unit.

[0045] In this embodiment of the disclosure, the second data write request can be understood as a request instruction to write non-Level 1 cache data in a non-Level 1 cache unit to an on-chip storage unit.

[0046] When a non-Level 1 cache unit needs to write non-Level 1 cache data to an on-chip storage unit, the non-Level 1 cache unit can generate a second data write request and then send the second data write request to the data writing system. The data writing system can receive the second data write request from the non-Level 1 cache unit through the second data distribution unit, and write the non-Level 1 cache data corresponding to the second data write request to the on-chip storage unit through the second data distribution unit.

[0047] It should be noted that the second data distribution unit can be the target data distribution unit in the related technology. After receiving non-Level 1 cache data, the second data distribution unit performs write arbitration processing on multiple data in the non-Level 1 cache data. The write arbitration processing may include steps such as cache area allocation of static random access memory, multi-way data arbitration, SRAM data readout, and SRAM area release. Then, according to the data write order after the write arbitration processing, the multiple data in the non-Level 1 cache data are written to the on-chip storage unit.

[0048] For example, Figure 2 This is a flowchart of a data writing method provided in an embodiment of this disclosure, such as... Figure 2 As shown, Level 1 cache data in the Level 1 cache unit is written to the on-chip storage unit through the first data distribution unit in the data writing system; non-Level 1 cache data in the non-Level 1 cache unit is written to the on-chip storage unit through the second data distribution unit in the data writing system.

[0049] In this embodiment, data writing is implemented through a data writing system. The data writing system includes a first data distribution unit for L1 cache data and a second data distribution unit for non-L1 cache data. The first data distribution unit receives a first data write request from the L1 cache unit and writes the L1 cache data corresponding to the first data write request to the on-chip storage unit. The second data distribution unit receives a second data write request from a non-L1 cache unit and writes the non-L1 cache data corresponding to the second data write request to the on-chip storage unit. Therefore, L1 cache data can be written to the on-chip storage unit through the first data distribution unit, and non-L1 cache data can be written to the on-chip storage unit through the second data distribution unit. L1 cache data and non-L1 cache data can be written to the on-chip storage unit through different data distribution units, thus separating the write paths for L1 cache data and non-L1 cache data. L1 cache data can be written to the on-chip storage unit without write arbitration with non-L1 cache data, thereby reducing write contention for L1 cache data, reducing latency in writing L1 cache data to the on-chip storage unit, shortening the time for writing L1 cache data to the on-chip storage unit, improving the write efficiency of L1 cache data, and thus improving the data write performance of the on-chip storage unit.

[0050] In some embodiments of this disclosure, the first data distribution unit described above can be configured to bypass a preset arbitration process and write first-level cache data into the on-chip storage unit.

[0051] The second data distribution unit described above can be configured to write non-Level 1 cache data into the on-chip storage unit through a preset arbitration process.

[0052] The preset arbitration process can be understood as the write arbitration process in related technologies, which may include steps such as applying for a cache area of ​​static random access memory, multi-way data arbitration, SRAM data reading, and SRAM area release.

[0053] In this embodiment, the second data distribution unit retains the traditional general processing path for processing non-Level 1 cache data. This general processing path includes processes such as allocating a cache region in Static Random Access Memory (SRAM), multi-way data arbitration, SRAM data reading, SRAM region release, and writing the data to the on-chip storage unit. The first data distribution unit, considering the sequential, continuous, and latency-sensitive characteristics of Level 1 cache data, designs a simplified dedicated processing path. This dedicated processing path includes receiving a data write request and directly writing the data to the on-chip storage unit. For Level 1 cache data, the first data distribution unit completely bypasses the preset arbitration process, writing the Level 1 cache data directly to the on-chip storage unit. This separates the write paths for Level 1 cache data and non-Level 1 cache data. Level 1 cache data can be written to the on-chip storage unit without needing to undergo write arbitration with non-Level 1 cache data, thereby reducing write contention for Level 1 cache data, reducing the latency of writing Level 1 cache data to the on-chip storage unit, shortening the time it takes to write Level 1 cache data to the on-chip storage unit, improving the write efficiency of Level 1 cache data, and thus improving the data write performance of the on-chip storage unit.

[0054] In some embodiments of this disclosure, the first data distribution unit writes the L1 cache data corresponding to the first data write request to the on-chip storage unit, and the data writing system can execute... Figure 3 A flowchart of a data writing method is provided, such as Figure 3 As shown, the data writing method provided in this embodiment includes the following steps: Step 310: Obtain the first-level cache data corresponding to the first data write request through the first data distribution unit. The first-level cache data includes multiple target data.

[0055] In this embodiment of the disclosure, after receiving the first data write request from the first-level cache unit through the first data distribution unit, the data writing system can obtain the first-level cache data corresponding to the first data write request through the first data distribution unit. The first-level cache data may include multiple target data.

[0056] In some embodiments, obtaining the first-level cache data corresponding to the first data write request through the first data distribution unit may include S11-S13: S11. Obtain the remaining buffer depth of the data buffer through the first data distribution unit.

[0057] The buffer depth of a data buffer can be understood as the maximum number of data items that the buffer can hold, usually measured in "items" or "strips". For example, a buffer depth of 8 means that a maximum of 8 data items can be temporarily stored.

[0058] The remaining buffer depth of a data buffer can be understood as the number of data items that the buffer can currently hold. For example, a remaining buffer depth of 5 means that 5 data items can be temporarily stored at present.

[0059] S12. When the remaining buffer depth of the data buffer is greater than or equal to a preset depth threshold, the first data distribution unit obtains the number of first-level cache data corresponding to the remaining buffer depth.

[0060] The preset depth threshold can be understood as the minimum buffer depth that is allowed to be stored in the data buffer. The preset depth threshold can be set as needed, such as 1 depth, but there is no limit here.

[0061] When the remaining buffer depth of the data buffer is greater than the preset depth threshold, it means that the current data buffer can store data, and the first data distribution unit can obtain the number of first-level cache data corresponding to the remaining buffer depth.

[0062] For example, if the remaining buffer depth is 5, then the corresponding number of remaining buffer depths is 5.

[0063] S13. When the remaining buffer depth of the data buffer is less than a preset depth threshold, control the first data distribution unit to stop acquiring the first-level cache data corresponding to the first data write request.

[0064] When the remaining buffer depth of the data buffer is less than the preset depth threshold, it indicates that data storage is prohibited in the current data buffer. In this case, the data writing system can control the first data distribution unit to stop acquiring the first-level cache data corresponding to the first data write request.

[0065] Therefore, the acquisition of first-level cache data by the first data distribution unit can be controlled according to the remaining buffer depth of the data buffer. When the remaining buffer depth of the data buffer is greater than or equal to a preset depth threshold, the first data distribution unit acquires the number of first-level cache data corresponding to the remaining buffer depth. When the remaining buffer depth of the data buffer is less than the preset depth threshold, the first data distribution unit is controlled to stop acquiring the first-level cache data corresponding to the first data write request. This can avoid data buffer overload and ensure the data storage performance of the first data distribution unit.

[0066] Step 320: Through the first data distribution unit, the multiple target data are sequentially stored into the data buffer in the first data distribution unit according to the acquisition order of the multiple target data.

[0067] In this embodiment of the disclosure, the first data distribution unit is provided with a data buffer, which is used to temporarily store multiple target data in the first-level cache data. The data buffer is also called a data buffer register.

[0068] After obtaining multiple target data from the first-level cache data through the first data distribution unit, the data writing system can use the first data distribution unit to sequentially store the multiple target data into the data buffer in the first data distribution unit according to the order in which the multiple target data were obtained.

[0069] For example, if multiple target data include three target data, A, B, and C, and the acquisition order of the multiple target data is C, A, and B, then the target data C, A, and B can be stored sequentially in the data buffer of the first data distribution unit.

[0070] Step 330: Write multiple target data from the data buffer into the on-chip storage unit through the first data distribution unit.

[0071] In this embodiment of the present disclosure, after storing multiple target data sequentially into the data buffer in the first data distribution unit, the data writing system can write the multiple target data in the data buffer into the on-chip storage unit through the first data distribution unit.

[0072] Therefore, the first data distribution unit can sequentially store multiple target data items contained in the L1 cache data into the data buffer within the first data distribution unit according to the acquisition order of the target data. Then, the multiple target data items in the data buffer are written to the on-chip storage unit. This achieves ordered storage of multiple target data items in the L1 cache data, ensuring the orderliness of L1 cache data storage, avoiding storage contention among multiple target data items in the L1 cache data, improving the storage efficiency of L1 cache data being stored in the data buffer, and improving the storage performance of the data buffer. Furthermore, the first data distribution unit stores multiple target data items contained in the L1 cache data in order through the buffer, and then writes the multiple target data items in the data buffer to the on-chip storage unit. This buffer allows multiple target data items to be written to the on-chip storage unit directly, eliminating the need for cumbersome and time-consuming write arbitration (such as SRAM area allocation, multi-way data arbitration, etc.), simplifying the process of writing L1 cache data to the on-chip storage unit. This reduces the latency of writing L1 cache data to the on-chip storage unit, shortens the time of writing L1 cache data to the on-chip storage unit, improves the write efficiency of L1 cache data, and thus improves the data write performance of the on-chip storage unit.

[0073] In some embodiments, the data writing system can use a first data distribution unit to sequentially write multiple target data in the data buffer into the on-chip storage unit according to the storage order of the multiple target data in the data buffer.

[0074] Therefore, the first data distribution unit can write the L1 cache data into the on-chip storage unit in an orderly manner according to the storage order of multiple target data in the data buffer, ensuring the orderliness of the L1 cache data writing into the on-chip storage unit, simplifying the process of writing L1 cache data into the on-chip storage unit, thereby reducing the latency of writing L1 cache data into the on-chip storage unit, shortening the time of writing L1 cache data into the on-chip storage unit, improving the writing efficiency of L1 cache data, and thus improving the data writing performance of the on-chip storage unit.

[0075] In other embodiments, the above-described writing of multiple target data from the data buffer to the on-chip storage unit can be performed by the data writing system through the first data distribution unit. Figure 4 A flowchart of a data writing method is provided, such as Figure 4 As shown, the data writing method may include the following steps: Step 410: For each target data in the data buffer, determine the target storage block corresponding to the target data in the on-chip storage unit. The on-chip storage unit includes multiple storage blocks for storing data, and the target storage block is the storage block in the on-chip storage unit used to store the target data.

[0076] In this embodiment of the disclosure, the on-chip storage unit includes multiple storage blocks, which are used to store data written to the on-chip storage unit.

[0077] For each target data in the data buffer, the data writing system can determine the target storage block corresponding to the target data in the on-chip storage unit through the first data distribution unit. The target storage block can be understood as the storage block in the on-chip storage unit where the target data requests storage.

[0078] In some embodiments, the first data write request may include the storage address of each target data in the on-chip storage unit, and there is a mapping relationship between the storage address and the storage block in the on-chip storage unit, that is, each storage address corresponds to a storage block in the on-chip storage unit.

[0079] For each target data in the data buffer, the target storage address of the target data in the on-chip storage unit can be obtained from the first data write request through the first data distribution unit; based on the mapping relationship between the target storage address and the storage block in the on-chip storage unit, the storage block corresponding to the target storage address is determined, and the storage block corresponding to the target storage address in the on-chip storage unit is determined as the target storage block corresponding to the target data.

[0080] Therefore, based on the target storage address of the target data in the L1 cache in the on-chip storage unit, the target storage block corresponding to the target data in the on-chip storage unit can be determined, and the target storage block corresponding to each target data in the on-chip storage unit can be accurately determined.

[0081] Step 420: Determine at least one target data to be stored for each target storage block. The target data to be stored is the target data in the data buffer that is requested to be written to the target storage block.

[0082] For example, Figure 5a This is a schematic diagram of the target data to be stored corresponding to a target storage block provided in an embodiment of this disclosure, such as... Figure 5a As shown, the target storage blocks corresponding to the multiple target data in the data buffer include target storage block A and target storage block B; The data buffer includes target data to be stored 501, target data to be stored 502, target data to be stored 503, target data to be stored 504, target data to be stored 505, and target data to be stored 506; The target data to be stored corresponding to target storage block A includes target data 501 and target data 502. The target data to be stored corresponding to target storage block B includes target data 503, target data 504, target data 505, and target data 506.

[0083] Step 430: For each target storage block, according to the storage order of each target data to be stored in the data buffer, write each target data to be stored corresponding to the target storage block into the target storage block in the on-chip storage unit in sequence.

[0084] Therefore, when the number of target storage blocks corresponding to multiple target data in the data buffer is greater than 1, the target data to be stored corresponding to each target storage block can be written into the target storage block in the on-chip storage unit in an orderly manner. This can reduce the write competition between the target data to be stored corresponding to the target storage block, shorten the time for multiple target data in the L1 cache to be written into the target storage block in the on-chip storage unit, reduce the latency of writing L1 cache data into the on-chip storage unit, improve the write efficiency of L1 cache data, and thus improve the data write performance of the on-chip storage unit.

[0085] In some embodiments, for each target storage block, the target data to be stored is sequentially written into the target storage block in the on-chip storage unit according to the storage order of each target data to be stored in the data buffer. The data writing system can perform this operation through the first data writing unit. Figure 6 A flowchart of a data writing method is provided, such as Figure 6 As shown, the data writing method may include the following steps: Step 610: For each target storage block, construct a pointer queue corresponding to the target storage block based on the target data to be stored corresponding to the target storage block.

[0086] Step 620: Based on the pointer queues corresponding to each target storage block, for each target storage block, according to the storage order of each target data to be stored in the data buffer, write each target data to be stored corresponding to the target storage block into the target storage block in the on-chip storage unit in sequence. The pointer queue includes pointer data for each target data to be stored corresponding to the target storage block. The order of pointer data in the pointer queue is the same as the storage order of the target data to be stored corresponding to the target storage block in the data buffer. The pointer data includes the storage address and storage sequence number of the target data to be stored in the data buffer. The size of the storage sequence number is negatively correlated with the storage duration of the target data to be stored in the data buffer.

[0087] In this embodiment of the disclosure, the first data distribution unit may include a data control module. When the number of target storage blocks corresponding to multiple target data in the data buffer is greater than one, for each target storage block, the data writing system can use the data control module in the first data writing unit to construct a pointer queue corresponding to the target storage block based on each target data to be stored corresponding to the target storage block. Then, based on the pointer queues corresponding to each target storage block, for each target storage block, according to the storage order of each target data to be stored in the data buffer, the target data to be stored corresponding to the target storage block is sequentially written into the target storage block in the on-chip storage unit.

[0088] The target data to be stored corresponding to the target storage block can be understood as the target data to be written into the target storage block.

[0089] A pointer queue (ptr queue) can be understood as a data queue composed of multiple pointer data arranged in a certain order.

[0090] The pointer queue corresponding to the target storage block can include pointer data of each target data to be stored corresponding to the target storage block. The order of the pointer data in the pointer queue is the same as the storage order of the target data to be stored corresponding to the target storage block in the data buffer.

[0091] The pointer data to the target data to be stored can include the storage address and storage sequence number of the target data in the data buffer. A one-to-one correspondence can be established between the pointer data and the target data in the data buffer. The size of the storage sequence number is negatively correlated with the storage duration of the target data in the data buffer; the longer the storage duration, the smaller the storage sequence number; conversely, the shorter the storage duration, the larger the storage sequence number.

[0092] For example, such as Figure 5a As shown, the data buffer includes target data to be stored 501, target data to be stored 502, target data to be stored 503, target data to be stored 504, target data to be stored 505, and target data to be stored 506; the storage order of the six target data to be stored in the data buffer is 501, 502, 503, 504, 505, and 506, then the storage sequence numbers of the target data to be stored 501, 502, 503, 504, 505, and 506 in the data buffer are 1, 2, 3, 4, 5, and 6; The order of the target data to be stored corresponding to target storage block A is target data to be stored 501, target data to be stored 502; The order of the target data to be stored corresponding to target storage block B is target data to be stored 503, target data to be stored 504, target data to be stored 505, and target data to be stored 506; Figure 7a This is a schematic diagram of a pointer queue provided in an embodiment of this disclosure, such as... Figure 7a As shown, pointer queue 710 is Figure 5a The pointer queue corresponding to target memory block A, pointer queue 720 is... Figure 5a The pointer queue corresponding to target storage block B in the middle; Pointer data 711 is the pointer data of target data 501 to be stored, and pointer data 712 is the pointer data of target data 502 to be stored. Since the storage order of target data 501 and 502 in the data buffer is 501 and 502 respectively, the arrangement order of pointer data 711 and pointer data 712 in pointer queue 710 is 711 and 712. The pointer queue 710 corresponding to target storage block A contains pointer data 711 and pointer data 712. The storage sequence number in pointer data 711 is 1, and the storage sequence number in pointer data 712 is 2. Pointer data 721 is the pointer data for target data 503 to be stored, pointer data 722 is the pointer data for target data 504 to be stored, pointer data 723 is the pointer data for target data 505 to be stored, and pointer data 724 is the pointer data for target data 506 to be stored. The storage order of target data 503, 504, 505, and 506 in the data buffer is 503, 504, 505, and 506. Therefore, the order of pointer data 721, 722, 723, and 724 in pointer queue 720 is 721, 722, 723, and 724. The pointer queue 720 corresponding to target storage block B contains pointer data 721, pointer data 722, pointer data 723, and pointer data 724. The storage sequence number in pointer data 721 is 3; the storage sequence number in pointer data 722 is 4; the storage sequence number in pointer data 723 is 5; and the storage sequence number in pointer data 724 is 6.

[0093] Therefore, for each target storage block, a pointer queue can be constructed based on the target data to be stored corresponding to that target storage block. Based on this pointer queue, for each target storage block, the target data to be stored is sequentially written into the target storage block in the on-chip storage unit according to the storage order of the target data in the data buffer. This allows for the direct and orderly writing of the target data to the target storage block for each target storage block, shortening the time required to write multiple target data to the target storage block in the on-chip storage unit, reducing latency, and improving the efficiency of writing multiple target data from the L1 cache to the target storage block in the on-chip storage unit, thereby improving the data write performance of the on-chip storage unit.

[0094] In some embodiments, the above-described pointer queue corresponding to the target storage block is constructed based on each target data to be stored corresponding to the target storage block, and the data writing system may include S21-S23 through the first data writing unit: S21. Obtain the storage address and storage sequence number of each target data to be stored in the data buffer.

[0095] S22. For each target data to be stored, construct pointer data for the target data to be stored based on its storage address and storage sequence number in the data buffer.

[0096] S23. Sort the pointer data of each target data to be stored according to the storage order of each target data in the data buffer to obtain the pointer queue corresponding to the target storage block.

[0097] Therefore, pointer data for each target data to be stored can be constructed based on its storage address and storage sequence number in the data buffer. Then, the pointer data for each target data to be stored can be sorted according to its storage order in the data buffer to construct a pointer queue corresponding to the target storage block. The pointer queue can be constructed accurately. Then, for each target storage block, each target data to be stored corresponding to that target storage block can be directly and orderly written into the target storage block in the on-chip storage unit. This can shorten the time for writing multiple target data into the target storage block in the on-chip storage unit, reduce the latency of writing multiple target data into the target storage block in the on-chip storage unit, improve the efficiency of writing multiple target data in the L1 cache into the target storage block in the on-chip storage unit, and thus improve the data writing performance of the on-chip storage unit.

[0098] In some embodiments, based on the pointer queues corresponding to each target storage block, for each target storage block, according to the storage order of each target data to be stored in the data buffer, the target data to be stored corresponding to the target storage block is sequentially written into the target storage block in the on-chip storage unit. The data writing system can perform this through the first data writing unit. Figure 8 A flowchart of a data writing method is provided, such as Figure 8 As shown, the data writing method may include the following steps: Step 810: Read the first pointer data in each pointer queue, sort the storage sequence number in each first pointer data in ascending order, and obtain the target sequence.

[0099] For example, such as Figure 7a As shown, the first pointer data 711 in the pointer queue 710 is read through the first data writing unit, and the first pointer data 721 in the pointer queue 720 is read. The storage sequence number in pointer data 711 is 1, and the storage sequence number in pointer data 721 is 3. The storage sequence numbers in pointer data 711 and pointer data 721 are sorted from small to large, and the target sequence X1 is 1 and 3.

[0100] Step 820: Starting from the first storage index of the target sequence, use the first storage index as the target storage index.

[0101] Step 830: Write the target data to be stored corresponding to the target storage sequence number into the target storage block corresponding to the target storage sequence number.

[0102] For example, the target data to be stored corresponding to the target storage sequence number can be placed on the data bus, waiting for the data control module in the first data distribution unit to handshake with the on-chip storage unit. After the data control module in the first data distribution unit and the on-chip storage unit successfully handshake, the target data to be stored on the data bus is written into the target storage block corresponding to the target storage sequence number.

[0103] For example, continue with Figure 7a For example, Figure 7a As shown, if the target storage sequence number is storage sequence number 3, the target data 503 to be stored corresponding to storage sequence number 3 can be written into the target storage block B.

[0104] Step 840: In response to the successful writing of the target data to be stored corresponding to the target storage number into the target storage block corresponding to the target storage number, the storage number greater than the target storage number is taken as the storage number to be processed. The storage address of the target data to be stored corresponding to the storage number to be processed in the data buffer is shifted one bit in the target direction to obtain the updated target data to be stored corresponding to each target storage block. The target direction is the direction of the storage address of the target data to be stored corresponding to the target storage number.

[0105] Step 850: Delete the pointer data corresponding to the target storage sequence number, and decrement the unprocessed storage sequence number in each pointer queue by one to obtain the updated pointer queue.

[0106] Step 860: Based on the updated target data to be stored and the updated pointer queue, re-execute the steps of reading the first pointer data in each pointer queue and subsequent data.

[0107] For example, continue with Figure 7a For example, Figure 7a As shown, if the target storage sequence number is storage sequence number 3, in response to the successful writing of the target data 503 to be stored corresponding to storage sequence number 3 into the target storage block B corresponding to storage sequence number 3, the storage sequence number greater than storage sequence number 3 is used as the storage sequence number to be processed, that is, the storage sequence number to be processed includes storage sequence number 4, storage sequence number 5, and storage sequence number 6. The storage addresses of the target data to be stored corresponding to the storage sequence number to be processed in the data buffer are shifted one position in the target direction. The target data to be stored corresponding to the other storage sequence numbers remain unchanged. The target direction is the direction of the storage address of the target data 503 to be stored corresponding to storage sequence number 3. That is, the storage address of the target data 504 to be stored corresponding to storage sequence number 4 is shifted one position in the direction of the storage address of the target data 503, the storage address of the target data 505 to be stored corresponding to storage sequence number 5 is shifted one position in the direction of the storage address of the target data 503, and the storage address of the target data 506 to be stored corresponding to storage sequence number 6 is shifted one position in the direction of the storage address of the target data 503. This yields the updated target data to be stored for each target storage block. Figure 5b This is a schematic diagram of the target data to be stored corresponding to a target storage block provided in an embodiment of this disclosure, such as... Figure 5b As shown, the updated target data to be stored corresponding to target storage block A includes target data 501 and target data 502, arranged in the order of target data 501 and target data 502; the updated target data to be stored corresponding to target storage block B includes target data 504, target data 505 and target data 506, arranged in the order of target data 504, target data 505 and target data 506. Delete the pointer data 721 corresponding to storage sequence number 3. The pointer data corresponding to other storage sequence numbers in the pointer queue, except for the storage sequence numbers to be processed, remain unchanged. Since storage sequence numbers 1 and 2 in pointer queue 710 are both less than 3, there is no need to change the storage sequence numbers in pointer queue 710. The updated pointer queue corresponding to pointer queue 710 is pointer queue 730. The target data to be stored corresponding to each pointer data in pointer queue 710 remains unchanged. In pointer queue 730, pointer data 711 still corresponds to target data 501 to be stored, and pointer data 712 still corresponds to target data 502 to be stored. Decrement the storage index 4 in pointer queue 720 by one, changing storage index 4 to storage index 3. Decrement the storage index 5 in pointer queue 720 by one, changing storage index 5 to storage index 4. Decrement the storage index 6 in pointer queue 720 by one, changing storage index 6 to storage index 5, to obtain the updated pointer queue 740 corresponding to pointer queue 720. like Figure 7b As shown, Figure 7b This is a schematic diagram of a pointer queue provided in an embodiment of this disclosure, such as... Figure 7b As shown, Figure 7bThe updated pointer queue 730 corresponding to pointer queue 710 and the updated pointer queue 740 corresponding to pointer queue 720 are shown in the figure; Due to the above-mentioned moving and decrementing operations, pointer data 711 in pointer queue 730 still corresponds to target data 501 to be stored, and pointer data 712 still corresponds to target data 502 to be stored; pointer data 722 in pointer queue 740 still corresponds to target data 504 to be stored, pointer data 723 still corresponds to target data 505 to be stored, and pointer data 724 still corresponds to target data 506 to be stored. Based on the updated target data to be stored and the updated pointer queues 730 and 740 corresponding to each target storage block, the steps of reading the first pointer data in each pointer queue and subsequent steps are re-executed.

[0108] In this embodiment, for each target storage block, a pointer queue is constructed based on at least one target data to be stored corresponding to the target storage block. Based on the pointer queues for each target storage block, the target data to be stored for each target storage block is sequentially written into the target storage block in the on-chip storage unit according to the storage order of the target data in the data buffer. This shortens the time for writing L1 cache data to the on-chip storage unit, reduces the latency of writing L1 cache data to the on-chip storage unit, improves the efficiency of writing L1 cache data to the on-chip storage unit, and thus improves the data write performance of the on-chip storage unit.

[0109] In some embodiments, the above-described writing of the target data to be stored corresponding to the target storage sequence number into the target storage block corresponding to the target storage sequence number can be performed by the data writing system through the first data writing unit. Figure 9 A flowchart of a data writing method is provided, such as Figure 9 As shown, the data writing method may include the following steps: Step 910: Identify whether the target storage block corresponding to the target storage sequence number meets the one-time write condition of the target data to be stored corresponding to the target storage sequence number.

[0110] The write condition for the target data to be stored can be understood as the condition that allows the target data to be written into the target storage block corresponding to the target data in one go.

[0111] For example, continue with Figure 7a For example, Figure 7a As shown, the target sequence X1 is 1 and 3; starting from the first storage number 1 of the target sequence, the first storage number 1 is used as the target storage number, and it is identified whether the target storage block A corresponding to storage number 1 meets the one-time write condition of the target data 501 to be stored corresponding to storage number 1.

[0112] Step 920: When the target storage block corresponding to the target storage sequence number does not meet the one-time write condition, pause the processing of the data to be stored corresponding to the target storage sequence number, take the next storage sequence number of the first storage sequence number in the target sequence as the target storage sequence number, and re-execute the steps in step 910 of identifying whether the target storage block corresponding to the target storage sequence number meets the one-time write condition of the target data to be stored corresponding to the target storage sequence number and the subsequent steps.

[0113] For example, continue with Figure 7a For example, Figure 7a As shown, the target sequence X1 is 1 and 3. Starting from the first storage number 1 of the target sequence, the first storage number 1 is used as the target storage number. It is identified whether the target storage block A corresponding to storage number 1 meets the one-time write condition of the target data 501 to be stored corresponding to storage number 1. When the target storage block A does not meet the one-time write condition of the target data 501 to be stored corresponding to storage number 1, the processing of the data 501 to be stored corresponding to storage number 1 can be paused. The next storage number 3 after the first storage number 1 in the target sequence is used as the target storage number. Then it is identified whether the target storage block B corresponding to storage number 3 meets the one-time write condition of the target data 503 to be stored corresponding to storage number 3.

[0114] Step 930: When the target storage block corresponding to the target storage sequence number meets the one-time write condition, write the target data to be stored corresponding to the target storage sequence number into the target storage block corresponding to the target storage sequence number.

[0115] For example, when the target storage block corresponding to the target storage sequence number meets the write condition, the target data to be stored corresponding to the target storage sequence number can be placed on the data bus and wait for the data control module in the first data distribution unit to handshake with the on-chip storage unit. After the data control module in the first data distribution unit and the on-chip storage unit successfully handshake, the target data to be stored on the data bus is written into the target storage block corresponding to the target storage sequence number.

[0116] For example, continue with Figure 7a For example, Figure 7a As shown, if the target storage sequence number is storage sequence number 3, when the target storage block B corresponding to storage sequence number 3 satisfies the one-time write condition of the target data 503 to be stored corresponding to storage sequence number 3, the target data 503 to be stored corresponding to storage sequence number 3 can be written into the target storage block B.

[0117] In this embodiment, for each target storage block, a pointer queue is constructed based on at least one target data to be stored corresponding to the target storage block. Based on the pointer queues for each target storage block, when the target storage block meets the one-time write condition for the target data to be stored, the target data to be stored is sequentially written into the target storage block in the on-chip storage unit according to the storage order of the target data in the data buffer. Each target data only requires one write operation to be written into the target storage block. Therefore, the success rate of writing multiple target data from the L1 cache into the target storage block in the on-chip storage unit can be improved, the time for writing L1 cache data to the on-chip storage unit can be shortened, the latency of writing L1 cache data to the on-chip storage unit can be reduced, and the efficiency of writing L1 cache data to the on-chip storage unit can be improved, thereby improving the data write performance of the on-chip storage unit.

[0118] In some embodiments of this disclosure, when none of the target storage blocks corresponding to each storage sequence number in the target sequence meet the one-time write condition corresponding to each storage sequence number, writing data to the on-chip storage unit can be stopped.

[0119] For example, such as Figure 7a As shown, the target sequence X1 is 1 and 3. If the target storage block corresponding to storage sequence number 1 in the target sequence does not meet the one-time write condition corresponding to storage sequence number 1, and the target storage block corresponding to storage sequence number 3 does not meet the one-time write condition corresponding to storage sequence number 3, then writing data to the on-chip storage unit can be stopped.

[0120] Therefore, data will only be written to the on-chip storage unit when at least one target storage block in the target sequence meets the corresponding write condition. This ensures that each target data to be stored can be written to the target storage block in the on-chip storage unit with only one write operation. This can improve the success rate of writing multiple target data in the L1 cache to the target storage block in the on-chip storage unit, shorten the time of writing L1 cache data to the on-chip storage unit, reduce the latency of writing L1 cache data to the on-chip storage unit, improve the efficiency of writing L1 cache data to the on-chip storage unit, and thus improve the data writing performance of the on-chip storage unit.

[0121] In some embodiments, the data writing system can execute the above-mentioned identification of whether the target storage block corresponding to the storage sequence number meets the one-time write condition of the target data to be stored corresponding to the storage sequence number. Figure 10 A flowchart of a data writing method is provided, such as Figure 10 As shown, the data writing method provided in this embodiment includes the following steps: Step 1010: Obtain the current write status of the target memory block corresponding to the memory sequence number in the on-chip memory unit.

[0122] The data writing system can obtain the current write status of the target storage block corresponding to the storage sequence number in the on-chip storage unit through the first data writing unit.

[0123] In one example embodiment, obtaining the current write status of the target storage block corresponding to the storage sequence number may include S31-S33: S31. Obtain the write enable signal of the target memory block corresponding to the memory sequence number from the on-chip memory cell.

[0124] The data writing system can obtain the write enable signal of the target memory block corresponding to the memory sequence number from the on-chip memory unit through the first data writing unit.

[0125] The write enable signal of the target memory block can be understood as a flag signal indicating whether data is currently allowed to be written to the target memory block. For example, the write enable signal can be 1 or 0.

[0126] For example, the write enable signal for the target memory block can be us wr enable.

[0127] S32. When the write enable signal of the target storage block is the first target enable signal, determine that the current write state of the target storage block is a writable state, and the first target enable signal is an enable signal that indicates that the target storage block is currently allowed to write data.

[0128] The current write-ready state of the target storage block can be understood as the target storage block currently allowing data to be written.

[0129] The first target enable signal can be understood as an enable signal that allows data to be written to the target memory block. For example, the first target enable signal can be 1.

[0130] S33. When the write enable signal of the target storage block is not the first target enable signal, determine that the current write state of the target storage block corresponding to the storage sequence number is an unwriteable state.

[0131] The current write-unwritable state of the target storage block can be understood as the target storage block currently prohibiting data from being written to.

[0132] Therefore, the current write state of the target storage block can be determined by the write enable signal of the target storage block, and the current write state of the target storage block can be accurately identified.

[0133] Step 1020: When the current write state of the target storage block is writable, identify whether there is a target number of target storage units in the target storage block. The target number is the number of target storage units requested by the storage sequence number for the target data to be stored. The target storage unit is the storage unit in the target storage block that is currently allowed to write data.

[0134] Each storage block in the on-chip storage unit may include multiple storage units, and each storage unit can be used to store data.

[0135] The additional information for the target data to be stored may include the target number of target storage units requested. A target storage unit can be understood as a storage unit within the target storage block that is currently allowed to write data.

[0136] For example, the target number of target storage units requested for the target data to be stored can be represented by the target control signal wrmask. If the flag bits of wrmask are 1, 1, it means that the target number of target storage units requested for the target data to be stored is 2; if the flag bits of wrmask are 1, 1, 1, it means that the target number of target storage units requested for the target data to be stored is 3.

[0137] For example, if the number of target storage units requested by the storage sequence number is 3, then it is necessary to identify whether there are 3 target storage units in the target storage block.

[0138] In one example embodiment, identifying whether the target number of target storage cells exists in the target storage block may include S41-S43: S41. Obtain the write enable signal of each memory cell in the target memory block.

[0139] The write enable signal of a memory cell can be understood as a flag signal indicating whether data is currently allowed to be written to the memory cell. For example, the write enable signal can be 1 or 0.

[0140] S42. When there is a target number of second target enable signals in the write enable signals of each memory cell, it is determined that there is a target number of target memory cells in the target memory block. The second target enable signal is an enable signal that represents the memory cell currently allowed to write data.

[0141] The second target enable signal of a storage cell can be understood as an enable signal that indicates that data is currently allowed to be written to the storage cell. For example, the second target enable signal can be 1.

[0142] S43. When there is no target number of second target enable signals in the write enable signals of each memory cell, it is determined that there are no target number of target memory cells in the target memory block.

[0143] Therefore, the existence of the target number of target storage cells in the target storage block can be determined by the write enable signal of each storage cell in the target storage block, and the existence of the target number of target storage cells in the target storage block can be accurately identified.

[0144] Step 1030: When the target number of target storage units exists in the target storage block, determine that the target storage block corresponding to the storage sequence number satisfies the one-time write condition of the target data to be stored corresponding to the storage sequence number.

[0145] Step 1040: When the current write state of the target storage block is unwriteable or there are no target storage units of the target number in the target storage block, determine that the target storage block corresponding to the storage sequence number does not meet the one-time write condition of the target data to be stored corresponding to the storage sequence number.

[0146] Therefore, when the current write state of the target storage block is writable and the target number of target storage units exist in the target storage block, it can be determined that the target storage block meets the one-time write condition. This can accurately determine whether the target storage block meets the one-time write condition, thereby improving the success rate of writing multiple target data from the L1 cache data into the target storage block in the on-chip storage unit, shortening the time for writing L1 cache data into the on-chip storage unit, reducing the latency of writing L1 cache data into the on-chip storage unit, improving the efficiency of writing L1 cache data into the on-chip storage unit, and thus improving the data writing performance of the on-chip storage unit.

[0147] Figure 11 This is a schematic diagram of the structure of a data writing system provided in an embodiment of this disclosure, as shown below. Figure 11 As shown, the data writing system 1100 may include a first data distribution unit 1110 and a second data distribution unit 1120. The first data distribution unit is a dedicated distribution unit for processing L1 cache data, and the second data distribution unit is a general-purpose distribution unit for processing non-L1 cache data. The first data distribution unit 1110 is used to receive a first data write request from the first level cache unit and write the first level cache data corresponding to the first data write request into the on-chip storage unit. The second data distribution unit 1120 is used to receive a second data write request from a non-Level 1 cache unit and to write the non-Level 1 cache data corresponding to the second data write request into the on-chip storage unit.

[0148] The data writing system provided in this disclosure can implement the methods of any of the above embodiments, and its execution method and beneficial effects are similar, so they will not be described again here.

[0149] This disclosure also provides a computer device, which includes a processor and a memory, wherein the memory stores a computer program. When the computer program is executed by the processor, it can implement the methods of any of the above embodiments. The execution method and beneficial effects are similar, and will not be described again here.

[0150] In other embodiments, the computer device may include the data writing system described above. The data writing system can be used to implement the methods of any of the above embodiments, and the execution method and beneficial effects are similar, so they will not be described again here.

[0151] The computer device in this disclosure can be understood as any device with processing and computing capabilities. This device may include, but is not limited to, mobile terminals such as smartphones, laptops, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), and wearable devices, as well as fixed electronic devices such as digital TVs, desktop computers, and smart home devices.

[0152] Figure 12 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure, such as... Figure 12 As shown, the computer device 1200 may include a processor 1210 and a memory 1220. The memory 1220 stores a computer program 1221. When the computer program 1221 is executed by the processor 1210, it can implement the method provided in any of the above embodiments. The execution mode and beneficial effects are similar and will not be described again here.

[0153] Of course, for the sake of simplicity, Figure 12 Only some of the components of the computer device 1200 relevant to the present invention are shown in this illustration; components such as buses, input / output interfaces, input devices, and output devices are omitted. In addition, the computer device 1200 may include any other suitable components depending on the specific application.

[0154] This disclosure provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the methods of any of the above embodiments. The execution method and beneficial effects are similar, and will not be described again here.

[0155] The aforementioned computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0156] The computer program described above can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer device, partially on the user's device, as a standalone software package, partially on the user's computer device and partially on a remote computer device, or entirely on a remote computer device or server.

[0157] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0158] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0159] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data writing method, characterized in that, The method is applied to a data writing system, which includes a first data distribution unit and a second data distribution unit. The first data distribution unit is a dedicated distribution unit for processing first-level cache data, and the second data distribution unit is a general-purpose distribution unit for processing non-first-level cache data. The first data distribution unit receives a first data write request from the first-level cache unit and writes the first-level cache data corresponding to the first data write request into the on-chip storage unit. The second data distribution unit receives a second data write request from a non-Level 1 cache unit and writes the non-Level 1 cache data corresponding to the second data write request into the on-chip storage unit.

2. The method according to claim 1, characterized in that, The first data distribution unit is configured to bypass the preset arbitration process and write the first-level cache data into the on-chip storage unit; The second data distribution unit is configured to write the non-Level 1 cache data into the on-chip storage unit through the preset arbitration process.

3. The method according to claim 1, characterized in that, The step of writing the first-level cache data corresponding to the first data write request to the on-chip storage unit through the first data distribution unit includes: The first-level cache data is obtained through the first data distribution unit, and the first-level cache data includes multiple target data. The first data distribution unit stores the multiple target data sequentially into the data buffer in the first data distribution unit according to the acquisition order of the multiple target data. The first data distribution unit writes the plurality of target data in the data buffer into the on-chip storage unit.

4. The method according to claim 3, characterized in that, The step of obtaining the first-level cache data through the first data distribution unit includes: The remaining buffer depth of the data buffer is obtained through the first data distribution unit; When the remaining buffer depth is greater than or equal to a preset depth threshold, the first data distribution unit obtains the number of first-level cache data corresponding to the remaining buffer depth. When the remaining buffer depth is less than the preset depth threshold, the first data distribution unit is controlled to stop acquiring the first-level cache data.

5. The method according to claim 3, characterized in that, The step of writing the plurality of target data in the data buffer into the on-chip storage unit includes: For each target data in the data buffer, a target storage block corresponding to the target data is determined in the on-chip storage unit. The on-chip storage unit includes multiple storage blocks for storing data, and the target storage block is the storage block in the on-chip storage unit used to store the target data. Determine at least one target data to be stored corresponding to each target storage block, wherein the target data to be stored is the target data in the data buffer that is requested to be written into the target storage block; For each target storage block, according to the storage order of each target data to be stored in the data buffer, each target data to be stored corresponding to the target storage block is sequentially written into the target storage block in the on-chip storage unit.

6. The method according to claim 5, characterized in that, Determining the target storage block corresponding to the target data in the on-chip storage unit includes: Obtain the target storage address of the target data in the on-chip storage unit from the first data write request; Based on the mapping relationship between the target storage address and the storage block in the on-chip storage unit, the storage block corresponding to the target storage address is determined, and the storage block corresponding to the target storage address in the on-chip storage unit is determined as the target storage block corresponding to the target data.

7. The method according to claim 5, characterized in that, For each target storage block, writing the target data to be stored sequentially into the target storage block in the on-chip storage unit according to the storage order of the target data to be stored in the data buffer includes: For each target storage block, a pointer queue corresponding to the target storage block is constructed based on each target data to be stored corresponding to the target storage block; Based on the pointer queues corresponding to each target storage block, for each target storage block, according to the storage order of each target data to be stored in the data buffer, the target data to be stored corresponding to the target storage block is sequentially written into the target storage block in the on-chip storage unit; The pointer queue includes pointer data for each target data to be stored corresponding to the target storage block. The order of the pointer data in the pointer queue is the same as the storage order of the target data to be stored in the data buffer. The pointer data includes the storage address and storage sequence number of the target data to be stored in the data buffer. The size of the storage sequence number is negatively correlated with the storage duration of the target data to be stored in the data buffer.

8. The method according to claim 7, characterized in that, The step of constructing a pointer queue corresponding to the target storage block based on each target data to be stored corresponding to the target storage block includes: Obtain the storage address and storage sequence number of each of the target data to be stored in the data buffer; For each of the target data to be stored, a pointer to the target data to be stored is constructed based on the storage address and storage sequence number of the target data in the data buffer; According to the storage order of each target data to be stored in the data buffer, the pointer data of each target data to be stored is sorted to obtain the pointer queue corresponding to the target storage block.

9. The method according to claim 7, characterized in that, Based on the pointer queues corresponding to each target storage block, for each target storage block, according to the storage order of each target data to be stored in the data buffer, the step of sequentially writing each target data to be stored corresponding to the target storage block into the target storage block in the on-chip storage unit includes: Read the first pointer data in each of the pointer queues, and sort the storage sequence numbers in each of the first pointer data in ascending order to obtain the target sequence; Starting from the first storage sequence number of the target sequence, the first storage sequence number is used as the target storage sequence number; Write the target data to be stored corresponding to the target storage number into the target storage block corresponding to the target storage number; In response to the successful writing of the target data to be stored corresponding to the target storage number into the target storage block corresponding to the target storage number, a storage number greater than the target storage number is used as a storage number to be processed. The storage address of the target data to be stored corresponding to the storage number to be processed in the data buffer is shifted one bit in the target direction to obtain the updated target data to be stored corresponding to each target storage block. The target direction is the direction of the storage address of the target data to be stored corresponding to the target storage number. Delete the pointer data corresponding to the target storage sequence number, and decrement the unprocessed storage sequence number in each of the pointer queues by one to obtain the updated pointer queue. Based on the updated target data to be stored and the updated pointer queue, the steps of reading the first pointer data in each pointer queue and subsequent data are re-executed.

10. The method according to claim 9, characterized in that, The step of writing the target data to be stored corresponding to the target storage sequence number into the target storage block corresponding to the target storage sequence number includes: Identify whether the target storage block corresponding to the target storage sequence number satisfies the one-time write condition of the target data to be stored corresponding to the target storage sequence number; When the target storage block corresponding to the target storage sequence number does not meet the one-time write condition, the processing of the data to be stored corresponding to the target storage sequence number is paused, and the next storage sequence number of the first storage sequence number in the target sequence is taken as the target storage sequence number. The steps of identifying whether the target storage block corresponding to the target storage sequence number meets the one-time write condition of the target data to be stored corresponding to the target storage sequence number and subsequent steps are re-executed. When the target storage block corresponding to the target storage sequence number meets the one-time write condition, the target data to be stored corresponding to the target storage sequence number is written into the target storage block corresponding to the target storage sequence number.

11. The method according to claim 10, characterized in that, The method further includes: When none of the target storage blocks corresponding to each storage sequence number in the target sequence meet the one-time write condition corresponding to each storage sequence number, the writing of data to the on-chip storage unit is stopped.

12. The method according to claim 10, characterized in that, The step of identifying whether the target storage block corresponding to the storage sequence number meets the one-time write condition of the target data to be stored corresponding to the storage sequence number includes: Obtain the current write status of the target storage block corresponding to the storage sequence number in the on-chip storage unit; When the current write state of the target storage block is a writable state, it is identified whether there is a target number of target storage units in the target storage block. The target number is the number of target storage units requested to store the target data corresponding to the storage sequence number, and the target storage unit is the storage unit in the target storage block that is currently allowed to write data. When the target number of target storage units exists in the target storage block, it is determined that the target storage block corresponding to the storage sequence number satisfies the one-time write condition; When the current write state of the target storage block is an unwriteable state or the target number of target storage units does not exist in the target storage block, it is determined that the target storage block corresponding to the storage sequence number does not meet the one-time write condition.

13. The method according to claim 12, characterized in that, The step of obtaining the current write status of the target storage block corresponding to the storage sequence number in the on-chip storage unit includes: Obtain the write enable signal of the target memory block corresponding to the memory sequence number from the on-chip memory unit; When the write enable signal of the target storage block is the first target enable signal, the current write state of the target storage block is determined to be a writable state, and the first target enable signal is an enable signal that indicates that the target storage block is currently allowed to write data. When the write enable signal of the target storage block is not the first target enable signal, the current write state of the target storage block corresponding to the storage sequence number is determined to be an unwriteable state.

14. The method according to claim 12, characterized in that, The step of identifying whether the target number of target storage units exists in the target storage block includes: Obtain the write enable signal of each memory cell in the target memory block; When the target number of second target enable signals are present in the write enable signals of each of the aforementioned storage cells, it is determined that the target number of target storage cells are present in the target storage block, wherein the second target enable signal is an enable signal that indicates that data is currently allowed to be written to the storage cell; If the target number of second target enable signals is not present in the write enable signals of each of the aforementioned memory cells, it is determined that the target number of target memory cells does not exist in the target memory block.

15. A data writing system, characterized in that, The data writing system includes a first data distribution unit and a second data distribution unit. The first data distribution unit is a dedicated distribution unit for processing first-level cache data, and the second data distribution unit is a general distribution unit for processing non-first-level cache data. The first data distribution unit is configured to receive a first data write request from the first-level cache unit and write the first-level cache data corresponding to the first data write request into the on-chip storage unit. The second data distribution unit is used to receive a second data write request from a non-Level 1 cache unit and to write the non-Level 1 cache data corresponding to the second data write request into the on-chip storage unit.

16. A computer device, characterized in that, include: A memory and a processor, wherein the memory stores a computer program that, when executed by the processor, implements the data writing method as described in any one of claims 1-14.

17. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the data writing method as described in any one of claims 1-14.

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