Test pattern generation unit and test pattern generation device

Abstract

The invention relates to a test pattern generation unit and a test pattern generation device. An address generation module performs logical operation on address data issued by a sequence controller in combination with immediate data to obtain first intermediate data; the first intermediate data is combined with second register data issued by the sequence controller to serve as a data source to perform M-path logical operation, and M-path post-operation addresses are output; and the data generation module performs logical operation on the fourth register data issued by the sequence controller in combination with the immediate data to obtain M-path fourth intermediate data, the M-path fourth intermediate data and the fifth register data issued by the sequence controller serve as data sources to perform M-path logical operation, and M-path operated data is output. And the signal mapping module synchronously receives the M-operated address and the M-path operated data, and outputs the address and the data after physical mapping. The data sources of the address generation module and the data generation module are expanded, so that the diversity of test patterns is increased, and different test requirements are met.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a test pattern generation unit and a test pattern generation apparatus. Background Technology

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to inspect various parameters of the device under test (DUT), eliminating defective products and controlling the quality of semiconductor devices before they leave the factory. The resource board of the test machine is responsible for generating corresponding test signals based on the test pattern information and sending them to the device under test. However, how to adapt the waveform data generated by the resource board to different test requirements is a problem that urgently needs to be solved. Summary of the Invention

[0003] Therefore, it is necessary to provide a test pattern generation unit and test pattern generation device that can adapt to different testing needs to address the above problems.

[0004] The first aspect of this application provides a test pattern generation unit, comprising: a sequence controller, an address generation module, a data generation module, and a signal mapping module. The signal mapping module is used to synchronously receive M-channel processed addresses and M-channel processed data, perform physical mapping, and output the addresses and data, where M is greater than or equal to 1.

[0005] The address generation module performs logical operations on the address data sent by the sequence controller in combination with immediate values ​​to obtain first intermediate data. The first intermediate data, combined with the second register data sent by the sequence controller, is used as the data source for M-way logical operations, and outputs M-way processed addresses. Each processed address includes the address after the leading edge operation and the address after the trailing edge operation. The data generation module performs logical operations on the fourth register data sent by the sequence controller in combination with immediate values ​​to obtain M-way fourth intermediate data. The M-way fourth intermediate data and the fifth register data sent by the sequence controller are used as the data source for M-way logical operations, and output M-way processed data. Each processed data includes the data after the leading edge operation and the data after the trailing edge operation.

[0006] In one embodiment, the address data includes X groups of address data, Y groups of address data, and Z groups of register data. The address data is combined with immediate values ​​to perform logical operations to obtain first intermediate data. The first intermediate data includes X groups of first intermediate data, Y groups of first intermediate data, and Z groups of first intermediate data. The first intermediate data and the second register data serve as data sources for M-way logical operations, wherein each logical operation includes three levels of logical operations.

[0007] In one embodiment, each logic operation includes three levels of logic operations, including:

[0008] The first intermediate data of group X, the first intermediate data of group Y, and the first intermediate data of group Z are used as data sources to perform first-level logical operations to obtain second intermediate data;

[0009] The second intermediate data and the first intermediate data of group Z are used as data sources to perform a second-level logical operation to obtain the third intermediate data;

[0010] The third intermediate data and the second register data are used as data sources to perform third-level logical operations to obtain the address after the leading edge operation and the address after the trailing edge operation.

[0011] In one embodiment, the address generation module also receives specified address data issued by the sequence controller. The specified address data, the second intermediate data, and the first intermediate data of the Z group are used as data sources to perform a second-level logical operation to obtain the third intermediate data.

[0012] In one embodiment, the address data includes X group address data, Y group address data, and Z group register data. The address generation module receives first register data issued by the sequence controller. The first register data includes the maximum limit of the X group address, the maximum limit of the Y group address, and third register data, which are used to perform logical operations on the X group address data, the Y group address data, and the immediate value to generate the first intermediate data.

[0013] In one embodiment, the first register number is used to perform logical operations with the X group of address data, the Y group of address data, and the immediate value, including:

[0014] The data selected from the third register is logically operated on with the X group address data / the Y group address data, and the output data after the logical operation is compared with the maximum limit of the X group address / the maximum limit of the Y group address;

[0015] If the data after the logical operation is greater than the maximum limit of the X group address / the maximum limit of the Y group address, the data after the logical operation is subtracted from the maximum limit of the X group address / the maximum limit of the Y group address, and the remainder is used as the first intermediate number of the X group / the first intermediate number of the Y group, and the carry data is output to participate in the logical operation of the Y group address data / Z group register data;

[0016] If the data after the logical operation is less than the maximum limit of address group X / the maximum limit of address group Y, the data after the logical operation will be output as the first intermediate number of group X / the first intermediate number of group Y.

[0017] In one embodiment, the data generation module receives 2M sets of fourth register data from the sequence controller. Each set of two sets of fourth register data is combined with an immediate value to perform logical operations, generating two sets of fourth intermediate data to form one path of fourth intermediate data. The fourth register data includes register assignment data and / or the previous logical operation value.

[0018] In one embodiment, the data generation module further receives a zeroing value from the sequence controller, the fourth intermediate data of the M-channel, and the fifth register data from the sequence controller as data sources for performing logical operations on the M-channel, including:

[0019] The first leading edge intermediate data and the first trailing edge intermediate data are selected based on the fourth intermediate data;

[0020] Each path of the first leading edge intermediate data and the first trailing edge intermediate data is used as the data source to perform a first-level logical operation with the zero value to obtain the fifth intermediate data, wherein the zero value is used for direct zeroing output.

[0021] The fifth intermediate data and the fifth register data are logically operated to output the leading edge data LDATA1 and the trailing edge data TDATA1.

[0022] In one embodiment, the fifth register includes toggle data and DBI comparison data. The fifth intermediate data and the data in the fifth register are logically operated to output the leading edge data LDATA1 and the trailing edge data TDATA1, including:

[0023] After the first leading edge intermediate data and the first trailing edge intermediate data are logically operated on with the flipped data, the operation results are respectively compared with the DBI comparison data to perform data bus flipping operation, and the operation results are output as the leading edge data LDATA1 and the trailing edge data TDATA1.

[0024] In one embodiment, the data generation module compares the DBI comparison data with the received calculation result. If the number of addresses with 1 in the calculation result is greater than the data bit width / 2, the received calculation result is completely flipped, and the leading edge data LDATA1 and the trailing edge data TDATA1 after the calculation are output.

[0025] A second aspect of this application provides a test pattern generation apparatus, including a first test pattern generation module and a second test pattern generation module;

[0026] The first test pattern generation module includes the aforementioned test pattern generation unit, output enable data module, comparison enable data module, and multiplexer. The output enable data module is connected to the sequence controller, the comparison enable data module is connected to the sequence controller, and the multiplexer is connected to the signal mapping module, the output enable data module, the comparison enable data module, and the timing module. The timing module is connected to the device under test via a PE chip.

[0027] The output enable data module enables or disables output according to the output enable parameters issued by the sequence controller, and the comparison enable data module performs comparison or does not perform comparison according to the comparison enable parameters issued by the sequence controller.

[0028] The multiplexer is used to select and output the enabled or disabled output, the comparison output or the non-comparison output, and the physically mapped address and data output by the signal mapping module to the timing module.

[0029] The aforementioned test pattern generation unit and device, in their respective address generation modules, combine the address data sent by the sequence controller with immediate values ​​to perform logical operations, obtaining first intermediate data. This first intermediate data, combined with second register data sent by the sequence controller, serves as the data source for M-way logical operations, outputting M-way processed addresses. Each processed address includes the address after the leading edge operation and the address after the trailing edge operation. The data generation module combines the fourth register data sent by the sequence controller with immediate values ​​to perform logical operations, obtaining M-way fourth intermediate data. This M-way fourth intermediate data, along with fifth register data sent by the sequence controller, serves as the data source for M-way logical operations, outputting M-way processed data. Each processed data includes the data after the leading edge operation and the data after the trailing edge operation. The signal mapping module synchronously receives the M-way processed addresses and M-way processed data, performs physical mapping, and outputs the resulting addresses and data, where M is greater than or equal to 1. By expanding the data sources of the address generation module and the data generation module, the diversity of test patterns can be increased to adapt to different testing requirements. Attached Figure Description

[0030] Figure 1 This is a structural block diagram of a test pattern generation unit in one embodiment;

[0031] Figure 2 Here is a logic block diagram of the address generation module (1WAY) in one embodiment;

[0032] Figure 3 Here is a logic block diagram of the address generation module (2WAY) in one embodiment;

[0033] Figure 4Here is a logic block diagram of the data generation module (1WAY) in one embodiment;

[0034] Figure 5 Here is a logic block diagram of a data generation module (2WAY) in one embodiment;

[0035] Figure 6 This is a schematic diagram of the structure of a test pattern generation device in one embodiment. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. It is understood that the term "connection" in the following embodiments, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, should be understood as "electrical connection," "communication connection," etc.

[0038] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0039] In one embodiment, such as Figure 1 As shown, a test pattern generation unit is provided, including: a sequence controller 110, an address generation module 120, a data generation module 130, and a signal mapping module 170. The sequence controller 110 is connected to the address generation module 120 and the data generation module 130, and the signal mapping module 170 is connected to the address generation module 120 and the data generation module 130. The signal mapping module 170 is used to synchronously receive M channels of processed addresses and M channels of processed data, perform physical mapping, and output the addresses and data, where M is greater than or equal to 1.

[0040] Address generation module 120 performs logical operations on the address data sent by sequence controller 110, combining them with immediate values ​​to obtain first intermediate data. This first intermediate data, combined with second register data sent by sequence controller 110, serves as the data source for M-way logical operations, outputting M-way processed addresses. Each processed address includes the address after the leading edge operation and the address after the trailing edge operation. Data generation module 130 performs logical operations on the fourth register data sent by sequence controller 110, combining them with immediate values ​​to obtain M-way fourth intermediate data. This M-way fourth intermediate data, along with fifth register data sent by sequence controller 110, serves as the data source for M-way logical operations, outputting M-way processed data. Each processed data includes the data after the leading edge operation and the data after the trailing edge operation. By expanding the data sources of address generation module 120 and data generation module 130, the diversity of test patterns can be increased to adapt to different test requirements.

[0041] The logical operations can include addition, subtraction, multiplication, division, AND, OR, XOR, and flipping operations, as well as selection operations. Delay units can be set internally or on the output lines of the address generation module 120 and the data generation module 130 to delay the M-path processed addresses and M-path processed data, ensuring that the processed addresses and data transmitted to the signal mapping module 170 at the same time are aligned with the signals issued by the sequence controller 110. The physically mapped addresses and data output by the signal mapping module 170 are fixed-bit length data. The signal mapping module 170 controls the selection of processed address information and processed data information for each bit according to the signals issued by the sequence controller 110, thereby forming fixed-bit physically mapped addresses and data.

[0042] Furthermore, such as Figure 6As shown, the test pattern generation unit also includes a first verification module 140 and a second verification module 150. The first verification module 140 is connected to the address generation module 120 and the signal mapping module 170. It is used to verify the received M-channel processed addresses according to the signals sent by the sequence controller 110. The output M-channel processed address information is delayed by a delay unit and then transmitted to the signal mapping module 170. The second verification module 150 is connected to the data generation module 130 and the signal mapping module 170. It is used to verify the received M-channel processed data according to the signals sent by the sequence controller 110. The output M-channel processed data information is delayed by a delay unit and then transmitted to the signal mapping module 170. Both the first verification module 140 and the second verification module 150 simultaneously receive the output data of the previous module and the signals sent by the sequence controller 110. They process the output data of the previous module accordingly based on the signals sent by the sequence controller 110. Correspondingly, the signal mapping module 170 selects the specified physically mapped address and data from the processed address information and processed data information received at the same time, based on the signal sent by the sequence controller 110, and outputs them.

[0043] The specific types of the first verification module 140 and the second verification module 150 are not unique. In this embodiment, the first verification module 140 is an even parity check module. Based on the signal sent by the sequence controller 110, it selects an even parity check rule to verify the processed address. The output processed address information includes the even parity check result and the processed address. The second verification module 150 is a CRC check module. Based on the signal sent by the sequence controller 110, it selects a CRC check rule (including not performing CRC operation), performs a CRC operation on the processed data according to the selected CRC check rule, and the output processed data information includes the check result, and, according to the check rule, also includes or partially includes the reversed data.

[0044] The functions performed by each module are different, so the signals sent by the sequence controller 110 to each module are also different. The sequence controller 110 can set different signal sending time intervals based on the data processing time of each module, so that each module simultaneously receives the output data of the previous module and the signals sent by the sequence controller 110, and processes the output data of the previous module accordingly based on the signals sent by the sequence controller 110. In other embodiments, the sequence controller 110 may also output signals from each module simultaneously, with each signal delayed through a corresponding transmission path to ensure that the signals received by each module and the output data of the previous module arrive at the same time.

[0045] Address generation module 120 can perform one-way address selection operations or multiple-way address selection operations. Data generation module 130 can perform one-way data selection operations or multiple-way data selection operations; that is, the value of M can be set according to actual test requirements. When performing multi-way (nWAY, n≥2) operations, the multi-way operations can be performed within the same address generation module 120 and the same data generation module 130. The number of address selection operations performed by address generation module 120, the number of data selection operations performed by data generation module 130, and the number of physically mapped addresses and data output by signal mapping module 170 are the same. Each channel of address generation module 120 outputs two sets of processed addresses (address after leading-edge operation and address after trailing-edge operation), and each channel of data generation module 130 outputs two sets of processed data (data after leading-edge operation and data after trailing-edge operation). After receiving the processed address information and data information of M channels, signal mapping module 170 selects and outputs a fixed number of bits of physically mapped addresses and data. In signal mapping module 170, a copy mechanism is added, that is, signal mapping module 2, signal mapping module 3, ..., signal mapping module M copy the output data of signal mapping module 1, so that the output of each signal mapping module is the same as the output of signal mapping module 1.

[0046] The specific methods by which the address generation module 120 and the data generation module 130 perform calculations are not unique. Specifically, the address generation module 120 receives data sent by the sequence controller 110, including address data, register data, immediate values, specified address data, etc., and divides the register data into first register data, second register data, third register data, or more types of register data, which are used to perform corresponding logical operations.

[0047] In one embodiment, such as Figure 2 As shown, the address data includes X group address data, Y group address data, and Z group register data. The address data are combined with immediate values ​​to perform logical operations to obtain the first intermediate data. The first intermediate data includes X group first intermediate data RXA-RXH, Y group first intermediate data RYA-RYH, and Z group first intermediate data RZA-RZE. The first intermediate data and the second register data are used as data sources to perform M-way logical operations. Each logical operation includes three levels of logical operations to obtain the address X1 after the leading edge operation and the address Y1 after the trailing edge operation.

[0048] Among them, the first intermediate data RXA-RXH of group X are intermediate data obtained by performing logical operations on immediate values ​​and address data of group X, and the first intermediate data RYA-RYH of group Y are intermediate data obtained by performing logical operations on immediate values ​​and address data of group Y. Incorporating address data of group X, address data of group Y, register data of group Z, and immediate values ​​into logical operations increases the diversity of the first intermediate data. Furthermore, performing multi-path logical operations on all first intermediate data increases the output diversity of address X1 after the leading edge operation and address Y1 after the trailing edge operation.

[0049] In this embodiment, each logic operation includes three levels of logic operations, specifically: the first intermediate data RXA-RXH of group X, the first intermediate data RYA-RYH of group Y, and the first intermediate data RZA-RZE of group Z are used as data sources to perform the first level of logic operations to obtain the second intermediate data XS1 and YS1; the second intermediate data XS1 and YS1 and the first intermediate data RZA-RZE of group Z are used as data sources to perform the second level of logic operations to obtain the third intermediate data XT and YT; the third intermediate data XT and YT and the second register data are used as data sources to perform the third level of logic operations to obtain the address X1 after the leading edge operation and the address Y1 after the trailing edge operation.

[0050] In addition, the address generation module 120 also receives the specified address data ACT issued by the sequence controller 110. The specified address data ACT, the second intermediate data XS1, YS1 and the first intermediate data RZA-RZE of the Z group are used as the data source to perform the second-level logical operation to obtain the third intermediate data XS1 and YS1.

[0051] In one embodiment, such as Figure 2 As shown, the address data includes X group address data, Y group address data and Z group register data. The address generation module 120 receives the first register data sent by the sequence controller 110. The first register data includes the maximum limit value XTH of the X group address, the maximum limit value YTH of the Y group address and the third register data R0-15, which are used to perform logical operations with the X group address data, the Y group address data and the immediate value respectively to generate the first intermediate data.

[0052] Logical operations include AND, OR, addition, subtraction, multiplication, division, XOR, and flipping operations, as well as selection operations. Taking the logical operation of X group address data, immediate values, the maximum limit of X group address data XTH, and the third register data R0-15 as an example, the logical operation generates the first intermediate number of X group. This intermediate number can be any one of the X group address data, immediate values, or the third register data R0-15, or it can be the result of operating on the first register data and the X group address data. Similarly, the logical operation principle is the same for the maximum limit of Y group address data YTH, the third register data R0-15, the Y group address data, and immediate values, and will not be elaborated here. The third register data R0-15 are combined with the X group address data, the Y group address data, and the immediate value for logical operations, increasing the diversity of the first intermediate data.

[0053] Furthermore, the first register number is used to perform logical operations with the X group of address data, the Y group of address data, and immediate values, including:

[0054] The data selected from the third register is logically operated on with the address data from group X / group Y. The output data after the logical operation is compared with the maximum limit of address XTH / group Y. If the data after the logical operation is greater than the maximum limit of address XTH / group Y, the data after the logical operation is subtracted from the maximum limit of address XTH / group Y, and the remainder is used as the first intermediate number of group X / group Y. The carry data is then output to participate in the logical operation of address data from group Y / group Z registers. If the data after the logical operation is less than the maximum limit of address X / group Y, the data after the logical operation is output as the first intermediate number of group X / group Y.

[0055] The logical operations include AND, OR, addition, subtraction, multiplication, division, XOR, and flipping operations, as well as selection operations. It selects data from the third register and performs logical operations with data from the X group address data / Y group address data, outputting the logically processed data. This includes selective output of the third register data, data from the X group address data / Y group address data, and data from the third register and X group address data / Y group address data. When the logically processed data exceeds the maximum limit of the X group address data (XTH) / Y group address data (YTH), carry and borrow data are added to participate in the logical operations of the Y group address data / Z group register data, increasing the diversity of logical operations for the Y group address data / Z group register data, and increasing the data diversity output of the corresponding first intermediate number of the Y group and the first intermediate number of the Z group.

[0056] In one embodiment, when the total number of logic operations M is even, the address generation module 120 sequentially combines the second intermediate data, the second register data, and the first intermediate data of every two logic operations as data sources to perform logic operations on each path; when the total number of logic operations M is odd, the address generation module 120 sequentially combines the second intermediate data, the second register data, and the first intermediate data of every two logic operations as data sources to perform logic operations on path M-1, and combines the second register data and the first intermediate data as data sources to perform logic operations on path M.

[0057] For example, address generation module 120 receives address data. The X group of address data, Y group of address data, and Z group of register data within the address data are combined with immediate values ​​for logical operations to obtain the first intermediate data, namely, the first intermediate data of group X (RXA-RXH), the first intermediate data of group Y (RYA-RYH), and the first intermediate data of group Z (RZA-RZE). In any one-way logical operation, address generation module 120 uses the same first intermediate data of group X (RXA-RXH), group Y (RYA-RYH), and group Z (RZA). -RZE is used as the data source and two logical operations are performed to obtain the second intermediate data XS1 and YS1. The second intermediate data XS1 and YS1, the first intermediate data RZA-RZE of group Z, and the second intermediate data XS2 and YS2 of another logical operation (adjacent to 1WAY) are used as the data source and two logical operations are performed to obtain the third intermediate data XT and YT. The third intermediate data XT and YT and the corresponding second register data are combined and two logical operations are performed to output the address X1 after the leading edge operation and the address Y1 after the trailing edge operation.

[0058] Furthermore, the address generation module 120 also combines the second intermediate data XS1, YS1, the first intermediate data RZA-RZE, the second intermediate data XS2 and YS2 of another logical operation, and the configured specified address data ACT as data sources to perform two logical operations respectively to obtain the third intermediate data XT and YT.

[0059] In one embodiment, the 1WAY logic block diagram of the address generation module 120 is as follows: Figure 2As shown. The X group address data includes XA-XH, the Y group address data includes YA-YH, the Z group register data includes ZA-ZE, R0-15 is the third register data issued by the sequence controller 110, XTH and YTH are the maximum limits of the X group address and Y group address issued by the sequence controller 110, XT0-15, XOS, YOS, and YT0-15 are the second register data issued by the sequence controller 110, CB0-1 is the carry / borrow flag, ACT is the specified address data, and ALU represents the arithmetic logic unit, performing AND, OR, addition, subtraction, multiplication, division, XOR, and flip operations, as well as selection operations. RXA-RXH, RYA-RYH, and RZA-RZE are the first intermediate data generated during data logic operations; the second intermediate data XS1 and YS1, and the third intermediate data XT and YT are the intermediate data generated by further logic operations. X1 and Y1 correspond to the addresses after the leading edge operation and the trailing edge operation of the 1WAY address, respectively.

[0060] Specifically, continue to refer to Figure 2 During logical operations on the address data within the purple dashed box (X group), the address data XA-XH of group X are used as the left-hand data. This can be an assignment value or the return value of the previous pattern operation. The data in the third register, R0-15, are used as the right-hand data and participate in the ALU operation along with the left-hand data. The ALU can either select data from the left and right-hand data for logical operations and then output it, or it can directly pass through data selected from the left and right-hand data and immediate values. When selecting data from the left and right-hand data for logical operations, XTH is the maximum limit of the address group X. The data after the ALU logical operation (the data after the logical operation) is compared with the maximum limit of the address group XTH. If the data after the logical operation is less than the maximum limit of the address group XTH, it is output directly. If the data after the logical operation is greater than the maximum limit of the address group XTH, the ALU subtracts the data after the logical operation from the maximum limit of the address group XTH and outputs the remainder as the first intermediate number of group X. The carry data CB0-1 is then carried over to the ALU of the address data group Y for logical operations.

[0061] When performing logical operations on the address data in the Y group within the purple dashed box, the ALU can either select data from the third register data R0-15 and the Y group address data YA-YH for logical operations and then output the result, or it can select data from the third register data R0-15, the Y group address data YA-YH, and the immediate value and transmit it directly. When performing logical operations on data selected from the third register data R0-15 and the third register data YA-YH, YTH is the maximum address limit of group Y. The ALU selects data from the third register data R0-15 and the third register data YA-YH for logical operations. The ALU compares the logically operated data with the maximum address limit of group YTH. If the logically operated data is less than the maximum address limit of group YTH, the logically operated data is directly output. If the logically operated data is greater than the maximum address limit of group YTH, the ALU subtracts the logically operated data from the maximum address limit of group YTH and outputs the remainder as the first intermediate number of group Y. The carry data CB0-1 is carried over to the data in the group Z register. The ALU participating in the logical operation participates in the operation.

[0062] Similarly, when performing logical operations on the data in register group Z within the purple dashed box, the ALU can either select data for logical operations or pass it directly through. When selecting data for logical operations, the ALU will also combine the selected data with the carry data output after logical operations on the address data in group Y, and output the first intermediate data RZA-RZE of group Z, which will not be elaborated further here.

[0063] Figure 2 Within the yellow dashed box, XT0-15 / YT0-15 are directly specified data that can be directly output, and XOS / YOS are address shifts. The corresponding ALU can select specified data from XT0-15 / YT0-15 as the output address X1 after the leading edge operation / Y1 after the trailing edge operation, or it can perform operations between the third intermediate data XT / YT and XOS / YOS, and then shift the address of the third intermediate data XT / YT accordingly to obtain the output address X1 after the leading edge operation / Y1 after the trailing edge operation.

[0064] The difference between 2WAY and 1WAY address generation: 2WAY is generated by copying the 1WAY logic block diagram ( Figure 2The logic within the yellow dashed box shares immediate values, address data sets XA-XH, YA-YH, register data sets ZA-ZE, R0-15, XTH, YTH, XT0-15, XOS, YOS, YT0-15, ACT, and the logic within the purple dashed box. Simultaneously, 2WAY shares the four sets of intermediate data (XS1, YS1, XS2, YS2) generated from the second intermediate data source, incorporating the second intermediate data generated from another path into one logic operation. This increases the diversity of obtaining the third intermediate data XT and YT, thereby enriching the data sources for the leading and trailing edge address data. Figure 3 As shown. 3-way address generation involves the first two logical operations generating X1, X2, Y1, and Y2 address signals (i.e., the processed addresses) according to the logic of 2-way, and the third operation generating X3 and Y3 address signals according to the logic of 1-way. 4-way address generation replicates the address generation logic of 2-way, meaning the first two operations generate X1, X2, Y1, and Y2 address signals according to the 2-way address generation method, and the last two operations generate X3, X4, Y3, and Y4 address signals according to the 2-way address generation method; and so on, thus achieving n-way address generation.

[0065] like Figure 3 As shown, taking the generation of a 2-way address as an example, each 1-way within the yellow dashed box uses X groups of first intermediate data RXA-RXH, Y groups of first intermediate data RYA-RYH, and Z groups of first intermediate data RZA-RZE as data sources for two logical operations. This can be achieved by selecting X groups of first intermediate data RXA-RXH, Y groups of first intermediate data RYA-RYH, and Z groups of first intermediate data RZA-RZE as inputs for logical operations, or by combining at least two of X groups of first intermediate data RXA-RXH, Y groups of first intermediate data RYA-RYH, and Z groups of first intermediate data RZA-RZE to select partial data (e.g., partial data from RXA-RXH and RYA-RYH) as inputs for logical operations, thereby generating address signals XS1, XS2, YS1, and YS2 (second intermediate data). In each wave, address signals XS1, XS2, YS1, and YS2 are shared. These signals, combined with the first intermediate data RZA-RZE from group Z and the configured specified address data ACT, serve as the data source for the next two logical operations. The outputs of these two logical operations are the third intermediate data XT and YT, respectively. In the final two logical operations, the third intermediate data XT, register data XT0-15, and XOS are used as the data source for one logical operation to obtain the address X1 (X2) after the leading edge operation. The third intermediate data YT, register data YT0-15, and YOS are used as the data source for one logical operation to obtain the address Y1 (Y2) after the trailing edge operation.

[0066] The data generation module 130 receives data from the sequence controller 110, including data from the fourth register, data from the fifth register, immediate values, and zero-values. Based on the signals from the sequence controller 110, the data generation module 130 performs logical operations on the fourth register data, fifth register data, immediate values, and zero-values ​​to generate intermediate data. Simultaneously, based on the signals from the sequence controller 110, the data generation module 130 also performs logical flips on specified positions (specified bits / regions / buses) of the intermediate data, outputting the leading edge data and the trailing edge data after the operations. Specifically, the specified bits specify which bits are flipped, the specified address region specifies which address field is flipped, and the specified bus specifies the entire bus is flipped. When flipping a specified address region, the data generation module 130 is also connected to the address generation module 120, and, in conjunction with the processed address output by the address generation module 120, performs region flips on the corresponding address regions of the intermediate data.

[0067] In one embodiment, the data generation module 130 receives 2M sets of fourth register data from the sequence controller 110. Each pair of fourth register data is combined with immediate values ​​for logical operations to generate two sets of fourth intermediate data, forming one channel of fourth intermediate data. The fourth register data includes register assignment data and / or the value of the previous logical operation. The M channels of fourth intermediate data and the fifth register data from the sequence controller 110 serve as the data source for the M channels of logical operations. Each channel outputs two sets of processed data (the leading edge data and the trailing edge data). The value of the previous logical operation is the register value obtained after the previous line of pattern operations, which can be directly assigned to the fourth register data.

[0068] Furthermore, the data generation module 130 also receives the zeroing value issued by the sequence controller 110, the fourth intermediate data of the M channels, and the fifth register data issued by the sequence controller 110 as data sources to perform logical operations on the M channels, including: selecting the first leading edge intermediate data and the first trailing edge intermediate data based on the fourth intermediate data; performing first-level logical operations on each of the first leading edge intermediate data and the first trailing edge intermediate data with the zeroing value as the data source to obtain the fifth intermediate data, wherein the zeroing value is used for direct zeroing output; and performing logical operations on the fifth intermediate data and the fifth register data to output the operational leading edge data LDATA1 and the operational trailing edge data TDATA1.

[0069] The fifth register includes toggled data and DBI comparison data. The fifth intermediate data and the data in the fifth register undergo logical operations to output the resulting leading edge data LDATA1 and the resulting trailing edge data TDATA1. This includes: logically operating the first leading edge intermediate data and the first trailing edge intermediate data with the toggled data, then performing data bus toggling operations on the results with the DBI comparison data, and outputting the resulting leading edge data LDATA1 and the resulting trailing edge data TDATA1. Specifically, the data generation module 130 compares the received operation results with the DBI comparison data. If the number of addresses with 1 in the operation result is greater than the data width / 2, then the received operation result is toggled, and the resulting leading edge data LDATA1 and the resulting trailing edge data TDATA1 are output.

[0070] In one embodiment, when the total number of logic operation paths M is even, the data generation module 130 sequentially combines the fourth intermediate data from every two paths with the corresponding fifth register data as data sources for each logic operation; when the total number of logic operation paths M is odd, the data generation module 130 sequentially combines the fourth intermediate data from every two paths with the corresponding fifth register data as data sources for the (M-1)th path logic operation, and then combines the fourth intermediate data from the Mth path with the corresponding fifth register data as data sources for the Mth path logic operation. The fourth intermediate data for each logic operation is obtained by performing logical operations on two sets of fourth register data combined with immediate values, resulting in two sets of fourth intermediate data, DPA and DPB.

[0071] The 1-way logic block diagram of data generation module 130 is as follows: Figure 4 As shown. Data DAR0-3, DAH0-3, and DPA_INI are the fourth register data issued by the sequence controller 110. DPA and DPB are the fourth intermediate data generated in the data logic operation. The fourth intermediate data DPA and DPB obtained after the previous row pattern operation can be used as the values ​​in the fourth register in the next row pattern operation to participate in the operation of data DAR0-3, DAH0-3, DPA_INI, and immediate values. SWAP indicates replacement, DINV is the toggle data issued by the sequence controller 110, and BUS_INV indicates bus toggle. DBI_CP is the DBI comparison data issued by the sequence controller 110, used to implement the data bus inversion mechanism.

[0072] Specifically, the DPA within the blue dashed box can be an assigned value or the DPA value calculated from the previous pattern operation. The ALU can either select a subset of data from DPA, DAR0-3, DAH0-3, DPA_INI, and immediate values, perform logical operations, and then output the fourth intermediate data DPA and DPB; or it can directly pass the selected data through to output the fourth intermediate data DPA and DPB. For example, the ALU can select data from DPA and DAR0-3, perform logical operations, and then output the result; or it can select data from DAH0-3, DPA_INI, and immediate values ​​for output. Figure 5 As shown, the corresponding values ​​of the fourth intermediate data DPA and DPB are different for 1-way, and the corresponding values ​​of the fourth intermediate data DPC and DPD are also different for 2-way, which can increase data diversity. The fourth intermediate data DPA, DPB, DPC, and DPD are input into the yellow dashed box and serve as the data source for the two ALUs in the first stage. The fourth intermediate data can be arbitrarily selected as the first leading-edge intermediate data or the first trailing-edge intermediate data to participate in the logic operation within the yellow box, outputting the calculated leading-edge data LDATA1 and the calculated trailing-edge data TDATA1. For example, DPA / DPC can be selected as the first leading-edge intermediate data, and DPB / DPD as the first trailing-edge intermediate data; or DPB / DPD can be selected as the first leading-edge intermediate data, and DPA / DPC as the first trailing-edge intermediate data. 0 represents a direct zeroing operation. The two ALUs in the first stage perform direct zeroing or select data from the fourth intermediate data DPA, DPB, DPC, and DPD to obtain the fifth intermediate data, which is output to the two ALUs in the second stage. The two ALUs in the second stage perform a logic operation with the toggled data DINV, and the output result is used for the next stage bus toggling.

[0073] BUS_INV receives the calculation result and determines whether the DBI condition is met. If it is, the address data is toggled. Specifically, DBI-CP represents the toggle condition. BUS_INV enables or disables the toggle operation based on the received control signal (toggle enable signal). When the toggle operation is enabled, the DBI comparison data is compared with the received calculation result. If the number of addresses with 1 in the received calculation result is greater than the data bit width / 2, the entire received calculation result is toggled, and the leading edge data LDATA1 and the trailing edge data TDATA1 are output.

[0074] The difference between 2-way and 1-way data generation: 2-way replicates the logic of 1-way. Each logic operation includes two sets of fourth register data. Each set contains DAR0-3, DAH0-3, and DPA_INI register data, as well as immediate values. Each set of fourth register data and the immediate values ​​involved in the logic operation are different, resulting in different fourth intermediate data for each path. Therefore, 2-way will generate two paths of fourth intermediate data: DPA, DPB, DPC, and DPD. 2-way shares these four sets of intermediate data (DPA, DPB, DPC, and DPD), enriching the data sources for both leading and trailing edges. Figure 5 As shown. 3-way data generation involves the first two channels generating LDATA1, TDATA1, LDATA2, and TDATA2 data signals (i.e., processed data) according to the 2-way logic, while the third channel generates LDATA1 and TDATA3 data signals according to the 1-way logic. 4-way data generation replicates the 2-way data generation logic; the first two channels generate LDATA1, TDATA1, LDATA2, and TDATA2 data signals according to the 2-way data generation method, and the last two channels generate LDATA3, TDATA3, LDATA4, and TDATA4 data signals according to the 2-way data generation method; and so on, thus achieving n-way data generation.

[0075] like Figure 5 As shown, taking 2-way data generation as an example, each channel combines immediate values, DAR0-3, DAH0-3, and DPA_INI register data for logical processing to generate fourth intermediate data DPA and DPB (fourth intermediate data DPC and DPD). Within the yellow dashed box, the two channels share the fourth intermediate data DPA, DPB, DPC, and DPD for two logic operations at the first level. The fifth intermediate data is output through direct zeroing or data selection. The fifth intermediate data from the two operations are then fed into two logic operations at the second level, combined with the toggled data DINV for the second-level logic operations. The results of the two second-level logic operations are combined with the DBI comparison data DBI_CP for bus toggling, resulting in the leading edge data LDATA1 (LDATA2) and the trailing edge data TDATA1 (TDATA2).

[0076] In one embodiment, a test pattern generation device is also provided. This device can be built based on an FPGA (Field-Programmable Gate Array) or other types of processing devices. Taking an FPGA as an example, the test pattern generation device can use a single FPGA to build internal modules, or it can use multiple FPGAs to build a separate architecture.

[0077] like Figure 6 As shown, the test pattern generation device includes the aforementioned test pattern generation unit, output enable data module 210, comparison enable data module 220, and multiplexer MUX. Output enable data module 210 is connected to sequence controller 110, comparison enable data module 220 is connected to sequence controller 110, and multiplexer MUX is connected to signal mapping module 170, output enable data module 210, comparison enable data module 220, and timing module 250. Timing module 250 is connected to device under test (DUT) via PE (pin circuit) chip 300.

[0078] The output enable data module 210 enables or disables the output according to the output enable parameters issued by the sequence controller 110, and the comparison enable data module 220 compares or does not compare according to the comparison enable parameters issued by the sequence controller 110. The multiplexer MUX is used to select and output the enabled or disabled output, the comparison output or not, and the physically mapped address and data output by the signal mapping module 170 to the timing module 250.

[0079] Specifically, the output enable data module 210 enables or disables the output based on the received output enable parameters (including enable and disable). Enabling output pulls the pin state of the device under test (DUT) high or low, while disabling output sets the pin state of the DUT to a high-impedance state. The comparison enable data module 220 performs comparison output and does not compare output based on the received comparison enable parameters (including comparison and non-comparison). This output indicates whether the current pattern and the waveform fed back by the DUT are compared; for example, 1 indicates comparison, and 0 indicates no comparison.

[0080] When the test pattern generation unit performs multi-channel logic operations and the signal mapping module 170 outputs multiple physical mapping addresses and data outputs, the multiplexer MUX selects the corresponding channel's enable output or disable output, compare output or non-compare output, as well as the physical mapping address and data, and outputs them as the calculated graphic data to the timing module 250.

[0081] Furthermore, the test pattern generation device also includes a designated data module 230 and a graphic data storage module 240. The designated data module 230 is connected to the sequence controller 110, and the multiplexer MUX is connected to both the designated data module 230 and the graphic data storage module 240. The designated data module 230 selects designated data from preset data according to the designated data parameters issued by the sequence controller 110 and sends it to the multiplexer MUX. The multiplexer MUX outputs the enabled or disabled outputs, the comparison outputs, the physically mapped addresses and data, the designated data, and the preset graphic data from the graphic data storage modules 240 to the timing module 250.

[0082] Similarly, when the test pattern generation unit performs multi-channel logic operations and the signal mapping module 170 outputs multiple physically mapped addresses and data outputs, the multiplexer MUX selects the enable or disable output, comparison or non-comparison output, and physically mapped addresses and data of the corresponding channel as the calculated graphic data output to the timing module 250, or selects the enable or disable output, comparison or non-comparison output, and specified data of the corresponding channel as the calculated graphic data output to the timing module 250, or outputs the preset graphic data in the graphic data storage module 240 of the corresponding channel to the timing module 250.

[0083] The timing module 250 performs waveform conversion and outputs the waveform change edge to the PE chip 300 after delaying the received data. It also samples and compares the signal returned by the PE chip 300 according to the comparison expectation value at the comparison time when the comparison is enabled, obtains the comparison result and stores it in the storage module.

[0084] The aforementioned test pattern generation device enables the generation of one or more waveforms. When generating multiple waveforms (nWAY, n≥2), it can increase the amount of waveform data generated while keeping the hardware architecture unchanged, thereby improving the test speed and efficiency.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A test pattern generation unit, characterized in that, include: The system includes a sequence controller, an address generation module, a data generation module, and a signal mapping module. The signal mapping module is used to synchronously receive M-channel processed addresses and M-channel processed data, perform physical mapping, and output the addresses and data, where M is greater than or equal to 1. The address generation module performs logical operations on the address data sent by the sequence controller in combination with immediate values ​​to obtain first intermediate data. The first intermediate data, combined with the second register data sent by the sequence controller, is used as the data source for M-way logical operations, and outputs M-way processed addresses. Each processed address includes the address after the leading edge operation and the address after the trailing edge operation. The data generation module performs logical operations on the fourth register data sent by the sequence controller in combination with immediate values ​​to obtain M-way fourth intermediate data. The M-way fourth intermediate data and the fifth register data sent by the sequence controller are used as the data source for M-way logical operations, and output M-way processed data. Each processed data includes the data after the leading edge operation and the data after the trailing edge operation.

2. The test pattern generation unit according to claim 1, characterized in that, The address data includes X groups of address data, Y groups of address data, and Z groups of register data. The address data are combined with immediate values ​​to perform logical operations to obtain first intermediate data. The first intermediate data includes X groups of first intermediate data, Y groups of first intermediate data, and Z groups of first intermediate data. The first intermediate data and the second register data serve as data sources for M-way logical operations, where each logical operation includes three levels of logical operations.

3. The test pattern generation unit according to claim 2, characterized in that, Each logic operation includes three levels of logic operations, including: The first intermediate data of group X, the first intermediate data of group Y, and the first intermediate data of group Z are used as data sources to perform first-level logical operations to obtain second intermediate data; The second intermediate data and the first intermediate data of group Z are used as data sources to perform a second-level logical operation to obtain the third intermediate data; The third intermediate data and the second register data are used as data sources to perform third-level logical operations to obtain the address after the leading edge operation and the address after the trailing edge operation.

4. The test pattern generation unit according to claim 3, characterized in that, The address generation module also receives specified address data issued by the sequence controller. The specified address data, the second intermediate data, and the first intermediate data of the Z group are used as data sources to perform second-level logical operations to obtain third intermediate data.

5. The test pattern generation unit according to claim 1, characterized in that, The address data includes X group address data, Y group address data, and Z group register data. The address generation module receives the first register data sent by the sequence controller. The first register data includes the maximum limit of the X group address, the maximum limit of the Y group address, and the third register data, which are used to perform logical operations on the X group address data, the Y group address data, and the immediate value to generate the first intermediate data.

6. The test pattern generation unit according to claim 5, characterized in that, The first register number is combined with the X group of address data, the Y group of address data, and the immediate value to perform logical operations, including: The data selected from the third register is logically operated on with the X group address data / the Y group address data, and the output data after the logical operation is compared with the maximum limit of the X group address / the maximum limit of the Y group address; If the data after the logical operation is greater than the maximum limit of the X group address / the maximum limit of the Y group address, the data after the logical operation is subtracted from the maximum limit of the X group address / the maximum limit of the Y group address, and the remainder is used as the first intermediate number of the X group / the first intermediate number of the Y group, and the carry data is output to participate in the logical operation of the Y group address data / Z group register data; If the data after the logical operation is less than the maximum limit of address group X / the maximum limit of address group Y, the data after the logical operation will be output as the first intermediate number of group X / the first intermediate number of group Y.

7. The test pattern generation unit according to claim 1, characterized in that, The data generation module receives 2M sets of fourth register data from the sequence controller. Each set of two sets of fourth register data is combined with an immediate value to perform logical operations, generating two sets of fourth intermediate data to form one path of fourth intermediate data. The fourth register data includes register assignment data and / or the previous logical operation value.

8. The test pattern generation unit according to claim 7, characterized in that, The data generation module also receives a zeroing value from the sequence controller, the fourth intermediate data from the M-channel, and the fifth register data from the sequence controller as data sources for performing logical operations on the M-channel, including: The first leading edge intermediate data and the first trailing edge intermediate data are selected based on the fourth intermediate data; Each path of the first leading edge intermediate data and the first trailing edge intermediate data is used as the data source to perform a first-level logical operation with the zero value to obtain the fifth intermediate data, wherein the zero value is used for direct zeroing output. The fifth intermediate data and the fifth register data are logically operated to output the leading edge data LDATA1 and the trailing edge data TDATA1.

9. The test pattern generation unit according to claim 8, characterized in that, The fifth register includes toggled data and DBI comparison data. The fifth intermediate data and the data in the fifth register are logically operated on to output the leading edge data LDATA1 and the trailing edge data TDATA1, including: After the first leading edge intermediate data and the first trailing edge intermediate data are logically operated on with the flipped data, the operation results are respectively compared with the DBI comparison data to perform data bus flipping operation, and the operation results are output as the leading edge data LDATA1 and the trailing edge data TDATA1.

10. The test pattern generation unit according to claim 9, characterized in that, The data generation module compares the DBI comparison data with the received calculation result. If the number of addresses with 1 in the calculation result is greater than the data bit width / 2, the received calculation result is completely flipped, and the leading edge data LDATA1 and the trailing edge data TDATA1 after the calculation are output.

11. A test pattern generation device, characterized in that, The device includes a test pattern generation unit, an output enable data module, a comparison enable data module, and a multiplexer as described in any one of claims 1-10. The output enable data module is connected to the sequence controller, the comparison enable data module is connected to the sequence controller, and the multiplexer is connected to the signal mapping module, the output enable data module, the comparison enable data module, and the timing module. The timing module is connected to the device under test via a PE chip. The output enable data module enables or disables output according to the output enable parameters issued by the sequence controller, and the comparison enable data module performs comparison or does not perform comparison according to the comparison enable parameters issued by the sequence controller. The multiplexer is used to select and output the enabled or disabled output, the comparison output or the non-comparison output, and the physically mapped address and data output by the signal mapping module to the timing module.

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