Register allocation method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a register allocation method and device, electronic equipment and a readable storage medium, aiming at any to-be-processed instruction, under the condition that a register is not allocated to a target operand of the to-be-processed instruction, the type attribute of the target operand is determined; under the condition that the type attribute of the target operand is a constant, determining an instruction allocation rule matched with the target operand based on a comparison result of a numerical value of the target operand and a constant value in each allocated register and a related dominating relation of a first basic block where the target operand is located; and determining a target register corresponding to the target operand based on the instruction distribution rule. Therefore, the instruction distribution rule matched with the target operand can be dynamically selected according to the type attribute of the target operand, the constant register distribution process is optimized, unnecessary register distribution is avoided, value loading operation and the number of occupied registers are reduced, instruction execution efficiency is improved, and meanwhile the register utilization rate and code execution performance are improved.

Description

Technical Field

[0001] This invention relates to the field of compiler technology, and in particular to a register allocation method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] During the compiler register allocation process, for constant operands, existing technologies have difficulty accurately determining whether existing registers can be safely reused for constants across basic blocks while ensuring the semantic correctness of the program. This leads to problems such as repeated loading of constant values, increased number of registers occupied, and reduced instruction execution efficiency. Summary of the Invention

[0003] To overcome the problems existing in related technologies, the present invention provides a register allocation method, apparatus, electronic device, and readable storage medium.

[0004] In a first aspect, the present invention provides a register allocation method, the method comprising: For any instruction to be processed, if no register is allocated to the target operand of the instruction to be processed, determine the type attribute of the target operand; When the type attribute of the target operand is constant, the instruction allocation rule matching the target operand is determined based on the comparison result between the value of the target operand and the constant values ​​in each allocated register, as well as the relevant dominance relationship of the first basic block where the target operand is located. Based on the instruction allocation rules, the target register corresponding to the target operand is determined.

[0005] In a second aspect, the present invention provides a register allocation apparatus, the apparatus comprising: The first determining module is used to determine the type attribute of the target operand for any instruction to be processed, in the case that no register is allocated to the target operand of the instruction to be processed; The second determining module is used to determine the instruction allocation rule matching the target operand, based on the comparison result between the value of the target operand and the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block where the target operand is located, when the type attribute of the target operand is a constant. The third determining module is used to determine the target register corresponding to the target operand based on the instruction allocation rules.

[0006] Thirdly, the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the register allocation method described in any one of the first aspects above.

[0007] Fourthly, the present invention provides a readable storage medium that, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform steps in the register allocation method as described in any of the embodiments of the first aspect above.

[0008] In this embodiment of the invention, for any instruction to be processed, if the target operand of the instruction to be processed has not been allocated a register, the type attribute of the target operand is determined; if the type attribute of the target operand is constant, based on the comparison result of the value of the target operand with the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block where the target operand is located, an instruction allocation rule matching the target operand is determined; based on the instruction allocation rule, the target register corresponding to the target operand is determined. Thus, by comparing the value of the target operand with the constant values ​​in each allocated register, and combining the relevant dominance relationship of the first basic block where the target operand is located, an instruction allocation rule matching the target operand is dynamically selected, optimizing the constant register allocation process, avoiding unnecessary register allocation, reducing unnecessary value loading operations and the number of registers occupied, improving instruction execution efficiency, and simultaneously improving register utilization and code execution performance. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a flowchart of the steps of a register allocation method provided in an embodiment of the present invention; Figure 2 This is a structural diagram of a register allocation device provided in an embodiment of the present invention; Figure 3 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] Figure 1This is a flowchart of the steps of a register allocation method provided in an embodiment of the present invention, as follows: Figure 1 As shown, the method may include: Step 101: For any instruction to be processed, if the target operand of the instruction to be processed has not been allocated a register, determine the type attribute of the target operand.

[0013] In this embodiment of the invention, the basic blocks in the control flow graph corresponding to the code to be processed are traversed. For each basic block, all instructions in that basic block are traversed. For each instruction, it is checked whether the operands contained in the instruction have been allocated to registers. Here, the code to be processed can be intermediate code (IR). The case where the operands have been allocated to registers can be as follows: the operands already have register numbers attached, and these numbers are not initial values ​​(e.g., a value greater than the maximum register number).

[0014] It is understood that the embodiments of the present invention can be applied to the conversion process from code to be processed, i.e., intermediate code, to machine instructions related to the target platform.

[0015] For any instruction to be processed, if a register has already been allocated for the target operand, no reallocation is needed; the already allocated register is used directly. If a register has not been allocated for the target operand, the type attribute of the target operand must be determined. The type attribute of the operand can include constants and variables. Constants refer to data whose values ​​cannot be changed during program execution, such as numbers, characters, or strings. Variables refer to data whose values ​​can be changed during program execution, and the corresponding memory location must be accessed through the variable name.

[0016] Step 102: If the type attribute of the target operand is constant, determine the instruction allocation rule that matches the target operand based on the comparison result between the value of the target operand and the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block where the target operand is located.

[0017] In this embodiment of the invention, when the type attribute of the target operand is constant, the value of the target operand is compared and matched with the constant values ​​in each allocated register. Based on the comparison results between the value of the target operand and the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block where the target operand is located, the instruction allocation rule matching the target operand is determined.

[0018] The comparison results between the value of the target operand and the constant values ​​in each allocated register can include: the value of the target operand is the same as the constant value in the allocated register, and the value of the target operand is different from the constant value in the allocated register. The relevant dominance relationships of the first basic block where the target operand resides can include a first dominance relationship, obtained from control flow graph analysis, representing a first basic block being dominated by another basic block, and a second dominance relationship, representing a basic block being dominated by another basic block. Dominance refers to the following: In the control flow graph starting from the program entry node, for the first basic block where the target operand resides, if there exists another basic block bi, then basic block bi constitutes a first dominance relationship with the first basic block if and only if that basic block bi is on every feasible control flow path from the program entry basic block b0 to the first basic block (i.e., the first basic block where the target operand resides). In other words, basic block bi is the dominator of the first basic block. Conversely, if the first basic block is a basic block on the path that a certain basic block bj must take to reach the program exit node, that is, every path from basic block bj to the program exit must pass through the first basic block, then the first basic block constitutes a second dominion relationship with basic block bj, that is, the first basic block is the dominator of basic block bj.

[0019] By comparing the value of the target operand with the constant values ​​in each allocated register and determining whether the dominance relationship of the first basic block containing the target operand meets preset allocation conditions, the instruction allocation rule matching the target operand can be determined. If the comparison result and the dominance relationship meet the preset allocation conditions, the instruction allocation rule is determined to be the first allocation rule; if the comparison result and the dominance relationship do not meet the preset allocation conditions, the instruction allocation rule is determined to be the second allocation rule. The preset allocation conditions can be that the value of the target operand is the same as the constant index value in the allocated register, and the second basic block corresponding to that allocated register can dominate the first basic block. The instruction allocation rule can include the first allocation rule and the second allocation rule. The first allocation rule can be to reuse the allocated registers that meet the preset allocation conditions, that is, to directly determine the allocated registers that meet the preset allocation conditions as the target registers. The second allocation rule can be to allocate a target register to the target operand based on the first set of registers.

[0020] Step 103: Based on the instruction allocation rules, determine the target register corresponding to the target operand.

[0021] In this embodiment of the invention, the target register corresponding to the target operand is determined according to the instruction allocation rule matching the target operand. When the instruction allocation rule is a first allocation rule, allocated registers that meet preset allocation conditions are reused based on the first allocation rule to identify the target register corresponding to the alphabetical operand. When the instruction allocation rule is a second allocation rule, a corresponding target register can be allocated to the target operand based on a first set of registers.

[0022] For example, if the value of the target operand is the same as the constant index value in any allocated register and the second basic block corresponding to that allocated register can dominate the first basic block, and the instruction allocation rule is determined to be the first allocation rule, then that allocated register can be determined as the target register. If the value of the target operand is not the same as the constant value in any allocated register, or there is no second basic block corresponding to an allocated register that can dominate the first basic block, and the instruction allocation rule is determined to be the second allocation rule, then the target register corresponding to the target operand can be determined based on the first set of registers.

[0023] In summary, in this embodiment of the invention, for any instruction to be processed, if the target operand of the instruction to be processed has not been allocated a register, the type attribute of the target operand is determined; if the type attribute of the target operand is constant, based on the comparison result of the value of the target operand with the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block where the target operand is located, an instruction allocation rule matching the target operand is determined; based on the instruction allocation rule, the target register corresponding to the target operand is determined. Thus, by comparing the value of the target operand with the constant values ​​in each allocated register, and combining the relevant dominance relationship of the first basic block where the target operand is located, an instruction allocation rule matching the target operand is dynamically selected, optimizing the constant register allocation process, avoiding unnecessary register allocation, reducing unnecessary value loading operations and the number of registers occupied, improving instruction execution efficiency, and simultaneously improving register utilization and code execution performance.

[0024] In one embodiment, a register allocation method is applied during the code generation phase of a compiler, the method comprising: (1) Upon receiving the instruction to be processed, the type attribute of the target operand is determined based on the static type information of the target operand; (2) When the type attribute is a constant, the numerical characteristics of the constant are obtained, and the numerical characteristics are matched and compared with the constant values ​​of each allocated register in the preceding dominance path of the current basic block to determine the candidate register set that satisfies the numerical consistency; (3) Based on the dominance relationship between the first basic block where the target operand is located and the corresponding definition points of each candidate register, a constant reuse reachability constraint is constructed, and a set of reusable registers that satisfies the dominance relationship constraint is selected; (4) According to the set of reusable registers and the set of register allocation rules preset for constant operands, a target instruction allocation rule that matches the target operand is dynamically selected; (5) Based on the target instruction allocation rule, conflict detection and priority sorting are further performed on the set of reusable registers to determine the target register corresponding to the target operand; (6) The target register is allocated to the target operand, and the corresponding constant value information and its lifetime range are recorded in the compiler register status table.

[0025] Among them, by combining numerical feature matching, dominance relationship constraints and dynamic rule selection, register reuse optimization for constant operands is achieved, reducing the number of load instructions and register occupancy, and improving register utilization and instruction execution efficiency.

[0026] In one embodiment, the numerical characteristics include one of the following: an immediate number field, a sign-extended result, or an intermediate expression value after constant folding. In this embodiment, to improve the accuracy and efficiency of register reuse and allocation for constant operands, the present invention performs unified abstraction and standardization on the numerical characteristics of the target operands, enabling constant values ​​from different sources to undergo consistency comparison and reuse judgment during the register allocation stage. In one implementation, when the instruction to be processed is an instruction containing immediate operands, the numerical characteristics of the target operand are directly determined by the immediate numeric field in the instruction encoding. The specific process is as follows: During the instruction parsing stage, the target operand is identified as an immediate type; the immediate value is extracted from the immediate numeric field of the target instruction; the immediate value is used as the numerical characteristic of the target operand and recorded in the constant characteristic table during the register allocation stage; in the subsequent register allocation process, the immediate value is compared with the constant values ​​stored in the allocated registers to determine if there is a reusable register with the same value. This implementation avoids allocating new registers for recurring immediate values, reducing the number of immediate load instructions.

[0027] In another implementation, when the target operand is an immediate value or constant whose width is smaller than the target register's bit width, this invention generates standardized numerical characteristics through sign extension. The specific process is as follows: determine if the original bit width of the target operand is smaller than the register bit width under the target architecture; perform sign extension or zero extension operations on the target operand based on its sign attribute; use the extended result as the numerical characteristic of the target operand; and in the register allocation phase, determine register reuse based on the extended numerical characteristics. For example, an 8-bit immediate value 0xFF generates a 32-bit value 0xFFFFFFFF after sign extension; if the same extension result appears in subsequent instructions, the corresponding register can be directly reused. This implementation eliminates the problem of inconsistent constant values ​​due to bit width differences, ensuring the correctness of constant reuse across instructions and basic blocks.

[0028] In another implementation, when the target operand is generated by the compiler front-end or middle-end through constant folding optimization, this invention uses the value of the intermediate expression after constant folding as a numerical feature. The specific process is as follows: In the intermediate representation (IR) stage, constant folding is performed on the expression containing constant operands; the result value of the folded expression is obtained; the result value is used as the numerical feature of the target operand and passed to the register allocation stage; in the register allocation stage, the numerical feature is compared uniformly with the constant values ​​in the allocated registers. For example, the expression 3 + 5 * 2 generates a constant value of 13 after constant folding; when subsequent instructions with the same calculation result appear, the existing register can be directly reused. This implementation incorporates constants at the intermediate expression level into the register reuse system, avoiding the repeated generation of load instructions for equivalent constant expressions.

[0029] In the above embodiments, regardless of whether the numerical features originate from the immediate number field, the result of sign expansion, or the intermediate expression value after constant folding, they are all converted into a unified numerical representation to support consistency comparison and reuse judgment during the register allocation stage. This unified processing mechanism includes: numerical normalization; bit width alignment; and sign consistency processing. Through the above embodiments, the present invention can uniformly map constant values ​​from different compilation stages and different instruction forms into comparable numerical features, and combine this with dominance relationships for register reuse judgment, thereby avoiding duplicate register allocations due to different constant sources, improving register utilization and instruction execution efficiency.

[0030] In one embodiment, the dominance relationship includes: strict dominance relationship, weak dominance relationship, or a global dominance path based on SSA. In this embodiment, to ensure the semantic correctness of constant register reuse in complex control flow environments, the present invention introduces a multi-level dominance relationship determination mechanism during the register allocation stage. Based on different control flow structures and variable definition locations, an appropriate dominance relationship model is selected to avoid register misuse problems caused by path uncertainty.

[0031] In one implementation, when the definition points of the instruction containing the target operand and the corresponding constant in the candidate register are located in different basic blocks, a strict dominance relationship is used to determine the legality of register reuse. The strict dominance relationship is defined as follows: if basic block A appears on all control flow paths from the entry basic block to basic block B, and A ≠ B, then A strictly dominates B. The specific process is as follows: determine the basic block containing the definition point of the constant stored in the candidate register; determine the first basic block containing the target operand; determine whether the basic block containing the definition point strictly dominates the first basic block; if the strict dominance relationship is satisfied, it is determined that the constant in the register is always reachable within the first basic block and can be used as a reusable register. This implementation ensures that the constant has been defined on all execution paths, avoiding the use of uninitialized or overridden register values ​​in branch paths.

[0032] In another implementation, when the target operand and the candidate register's definition point are located within the same basic block, or when a local control flow order relationship exists, a weak dominance relationship is used for register reuse determination. The weak dominance relationship is defined as follows: if basic block A is located on at least one control flow path from the entry point to basic block B, or A and B are the same basic block, then A weakly dominates B. The specific process is as follows: determine whether the candidate register's definition point is located within the first basic block; determine whether the definition point instruction is executed before the instruction corresponding to the target operand; if the execution order relationship is satisfied, then the register is allowed to be reused within the current basic block. This implementation supports constant reuse within the same basic block, reduces the overly conservative restrictions caused by strict dominance relationships, and increases the chances of register reuse.

[0033] In another implementation, when the compiler uses an intermediate representation in the form of Static Single Assignment (SSA), this invention determines register reuse relationships based on the global dominance path in the SSA graph structure. SSA dominance path definition: In SSA form, each variable has only one unique definition point, and the usage point of a variable can be uniquely traced along the dominance path from its definition point. Specific process: Map the constant value in the candidate register to the definition node of the SSA variable; through the dominance tree structure of the SSA, determine whether the definition node is located on the global dominance path of the usage node corresponding to the target operand; if a dominance path exists from the definition node to the usage node, then the register can be reused. For example: A constant is defined in SSA node v1; the target operand usage point is located in SSA node v3; if v1 is located on the dominance path of v3, then the register can be safely reused. This implementation supports global constant reuse across basic blocks and across function paths, improving register utilization under complex control flow structures.

[0034] In this invention, the register allocation module can dynamically select between strict dominance, weak dominance, and global dominance paths under SSA (Strictly Defined Accounting) for different control flow scenarios, balancing the safety and allocation efficiency of register reuse. For example, strict dominance is preferred in complex branching scenarios; weak dominance is used in linear code segments; and SSA dominance paths are used in the global optimization phase of SSA. By introducing a multi-level dominance determination mechanism, this invention can flexibly adjust the constant register reuse strategy for different control flow structures, improving register reuse rate and reducing unnecessary register allocation and loading operations while ensuring the semantic correctness of the program.

[0035] In one embodiment, the determination of candidate registers further includes filtering based on the active range information, overflow risk, and register type. In this embodiment, to improve the reuse rate of constant registers while avoiding register conflicts and overflows, the present invention introduces a multi-dimensional filtering mechanism in the candidate register determination stage. This mechanism comprehensively considers the active range information of registers, potential overflow risks, and register type restrictions to screen the candidate register set, thereby improving the stability and execution efficiency of register allocation.

[0036] In one implementation, the present invention utilizes the active range information of the corresponding variables in the registers to perform a first round of filtering on candidate registers. The specific process is as follows: obtain the active range of the variables corresponding to the constant values ​​in each candidate register; determine the time point or instruction number corresponding to the instruction location where the target operand is located; determine whether the active range of the candidate registers covers the time point; for registers that have already ceased activity before the target operand's usage point, or registers that are about to be redefined after that usage point, remove them from the candidate register set. This implementation prevents the reuse of registers that are about to expire or be overwritten, ensuring the timing correctness of register reuse.

[0037] In another implementation, this invention introduces an overflow risk assessment mechanism during the candidate register filtering process to reduce the probability of overflows triggered by excessive register pressure. The specific process involves: counting the number of registers used within the current basic block or function range; assessing the expected occupancy time of each candidate register based on the subsequent usage frequency of the target operand; marking candidate registers with long expected occupancy times and falling within the high register pressure range as high overflow risk registers; and excluding high overflow risk registers from the candidate register set or reducing their reuse priority. This implementation reduces subsequent spill / load instructions caused by insufficient registers, improving overall code execution performance.

[0038] In another implementation, the present invention performs adaptability filtering on candidate registers based on the category attributes of registers in the target processor architecture. Examples of register categories include: general-purpose registers, floating-point registers, vector registers, read-only registers, and special-purpose registers. The specific process involves: determining the register category required for the target operand; judging whether the category of the candidate register matches the target operand type; and removing registers with mismatched categories or those constrained by hardware instructions from the candidate register set. This implementation avoids generating illegal instructions that do not conform to instruction constraints, improving the executableness of the generated code on the target architecture.

[0039] In this invention, the aforementioned active range filtering, overflow risk filtering, and register category filtering are not executed in isolation, but rather jointly filtered according to a preset order or dynamic strategy. For example, initial screening is performed based on register category; then reachability filtering is performed based on active range; and finally, optimization-level filtering is performed based on overflow risk. By introducing a multi-dimensional filtering mechanism based on active range, overflow risk, and register category, this invention can reduce conflicts and overflow risks during the register allocation stage while ensuring the correctness of register reuse, further reducing invalid register allocation and loading operations, thereby improving register utilization and code execution performance.

[0040] In one embodiment, the dynamically selected instruction allocation rules include: constant reuse rules; constant merging rules; constant cross-block reuse extension rules; and constant priority overriding rules. In this embodiment, the register allocation module presets multiple constant-related instruction allocation rules for cases where the target operand is a constant, and dynamically selects from these rules based on the numerical characteristics of the target operand, the control flow characteristics of the basic block it belongs to, and the current register state information. This improves the efficiency of constant register reuse and reduces register usage while ensuring the correctness of program semantics.

[0041] In one implementation, when a constant value matching the numerical characteristics of the target operand is detected in a candidate register, instruction allocation is performed using constant reuse rules. Triggering conditions: the target operand's type attribute is constant; a candidate register with numerical characteristics matching the target operand exists; the candidate registers satisfy dominance and active range constraints. Processing flow: a register with the same value is selected from the candidate register set; this register is directly allocated as the target register to the target operand; a target instruction using the register is generated, without generating a new constant loading instruction. This implementation avoids repeatedly loading the same constant, reducing the number of instructions and register usage.

[0042] In another implementation, a constant merging rule is used when the constant value of the target operand can be obtained from the value in an existing constant register through simple arithmetic. Triggering condition: A candidate register contains a constant value with a defined arithmetic relationship to the target operand; this arithmetic relationship can be completed within a single or a few instructions. Processing flow: Determine whether the constant value of the target operand can be obtained from the constant value in the candidate register through addition, subtraction, shifting, or bitwise operations; if feasible, generate a derived instruction based on the candidate register; use the derived result register as the target register. Example: The existing register contains a constant value of 8; the target operand constant value is 16; the target constant is generated by left-shifting by one bit. This implementation reduces the loading of new constants and increases the reuse value of existing constants.

[0043] In another implementation, when the base block containing the target operand and the candidate register constant definition point are not in the same base block, a constant cross-block reuse extension rule is adopted. Triggering conditions: the constant definition point in the candidate register is located in the preceding base block; the base block containing the definition point dominates the base block containing the target operand; the candidate register has not been redefined in the cross-block path. Processing flow: the dominance relationship between the candidate register definition point and the target base block is determined based on the control flow graph; the activity of the candidate register in the cross-block path is verified; if the conditions are met, the register is allowed to be reused in the target base block. This implementation supports constant register reuse across base blocks, reducing the instruction overhead of repeated cross-block loading.

[0044] In another implementation, when multiple candidate registers meet the criteria, a constant priority overriding rule is used for final selection. Triggering conditions: multiple candidate registers with identical or derived values ​​exist; current register resources are limited or under high pressure. Processing flow: Priorities are assigned to each candidate register based on the expected number of reuses, active range length, and overflow risk; the register with the highest priority is selected as the target register; lower-priority candidate registers maintain their original allocation or have their reuse delayed. This implementation avoids increased register pressure due to blind reuse, balancing short-term performance gains with long-term register occupancy.

[0045] In this invention, the aforementioned constant reuse rules, constant merging rules, constant cross-block reuse extension rules, and constant priority override rules are not executed in a fixed manner, but are dynamically selected or combined based on the characteristics of the target operand and the register state. For example: constant reuse rules are preferred for operands within the same block with consistent values; constant merging rules are used for operands that can be derived but are inconsistent; cross-block reuse extension rules are used for operands across blocks but satisfying the dominance relationship; and priority override rules are used for multiple candidate conflicts. By introducing various constant-related instruction allocation rules and dynamically selecting them, this invention can flexibly adjust the constant register allocation strategy for different control flows and register states, maximizing the degree of constant reuse while ensuring semantic correctness, reducing unnecessary register allocation and loading operations, thereby improving overall code execution performance.

[0046] In one embodiment, the conflict detection includes mechanisms for detecting at least one of the following: register write-after-read conflict, read-after-write conflict, risk of impending overflow, and value overwriting conflict across basic blocks. In this embodiment, to avoid introducing data dependency errors or register resource anomalies when reusing constant operands in registers, the present invention performs conflict detection on candidate registers before determining the target register, in order to identify conflict situations that may affect the semantic correctness and execution stability of the program in advance.

[0047] In one implementation, the present invention detects read-after-write conflicts by analyzing the usage of candidate registers in the current basic block and its successor basic blocks. When an instruction corresponding to the target operand performs a write operation on a candidate register, and a read-after-write instruction still exists after the write operation, the candidate register is determined to have a read-after-write conflict and is excluded from the set of reusable registers. This implementation prevents the original register value from being incorrectly used by subsequent instructions after it has been overwritten.

[0048] In another implementation, the present invention detects whether a candidate register is overwritten by a write operation before its current value has been fully read. When the constant value in the candidate register still needs to be read in a subsequent instruction, and the instruction corresponding to the target operand plans to perform a write operation on that register, a read-write conflict is determined, thereby prohibiting the reuse of that register. This implementation avoids destroying constant values ​​that are still in use, ensuring the correctness of the instruction execution order.

[0049] In another implementation, the present invention detects the risk of an impending register overflow by assessing the current register usage pressure. When the number of registers used within the current basic block or function range exceeds a preset threshold after allocating the target register, an overflow risk is determined, and the reuse priority of candidate registers is reduced or other registers are selected to avoid triggering the overflow. This implementation reduces the additional load and store instructions introduced by register overflows.

[0050] In another implementation, when the definition point of a constant in a candidate register is located in a different base block than the instruction containing the target operand, this invention performs cross-base block value overwriting conflict detection. If a redefinition operation of the register exists on any control flow path from the candidate register definition point to the target base block, it is determined that the candidate register has a cross-base block value overwriting conflict, thereby prohibiting the reuse of the register in the target base block. This implementation ensures the semantic consistency of cross-base block register reuse across all execution paths.

[0051] In this invention, the various conflict detection mechanisms described above can be executed independently or in combination. Once any conflict is detected, the reuse judgment of the corresponding candidate register is terminated to ensure the correctness and stability of the register allocation result. By introducing detection mechanisms for multiple conflict types during the register allocation stage, this invention can effectively avoid potential data dependency errors and register overflow problems while improving the constant register reuse rate, thereby improving the execution correctness and performance stability of the generated code.

[0052] In one embodiment, the priority ranking is based on at least one of the following: the current usage frequency of the register, the expected number of times the constant value in the register is reused, and the access cost of the register category. In this embodiment, when there are multiple candidate registers that meet the reuse conditions, the present invention constructs a priority ranking mechanism to sort and select candidate registers, so as to further reduce register pressure and improve the overall benefits of constant reuse while ensuring the correctness of register allocation.

[0053] In one implementation, the present invention sorts candidate registers based on their usage frequency within the current function or basic block. Specifically, it counts the number of times each candidate register is referenced within the current function or a preset window; registers with lower usage frequency are assigned higher reuse priority; and registers with lower usage frequency are preferentially selected as target registers in the sorting results. This implementation avoids frequently used registers being occupied for extended periods, reducing contention for high-frequency registers in subsequent instructions.

[0054] In another implementation, the present invention prioritizes the constant values ​​stored in candidate registers based on their expected reuse frequency in subsequent instructions. Specifically, it analyzes the basic block containing the target operand and its successor basic blocks; predicts the number of times the constant values ​​in each candidate register will be used in subsequent instructions; and assigns higher priority to registers with higher expected reuse frequencies. This implementation maximizes the reuse benefits of individual constant values ​​and reduces the number of instructions that repeatedly load the same constant.

[0055] In another implementation, the present invention prioritizes candidate registers based on the access cost of different register categories under the target processor architecture. Examples of register categories include: general-purpose registers, special-purpose registers, and read-only or restricted registers. Specifically, the register category to which the candidate registers belong is obtained; access cost weights are assigned to different register categories based on information such as access latency and instruction restrictions of the target processor architecture; registers with lower access costs are assigned higher reuse priority. This implementation prioritizes the use of registers with low access costs, avoiding the occupation of register resources with high access costs or restrictions.

[0056] In this invention, the aforementioned register usage frequency, expected reuse count of constant values, and register category access cost can be used individually or combined according to preset weights to form a comprehensive priority score. For example: Priority score = α × (expected reuse count) β × (usage frequency) γ × (access cost), where α, β, and γ are preset weight parameters. By introducing a priority ranking mechanism based on multi-dimensional indicators, this invention can make more reasonable choices among multiple reusable registers, reduce register conflicts and overflow risks, and further improve the effectiveness of constant register reuse and overall code execution performance.

[0057] In one embodiment, if there is no reusable register that satisfies the dominance constraint, an idle register is allocated according to the spare rule, and a local overflow strategy is triggered if necessary.

[0058] In one embodiment, a mapping between constant values ​​and their definition points is maintained in the register status table to support fast reuse judgment of constant operands in subsequent instructions.

[0059] In one embodiment, the method performs constant priority matching by hardware-specific register categories (such as immediate registers, read-only registers, etc.) to reduce the use of general-purpose registers.

[0060] Optionally, embodiments of the present invention may further include the following steps: Step 201: If the type attribute of the target operand is a variable, determine the target register corresponding to the target operand based on the first register set.

[0061] In this embodiment of the invention, when the type attribute of the target operand is a variable, a register can be directly selected and allocated as the target register from the first register set. The first register set can be the intersection of the current set of free registers and the set of allocable registers; that is, the registers included in the first register set belong to both the free register set and the allocable register set. The free register set can be registers that are currently not in use, and the allocable registers can be registers that can theoretically be allocated to references of the currently processed instruction. The allocable registers can be determined based on the matching between the type and purpose of different registers and the currently processed instruction. For example, if the variable of the processed instruction is a function parameter, the corresponding allocable register is determined to be the parameter register; if the type of the variable of the processed instruction is floating-point, the corresponding allocable register is determined to be the floating-point register. Through intersection operations, it can be ensured that the selected register is both in a free state and meets the allocability condition, avoiding register conflicts and ensuring the stability of variable storage.

[0062] For example, suppose there are 10 registers from 0 to 9, where {0,1,2,3,4} have been allocated and {5,6,7,8,9} are free registers. For the instruction to be processed that requires register allocation, theoretically the set of allocable registers includes registers {3,4,5,6}. Therefore, the first set of registers can include the intersection of {3,4,5,6} and {5,6,7,8,9}, that is, the first set of registers includes register 5 and register 6.

[0063] Based on the first set of registers, a register is selected from the first set of registers as the target register corresponding to the target operand. For example, the register is selected from the first set of registers by random selection or by selection according to a preset selection rule, such as selecting from the most significant bit downwards.

[0064] In this embodiment of the invention, when the type attribute of the target operand is a variable, the target register corresponding to the target operand is determined based on the first register set. By dividing the first register set, registers that meet the requirements can be filtered out, reducing the invalid search range, speeding up the register allocation speed, and improving the instruction processing efficiency.

[0065] Optionally, embodiments of the present invention may further include the following steps: Step 301: Update the reference index value corresponding to the target register in the reference index array to the target operand.

[0066] In this embodiment of the invention, a reference index array (such as regref) is pre-created. This reference index array can be used to record the relationship between registers and intermediate code references. The structure of the reference index array can include an index and its corresponding value. The index represents the physical register number, and the value is the intermediate code reference corresponding to the register currently allocated to the intermediate code. The initial value can be 0 or null. The initial value means that when the program starts running, the register has not yet been allocated to the intermediate code and is in an unused state. The array type can be IRref, representing an intermediate code reference. The intermediate code reference ref can be in the form of the number 0001 or 1, or it can be the identifier v1, etc. Through this reference, the corresponding intermediate code object can be located directly or indirectly. Based on the located intermediate code object, the basic block in which the intermediate code is located can be further determined. A basic block is a basic unit in the program control flow graph, which contains a series of sequentially executed statements. By checking the dominance relationship between basic blocks, it can be determined whether there is data flow between any two instructions. If basic block A dominates basic block B, it means that in the program's control flow, every path from the program's start point to basic block B must pass through basic block A. In this case, all values ​​defined in basic block A can flow to basic block B, meaning that basic block B can use the data defined in basic block A.

[0067] When the type attribute of the target operand is a variable, after determining the target register corresponding to the target operand, update the reference index value of the target register in the reference index array to the target operand.

[0068] In this embodiment of the invention, a reference index array can be set to record the correspondence between registers and operands, facilitating rapid querying and tracing. Furthermore, by updating the reference index values ​​in a timely manner, it is ensured that the array information is synchronized with the actual register allocation in real time, avoiding register misuse or data errors caused by information lag, improving instruction execution accuracy, optimizing the variable register allocation process, and enhancing the overall system operating efficiency and stability.

[0069] Optionally, step 102 may include the following steps: Step 401: Determine the allocated registers based on the set of allocable registers corresponding to the instruction to be processed.

[0070] In this embodiment of the invention, the set of allocable registers corresponding to the instruction to be processed may include allocated registers and unallocated registers. Based on the set of allocable registers corresponding to the instruction to be processed, the registers that have been allocated in the set of allocable registers are determined as allocated registers. For example, assuming that the set of allocable registers corresponding to the instruction to be processed contains registers {5,6,7,8,9}, where registers {5,6,7} are unallocated registers and registers {8,9} are allocated registers, then the allocated registers can be determined as {8,9}.

[0071] Step 402: For any of the allocated registers, obtain the constant index value corresponding to the allocated register according to the numerical index array.

[0072] In this embodiment of the invention, a numerical index array is pre-created. The structure of the numerical index array may include an index and its corresponding value. The index is used to represent the physical register number, and the value is the constant value stored in the register currently allocated to the constant. The initial values ​​can all be set to 0.

[0073] Find the constant index value corresponding to the allocated register based on the numerical index array.

[0074] Step 402: Obtain the reference index value corresponding to each of the allocated registers based on the reference index array.

[0075] In this embodiment of the invention, the reference index value corresponding to the allocated register is found according to the reference index array.

[0076] Step 403: If the value of the target operand is the same as the constant index value corresponding to the allocated register and the second basic block where the reference index value corresponding to the allocated register is located dominates the first basic block, then the instruction allocation rule matching the target operand is determined to be the first allocation rule.

[0077] In this embodiment of the invention, after determining the constant index value and reference index value corresponding to the allocated register, the second basic block where the reference index value is located is determined based on the reference index value corresponding to the allocated register. If the value of the target operand is the same as the constant index value corresponding to the allocated register, and the second basic block where the reference index value corresponding to the allocated register is located dominates the first basic block, then the instruction allocation rule matching the target operand can be determined as the first allocation rule.

[0078] If the value of the target operand and its corresponding dominance conditions satisfy the preset allocation conditions—that is, if the value of the target operand is the same as the constant index value of the allocated register—then the allocated register can be reused without affecting the logical structure of the code or data flow. Therefore, the instruction allocation rule matching the target operand can be determined as the first allocation rule.

[0079] Accordingly, step 103 may include the following steps: Step 404: Based on the first allocation rule, determine the allocated register as the target register.

[0080] In this embodiment of the invention, allocated registers that meet preset allocation conditions are directly determined as target registers allocated to the target operand. That is, allocated registers whose constant index value is the same as the value of the target operand and whose second basic block can control the first basic block where the target operand is located are directly determined as the target registers corresponding to the target operand.

[0081] In this embodiment of the invention, allocated registers are determined based on the set of allocable registers for the instruction to be processed, and corresponding values ​​are obtained using a numerical index array and a reference index array. When the target operand value is the same as the constant index value of the allocated register and the second basic block containing the reference index value dominates the first basic block, the allocated register is reused as the target register. This eliminates the need to re-execute the numerical loading operation during the register allocation process for the target operand, avoids repeatedly allocating new registers for the same operand, reduces the number of registers used, and improves register utilization. Furthermore, since reusing registers eliminates the need for additional data transfer operations, instruction execution efficiency is improved.

[0082] Optionally, step 102 may also include the following steps: Step 501: For any of the allocated registers, if the value of the target operand is different from the constant index value in the allocated register, and / or the second basic block where the reference index value corresponding to the allocated register is located cannot dominate the first basic block, then the instruction allocation rule matching the target operand is determined to be the second allocation rule.

[0083] In this embodiment of the invention, when the type attribute of the target operand is constant, for each allocated register in the allocatable register set, it is determined whether the allocated register meets the preset allocation conditions. If, for any allocated register, at least one sub-condition of the preset allocation conditions is not met—that is, for any allocated register: the constant index value of the allocated register is different from the value of the target operand, and / or the second basic block where the reference index value of the allocated register is located cannot dominate the first basic block—then the instruction allocation rule matching the target operand is determined to be the second allocation rule. If none of the allocated registers meet the preset allocation conditions, then the instruction allocation rule matching the target operand is determined to be the second allocation rule.

[0084] Accordingly, step 103 may include the following steps: Step 502: Based on the second allocation rule and the first register set, determine the target register corresponding to the target operand.

[0085] In this embodiment of the invention, if none of the allocated registers meet the preset allocation conditions, the target register corresponding to the target operand is determined based on the first register set according to the second allocation rule. That is, if the allocated registers do not meet the preset allocation conditions and cannot be reused, the target register corresponding to the target operand can be determined based on the first register set using a conventional register allocation method.

[0086] In this embodiment of the invention, when the value of the target operand is different from the constant index value in the allocated register, and / or the reference index value corresponding to the allocated register is in a second basic block that cannot dominate the first basic block, a second allocation rule is adopted to determine the target register based on the first register set. This ensures that in scenarios where the allocated register cannot be reused, a suitable register can be accurately allocated to the target operand according to a conventional and reliable register allocation mechanism, thus guaranteeing the correctness and stability of instruction execution and enabling the system to efficiently and reliably complete the register allocation task under different conditions.

[0087] Optionally, after step 502, the embodiments of the present invention may further include the following steps: Step 601: Update the constant index value of the target register in the numerical index array to the value corresponding to the target operand.

[0088] In this embodiment of the invention, after allocating the target register to the target operand, the constant index value of the target register in the value index array can be updated to the value corresponding to the target operand. For example, for the target operand v0, the value of the register identifier (e.g., regn) at the index corresponding to the target register in the value index array regconst can be updated to the value corresponding to the target operand (assuming it is const_v0), that is, regconst[regn]=const_v0 is executed.

[0089] Step 602: Update the reference index value of the target register in the reference index array to the target operand.

[0090] In this embodiment of the invention, the reference index value of the target register in the reference index array is updated to the target operand. For example, for the target operand v0, the value of the register identifier (e.g., regn) corresponding to the target register in the reference index array regref can be updated to the target operand (e.g., v0), that is, regref[regn]=v0 is executed.

[0091] In this embodiment of the invention, after determining the target register based on the first register set according to the second allocation rule, the constant index value of the target register in the numerical index array is updated to the value corresponding to the target operand in a timely manner, and the reference index value in the reference index array is updated to the target operand. This ensures that the numerical index array, the reference index array, and the actual register usage status are synchronized in real time. During subsequent instruction processing, registers can be quickly matched and allocated based on the updated information, thereby optimizing the entire register allocation process.

[0092] Optionally, embodiments of the present invention may further include the following steps: Step 701: Obtain the set of free registers and the set of allocable registers corresponding to the target operand.

[0093] In this embodiment of the invention, a set of free registers and the allocatable registers corresponding to the target operand are predefined. The set of free registers and the allocatable registers can be determined based on the state division of each register on the target platform. A code structure is pre-created and initialized, using `freeset` to represent the currently actually free set of registers. `freeset` can be a 64-bit unsigned integer, with each bit corresponding to one physical register, meaning it can represent up to 64 registers. A bit value of 1 indicates that the register is in a free state, and a bit value of 0 indicates that the register is occupied. For example, when `freeset = 0xfffffff6` (i.e., the binary form is "...1111110110", where the lower 4 bits are "0110"), this indicates that registers 0 and 3 are in a non-free state, while the other registers are in a free state. `allowset` is used to represent the theoretically allocatable set of registers. Similarly, each bit can correspond to one physical register, with a bit value of 1 indicating that the register is allocatable, and a bit value of 0 indicating that the register is not allocatable.

[0094] For example, a structure like the one shown below can be created and initialized: struct { int regnum; int64_t regconst[regnum]; IRref regref[regnum]; uint64_t freeset; uint64_t allowset; } The fields can be interpreted as follows: `regnum` represents the number of general-purpose physical registers on the target platform. `regconst` represents a numerical index array, where the index represents the physical register number and the value is the constant value currently allocated to the register. `regref` represents a reference index array, where the index represents the physical register number and the value is the intermediate code reference corresponding to the register currently allocated to the intermediate code corresponding to the target operand. `freeset` represents the set of currently available free registers. `allowset` represents the set of currently theoretically allocable registers.

[0095] Step 702: Determine the first register set based on the intersection of the free register set and the allocatable register set.

[0096] In this embodiment of the invention, a first register set is determined based on the intersection of the set of free registers and the set of allocable registers. That is, registers that are in both the set of free registers and the set of allocable registers are determined as the first register set.

[0097] In this embodiment of the invention, by obtaining the set of free registers and the set of allocable registers corresponding to the target operand, and determining the first set of registers based on the intersection of the two, registers that are both free and allocable can be filtered out. This allows for allocation from the first set of registers, which can improve the success rate and rationality of register allocation, reduce subsequent operational errors caused by improper register selection, and thus improve the overall operating efficiency and stability of the system.

[0098] For example, the complete method of register allocation according to an embodiment of the present invention can be as follows: 1. Traverse all basic blocks in the control flow graph.

[0099] 2. Traverse all instructions in each basic block.

[0100] 3. For any instruction to be processed, for example, the format could be: v2<=op v0, v1, check whether the target operand v0 has been allocated a register: 3.1 If v0 has already been allocated a register, there is no need to reallocate the register; the already allocated register can be used directly as the target register for the target operand.

[0101] 3.2 If it has not yet been allocated, further check whether v0 is a constant: 3.2.1 If v0 is a variable, then a register is selected from the first register set, which is the set of free and allocable registers in the current state (freeset & allowset), for allocation. Assuming the target register is regn, after allocation, the value at index regn in the reference index array regref is updated to v0, that is, regref[regn] = v0 is executed; 3.2.2 If v0 is a constant, iterate through the theoretically allocatable registers (allowset) in the current state and find the corresponding value constn and reference refn in the arrays regconst and regref. Only when the following preset allocation conditions are met simultaneously can an allocated register satisfying the preset allocation conditions be assigned to the target operand v0, without needing to reload the value of v0 into regn. The preset allocation conditions can be: a) The value of v0 is equal to constn; b) The basic block containing refn can dominate the basic block containing v0.

[0102] 3.2.3 If v0 is a constant, but no register satisfying the above-mentioned preset allocation conditions is found, then a register is allocated for v0 based on the first register set, i.e., from the free and allocable register sets (freeset & allowset). Meanwhile, assuming the target register is regn, the following operations are performed: a) Update the value of the array regref at index regn to v0, that is, execute regref[regn] = v0.

[0103] b) Update the value at index regn in the array regconst to the constant value of v0 (assuming it is const_v0), that is, execute regconst[regn] = const_v0.

[0104] 4. Check whether operand v1 and result v2 need to be allocated registers. Following the same steps as v0 (3.2.1 to 3.2.3), allocate the corresponding registers for v1 and v2 in sequence.

[0105] For example, suppose the following code is intermediate code of a program generated by a compiler, i.e., the code to be processed. Based on the register allocation method of this embodiment of the invention, the corresponding machine instructions are generated. Assume the code is as follows: b0: v0<= kint 0xffff v1<= load #4 br v1, b1, b2 b1: v2<= add v0, v1 v3<= mul v2, 0xff00 br b3 b2: v4 <= mul v1, 0xffff v5 <= add v4, 0xff00 br b3 b3: ret Assume the target chip has 32 general-purpose physical registers, of which 16 are general-purpose registers and 16 are floating-point registers. Among the general-purpose registers, register 0 always has a value of 0, register 1 is used to store the return address, and register 3 is used as the stack base. Based on this characteristic, the register parameters can be initialized as follows: 1) Setting regnum to 16 means providing 16 general-purpose physical registers.

[0106] 2) The lengths of the regconst and regref arrays are both 16, which store the mapping relationship between constant values ​​in registers and intermediate code variable references, respectively, and their initial values ​​are both 0.

[0107] 3) The freeset uses bits to indicate the usage of registers, where bits 0-15 represent 16 general-purpose registers and bits 16-31 represent 16 floating-point registers. Since general-purpose registers 0, 1, and 3 are already in use, the freeset is initialized to 0xfffffff4.

[0108] 4) allowset represents the set of currently available registers. Assuming this scheme does not use floating-point registers, allowset can be initialized to 0xffff.

[0109] Next, the above example code will be applied instruction by instruction to the register allocation method provided in this embodiment of the invention: When traversing the instructions in basic block b0, v0 is processed first. The only target operand of v0 is the constant 0xffff, therefore a register needs to be allocated for v0. At this point, freeset = 0xfffffff4, allowset = 0xffff, and freeset&allowset = 0xfff4. Since this is the first time a register is allocated for v0, and it is a constant, we can first traverse regref and regconst based on the register indices in allowset, finding that all elements corresponding to the register indices are 0. A register is allocated from the first register set, i.e., the freeset&allowset set. Assuming the rule of selecting from the most significant bit downwards, general-purpose register number 15 is allocated to v0. regref is updated to {15:v0}, and regconst is updated to {15:0xffff}.

[0110] Next, process v1. v1 is a variable, currently freeset=0xffff7ff4, allowset=0xffff, and freeset&allowset=0x7ff4. Based on the first register set, i.e., freeset&allowset, allocate register 14 for v1. Update regref to {15:v0,14:v1}.

[0111] When traversing the instructions to be processed in basic block b1, the target operand v2 is processed first. v2 is a variable whose two operands v0 and v1 have been allocated registers. At this time, freeset = 0xffff3ff4, allowset = 0xffff, and freeset&allowset = 0x3ff4. Based on the first register set, i.e., freeset&allowset, register 13 is allocated for v2, and regref is updated to {15:v0, 14:v1, 13:v2}.

[0112] Then v3 is processed. v3 is a variable whose operands include the variable v2 in the allocated register and the constant 0xff00. After iterating through regconst, no value equal to 0xff00 is found, so a new register needs to be allocated for 0xff00 based on the first register set. At this point, freeset = 0xffff1ff4, allowset = 0xffff, and freeset&allowset = 0x1ff4. Register 12 is then allocated to the constant 0xff00, and regconst is updated to {15:0xffff, 12:0xff00}. Since the constant 0xff00 has no direct reference, its result is used to reference v3, so regref can be updated to {15:v0, 14:v1, 13:v2, 12:v3}.

[0113] Then, a register is allocated for the target operand v3. Currently, freeset=0xffff0ff4, allowset=0xffff, and freeset&allowset=0x0ff4. Based on the first register set, register 11 is allocated to v3. regref is updated to {15:v0, 14:v1, 13:v2, 12:v3, 11:v3}.

[0114] When traversing the instructions to be processed in basic block b2, v4 is processed first. v4 is a variable whose operands include the variable v1 in the allocated register and the constant 0xffff. After traversing regconst, it is found that the constant index value stored in register 15 is equal to the constant 0xffff, and the reference corresponding to regref

[15] is v0. Basic block b0, where v0 is located, can dominate basic block b2, so register 15 can be reused directly. Then, registers are allocated for v4. Currently, freeset=0xffff07f4, allowset=0xffff, freeset&allowset=0x07f4, and register 10 is allocated to v4. regref is updated to {15:v0,14:v1,13:v2,12:v3,11:v3,10:v4}.

[0115] Next, v5 is processed. v5 is a variable whose operands include the variable v4 in the allocated register and the constant 0xff00. After traversing regconst, it is found that the constant index value stored in register 12 is equal to the constant 0xff00, but the reference corresponding to regref

[12] is v3, and the basic block b1 where v3 is located cannot dominate the basic block b2. Therefore, register 12 cannot be reused directly, and a register needs to be reallocated for the constant 0xff00. At this time, freeset=0xffff03f4, allowset=0xffff, freeset&allowset=0x03f4. Based on the first register set, register 9 is allocated to the constant 0xff00, and regconst is updated to {15:0xffff,12:0xff00,9:0xff00}. Then, a register is allocated for the target operand v5, and regref is updated to {15:v0, 14:v1, 13:v2,12:v3,11:v3,10:v4, 9:v5}.

[0116] Finally, after traversing the instructions in basic block b3, it was found that there were no instructions in this basic block that required register allocation. At this point, the register allocation for the aforementioned code to be processed was complete.

[0117] Figure 2 This is a schematic diagram of a register allocation device provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the device may specifically include: The first determining module 801 is used to determine the type attribute of the target operand for any instruction to be processed, in the case that no register is allocated to the target operand of the instruction to be processed. The second determining module 802 is used to determine the instruction allocation rule matching the target operand based on the comparison result between the value of the target operand and the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block where the target operand is located, when the type attribute of the target operand is a constant. The third determining module 803 is used to determine the target register corresponding to the target operand based on the instruction allocation rules.

[0118] This invention provides a register allocation apparatus. For any instruction to be processed, if the target operand of the instruction has not been allocated a register, the type attribute of the target operand is determined. If the type attribute of the target operand is constant, an instruction allocation rule matching the target operand is determined based on the comparison result of the value of the target operand with the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block in which the target operand is located. Based on the instruction allocation rule, the target register corresponding to the target operand is determined. In this way, by comparing the value of the target operand with the constant values ​​in each allocated register, and combining the relevant dominance relationship of the first basic block in which the target operand is located, the instruction allocation rule matching the target operand is dynamically selected, optimizing the constant register allocation process, avoiding unnecessary register allocation, reducing unnecessary value loading operations and the number of registers occupied, improving instruction execution efficiency, and simultaneously improving register utilization and code execution performance.

[0119] Optionally, the method further includes: The fourth determining module is used to determine the target register corresponding to the target operand based on the first register set, when the type attribute of the target operand is a variable.

[0120] Optionally, the device further includes: The first update module is used to update the reference index value corresponding to the target register in the reference index array to the target operand.

[0121] Optionally, the second determining module 802 includes: The first determining submodule is used to determine the allocated registers based on the set of allocable registers corresponding to the instruction to be processed; The first acquisition module is used to acquire, for any of the allocated registers, the constant index value corresponding to the allocated register according to the numerical index array; The second acquisition module is used to acquire the reference index value corresponding to the allocated register based on the reference index array; The second determining submodule is used to determine the instruction allocation rule that matches the target operand as the first allocation rule if the value of the target operand is the same as the constant index value corresponding to the allocated register and the second basic block where the reference index value corresponding to the allocated register is located dominates the first basic block. The third determining module 803 includes: The third determining submodule is used to determine the allocated register as the target register based on the first allocation rule.

[0122] Optionally, the second determining module 802 further includes: The fourth determination submodule is used to determine the instruction allocation rule matching the target operand as the second allocation rule if, for any of the allocated registers, the value of the target operand is different from the constant index value in the allocated register, and / or the second basic block where the reference index value corresponding to the allocated register is located cannot dominate the first basic block. The third determining module 803 includes: The fifth determining submodule is used to determine the target register corresponding to the target operand based on the first register set according to the second allocation rule.

[0123] Optionally, the device further includes: The second update module is used to update the constant index value of the target register in the numerical index array to the numerical value corresponding to the target operand; The third update module is used to update the reference index value of the target register in the reference index array to the target operand.

[0124] Optionally, the device further includes: The third acquisition module is used to acquire the set of free registers and the set of allocable registers corresponding to the target operand; The fifth determining module is used to determine the first register set based on the intersection of the free register set and the allocatable register set.

[0125] The present invention also provides an electronic device, see [link to relevant documentation]. Figure 3 It includes: a processor 901, a memory 902, and a computer program 9021 stored in the memory and executable on the processor. When the processor executes the program, it implements the register allocation method of the foregoing embodiments.

[0126] The present invention also provides a readable storage medium that, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to perform the register allocation method of the foregoing embodiments.

[0127] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0128] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0129] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0130] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0131] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0132] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or apparatus program for performing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0133] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0134] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0135] It should be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0136] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A register allocation method, characterized in that, The method includes: For any instruction to be processed, if no register is allocated to the target operand of the instruction to be processed, determine the type attribute of the target operand; When the type attribute of the target operand is constant, the instruction allocation rule matching the target operand is determined based on the comparison result between the value of the target operand and the constant values ​​in each allocated register, as well as the relevant dominance relationship of the first basic block where the target operand is located. Based on the instruction allocation rules, the target register corresponding to the target operand is determined.

2. The method according to claim 1, characterized in that, The method further includes: If the type attribute of the target operand is a variable, the target register corresponding to the target operand is determined based on the first register set.

3. The method according to claim 2, characterized in that, When the type attribute of the target operand is a variable, after determining the target register corresponding to the target operand based on the first register set, the method further includes: Update the reference index value corresponding to the target register in the reference index array to the target operand.

4. The method according to claim 1, characterized in that, The determination of the instruction allocation rule matching the target operand, based on the comparison results between the value of the target operand and the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block where the target operand is located, includes: Based on the set of allocable registers corresponding to the instruction to be processed, the allocated registers are determined; For any of the allocated registers, obtain the constant index value corresponding to the allocated register based on the numerical index array; Based on the reference index array, obtain the reference index value corresponding to the allocated register; If the value of the target operand is the same as the constant index value corresponding to the allocated register, and the second basic block where the reference index value corresponding to the allocated register is located dominates the first basic block, then the instruction allocation rule matching the target operand is determined to be the first allocation rule. The step of determining the target register corresponding to the target operand based on the instruction allocation rule includes: Based on the first allocation rule, the allocated register is determined as the target register.

5. The method according to claim 4, characterized in that, The step of determining the instruction allocation rule matching the target operand based on the comparison results between the value of the target operand and the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block where the target operand is located, further includes: For any of the allocated registers, if the value of the target operand is different from the constant index value in the allocated register, and / or the second basic block where the reference index value corresponding to the allocated register is located cannot dominate the first basic block, then the instruction allocation rule matching the target operand is determined to be the second allocation rule. The step of determining the target register corresponding to the target operand based on the instruction allocation rule includes: According to the second allocation rule, the target register corresponding to the target operand is determined based on the first register set.

6. The method according to claim 5, characterized in that, After determining the target register corresponding to the target operand based on the first register set according to the second allocation rule, the method further includes: Update the constant index value of the target register in the numerical index array to the value corresponding to the target operand; Update the reference index value of the target register in the reference index array to the target operand.

7. The method according to claim 1, characterized in that, The method further includes: Obtain the set of free registers and the set of allocable registers corresponding to the target operand; The first register set is determined based on the intersection of the set of free registers and the set of allocable registers.

8. The method according to claim 1, characterized in that, The dynamically selected instruction allocation rules include at least one of the following: constant reuse rules; constant merging rules; constant cross-block reuse extension rules; constant priority overriding rules.

9. The method according to claim 8, characterized in that, Before determining the target register corresponding to the target operand based on the instruction allocation rule, the method further includes performing conflict detection on the candidate register. The conflict detection is used to detect at least one of the following: register write-after-read conflict; register read-after-write conflict; risk of register overflow; value overwrite conflict across basic blocks.

10. The method according to claim 9, characterized in that, In the presence of multiple candidate registers, the candidate registers are prioritized based on at least one of the following: the current frequency of use of the register; the expected number of times the constant value in the register is reused; and the access cost of the register class.

11. A register allocation device, characterized in that, The device includes: The first determining module is used to determine the type attribute of the target operand for any instruction to be processed, in the case that no register is allocated to the target operand of the instruction to be processed; The second determining module is used to determine the instruction allocation rule matching the target operand, based on the comparison result between the value of the target operand and the constant values ​​in each allocated register, and the relevant dominance relationship of the first basic block where the target operand is located, when the type attribute of the target operand is a constant. The third determining module is used to determine the target register corresponding to the target operand based on the instruction allocation rules.

12. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the register allocation method as described in any one of claims 1-10.

13. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the register allocation method according to any one of claims 1-10.

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