Interrupt and exception cooperative processing method suitable for supporting RISC-V vector extension processor
By adopting a system architecture that decouples the CPU and VPU and implementing hierarchical interrupt handling, the resource consumption, execution timing complexity, and interrupt handling challenges of the RISC-V vector extension processor are solved. This achieves efficient and lightweight exception and interrupt management, improving system performance and consistency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING YINGQI INTELLIGENT TECH CO LTD
- Filing Date
- 2026-01-20
- Publication Date
- 2026-05-12
AI Technical Summary
Existing RISC-V vector extension processors have problems in terms of resource consumption, execution timing complexity, hindered resource reclamation, and lack of vector-aware interrupt handling strategies, which leads to increased hardware complexity, decreased execution performance, and increased difficulty in exception handling.
The system adopts a collaborative and decoupled system architecture between the CPU and VPU. An exception detection module dynamically monitors exception events in both the VPU and CPU and processes them uniformly during the instruction submission phase. Combined with an interrupt level-based handling mechanism, it achieves lightweight and precise exception and interrupt management.
In high-concurrency vector operation scenarios, this approach reduces hardware overhead, improves system performance and throughput, ensures consistency of calculation results and semantic correctness of the program, and simplifies debugging and verification processes.
Smart Images
Figure CN122019151A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of general-purpose processor technology, and in particular to a method for co-processing interrupts and exceptions suitable for RISC-V vector extension processors. Background Technology
[0002] As an open-source, modular instruction set architecture, RISC-V's Vector Extension (RVV) provides significant flexibility for integrating high-performance computing units, particularly in superscalar microarchitecture design, where it has garnered widespread attention and research. With the introduction of RISC-V Vector Extension, processors have gained powerful capabilities for data-level parallel computing, making them especially suitable for high-performance computing fields such as artificial intelligence inference, image processing, and scientific computing. To adapt to this trend, an increasing number of processor architectures integrate Vector Processing Units (VPUs) to support high-throughput vector computation. However, the introduction of vector processing logic reveals the following prominent shortcomings in the original mechanism:
[0003] High resource consumption and increased hardware complexity: Vector instructions typically involve a large number of sub-operations, and their execution and state management granularity is much higher than that of scalar instructions. To support precise exception handling for these sub-operations, traditional reorder buffers (ROBs) need to expand their capacity and introduce more state tracking and exception marking logic, significantly increasing hardware area and power consumption, resulting in increased implementation complexity.
[0004] The complex execution timing and the difficulty in precise exception handling: In superscalar out-of-order processors, the out-of-order issuance and commit of instructions already present timing control challenges. The introduction of the VPU, with its decoupled execution model and multi-cycle instruction characteristics, further disrupts commit boundaries, making it extremely complex to ensure consistent instruction commit order and precise exception handling. Traditional methods often require adding extra control paths, extending the timing of critical paths and impacting overall execution performance.
[0005] Resource reclamation is hindered, impacting throughput: Due to the long duration of vector operations, their corresponding resources (such as execution units, registers, and status queues) are difficult to release in a timely manner. If interrupts cannot be processed within a reasonable time, they not only occupy critical hardware resources but may also block the issuance of subsequent instructions, severely limiting overall throughput and system responsiveness.
[0006] Lack of vector-aware interrupt handling strategies: Traditional interrupt mechanisms mainly rely on the ROB commit status of the scalar path to determine the timing of interruption, lacking awareness of the VPU's execution status. Rushing to respond to interrupts before the VPU has completed its task may result in uncommitted intermediate states, inconsistent data, or incomplete exception handling, affecting the correctness of the program's semantics.
[0007] The vector exception handling path is unclear, making debugging and verification difficult: There is currently no unified architecture standard for vector exception handling. The internal execution process of VPU lacks a standardized exception reporting mechanism and status query interface, making it difficult for developers to locate the source of exceptions during debugging. The exception handling process is not transparent, and the verification and testing costs are high, making it difficult to meet industrial-grade stability requirements. Summary of the Invention
[0008] Purpose of the invention: The purpose of this invention is to provide a method for co-processing interrupts and exceptions that supports RISC-V vector extension processors. By decoupling and co-processing the CPU and vector processing unit, it achieves lightweight, accurate and efficient exception and interrupt management, which is suitable for low-overhead system control in high-concurrency vector operation scenarios.
[0009] Technical Solution: To achieve the above objectives, the present invention provides a method for co-processing interrupts and exceptions applicable to RISC-V vector extension processors. This method is applied to a RISC-V architecture system where the CPU and VPU are co-operated and decoupled. The method includes exception handling, interrupt handling, and concurrent exception and interrupt handling. The exception handling includes equipping the VPU and CPU with exception detection modules. The exception detection module in the VPU dynamically monitors various exception events during instruction execution and marks and feeds them back to the CPU along with the instruction. The exception detection module in the CPU judges the exceptions of the marked instructions and handles the exception events uniformly during the instruction submission phase.
[0010] The interrupt handling includes the CPU first classifying the interrupt type according to the interrupt level after receiving the interrupt request. If the interrupt level is classified as low, the CPU suspends the interrupt request. If the interrupt level is classified as high, the CPU immediately starts the interrupt handling process.
[0011] The concurrent handling of exceptions and interrupts includes: when the CPU receives an interrupt request marked as high-level, it immediately initiates the interrupt handling process regardless of whether there is an exception event; when the CPU receives an interrupt request marked as low-level, it suspends the interrupt request and prioritizes handling exception events.
[0012] Preferably, during the exception handling process, when multiple instructions carrying exception flags enter the submission stage, the CPU processes the earliest instruction carrying an exception flag in the submission queue.
[0013] Preferably, after the anomaly detection module in the CPU determines the anomaly, the CPU triggers a unified pipeline cleaning mechanism, stops sending new instructions to the VPU, flushes uncommitted instructions in the VPU, clears uncommitted instructions in the CPU front end and execution queue, retains the context information corresponding to the abnormal instruction, and jumps to the RISC-V standard anomaly handling entry point to execute the subsequent anomaly handling process.
[0014] Preferably, during the interrupt handling process, for low interrupt level interrupt requests, the CPU temporarily stores the interrupt signal in the wait register in the interrupt handling module, putting it in a suspended state. When it is confirmed that the VPU instruction submission queue has been cleared, the CPU sends an "interrupt start processing" signal to the interrupt handling module, thereby starting the subsequent processing flow of the suspended interrupt.
[0015] Preferably, during the interrupt handling process, for interrupt requests with high interrupt levels, the CPU immediately stops issuing instructions to the VPU and discards the execution results of all issued but not yet submitted vector instructions, and directly starts the interrupt handling process.
[0016] Preferably, during the interrupt handling process, the CPU saves the context information corresponding to the earliest instruction waiting to be submitted in the submission queue as the minimum recovery point of the interrupt situation.
[0017] Preferably, in the concurrent exception and interrupt handling, when the CPU receives an interrupt request number marked as high-level, it immediately starts the interrupt handling process, and at the same time, the CPU immediately stops sending new instructions to the VPU, clears the execution instructions that have not yet been submitted inside the VPU, and the CPU no longer accepts submissions from the VPU.
[0018] Preferably, in the concurrent exception and interrupt handling, when the CPU receives an interrupt request number marked as ground level, it suspends the interrupt while allowing the vector instructions already issued in the VPU to continue execution until all are committed.
[0019] Preferably, in the concurrent handling of exceptions and interrupts, when the CPU receives an interrupt request number marked as ground level, the CPU first processes the exception and then resumes the response to the pending interrupt, entering the interrupt service procedure.
[0020] Beneficial effects: The present invention has the following advantages: 1. The present invention does not limit the VPU execution model, and can be adapted to variable-length vector instructions, composite instructions, and multi-cycle high-latency operations. At the same time, it can also be extended to various application scenarios such as AI accelerators, heterogeneous computing SoCs, and mixed-precision processors. It has good scalability and versatility, and has strong general value and industrial application potential.
[0021] 2. The "first exception priority" strategy submitted in this invention ensures that the pipeline is interrupted only once due to the earliest exception, avoiding repeated pipeline flushing. When an interruption occurs, there is no need to disrupt the VPU execution process. Execution can continue by relying on the CPU-side snapshot recovery mechanism, reducing the additional overhead caused by VPU instruction restarts. This helps maintain a high IPC (instructions per cycle) and overall throughput, improving the system's performance in high-concurrency vector computing scenarios. Attached Figure Description
[0022] Figure 1 This is a flowchart for exception handling;
[0023] Figure 2 This is a flowchart of the interrupt handling process;
[0024] Figure 3 This is a flowchart for handling concurrent exceptions and interruptions. Detailed Implementation
[0025] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0026] Example 1
[0027] This invention proposes an efficient and lightweight interrupt and exception handling scheme for the RISC-V architecture, specifically addressing the collaborative yet decoupled system architecture of the CPU and VPU. In conventional VPU designs, the VPU primarily handles large-scale parallel data computation, has a simple structure, only performs instruction operations, lacks complex control logic, and does not maintain global CSR registers or related system control states. Therefore, the VPU is ill-suited for complex interrupt and exception handling, system state maintenance, and recovery tasks. This invention fully leverages the VPU's "dedicated computation, simplified control" characteristics. The VPU only handles exception detection for vector instructions, enabling real-time event identification and marking during computation. All actual interrupt and exception handling, system state management, and subsequent recovery processes are uniformly completed by the CPU. Specifically, this includes exception handling, interrupt handling, and concurrent exception and interrupt handling.
[0028] The exception handling process is as follows:
[0029] In this embodiment, abnormal events can be detected either within the CPU (such as scalar instruction exceptions) or within the VPU through a dedicated exception detection module (such as illegal access or data overflow during vector computation). Regardless of the source of the exception, its final processing and system state maintenance are always completed on the CPU side. This design not only greatly simplifies the complexity of the VPU control logic but also improves the system's scalability and the uniformity of exception management.
[0030] like Figure 1 As shown, the VPU is equipped with a dedicated exception detection module to dynamically monitor various exception events during instruction execution. Once an exception is detected, the VPU marks the exception type and related status along with the instruction and feeds it back to the CPU during the instruction commit phase. Simultaneously, the CPU also contains an exception detection module for scalar instruction exception judgment and handles them uniformly during the instruction commit phase. It is worth emphasizing that in modern processor microarchitectures, even with out-of-order execution, the final commit phase of all instructions strictly follows the original program order. Therefore, regardless of whether the CPU uses sequential or out-of-order execution, and regardless of whether the exception occurs within the CPU or in the VPU path, this invention achieves unified and sequential exception judgment and handling by maintaining an ordered instruction commit queue (this solution does not limit the specific method of implementing the commit order; the queue implementation is merely an example). When multiple instructions carrying exception flags enter the commit phase, the system only processes the earliest exception instruction in the commit queue; the remaining exception flags are ignored, thus preventing duplicate traps or multiple exception interference. This strategy not only ensures the "first exception priority" principle in exception handling but also is naturally compatible with software exception handling semantics (such as breakpoint debugging and exception chaining), improving the system's predictability and debuggability. Once an exception is formally determined, the CPU immediately triggers a unified pipeline cleaning mechanism, stopping the issuance of new instructions to the VPU and flushing uncommitted instructions within the VPU. It clears uncommitted instructions from the CPU front-end (fetch, decode) and execution queue, retains the context information corresponding to the exception instruction, and jumps to the RISC-V standard exception handling entry point (traphandler) to execute subsequent exception handling procedures. This exception handling mechanism, while ensuring unified, accurate, and low-overhead exception management through CPU and VPU collaboration, effectively avoids redundant control and state chaos through a submission-driven exception determination mechanism and the first exception priority handling strategy, achieving lightweight and accurate exception synchronization and recovery in a high-performance heterogeneous processor environment.
[0031] The interrupt handling process is as follows:
[0032] External interrupts (such as timer interrupts, I / O requests, etc.) are uniformly sent to the CPU by the interrupt control unit. For example... Figure 3 As shown, in this embodiment, after receiving an interrupt signal, the CPU first classifies it according to the interrupt type. The division of interrupt levels can be customized according to specific application scenarios and system requirements to support flexible interrupt priority management. Subsequently, the CPU will immediately stop issuing new vector instructions to the VPU and determine whether there are still unsubmitted vector instructions and their related information by querying the vector instruction issuance record.
[0033] For low-priority interrupts, when an uncommitted vector instruction is detected and the interrupt is low-priority, the CPU does not immediately respond to the interrupt request. Instead, it temporarily stores the interrupt signal in the wait register of the interrupt handling module, putting it in a suspended state. The system continues to allow the instructions being executed internally by the VPU to run until all instructions are committed. Only after confirming that the VPU instruction commit queue is empty will the CPU send an "interrupt start processing" signal to the interrupt handling module, thereby initiating the subsequent processing flow of the suspended interrupt. The logical structure of this mechanism is as follows: Figure 3 This approach avoids forcibly interrupting the VPU's long-cycle operations, reducing resource waste and ensuring the consistency of calculation results and the overall system execution efficiency. For high-priority interrupts, when the interrupt level is marked as high, the system prioritizes responding to the interrupt. Upon receiving such an interrupt, the CPU immediately stops issuing instructions to the VPU and discards the execution results of all issued but uncommitted vector instructions, directly initiating the interrupt handling process. In this case, to ensure system state consistency, the CPU needs to carefully save the context information corresponding to the earliest instruction waiting to be committed in the commit queue, serving as the minimum recovery point for the interrupt context. By saving the context of critical instructions, the correctness of the interrupt service process is ensured, and a precise semantic starting point is provided for subsequent system recovery. This solution, through its hierarchical interrupt handling mechanism, achieves delayed response to low-priority interrupts and immediate response to high-priority interrupts. This avoids frequent interference with the VPU's long-cycle operations and allows for rapid intervention in the interrupt handling process in emergency situations, thus achieving a balance between system throughput and real-time response capability, effectively improving interrupt response speed and system concurrency.
[0034] The process for handling concurrent exceptions and interruptions is as follows:
[0035] In processor architectures that support VPUs, exceptions and interrupts may occur simultaneously. Without a reasonable arbitration mechanism, this can easily lead to disordered instruction semantics, inconsistent states, or unpredictable system execution results. To address this issue, this invention provides a concurrent exception and interrupt handling strategy to ensure that system real-time performance is achieved while maintaining the consistency and correctness of instruction execution.
[0036] When the CPU receives a high-level interrupt signal, it immediately triggers the interrupt handling procedure regardless of whether an abnormal event exists. The CPU also immediately stops issuing new instructions to the VPU and clears any uncommitted execution instructions within the VPU, ensuring the system quickly enters the interrupt service routine. During this process, the CPU no longer accepts submissions from the VPU, thus preventing the VPU from simultaneously submitting an exception. Throughout this process, the CPU still saves the context according to the interrupt handler to ensure the system can subsequently resume operation from a consistent state. This mechanism guarantees real-time and deterministic response to emergency events, making it particularly suitable for applications with extremely high real-time requirements.
[0037] When the interrupt level is set to low, the CPU does not immediately process the interrupt request. Instead, it suspends the interrupt and pauses external responses, as described earlier. During this time, the system allows the vector instructions already issued within the VPU to continue execution until all are committed. Only after the commit is complete will the CPU issue an "interrupt processing begins" signal and formally enter the interrupt service routine. During the low-priority interrupt suspension, if the commit queue detects an exception instruction entering the commit phase, the system will handle the exception first. That is, if the CPU receives an exception from the VPU at this time, it will handle that exception first. After exception handling is complete, the CPU resumes responding to the suspended interrupt and enters the interrupt service flow. During this process, the CPU saves necessary context information to ensure correct context switching between exceptions and interrupts. This "exceptions take precedence over low-priority interrupts" strategy ensures that consistency is restored first in the event of potential system state failure before processing interrupt requests, thereby maintaining the correctness of program semantics and the robustness of the system.
[0038] In summary, this invention achieves precise management of various exception and interrupt situations through a mechanism of "immediate response to high-priority interrupts, suspension and waiting for low-priority interrupts, and priority of exceptions over low-priority interrupts." While maintaining low hardware overhead, it also takes into account the real-time performance and consistency of the system, significantly improving the robustness and predictability of the processor in complex concurrent scenarios.
[0039] Example 2
[0040] This invention primarily targets processor products integrating RISC-V vector extensions and is suitable for application environments requiring high-concurrency vector computation. Typical application scenarios include:
[0041] AI Accelerator: In tasks such as large-scale matrix computation and deep learning inference, this invention can quickly respond to external interruptions without interrupting vector operations, ensuring a balance between high performance and real-time performance.
[0042] High-performance SoC: In scenarios such as image processing, video decoding, or edge computing, it can flexibly arbitrate based on interrupt priority to avoid resource waste caused by low-priority interrupts, while ensuring the timely processing of high-priority events.
[0043] Scientific computing and mixed-precision processors: In long-cycle simulations or high-precision computing tasks, exception handling takes precedence over low-priority interrupts to ensure data consistency and result reliability.
[0044] Furthermore, this invention can also be extended to various heterogeneous computing products such as autonomous driving domain control chips and communication baseband processors, possessing good versatility and industrial promotion value.
Claims
1. A method for co-processing interrupts and exceptions in a RISC-V vector extension processor, applied to a system architecture where the CPU and VPU are co-operated and decoupled under the RISC-V architecture, characterized in that... It includes exception handling, interrupt handling, and concurrent exception and interrupt handling. The exception handling includes equipping the VPU and CPU with an exception detection module. The exception detection module in the VPU is used to dynamically monitor various exception events during instruction execution and mark them along with the instruction and feed them back to the CPU. The exception detection module in the CPU is used to judge the exception of the marked instruction and handle the exception events uniformly when the instruction enters the submission stage. The interrupt handling includes the CPU first classifying the interrupt type according to the interrupt level after receiving the interrupt request. If the interrupt level is classified as low, the CPU suspends the interrupt request. If the interrupt level is classified as high, the CPU immediately starts the interrupt handling process. The concurrent handling of exceptions and interrupts includes: when the CPU receives an interrupt request marked as high-level, it immediately initiates the interrupt handling process regardless of whether there is an exception event; when the CPU receives an interrupt request marked as low-level, it suspends the interrupt request and prioritizes handling exception events.
2. The interruption and exception co-processing method according to claim 1, characterized in that, During the exception handling process, when multiple instructions carrying exception flags enter the submission stage, the CPU processes the earliest instruction carrying an exception flag in the submission queue.
3. The interruption and exception co-processing method according to claim 1, characterized in that, After the anomaly detection module in the CPU determines the anomaly, the CPU triggers a unified pipeline cleaning mechanism, stops sending new instructions to the VPU, flushes uncommitted instructions in the VPU, clears uncommitted instructions in the CPU front end and execution queue, retains the context information corresponding to the abnormal instruction, and jumps to the RISC-V standard anomaly handling entry point to execute the subsequent anomaly handling process.
4. The interruption and exception co-processing method according to claim 1, characterized in that, During the interrupt handling process, for low interrupt level interrupt requests, the CPU temporarily stores the interrupt signal in the wait register in the interrupt handling module, putting it in a suspended state. When it is confirmed that the VPU instruction submission queue has been cleared, the CPU sends an "interrupt start processing" signal to the interrupt handling module, thereby starting the subsequent processing flow of the suspended interrupt.
5. The interruption and exception co-processing method according to claim 1, characterized in that, During the interrupt handling process, for interrupt requests with high interrupt levels, the CPU immediately stops issuing instructions to the VPU and discards the execution results of all issued but not yet committed vector instructions, and directly starts the interrupt handling process.
6. The interruption and exception co-processing method according to claim 5, characterized in that, During the interrupt handling process, the CPU saves the context information corresponding to the earliest instruction waiting to be submitted in the submission queue, as the minimum recovery point of the interrupt situation.
7. The interruption and exception co-processing method according to claim 1, characterized in that, In the concurrent exception and interrupt handling, when the CPU receives an interrupt request number marked as high-level, it immediately starts the interrupt handling process. At the same time, the CPU immediately stops sending new instructions to the VPU and clears the uncommitted execution instructions inside the VPU. The CPU also no longer accepts submissions from the VPU.
8. The interruption and exception co-processing method according to claim 1, characterized in that, In the concurrent exception and interrupt handling, when the CPU receives an interrupt request number marked as ground level, it suspends the interrupt while allowing the vector instructions already issued in the VPU to continue execution until all are committed.
9. The interruption and exception co-processing method according to claim 1, characterized in that, In the concurrent handling of exceptions and interrupts, when the CPU receives an interrupt request number marked as low level, the CPU first processes the exception, then resumes the response to the pending interrupt and enters the interrupt service procedure.