Data processing method and device and storage medium

Abstract

The invention discloses a data processing method and device and a storage medium, and relates to the technical field of data processing, and the data processing method comprises the steps that when a data transmission request is received, a target protocol type, a target data bit width and a target sampling mode corresponding to the data transmission request are obtained in a register; based on the target sampling mode and a sampling clock corresponding to the data transmission request, sampling input serial data of the target protocol type to obtain sampling data; generating a data frame based on the sampling data and a target data bit width; and writing the data frame into an asynchronous first-in first-out queue based on the sampling clock. According to the application, the compatibility of multiple protocols, multiple bit widths and multiple modes under the same set of hardware architecture is realized.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data processing method, apparatus and storage medium. Background Technology

[0002] As the complexity of RF communication systems, audio interfaces, and on-chip multi-protocol data channels continues to increase, digital chips need to simultaneously support multiple common data transmission protocols, such as SSI (Synchronous Serial Interface), McBSP (Multichannel Buffered Serial Port), and I²S (Inter-IC Sound). Traditionally, a separate set of transmit and receive logic is designed for each protocol, including independent clock generation, shift registers, frame synchronization, and control circuits. While this approach is simple to implement, it results in a significant waste of redundant logic resources. Especially when the protocol differences lie only in frame format or bit width definition, shift sampling units often have similar structures, leading to unnecessary increases in area and power consumption.

[0003] Furthermore, different protocols have different requirements for data bit width and transmission modes. If multiple sets of hardware logic are used, resources cannot be shared between channels, and dynamic switching within the same interface is difficult to achieve. Designers need to constrain each interface unit separately during the synthesis and placement / routing phases, leading to more complex timing management issues. In multi-rate communication scenarios, as the master clock frequency increases, the timing margin of the serial-to-parallel conversion unit decreases, making it prone to edge sampling errors; if designed separately, each interface needs to be re-verified, further increasing the verification workload.

[0004] Therefore, how to achieve compatibility with multiple protocols, multiple bit widths, and multiple modes under the same hardware architecture is a problem that urgently needs to be solved.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main purpose of this application is to provide a data processing method, apparatus and storage medium, which aims to solve the technical problem of how to achieve compatibility with multiple protocols, multiple bit widths and multiple modes under the same hardware architecture.

[0007] To achieve the above objectives, this application proposes a data processing method, which includes: Upon receiving a data transmission request, the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request are retrieved from the register. Based on the target sampling mode and the sampling clock corresponding to the data transmission request, the input serial data of the target protocol type is sampled to obtain sampled data; Based on the sampled data and the target data bit width, a data frame is generated; Based on the sampling clock, the data frame is written into an asynchronous first-in-first-out queue.

[0008] In one embodiment, the step of sampling the input serial data of the target protocol type based on the target sampling mode and the sampling clock corresponding to the data transmission request to obtain sampled data includes: Obtain the system master clock corresponding to the host computer; The system master clock is divided based on the sampling frequency corresponding to the data transmission request to obtain the sampling clock. Based on the target sampling mode and the sampling clock, the input serial data of the target protocol type is sampled to obtain sampled data.

[0009] In one embodiment, the step of sampling the input serial data of the target protocol type based on the target sampling mode and the sampling clock to obtain sampled data includes: If the target sampling mode is a single-edge mode, the input serial data is sampled on the rising edge of the sampling clock to obtain sampled data; If the target sampling mode is a double-edge mode, the input serial data is sampled on the rising and falling edges of the sampling clock to obtain sampled data.

[0010] In one embodiment, the step of generating a data frame based on the sampled data and the target data bit width includes: Write the sampled data into the shift register; When the sampled data in the shift register reaches the target data bit width, the data frame is generated based on the sampled data in the shift register.

[0011] In one embodiment, the step of generating the data frame based on the sampled data in the shift register includes: Obtain the number of lanes corresponding to the data transmission request; The data frame is generated based on the number of lanes and the sampled data in the shift register.

[0012] In one embodiment, the step of writing the data frame into the asynchronous first-in-first-out queue based on the sampling clock includes: A frame synchronization signal is generated based on the sampling clock, wherein the rising edge of the frame synchronization signal is synchronized with the rising edge of the sampling clock corresponding to the first sampling result in the data frame; The data frame is written into the asynchronous first-in-first-out queue based on the frame synchronization signal.

[0013] In one embodiment, before the step of obtaining the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request from the register when the data transmission request is received, the data processing method further includes: Upon receiving a configuration command from the host computer, acquire multiple protocol type information, multiple data bit width information, and multiple sampling mode information corresponding to the configuration command; The protocol type information, the data bit width information, and the sampling mode information are written into the registers respectively.

[0014] In one embodiment, the protocol type information includes at least SSI protocol, McBSP protocol, and I²S protocol; the data bit width information includes at least 16 bits, 24 bits, and 48 bits; and the sampling mode information includes single-edge SDR mode and double-edge DDR mode.

[0015] In addition, to achieve the above objectives, this application also proposes a data processing apparatus, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the aforementioned data processing method.

[0016] Furthermore, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the aforementioned data processing method. One or more technical solutions proposed in this application have at least the following technical effects: Upon receiving a data transmission request, the system retrieves the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request from the register. Then, based on the target sampling mode and the sampling clock corresponding to the data transmission request, it samples the input serial data of the target protocol type to obtain sampled data. Next, based on the sampled data and the target data bit width, a data frame is generated. Finally, based on the sampling clock, the data frame is written to an asynchronous first-in-first-out queue. By configuring multiple protocols, bit widths, and modes in the register, and retrieving the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request from the register according to the data transmission request, and performing data transmission according to the target protocol type, target data bit width, and target sampling mode, the system achieves unified support for multiple serial communication protocols (SSI, McBSP, I²S) on a single hardware platform through the separation of the parameterized core and the protocol encapsulation layer. This enables compatibility with multiple protocols, bit widths, and modes under the same hardware architecture. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating an embodiment of the data processing method of this application. Figure 2 This is a timing diagram of serial data transmission provided in an embodiment of the data processing method of this application; Figure 3 This is a timing diagram for serial data transmission provided in another embodiment of the data processing method of this application; Figure 4 This is a timing diagram of parallel data transmission provided in an embodiment of the data processing method of this application; Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the data processing method in the embodiments of this application.

[0020] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0022] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0023] The main solution of this application embodiment is as follows: Upon receiving a data transmission request, the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request are obtained from a register; based on the target sampling mode and the sampling clock corresponding to the data transmission request, the input serial data of the target protocol type is sampled to obtain sampled data; based on the sampled data and the target data bit width, a data frame is generated; based on the sampling clock, the data frame is written into an asynchronous first-in-first-out queue. In this embodiment, for ease of description, the following description uses a data processing device as the execution subject.

[0024] As the complexity of RF communication systems, audio interfaces, and on-chip multi-protocol data channels continues to increase, digital chips need to simultaneously support multiple common data transmission protocols, such as SSI (Synchronous Serial Interface), McBSP (Multichannel Buffered Serial Port), and I²S (Inter-IC Sound). Traditionally, a separate set of transmit and receive logic is designed for each protocol, including independent clock generation, shift registers, frame synchronization, and control circuits. While this approach is simple to implement, it results in a significant waste of redundant logic resources. Especially when the protocol differences lie only in frame format or bit width definition, shift sampling units often have similar structures, leading to unnecessary increases in area and power consumption.

[0025] Furthermore, different protocols have different requirements for data bit width and transmission modes. If multiple sets of hardware logic are used, resources cannot be shared between channels, and dynamic switching within the same interface is difficult to achieve. Designers need to constrain each interface unit separately during the synthesis and placement / routing phases, leading to more complex timing management issues. In multi-rate communication scenarios, as the master clock frequency increases, the timing margin of the serial-to-parallel conversion unit decreases, making it prone to edge sampling errors; if designed separately, each interface needs to be re-verified, further increasing the verification workload.

[0026] In traditional interface architectures, frame synchronization signals are typically generated by upper-layer modules or external basebands, lacking a unified definition. When protocols switch, the frame synchronization logic needs to be reconfigured, leading to complex and error-prone timing interfaces between upstream and downstream modules. Furthermore, data transmission between asynchronous domains requires additional synchronization logic (such as handshakes or multi-level buffering), making it difficult to guarantee stability as the design scales up.

[0027] Therefore, how to achieve compatibility with multiple protocols, multiple bit widths, and multiple modes under the same hardware architecture is a problem that urgently needs to be solved.

[0028] This application provides a solution that, by configuring multiple protocols, multiple bit widths, and multiple modes in registers, obtains the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request from the registers according to the data transmission request, and performs data transmission according to the target protocol type, target data bit width, and target sampling mode. Under a single hardware platform, by separating the parameterized core and the protocol encapsulation layer, unified support for multiple serial communication protocols (SSI, McBSP, I²S) is achieved, realizing compatibility with multiple protocols, multiple bit widths, and multiple modes under the same hardware architecture.

[0029] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or data processing device capable of performing the above functions. The following description uses a data processing device as an example to illustrate this embodiment and the subsequent embodiments.

[0030] Based on this, embodiments of this application provide a data processing method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the data processing method of this application.

[0031] In this embodiment, the data processing method includes steps S110~S140: Step S110: When a data transmission request is received, the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request are obtained from the register. Step S120: Based on the target sampling mode and the sampling clock corresponding to the data transmission request, sample the input serial data of the target protocol type to obtain sampled data; Step S130: Generate a data frame based on the sampled data and the target data bit width; Step S140: Based on the sampling clock, write the data frame into an asynchronous first-in-first-out queue.

[0032] The data processing apparatus of this embodiment may include a configuration control unit (Wrapper), a clock control unit (ClockCtrl), a serial sampling and shifting core unit (Shift Core), a frame output unit (Frame Output), and an asynchronous buffer unit (Async FIFO).

[0033] The Wrapper receives external configuration commands through the SPI (Serial Peripheral Interface) interface, writes information such as protocol type, data bit width, and transmission mode (SDR / DDR) into the register (internal register), and sends configuration parameters to each functional unit when the system starts or shifts gears, thus realizing the dynamic configurability of the interface.

[0034] The Clock Ctrl receives the system master clock from the chip PLL (host computer) and performs frequency division and mode selection according to the configuration register parameters to generate the sampling clock required by the interface. In DDR (Double Data Rate Sampling) mode, it supports double-edge sampling to achieve twice the data throughput; in SDR (Single Data Rate Sampling) mode, it only uses single-edge sampling to maintain timing stability. The design of this unit ensures that the sampling clock always maintains a fixed phase relationship with the system master clock under different levels and frequencies.

[0035] The Shift Core is used to acquire serial input data driven by a sampling clock and performs bit concatenation through a parameterizable shift register. When the counter detects that the number of acquired data bits has reached the frame length defined by the current protocol (such as 16 bits or 24 bits), a complete frame of parallel data is output. Through parameterized design, the Shift Core can adapt to the data frame format and bit width requirements of different protocols without changing the hardware structure, avoiding the need to instantiate shift registers independently for each protocol.

[0036] Frame Output generates a frame synchronization signal (UPD) while outputting parallel data from the Shift Core. This signal is a periodic pulse with a duty cycle of approximately 50%, whose rising edge indicates the valid output time of a frame of data and is used to drive the write enable of the asynchronous FIFO. This unified frame synchronization mechanism decouples upstream sampling from downstream buffering operations in terms of timing, simplifying system design. The UPD signal can also serve as a frame alignment reference for downstream modules (such as the digital front-end DFE), improving the overall system synchronization consistency.

[0037] The asynchronous FIFO, acting as a cross-clock domain buffer unit, completes writing in the interface sampling clock domain and reads in the DFE working clock domain, ensuring that rate differences between different modules do not cause data loss or duplication. Internally, the FIFO employs standard Gray-coded read / write pointers and a dual-trigger synchronization structure to guarantee metastability safety during cross-clock domain operations.

[0038] In one feasible implementation, prior to step S10, the data processing method may include steps A110 to A120: Step A110: When a configuration instruction is received from the host computer, multiple protocol type information, multiple data bit width information, and multiple sampling mode information corresponding to the configuration instruction are obtained; Step A120: Write the protocol type information, the data bit width information, and the sampling mode information into the registers respectively.

[0039] In this embodiment, after the system corresponding to the data processing device is powered on or reset, the Wrapper receives configuration instructions from the host computer via the SPI interface, and obtains multiple protocol type information, multiple data bit width information, and multiple sampling mode information corresponding to the configuration instructions. The protocol type information includes at least SSI, McBSP, and I²S protocols; the data bit width information includes at least 16 bits, 24 bits, and 48 bits; and the sampling mode information includes single-edge SDR mode and double-edge DDR mode. The number of lanes corresponding to the configuration instructions can also be obtained, including 1 lane and 2 lanes.

[0040] After obtaining the protocol type information, multiple data bit width information, and multiple sampling mode information, the protocol type information, the data bit width information, and the sampling mode information are written into the registers respectively. Specifically, the protocol type information, the data bit width information, and the sampling mode information can be written into different registers respectively, or the protocol type information, the data bit width information, and the sampling mode information can be written into the same register.

[0041] In this embodiment, when a data transmission request is received, the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request are obtained from the register. From the multiple protocol type information, multiple data bit width information, and multiple sampling mode information in the register, the target protocol type, target data bit width, and target sampling mode corresponding to the target data required by the data transmission request are obtained.

[0042] When the target protocol type, target data bit width, and target sampling mode are obtained, the input serial data of the target protocol type is sampled based on the target sampling mode and the sampling clock corresponding to the data transmission request to obtain sampled data. Specifically, the input serial data is sampled according to the target sampling mode based on the sampling clock to obtain sampled data.

[0043] Furthermore, in one feasible implementation, step S120 may include steps B110-B130: Step B110: Obtain the system master clock corresponding to the host computer; Step B120: Divide the system master clock based on the sampling frequency corresponding to the data transmission request to obtain the sampling clock; Step B130: Based on the target sampling mode and the sampling clock, sample the input serial data of the target protocol type to obtain sampled data.

[0044] In this embodiment, Clock Ctrl obtains the system master clock from the upstream PLL (host computer) and performs a frequency division operation on the system master clock based on the sampling frequency corresponding to the data transmission request to obtain the sampling clock. That is, the system master clock is configured with frequency division according to the sampling frequency level corresponding to the data transmission request, and the sampling clock is output to maintain a stable phase relationship after the frequency division operation, ensuring consistent signal boundaries under different sampling modes. Figure 2 and Figure 3 As shown, Figure 2 In this context, the target protocol type is McBSP, meaning that the input serial data is input through the McBSP interface, and DP_TX_CLK_IN(CLKR) is the sampling clock. Figure 3 In this context, the target protocol type is SSI protocol, meaning that the input serial data is input through the SSI interface, and DP_TX_CLK_IN (TX_DCLK_IN) is the sampling clock.

[0045] When the sampling clock is obtained, the input serial data of the target protocol type is sampled based on the target sampling mode and the sampling clock to obtain sampled data. Specifically, the input serial data is sampled according to the target sampling mode based on the sampling clock to obtain sampled data.

[0046] Furthermore, in one feasible implementation, step B130 may include steps B131-B132: Step B131: If the target sampling mode is a single-edge mode, the input serial data is sampled on the rising edge of the sampling clock to obtain sampled data. Step B132: If the target sampling mode is a double-edge mode, the input serial data is sampled at the rising and falling edges of the sampling clock to obtain sampled data.

[0047] In this embodiment, during sampling, if the target sampling mode is a single-edge mode, the input serial data is sampled on the rising edge of the sampling clock to obtain sampled data. Specifically, 1 bit is sampled on each rising edge of the clock, and the sampled data is sequentially written to the shift register shift_reg. Figure 2 As shown, Figure 2 In DP_TX_DATA_0(DR), I23, I22, Q23, Q22, etc. are all sampled data.

[0048] If the target sampling mode is a dual-edge sampling mode, the input serial data is sampled at both the rising and falling edges of the sampling clock to obtain sampled data, such as... Figure 3 As shown, Figure 3 In DP_TX_DATA_0(TX_IDATA_IN), I15 represents the sampled data of input serial data I at the rising edge, and I16 represents the sampled data of input serial data I at the falling edge. In DP_TX_DATA_0(TX_QDATA_IN), Q15 represents the sampled data of input serial data I at the rising edge, and Q16 represents the sampled data of input serial data I at the falling edge.

[0049] After acquiring the sampled data, a data frame is generated based on the sampled data and the target data bit width. Specifically, when the sampled data reaches the target data bit width, the current target data bit width is used to generate a data frame. Furthermore, in one feasible implementation, step S130 may include steps C110-C120: Step C110: Write the sampled data into the shift register; Step C120: When the sampled data in the shift register reaches the target data bit width, the data frame is generated based on the sampled data in the shift register.

[0050] In this embodiment, each time sampled data is obtained, the sampled data is written to a shift register, and the amount of sampled data in the shift register is accumulated. It is determined whether this amount of data reaches the target data bit width. When the sampled data in the shift register reaches the target data bit width, a data frame is generated based on the sampled data in the shift register. That is, all sampled data in the shift register is generated into one data frame, such as... Figure 2 As shown, Figure 2 The target data width is 48 bits, and the I / Q occupies 24 bits each in the generated data frame DP_TX_DATA_0(DR).

[0051] Furthermore, in one feasible implementation, step C120 may include steps C121-C122: Step C121: Obtain the number of lanes corresponding to the data transmission request; Step C122: Generate the data frame based on the number of lanes and the sampled data in the shift register.

[0052] In this embodiment, the number of lanes corresponding to the data transmission request can also be obtained, and a data frame can be generated based on the number of lanes and the sampled data in the shift register. Specifically, if the number of lanes is 1, such as... Figure 2 As shown, the sampled data in the shift register is used to generate a data frame DP_TX_DATA_0(DR). If the number of lanes is 2, then... Figure 3 As shown, the I data in the sampled data in the shift register is used to generate a data frame DP_TX_DATA_0(TX_IDATA_IN), and the Q data in the sampled data in the shift register is used to generate a data frame DP_TX_DATA_0(TX_QDATA_IN).

[0053] In this embodiment of the application, when generating a data frame, the data frame is written into an asynchronous first-in-first-out queue based on the sampling clock. Specifically, a corresponding frame synchronization signal is generated according to the sampling clock, and the data frame is written into the asynchronous first-in-first-out queue based on the frame synchronization signal.

[0054] Furthermore, in one feasible implementation, step S140 may include steps D121-D122: Step D121: Generate a frame synchronization signal based on the sampling clock, wherein the rising edge of the frame synchronization signal is synchronized with the rising edge of the sampling clock corresponding to the first sampling result in the data frame; Step D122: Write the data frame into an asynchronous first-in-first-out queue based on the frame synchronization signal.

[0055] In this embodiment, when generating a data frame, the contents of the shift register are output to Frame Output. Frame Output latches the output data on the rising edge of the same sampling clock and simultaneously generates a frame synchronization signal UPD. The rising edge of the frame synchronization signal is synchronized with the rising edge of the sampling clock corresponding to the first sampling result in the data frame. Therefore, the rising edge of UPD can be used as a frame boundary marker to indicate that the current parallel data in the asynchronous first-in-first-out (FIFO) queue is valid and triggers a write operation. This allows the data frame to form a natural register segmentation point within the clock domain, effectively avoiding timing uncertainties caused by combined path delays. Figure 4 As shown.

[0056] In this embodiment, after obtaining the frame synchronization signal UPD, the data frame is written into the asynchronous first-in-first-out queue based on the frame synchronization signal. The asynchronous FIFO in this embodiment is a general asynchronous FIFO structure, which can directly call the general ASYNCFIFO module. The UPD signal distinguishes different data frames for the asynchronous FIFO, ensuring the correct transmission result of each frame of data. Driven by the UPD signal, the current frame data is written to the buffer through the write port of the asynchronous FIFO. The asynchronous FIFO write clock and read clock run independently, and cross-domain reliability is ensured through a pointer synchronization mechanism. The downstream DFE module reads FIFO data under its local clock, realizing the data flow balance between different rate domains. The traffic difference between the write end and the read end is deeply absorbed by the asynchronous FIFO, ensuring stable continuous transmission.

[0057] In this embodiment, during system operation, the host computer can reconfigure registers via the SPI interface to change the transmission protocol, bit width, or rate. The new configuration takes effect during the inter-frame interval and does not affect the currently output data frame. ClockCtrl and Shift Core automatically adjust the division coefficient and shift count threshold based on the updated parameters to achieve uninterrupted gear switching. The entire process requires no additional protection logic, and timing boundaries are naturally defined through frame synchronization.

[0058] This application achieves unified support for multiple serial communication protocols (SSI, McBSP, I²S) on a single hardware platform by separating the parameterized core and protocol encapsulation layer. It adopts a Core + Wrapper architecture and a timing control mechanism that coordinates UPD signals and asynchronous FIFOs, forming a novel structural scheme that differs from traditional independent implementations of multiple interfaces. This structural approach is innovative and scalable, demonstrating innovation in reusability and timing reliability for digital interface modules. By unifying the implementation of multiple protocols (SSI, McBSP, I²S) within the same core structure and employing a shared mechanism of parameterized shift registers and parallel output logic, the redundant logic unit design found in traditional multi-interface architectures is avoided. Therefore, the number of shift registers occupying the majority of the interface module area is reduced to 1 / 12 of the original, which is expected to reduce the overall interface module area by 80%, achieving hardware resource reuse and significantly reducing area overhead.

[0059] This application uses the UPD signal as a unified frame boundary identifier to ensure that the synchronization method of the interface remains consistent across multiple protocols and modes. The rising edge of UPD serves as both a frame synchronization flag and a write trigger for the asynchronous FIFO, ensuring clear data boundaries for each frame, reducing the risk of data misalignment across clock domains, and improving timing reliability.

[0060] By employing register parameterization design, flexible configuration of protocol, bit width, number of lanes, and sampling mode is achieved, enabling rapid adaptation to different projects and application scenarios and reducing the design and verification costs of subsequent chip development. The interface features centralized functionality and clear module division; upper-layer software only needs to modify configuration registers to adapt to different communication standards, reducing the difficulty of later maintenance and reuse. Through the standardized cross-domain structure of asynchronous FIFO, inter-module interaction is simple, requiring no additional handshake logic, making the design easier to integrate into the SoC system.

[0061] In this embodiment, the frame synchronization signal UPD clearly delineates the sampling and writing operations into register boundaries, resulting in shorter combinational logic paths and more direct timing analysis and synthesis constraints. For both SDR and DDR modes, a unified generated clock model can be used for static timing analysis, reducing constraint complexity. In simulation verification, UPD provides a clear frame alignment reference, making waveform observation and assertion writing more intuitive.

[0062] This embodiment provides a data processing method. Upon receiving a data transmission request, the method retrieves the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request from a register. Then, based on the target sampling mode and the sampling clock corresponding to the data transmission request, the method samples the input serial data of the target protocol type to obtain sampled data. Subsequently, based on the sampled data and the target data bit width, a data frame is generated. Then, based on the sampling clock, the data frame is written into an asynchronous first-in-first-out queue. By configuring multiple protocols, multiple bit widths, and multiple modes in the register, and retrieving the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request from the register according to the data transmission request, and performing data transmission according to the target protocol type, target data bit width, and target sampling mode, this method achieves unified support for multiple serial communication protocols (SSI, McBSP, I²S) under a single hardware platform through the separation of the parameterized core and the protocol encapsulation layer. This achieves compatibility with multiple protocols, multiple bit widths, and multiple modes under the same hardware architecture.

[0063] This application provides a data processing apparatus, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the data processing method in Embodiment 1 above.

[0064] The following is for reference. Figure 5The diagram illustrates a structural schematic of a data processing apparatus suitable for implementing embodiments of this application. The data processing apparatus in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The data processing apparatus shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0065] like Figure 5 As shown, the data processing device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the data processing device. The processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the data processing device to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows a data processing device with various systems, it should be understood that it is not required to implement or possess all of the systems shown. More or fewer systems may be implemented alternatively.

[0066] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0067] The data processing apparatus provided in this application, employing the data processing method described in the above embodiments, can solve the technical problem of achieving compatibility with multiple protocols, multiple bit widths, and multiple modes under the same hardware architecture. Compared with the prior art, the beneficial effects of the data processing apparatus provided in this application are the same as those of the data processing method provided in the above embodiments, and other technical features in this data processing apparatus are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0068] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0069] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0070] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the data processing method described in the above embodiments.

[0071] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0072] The aforementioned computer-readable storage medium may be included in a data processing apparatus or may exist independently without being assembled into a data processing apparatus.

[0073] The aforementioned computer-readable storage medium carries one or more programs. When the one or more programs are executed by a data processing device, the data processing device: upon receiving a data transmission request, obtains from a register the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request; samples the input serial data of the target protocol type based on the target sampling mode and the sampling clock corresponding to the data transmission request to obtain sampled data; generates a data frame based on the sampled data and the target data bit width; and writes the data frame into an asynchronous first-in-first-out queue based on the sampling clock.

[0074] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0075] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0076] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0077] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described data processing method. This solves the technical problem of achieving compatibility across multiple protocols, bit widths, and modes under the same hardware architecture. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the data processing method provided in the above embodiments, and will not be repeated here.

[0078] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data processing method described above.

[0079] The computer program product provided in this application solves the technical problem of how to achieve compatibility with multiple protocols, multiple bit widths, and multiple modes under the same hardware architecture. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the data processing method provided in the above embodiments, and will not be repeated here.

[0080] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A data processing method, characterized in that, The data processing method includes: Upon receiving a data transmission request, the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request are retrieved from the register. Based on the target sampling mode and the sampling clock corresponding to the data transmission request, the input serial data of the target protocol type is sampled to obtain sampled data; Based on the sampled data and the target data bit width, a data frame is generated; Based on the sampling clock, the data frame is written into an asynchronous first-in-first-out queue.

2. The data processing method as described in claim 1, characterized in that, The step of sampling the input serial data of the target protocol type based on the target sampling mode and the sampling clock corresponding to the data transmission request to obtain sampled data includes: Obtain the system master clock corresponding to the host computer; The system master clock is divided based on the sampling frequency corresponding to the data transmission request to obtain the sampling clock. Based on the target sampling mode and the sampling clock, the input serial data of the target protocol type is sampled to obtain sampled data.

3. The data processing method as described in claim 2, characterized in that, The step of sampling the input serial data of the target protocol type based on the target sampling mode and the sampling clock to obtain sampled data includes: If the target sampling mode is a single-edge mode, the input serial data is sampled on the rising edge of the sampling clock to obtain sampled data; If the target sampling mode is a double-edge mode, the input serial data is sampled on the rising and falling edges of the sampling clock to obtain sampled data.

4. The data processing method as described in claim 1, characterized in that, The step of generating a data frame based on the sampled data and the target data bit width includes: Write the sampled data into the shift register; When the sampled data in the shift register reaches the target data bit width, the data frame is generated based on the sampled data in the shift register.

5. The data processing method as described in claim 4, characterized in that, The step of generating the data frame based on the sampled data in the shift register includes: Obtain the number of lanes corresponding to the data transmission request; The data frame is generated based on the number of lanes and the sampled data in the shift register.

6. The data processing method as described in claim 1, characterized in that, The step of writing the data frame into the asynchronous first-in-first-out queue based on the sampling clock includes: A frame synchronization signal is generated based on the sampling clock, wherein the rising edge of the frame synchronization signal is synchronized with the rising edge of the sampling clock corresponding to the first sampling result in the data frame; The data frame is written into the asynchronous first-in-first-out queue based on the frame synchronization signal.

7. The data processing method according to any one of claims 1 to 6, characterized in that, Before the step of obtaining the target protocol type, target data bit width, and target sampling mode corresponding to the data transmission request from the register when the data transmission request is received, the data processing method further includes: Upon receiving a configuration command from the host computer, acquire multiple protocol type information, multiple data bit width information, and multiple sampling mode information corresponding to the configuration command; The protocol type information, the data bit width information, and the sampling mode information are written into the registers respectively.

8. The data processing method as described in claim 7, characterized in that, The protocol type information includes at least SSI protocol, McBSP protocol, and I²S protocol; the data bit width information includes at least 16 bits, 24 bits, and 48 bits; and the sampling mode information includes single-edge SDR mode and double-edge DDR mode.

9. A data processing apparatus, characterized in that, The data processing apparatus includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the data processing method as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the data processing method as described in any one of claims 1 to 8.

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