Core particle interconnection interface circuit and core particle interface signal processing method and device

Abstract

The invention discloses a core particle interconnection interface circuit and a core particle interface signal processing method and device.The core particle interconnection interface circuit comprises a core particle interface circuit, a data coding circuit and a data decoding circuit, and the core particle interface circuit comprises a physical layer circuit, an inter-core-particle adaptation layer circuit and a protocol layer circuit; the inter-core-particle adaptation layer circuit is respectively connected with the physical layer circuit and the protocol layer circuit; the data coding circuit and the data decoding circuit are deployed between the protocol layer circuit and the system-on-chip bus interface or between the inter-core-particle adaptation layer circuit and the protocol layer circuit; the data coding circuit is used for carrying out selection overturning processing on a sending signal of the core particle interface circuit; and the data decoding circuit is used for carrying out selection overturning processing on the received signal of the core particle interface circuit. According to the technical scheme, the power consumption of the core particle interface circuit can be effectively reduced, and the data transmission quality of the core particle interface circuit is ensured.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a chip interconnect interface circuit, a chip interface signal processing method and apparatus. Background Technology

[0002] Chiplet technology is a novel chip design approach that breaks down a complex chip into multiple small functional modules (die) and then integrates them together through advanced packaging.

[0003] Currently, with the increasing speed of the NAND flash interface and the growing demand for system bandwidth, the power consumption of NAND flash interface circuits is rising, and the power supply noise is also increasing. Therefore, there is an urgent need to provide an effective technical means to reduce the power consumption of NAND flash interface circuits while ensuring data transmission stability. Summary of the Invention

[0004] This invention provides a chip interconnect interface circuit, a chip interface signal processing method and apparatus, which can effectively reduce the power consumption of the chip interface circuit and ensure the data transmission quality of the chip interface circuit.

[0005] According to one aspect of the present invention, a chip interconnect interface circuit is provided, including a chip interface circuit, a data encoding circuit, and a data decoding circuit; The chip interface circuit includes a physical layer circuit, an inter-chip adaptation layer circuit, and a protocol layer circuit; the inter-chip adaptation layer circuit is connected to the physical layer circuit and the protocol layer circuit respectively. The data encoding circuit and data decoding circuit are deployed between the protocol layer circuit and the on-chip system bus interface, or between the inter-chip adapter layer circuit and the protocol layer circuit. The data encoding circuit is used to perform selective inversion processing on the transmitted signal of the chip interface circuit; the data decoding circuit is used to perform selective inversion processing on the received signal of the chip interface circuit.

[0006] According to another aspect of the present invention, a chip interface signal processing method is provided, applied to the data encoding circuit described in any embodiment of the present invention, the method comprising: The system obtains the transmit signal output from the on-chip system bus interface, performs a bitwise XOR operation on the transmit signal and the historical signal in the register, and obtains the flip vector corresponding to the transmit signal. The flip vector is accumulated to obtain the flip amount, and the flip amount is compared with a threshold. The flag bit corresponding to the transmitted signal is determined based on the comparison result, and the transmitted signal is output directly or bitwise inverted based on the flag bit.

[0007] According to another aspect of the present invention, a chip interface signal processing method is provided, applied to the data decoding circuit described in any embodiment of the present invention, the method comprising: Obtain the received signal of the chip interface circuit and the corresponding flag bit of the received signal; If the flag bit corresponding to the received signal is the first identifier, then the received signal is inverted bit by bit and output. If the flag bit corresponding to the received signal is the second identifier, then the received signal is directly output.

[0008] According to another aspect of the present invention, a chip interface signal processing device is provided, applied to the data encoding circuit described in any embodiment of the present invention, the device comprising: The signal acquisition module is used to acquire the transmission signal output by the on-chip system bus interface, and perform bitwise XOR processing on the transmission signal and the historical signal in the register to obtain the flip vector corresponding to the transmission signal; The flip amount comparison module is used to accumulate the flip vector to obtain the flip amount, and compare the flip amount with a threshold. The signal output module is used to determine the flag bit corresponding to the transmitted signal based on the comparison result, and to output the transmitted signal directly or to invert the bits according to the flag bit.

[0009] According to another aspect of the present invention, a chip interface signal processing device is provided, applied to the data decoding circuit described in any embodiment of the present invention, the device comprising: The flag acquisition module is used to acquire the received signal of the chip interface circuit and the flag corresponding to the received signal; The received signal inversion module is used to invert the received signal bit by bit and output it if the flag bit corresponding to the received signal is a first identifier. The receiving signal output module is used to directly output the receiving signal if the flag bit corresponding to the receiving signal is the second identifier.

[0010] According to another aspect of the present invention, a chip is provided, the chip comprising: At least one processor; and a memory communicatively connected to said at least one processor; The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the chip interface signal processing method according to any embodiment of the present invention.

[0011] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the chip interface signal processing method according to any embodiment of the present invention.

[0012] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the chip interface signal processing method according to any embodiment of the present invention.

[0013] The technical solution provided by this invention deploys the data encoding circuit and the data decoding circuit between the protocol layer circuit and the on-chip system bus interface, or between the inter-chip adapter layer circuit and the protocol layer circuit. The data encoding circuit performs selective toggling processing on the transmitted signal of the inter-chip interface circuit, and the data decoding circuit performs selective toggling processing on the received signal of the inter-chip interface circuit. This can effectively reduce the power consumption of the inter-chip interface circuit and ensure the data transmission quality of the inter-chip interface circuit.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a chip interconnect interface circuit according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a data encoding circuit according to Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of a data decoding circuit according to Embodiment 1 of the present invention; Figure 4 This is a flowchart of a chip interface signal processing method provided in Embodiment 2 of the present invention; Figure 5 This is a flowchart of another chip interface signal processing method provided in Embodiment 3 of the present invention; Figure 6 This is a schematic diagram of the structure of a chip interface signal processing device according to Embodiment 4 of the present invention; Figure 7 This is a schematic diagram of another chip interface signal processing device provided in Embodiment 5 of the present invention; Figure 8 This is a schematic diagram of the chip structure for implementing the chip interface signal processing method of Embodiment Six of the present invention. Detailed Implementation

[0017] This embodiment provides a chip interconnect interface circuit. Figure 1 This is a schematic diagram of the structure of the chip interconnect interface circuit, including the chip interface circuit, the data encoding circuit, and the data decoding circuit.

[0018] The chip interface circuit includes a physical layer circuit, an inter-chip adapter layer circuit, and a protocol layer circuit. The inter-chip adapter layer circuit is connected to the physical layer circuit and the protocol layer circuit, respectively.

[0019] Specifically, the protocol layer circuitry encapsulates the data to be sent into data packets conforming to the protocol specifications, and parses the received data packets to obtain the original data. The physical layer circuitry converts the data into a signal format suitable for transmission over the physical medium. The die-to-die adaptation layer circuitry acts as a bridge connecting the physical layer circuitry and the protocol layer circuitry. It manages the transmission links between dies, ensuring the stability and reliability of transmission links between different dies, and supports dynamic multiplexing of multiple transmission protocols, allowing different types of data transmission to share the same physical link.

[0020] In an optional implementation of this embodiment, the chip interface circuit can perform data transmission based on the Universal Chipplet Interconnect Express (UCIE) protocol or other chip interface protocols; this embodiment does not limit this. The UCIE protocol specifies scrambling and descrambling of transmitted data in the physical layer circuitry to improve data transmission quality and enhance data security. The UCIE protocol also specifies a standard interface (Flit-Aware Die-to-Die Interface, FDI) between the inter-chip adapter layer circuitry and the protocol layer circuitry. This interface is used for data transmission with flow control units (Flits) as the basic unit, thereby achieving efficient communication between chips.

[0021] In this embodiment, the data encoding circuit and the data decoding circuit are deployed between the protocol layer circuit and the System on Chip (SOC) bus interface, or between the inter-chip adapter layer circuit and the protocol layer circuit (i.e., the FDI interface). This embodiment does not limit this.

[0022] The data encoding circuit is used to select and toggle the transmitted signals of the chip interface circuit; the data decoding circuit is used to select and toggle the received signals of the chip interface circuit. Optionally, the Data Bus Inversion (DBI) logic can be deployed within the data encoding and data decoding circuits.

[0023] In one specific implementation, the data decoding circuit and the data encoding circuit can be based on DBI logic to determine the signal flip probability before transmitting the signal and select to transmit the original signal or the inverted signal, thereby reducing the number of signal flips on the chip interface circuit bus and reducing the dynamic power consumption of the chip interface circuit. Furthermore, since the physical layer circuit in this embodiment needs to scramble and descramble the transmitted data, by deploying the data encoding circuit and the data decoding circuit on the physical layer circuit, the power consumption of the chip interface circuit can be reduced while ensuring the quality of data transmission.

[0024] The technical solution provided in this embodiment, by deploying the data encoding circuit and the data decoding circuit between the protocol layer circuit and the SOC bus interface, or between the inter-chip adapter layer circuit and the protocol layer circuit, and by having the data encoding circuit perform selective toggling processing on the transmitted signal of the chip interface circuit, and the data decoding circuit perform selective toggling processing on the received signal of the chip interface circuit, can effectively reduce the power consumption of the chip interface circuit and ensure the data transmission quality of the chip interface circuit.

[0025] Based on the above embodiments, Figure 2 This is a schematic diagram of a data encoding circuit, such as... Figure 2 As shown, the data encoding circuit includes a register, a bitwise XOR, an adder, a comparator, a data selector, and a bitwise inverter.

[0026] The input of the bitwise XOR is connected to the input interface of the data encoding circuit and the output of the register, respectively; the output of the bitwise XOR is connected to the input of the adder; the output of the adder is connected to the input of the comparator; the input of the bitwise inverter is connected to the input interface; and the input of the data selector is connected to the input interface and the output of the bitwise inverter, respectively.

[0027] The data encoding circuit is used to acquire the transmit signal output from the SOC bus interface, determine the toggle amount corresponding to the transmit signal, determine the flag bit corresponding to the transmit signal based on the comparison result of the toggle amount and the threshold, and output the transmit signal directly or bitwise inverted based on the flag bit corresponding to the transmit signal.

[0028] In a specific embodiment, such as Figure 2As shown, after obtaining the transmit signal output from the SOC bus interface through the input interface, the transmit signal can be transmitted to both the register and the bitwise XOR. The bitwise XOR performs bitwise XOR processing on the transmit signal and the historical signal in the register to obtain the toggling vector corresponding to the transmit signal. Then, the adder accumulates the toggling vector to obtain the toggling amount. The comparator compares the toggling amount with a threshold and determines the flag bit corresponding to the transmit signal based on the comparison result.

[0029] Optionally, if the toggle amount corresponding to the transmitted signal is greater than or equal to the threshold, the data selector determines the flag bit as the first identifier (e.g., sets the flag bit to "1") and outputs the transmitted signal bit-by-bit. If the toggle amount corresponding to the transmitted signal is less than the threshold, the data selector determines the flag bit as the second identifier (e.g., sets the flag bit to "0") and outputs the transmitted signal directly.

[0030] In one embodiment of this invention, when the transmitted signal is output bit-inverted or directly, the transmitted signal and the flag bit can be transmitted using the same physical channel. Optionally, the transmitted signal includes at least one of the following: user data, address signal, and control signal.

[0031] The advantage of this configuration is that, in addition to flipping user data, the chip interface circuit can also select and flip address and control signals according to actual needs. This reduces the power consumption of the chip interface circuit while improving its adaptability in different application scenarios.

[0032] Figure 3 This is a schematic diagram of a data decoding circuit, such as... Figure 3 As shown, the data decoding circuit includes a data selector and a bit-inverter. The input terminal of the bit-inverter is connected to the input interface of the data decoding circuit; the input terminal of the data selector is connected to both the input interface of the data decoding circuit and the output terminal of the bit-inverter.

[0033] The data decoding circuit is used to acquire the received signal from the chip interface circuit. Based on the flag bit corresponding to the received signal, it outputs the received signal directly or inverts the bits.

[0034] Optionally, if the flag bit corresponding to the received signal is the first identifier (e.g., the flag bit is set to "1"), the received signal is inverted bit by bit and output; if the flag bit corresponding to the received signal is the second identifier (e.g., the flag bit is set to "0"), the received signal is output directly.

[0035] In one embodiment of this example, when the data encoding circuit and the data decoding circuit are deployed between the protocol layer circuit and the SOC bus interface, the protocol layer circuit is used to perform protocol conversion on the flag bit corresponding to the transmitted signal and write the converted flag bit into Flit; the protocol layer circuit is also used to obtain the flag bit corresponding to the received signal in Flit and restore the flag bit corresponding to the received signal.

[0036] In another embodiment of this example, when the data encoding circuit and the data decoding circuit are deployed on the FDI interface, the flag bits corresponding to the transmit or receive signals of the chip interface circuit can be written into the reserved bits in the output data of the FDI interface to meet the standard data format (Format4) of the FDI interface output.

[0037] This second embodiment provides a chip interface signal processing method. Figure 4 This is a flowchart of the chip interface signal processing method. This embodiment is applicable to the case of encoding the transmitted signals of the chip interface circuit. This method can be executed by a chip interface signal processing device, which can be configured in the data encoding circuit. Figure 4 As shown, the method includes: Step 310: Obtain the transmit signal output from the on-chip system bus interface, and perform bitwise XOR processing on the transmit signal and the historical signal in the register to obtain the flip vector corresponding to the transmit signal.

[0038] Step 320: Accumulate the flip vector to obtain the flip amount, and compare the flip amount with the threshold.

[0039] Step 330: Determine the flag bit corresponding to the transmitted signal based on the comparison result, and output the transmitted signal directly or output it bit by bit according to the flag bit.

[0040] In one embodiment of this example, determining the flag bit corresponding to the transmitted signal based on the comparison result, and directly outputting the transmitted signal or inverting the bits based on the flag bit, includes: if the toggle amount corresponding to the transmitted signal is greater than or equal to a threshold, then determining the flag bit as a first identifier and inverting the bits of the transmitted signal for output; if the toggle amount corresponding to the transmitted signal is less than the threshold, then determining the flag bit as a second identifier and directly outputting the transmitted signal.

[0041] The technical solution provided in this embodiment obtains the transmit signal output from the on-chip system bus interface through a data encoding circuit, performs bitwise XOR processing on the transmit signal and the historical signal in the register to obtain the flip vector corresponding to the transmit signal, accumulates the flip vector to obtain the flip amount, compares the flip amount with a threshold, determines the flag bit corresponding to the transmit signal based on the comparison result, and outputs the transmit signal directly or bitwise based on the flag bit. This technical means can effectively reduce the power consumption of the chip interface circuit and ensure the data transmission quality of the chip interface circuit.

[0042] This third embodiment provides a chip interface signal processing method. Figure 5 This is a flowchart of the chip interface signal processing method. This embodiment is applicable to the case of decoding the received signal of the chip interface circuit. This method can be executed by a chip interface signal processing device, which can be configured in the data decoding circuit. Figure 5 As shown, the method includes: Step 410: Obtain the received signal of the chip interface circuit and the flag bit corresponding to the received signal.

[0043] Step 420: If the flag bit corresponding to the received signal is the first identifier, then the received signal is bitwise inverted and output.

[0044] Step 430: If the flag bit corresponding to the received signal is the second identifier, then the received signal is directly output.

[0045] The technical solution provided in this embodiment obtains the received signal and the corresponding flag bit of the chip interface circuit through a data decoding circuit. If the flag bit corresponding to the received signal is the first identifier, the received signal is output bit by bit inverted. If the flag bit corresponding to the received signal is the second identifier, the received signal is directly output. This technical means can effectively reduce the power consumption of the chip interface circuit and ensure the data transmission quality of the chip interface circuit.

[0046] Figure 6 This is a schematic diagram of a chip interface signal processing device provided in Embodiment 4 of the present invention. The device is applied to a data encoding circuit. Figure 6 As shown, the device includes: a signal acquisition module 510, a flip-point comparison module 520, and a signal output module 530.

[0047] The signal acquisition module 510 is used to acquire the transmission signal output by the on-chip system bus interface, and perform bitwise XOR processing on the transmission signal and the historical signal in the register to obtain the flip vector corresponding to the transmission signal. The flip amount comparison module 520 is used to accumulate the flip vector to obtain the flip amount, and compare the flip amount with a threshold. The signal output module 530 is used to determine the flag bit corresponding to the transmitted signal based on the comparison result, and to output the transmitted signal directly or to invert the bits according to the flag bit.

[0048] The technical solution provided in this embodiment obtains the transmit signal output from the on-chip system bus interface through a data encoding circuit, performs bitwise XOR processing on the transmit signal and the historical signal in the register to obtain the flip vector corresponding to the transmit signal, accumulates the flip vector to obtain the flip amount, compares the flip amount with a threshold, determines the flag bit corresponding to the transmit signal based on the comparison result, and outputs the transmit signal directly or bitwise based on the flag bit. This technical means can effectively reduce the power consumption of the chip interface circuit and ensure the data transmission quality of the chip interface circuit.

[0049] Based on the above embodiments, the transmitted signal includes at least one of the following: user data, address signal, and control signal.

[0050] The signal output module 530 includes: An inverted output unit is used to determine the flag bit as the first identifier if the flip amount corresponding to the transmitted signal is greater than or equal to a threshold, and to invert the transmitted signal bit by bit and output it. A direct output unit is used to determine the flag bit as a second identifier and directly output the transmitted signal if the toggle amount corresponding to the transmitted signal is less than a threshold.

[0051] The above-described apparatus can execute the methods provided in all the foregoing embodiments of the present invention, and has the corresponding functional modules and beneficial effects for executing the above methods. Technical details not described in detail in this embodiment can be found in the methods provided in all the foregoing embodiments of the present invention.

[0052] Figure 7 This is a schematic diagram of a chip interface signal processing device provided in Embodiment 5 of the present invention. The device is applied to a data decoding circuit. Figure 7 As shown, the device includes: a signal acquisition module 610, a first identification processing module 620, and a second identification processing module 630.

[0053] The receiving signal acquisition module 610 is used to acquire the received signal of the chip interface circuit and the flag bit corresponding to the received signal; The first identifier processing module 620 is used to invert the bits of the received signal and output it if the flag bit corresponding to the received signal is the first identifier. The second identifier processing module 630 is used to directly output the received signal if the flag bit corresponding to the received signal is the second identifier.

[0054] The technical solution provided in this embodiment obtains the received signal and the corresponding flag bit of the chip interface circuit through a data decoding circuit. If the flag bit corresponding to the received signal is the first identifier, the received signal is output bit by bit inverted. If the flag bit corresponding to the received signal is the second identifier, the received signal is directly output. This technical means can effectively reduce the power consumption of the chip interface circuit and ensure the data transmission quality of the chip interface circuit.

[0055] Figure 8 A schematic diagram of the structure of a chip 10 that can be used to implement an embodiment of the present invention is shown. Figure 8 As shown, chip 10 includes at least one processor 11 and a memory, such as read-only memory (ROM) or random access memory (RAM), communicatively connected to at least one processor 11. The memory stores computer programs executable by at least one processor. Processor 11 can perform various appropriate actions and processes based on the computer program stored in read-only memory 12 or loaded from storage unit 18 into random access memory 13. Random access memory 13 can also store various programs and data required for the operation of chip 10. Processor 11, read-only memory 12, and random access memory 13 are interconnected via bus 14. Input / output (I / O) interfaces are also connected to bus 14.

[0056] Multiple components in chip 10 are connected to input / output interface 15, including: input unit 16, such as a keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as a disk, optical disk, etc.; and communication unit 19, such as a network card, modem, wireless transceiver, etc. Communication unit 19 allows chip 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0057] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as chip interface signal processing methods.

[0058] In some embodiments, the chip interface signal processing method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted onto chip 10 via read-only memory 12 and / or communication unit 19. When the computer program is loaded into random access memory 13 and executed by processor 11, one or more steps of the chip interface signal processing method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the chip interface signal processing method by any other suitable means (e.g., by means of firmware).

[0059] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0060] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or electronic device.

[0061] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0062] To provide interaction with a user, the systems and techniques described herein can be implemented on a chip having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the chip. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0063] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0064] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0065] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0066] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A chip interconnect interface circuit, characterized in that, This includes the chip interface circuit, data encoding circuit, and data decoding circuit; The chip interface circuit includes a physical layer circuit, an inter-chip adaptation layer circuit, and a protocol layer circuit; the inter-chip adaptation layer circuit is connected to the physical layer circuit and the protocol layer circuit respectively. The data encoding circuit and data decoding circuit are deployed between the protocol layer circuit and the on-chip system bus interface, or between the inter-chip adapter layer circuit and the protocol layer circuit. The data encoding circuit is used to perform selective inversion processing on the transmitted signal of the chip interface circuit; the data decoding circuit is used to perform selective inversion processing on the received signal of the chip interface circuit.

2. The circuit according to claim 1, characterized in that, The data encoding circuit includes a register, a bitwise XOR, an adder, a comparator, a data selector, and a bitwise inverter; The input terminals of the bitwise XOR are connected to the input interface of the data encoding circuit and the output terminal of the register, respectively; the output terminal of the bitwise XOR is connected to the input terminal of the adder; the output terminal of the adder is connected to the input terminal of the comparator; the input terminal of the bitwise NOT is connected to the input interface; the input terminal of the data selector is connected to the input interface and the output terminal of the bitwise NOT, respectively. The data encoding circuit is used to acquire the transmit signal output by the on-chip system bus interface, determine the toggle amount corresponding to the transmit signal, and determine the flag bit corresponding to the transmit signal based on the comparison result of the toggle amount and the threshold. The data encoding circuit is also used to directly output the transmitted signal or invert the bits according to the flag bit corresponding to the transmitted signal.

3. The circuit according to claim 2, characterized in that, The data decoding circuit includes a data selector and a bit-inverter; The input terminal of the bit-inverter is connected to the input interface of the data decoding circuit; the input terminal of the data selector is connected to both the input interface of the data decoding circuit and the output terminal of the bit-inverter. The data decoding circuit is used to acquire the received signal from the chip interface circuit, and outputs the received signal directly or by bit-inverting it according to the flag bit corresponding to the received signal.

4. The circuit according to claim 3, characterized in that, When the data encoding circuit and data decoding circuit are deployed between the protocol layer circuit and the on-chip system bus interface... The protocol layer circuit is used to perform protocol conversion on the flag bit corresponding to the transmitted signal and write the converted flag bit into the stream control unit; The protocol layer circuit is also used to obtain the flag bit corresponding to the received signal in the flow control unit and to recover the flag bit corresponding to the received signal.

5. A chip interface signal processing method, characterized in that, Applied to the data encoding circuit according to any one of claims 1-4, the method includes: The system obtains the transmit signal output from the on-chip system bus interface, performs a bitwise XOR operation on the transmit signal and the historical signal in the register, and obtains the flip vector corresponding to the transmit signal. The flip vector is accumulated to obtain the flip amount, and the flip amount is compared with a threshold. The flag bit corresponding to the transmitted signal is determined based on the comparison result, and the transmitted signal is output directly or bitwise inverted based on the flag bit.

6. The method according to claim 5, characterized in that, Based on the comparison result, determine the flag bit corresponding to the transmitted signal, and output the transmitted signal directly or bitwise inverted based on the flag bit, including: If the flip value corresponding to the transmitted signal is greater than or equal to the threshold, then the flag bit is determined as the first identifier, and the transmitted signal is bitwise inverted and output. If the toggle amount corresponding to the transmitted signal is less than the threshold, then the flag bit is determined to be the second identifier, and the transmitted signal is directly output.

7. The method according to claim 5, characterized in that, The transmitted signal includes at least one of the following: user data, address signal, and control signal.

8. A chip interface signal processing method, characterized in that, The method, applied to the data decoding circuit according to any one of claims 1-4, comprises: Obtain the received signal of the chip interface circuit and the corresponding flag bit of the received signal; If the flag bit corresponding to the received signal is the first identifier, then the received signal is inverted bit by bit and output. If the flag bit corresponding to the received signal is the second identifier, then the received signal is directly output.

9. A chip interface signal processing device, characterized in that, The device is applied to the data encoding circuit according to any one of claims 1-4, the device comprising: The signal acquisition module is used to acquire the transmission signal output by the on-chip system bus interface, and perform bitwise XOR processing on the transmission signal and the historical signal in the register to obtain the flip vector corresponding to the transmission signal. The flip amount comparison module is used to accumulate the flip vector to obtain the flip amount, and compare the flip amount with a threshold. The signal output module is used to determine the flag bit corresponding to the transmitted signal based on the comparison result, and to output the transmitted signal directly or to invert the bits according to the flag bit.

10. A chip interface signal processing device, characterized in that, The device is applied to the data decoding circuit according to any one of claims 1-4, the device comprising: The flag acquisition module is used to acquire the received signal of the chip interface circuit and the flag corresponding to the received signal; The received signal inversion module is used to invert the received signal bit by bit and output it if the flag bit corresponding to the received signal is a first identifier. The receiving signal output module is used to directly output the receiving signal if the flag bit corresponding to the receiving signal is the second identifier.

Images