A method, device and equipment for extracting a capacitance value

Abstract

The application relates to the field of integrated circuit design, and discloses a method, device and equipment for extracting a capacitance value, wherein the method comprises the following steps: determining a combined capacitance matched with each sidewall offset based on the relative position relationship between adjacent first and second metal layers in a pre-generated capacitance query table; wherein the sidewall offset of one side of the two adjacent metal layers represents the offset of a group of sidewalls of one metal layer on the side of another metal layer; calculating the surface capacitance component of the first and second metal layers based on a preset unit surface capacitance and the projection overlap width between the first and second metal layers; and calculating the capacitance value between the first and second metal layers according to the surface capacitance component and the combined capacitance matched with each sidewall offset. The technical scheme provided by the application can improve the extraction efficiency of the parasitic capacitance of the metal layer.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and in particular to a method, apparatus and device for extracting capacitance values. Background Technology

[0002] In the field of integrated circuit design, parasitic capacitance can introduce interference, signal delay, or frequency response limitations in circuit layout. As a key influencing factor in integrated circuit design, extracting parasitic capacitance can ensure the accuracy and reliability of integrated circuit design.

[0003] In related technologies, parasitic capacitance is usually extracted using pattern matching. By matching the metal layer pattern with a pre-built pattern library, the capacitance value can be directly determined. However, for large-scale or complex integrated circuits, pattern matching requires the construction of a fairly rich pattern library, and the matching process takes a long time, which reduces the efficiency of capacitance extraction.

[0004] Therefore, improving the extraction efficiency of parasitic capacitance of metal layers has become a key research focus in the field of integrated circuit design. Summary of the Invention

[0005] This application provides a method, apparatus, and device for extracting capacitance values, which can improve the extraction efficiency of parasitic capacitance of metal layers.

[0006] The first aspect of this application provides a method for extracting capacitance values. The method includes: determining a combined capacitance matching each sidewall offset in a pre-generated capacitance lookup table based on the relative positional relationship between adjacent first and second metal layers; wherein the sidewall offset of one side of two adjacent metal layers represents the offset of a set of sidewalls of one metal layer and another metal layer on that side; calculating the surface capacitance components of the first and second metal layers based on a preset unit surface capacitance and the projected overlap width between the first and second metal layers; and calculating the capacitance value between the first and second metal layers according to the combined capacitance matching each sidewall offset.

[0007] A second aspect of this application also provides a capacitance value extraction apparatus, the apparatus comprising: a combined capacitance lookup unit, configured to determine a combined capacitance matching each sidewall offset in a pre-generated capacitance lookup table based on the relative positional relationship between a first metal layer and a second metal layer; wherein the first metal layer and the second metal layer are adjacent; the sidewall offset is used to characterize the offset of a set of sidewalls on the same side of the first metal layer and the second metal layer; a surface capacitance component calculation unit, configured to calculate the surface capacitance components of the first metal layer and the second metal layer based on a preset unit surface capacitance and the projected overlap width between the first metal layer and the second metal layer; and a capacitance value calculation unit, configured to calculate the capacitance value between the first metal layer and the second metal layer according to the surface capacitance components and the combined capacitances matching each sidewall offset.

[0008] A third aspect of this application also provides a computer device, the computer device including a memory and a processor, the memory being used to store a computer program, the computer program being executed by the processor to implement the capacitance value extraction method described in the first aspect.

[0009] A fourth aspect of this application also provides a computer program product, including computer instructions for causing a computer to execute the capacitance value extraction method described in the first aspect.

[0010] The technical solution provided in one or more embodiments of this application can improve the extraction efficiency of parasitic capacitance of metal layers by using a capacitance lookup table matching method. Specifically, matching combined capacitances are determined in the capacitance lookup table based on sidewall offsets. After obtaining the surface capacitance components, the capacitance values ​​between metal layers are determined based on the surface capacitance components and the aforementioned combined capacitances. In related technologies, capacitance values ​​are typically determined in a capacitance lookup table based on multiple structural parameters of the metal layer combination. For complex metal layer combinations, a large number of metal layer samples need to be constructed in the capacitance lookup table, and the matching time for metal layer combinations is relatively long. The technical solution provided in this application can quickly determine the combined capacitances in the capacitance lookup table based on sidewall offsets and a small amount of metal layer structural information. Based on obtaining the surface capacitance components, the capacitance values ​​can be quickly determined, reducing the table construction time and the matching time for metal layer combinations, thereby improving the extraction efficiency of parasitic capacitance of metal layers.

[0011] As can be seen, the technical solution provided in this application can quickly match the capacitance value of the metal layer combination. At the same time, reducing the matching parameters of the capacitance lookup table can speed up the table building efficiency, thereby improving the extraction efficiency of the parasitic capacitance of the metal layer. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0013] Figure 1(a) is a schematic diagram of a metal layer combination provided in an embodiment of this application; Figure 1(b) is a schematic diagram of another metal layer combination provided in one embodiment of this application; Figure 2 A schematic diagram illustrating the steps of a capacitance value extraction method provided in this application embodiment; Figure 3 A schematic diagram of the metal layer reconstruction process provided for an embodiment of this application; Figure 4 This is a schematic diagram illustrating the process of converting metal layer combinations according to one embodiment of this application; Figure 5 This is a schematic diagram illustrating the process of converting metal layer combinations according to another embodiment of this application; Figure 6 This is a schematic diagram of the structural type of a metal layer combination sample provided in one embodiment of this application; Figure 7 A schematic diagram of a combination of two sets of symmetrical metal layers provided in one embodiment of this application; Figure 8 A schematic diagram of a capacitance value extraction device provided in one embodiment of this application; Figure 9 This is a schematic diagram of the structure of a computer device provided in one embodiment of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] Furthermore, the use of terms such as "first," "second," etc., in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments in this application, unless otherwise stated, "multiple" means two or more. Additionally, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0016] In the field of integrated circuit design, the extraction of parasitic capacitance is crucial. When a potential difference exists between any two conductors, parasitic capacitance forms in the insulating medium between them. This parasitic capacitance occurs in circuit layouts such as between wires, between wires and electronic components, or between electronic components. Parasitic capacitance introduces interference, signal delay, or frequency response limitations into the circuit, thus affecting the system performance of the integrated circuit. As a key influencing factor in integrated circuit design, extracting parasitic capacitance ensures the accuracy and reliability of the integrated circuit design.

[0017] Generally, parasitic capacitance can be extracted using two methods: field solvers and pattern matching. Specifically, multiple graphic samples with different structures are pre-enumerated, and the parasitic capacitance of each graphic sample is extracted by the field solver. Based on different structural parameters, a pattern library is constructed from these multiple graphic samples and their parasitic capacitances. When extracting the parasitic capacitance of the geometric figure to be tested, sample matching is performed in the pattern library based on the structural parameters of the geometric figure to obtain the parasitic capacitance of the matched graphic sample as the capacitance value of the geometric figure. The parasitic capacitance of the geometric figure is further calculated based on the capacitance value. For example, please refer to Figure 1(a). When establishing a capacitance lookup table for the metal layer combination formed by the two geometric figures to be tested shown in Figure 1(a), it is necessary to construct graphic samples based on the metal layer information and geometric structure information. The metal layer information is the metal layer where the geometric figure is located. The geometric structure information includes m1, m2 and s, where m1 is the width of geometric figure 1, m2 is the width of geometric figure 2, and s is the distance between the two geometric figures. For each geometric structure information, multiple sampling points are sampled, such as six sampling points: 1, 2, 4, 10, 20 and 40. The product of each sampling point and the minimum value of each geometric structure information is used as the geometric structure information of the geometric figure. That is to say, for the geometric figure shown in Figure 1(a), at least six graphic samples must be established in each metal layer.

[0018] However, for metal layer combinations formed by two geometric shapes with relatively complex positional structures, such as metal layer combinations where the two geometric shapes are in different metal layers, there are usually multiple structural parameters used to describe the structure of the metal layer combination. These structural parameters also include parameter values ​​under multiple sample values ​​of the metal layer combination structure. Constructing a pattern library in the above manner takes a long time, and the search time in the matching process is also long, resulting in low efficiency in extracting parasitic capacitance. For example, please refer to Figure 1(b). Figure 1(b) contains two geometric figures to be tested located in different metal layers. Geometric figure 1 is located in the second metal layer, and geometric figure 2 is located in the first metal layer. When building a pattern library for the geometric figures to be tested in the figure, it is necessary to construct metal layer samples based on the metal layer information and geometric structure information. The aforementioned metal layer information refers to the metal layer in which each geometric figure to be tested is located. The aforementioned geometric structure information includes at least three parameters between s1, s2, m1, and m2. Furthermore, building multiple metal layer samples also requires considering multiple possible values ​​for each geometric structure information. Here, s1 is the offset of the left side wall of the metal layer combination, s2 is the offset of the right side wall of the metal layer combination, m1 is the width of the second metal layer, and m2 is the width of the first metal layer. Due to the large number of metal layer samples, the construction of the capacitance lookup table is slow, and the complex structural parameters result in a long matching process time. This method is not suitable and will instead reduce the efficiency of parasitic capacitance extraction.

[0019] In view of the above, one or more embodiments of this application provide a method, apparatus and device for extracting capacitance values, which can solve the above problems and improve the extraction efficiency of parasitic capacitance of metal layers.

[0020] Please see Figure 2 In one aspect, this application provides a method for extracting capacitance values. This method is applied to a metal layer assembly, which includes at least a first metal layer and a second metal layer. The first and second metal layers are different metal layers in an integrated circuit, and they have a vertical relationship in a vertical plane, for example, the second metal layer is directly below the first metal layer. Furthermore, the first and second metal layers have surface capacitance and sidewall capacitance. The surface capacitance can be understood as the parasitic capacitance caused between the opposing surfaces of the first and second metal layers, and the sidewall capacitance can be understood as the parasitic capacitance caused between the sidewall portions of the first and second metal layers. Specifically, the method may include the following steps: S1: Based on the relative positional relationship between adjacent first and second metal layers, determine the combined capacitance that matches each sidewall offset in a pre-generated capacitance lookup table; wherein, the sidewall offset of two adjacent metal layers represents the offset of a set of sidewalls of one metal layer relative to the other metal layer on that side.

[0021] S3: Based on the preset unit surface capacitance and the projected overlap width between the first metal layer and the second metal layer, calculate the surface capacitance components of the first metal layer and the second metal layer.

[0022] S5: Calculate the capacitance value between the first metal layer and the second metal layer based on the combined capacitance that matches the surface capacitance component and the offset of each sidewall.

[0023] The aforementioned relative positional relationship can be understood as the geometric positional relationship between the first metal layer and the second metal layer. This relative positional relationship includes both horizontal and vertical aspects. The horizontal positional relationship includes the offset of the sidewalls and the length of each metal layer. The vertical positional relationship includes the height of each metal layer and the spacing between the metal layers.

[0024] In integrated circuits, different metal layers are typically located on different process layers. Therefore, the first and second metal layers are usually vertically opposite each other, and there may be some horizontal offset between them. This relative position directly determines the electric field distribution between the metal layers. Different relative positions lead to changes in the density and path of the electric field lines, thus affecting the capacitance between the metal layers. Therefore, when extracting the parasitic capacitance between the first and second metal layers, it is essential to first obtain their relative position to determine the parasitic capacitance.

[0025] Because the two metal layers may have different area offsets at their ends in the horizontal direction, meaning the non-overlapping portions of the first and second metal layers are of different sizes at both ends, this will lead to different sidewall capacitances at the ends of the metal layer combination. However, to simplify capacitance extraction of the metal layer combination while keeping the overlapping portion unchanged, the metal layer combination can be adjusted to a symmetrical metal layer reconstruction combination, so that each of the two reconstructed metal layer combinations corresponds to the sidewall offsets on both sides of the metal layer combination. Since capacitance calculation for symmetrical structures is relatively simple and easy to create and look up tables, a capacitance generation table can be pre-generated based on the various possibilities of symmetrical metal layer reconstruction combinations. Subsequently, the capacitance lookup table can be used to more accurately and efficiently determine the combined capacitance of the metal layer combination, thereby reducing the complexity of capacitance extraction of the metal layer combination, accurately and quickly extracting the parasitic capacitance of the metal layer combination, and improving the extraction efficiency of parasitic capacitance of the metal layers.

[0026] In one implementation, when generating a capacitance lookup table in advance, multiple metal layer combination samples can be calculated and analyzed to establish the correlation between the combined capacitance and the sidewall offset. The sidewall offset or metal layer structure information of each metal layer combination sample can be different. The metal layer structure information can be understood as the hierarchical information characterizing the process level of each of the two metal layers, or as the structural type characterizing the relative length relationship between the two metal layers. For any given metal layer combination sample, it can include an adjacent target metal layer and a reference metal layer. The width of the target metal layer is a specified unit width, and in a metal layer combination sample, the sidewall offsets on both sides of the target metal layer and the reference metal layer are the same. That is, structurally, the metal layer combination sample can be a symmetrical structure. From the cross-section of the metal layer combination sample, the axis of symmetry of this symmetrical structure is perpendicular to the direction of the two metal layers, thus the sidewall offsets on both sides of the metal layer combination sample can be the same.

[0027] In this embodiment, the target metal layer typically refers to the upper metal layer, and the reference metal layer refers to the lower metal layer. The combined capacitance of the metal layer combination sample can be the sum of the sidewall capacitance between the target metal layer and the reference metal layer, and the surface capacitance between the target metal layer and the reference metal layer. The unit width is preset before table creation, preferably set to 1 unit. Thus, for each metal layer combination sample, the combined capacitance of the metal layer combination sample can be calculated by the field solver based on the sidewall offset in the metal layer combination sample, and a correlation relationship can be established between the combined capacitance and the sidewall offset of the metal layer combination sample. For each metal layer combination sample, the correlation relationship between its own sidewall offset and combined capacitance can be obtained. In this way, by statistically analyzing the correlation relationship between the combined capacitance and sidewall offset of each metal layer combination sample, a capacitance lookup table can be generated based on the statistical results.

[0028] In one implementation, the sidewall offset can have positive and negative values. In practical applications, the positive or negative value of the sidewall offset can be related to the metal layer structure information. This metal layer structure information can represent a structural feature that is shorter at the top and longer at the bottom, or vice versa. For example, in... Figure 4 In the diagram, metal layer reconstruction combination B1 has a shorter top and longer bottom structure, while metal layer reconstruction combination B2 has a longer top and shorter bottom structure. In a specific application example, the sidewall offset of the shorter top and longer bottom structure can be positive, while the sidewall offset of the longer top and shorter bottom structure can be negative. Of course, in practical applications, the criteria for determining the positive or negative value of the sidewall offset can be set according to actual needs, and this application does not impose any limitations on this.

[0029] In a specific application example, the target metal layer is one of the metal layers in the metal layer combination sample that requires capacitance extraction, and the reference metal layer is another metal layer in the same sample that requires capacitance extraction. The target and reference metal layers interact and jointly form a parasitic capacitance. The target metal layer is set to a specified unit width, which standardizes the sample parameters. This facilitates the calculation of the areal capacitance component of the metal layer combination based on the unit areal capacitance and the projected overlap width of the metal layer combination in subsequent calculations, thereby improving capacitance extraction efficiency. Furthermore, a correlation is established between the calculated combined capacitance and the sidewall offset of the metal layer combination sample. This allows for quick and accurate matching of the combined capacitance corresponding to the metal layer combination based on the sidewall offset, further improving capacitance extraction efficiency.

[0030] In one embodiment, the unit area capacitance can be understood as the parasitic capacitance calculated for a metal layer of unit width, where the unit width remains the same as the unit width in the capacitance lookup table. Since the parasitic capacitance between metal layers is affected by the process level of the metal layer, the unit area capacitance of metal layer combinations with different process level information is different. Therefore, when calculating the parasitic capacitance of a metal layer combination, the unit area capacitance corresponding to that metal layer combination should first be determined, and the unit area capacitance of that metal layer combination should be the same as the unit area capacitance in the combined capacitance matching the metal layer reconstruction combination determined in the capacitance lookup table.

[0031] For example, if an integrated circuit includes four metal layers arranged from bottom to top as metal1, metal2, metal3, and metal4, the possible layer hierarchy information for the metal layer combinations is that the first metal layer and the second metal layer are located at metal1 and metal2, respectively; or the first metal layer and the second metal layer are located at metal2 and metal3, respectively; or the first metal layer and the second metal layer are located at metal3 and metal4, respectively. The unit area capacitance differs between metal layer combinations with different hierarchy information because, in practical applications, the distance between metal layers at different structural positions in the vertical direction varies, resulting in different unit area capacitances between different metal layer combinations. For example, metal3 and metal4, as higher metal layers, have a larger vertical distance and typically have a smaller unit area capacitance, while metal1 and metal2, as lower metal layers, have a smaller vertical distance and typically have a larger unit area capacitance.

[0032] In this embodiment, since the combined capacitor already includes the unit surface capacitance, when calculating the capacitance of the metal layer combination, the surface capacitance of the overlapping portion of the two metal layers includes the unit surface capacitance of the unit width. In order to prevent double calculation, it is necessary to determine the surface capacitance component of the metal layer combination. The above-mentioned surface capacitance component can be understood as the parasitic capacitance formed by the overlapping surface capacitance formed by the projected overlap width of the first metal layer and the second metal layer minus the unit surface capacitance of the unit width.

[0033] Specifically, the capacitance value of the metal layer combination can be expressed as: ,in, Indicates the capacitance of the overlapping surface. Represents capacitance per unit area. The projection overlap width, per unit width For a metal layer reconstruction combination, the corresponding combined capacitor, Reconstruct the combined capacitor corresponding to the other metal layer. This constitutes the surface capacitance component between the two metal layers in the metal layer assembly.

[0034] by Figure 3 For example, the capacitance value of the above-mentioned metal layer combination can be derived as follows: Suppose we need to calculate the capacitance between metal layer 1 and metal layer 2 on the left. We can first decompose the basic structure on the left into two symmetrical structures on the right. In this case, Cf1≈Cf3, Cf2≈Cf4, and Ca1≈Ca2≈Ca3. Let C be the capacitance between the two figures on the left, C1 for the upper right figure, and C2 for the lower right figure. C = Ca1 + Cf1 + Cf2 = ((Ca1 + 2*Cf1) + (Ca1 + 2*Cf2)) / 2 ≈((Ca2 + 2*Cf3) + (Ca3 + 2*Cf4)) / 2 =(C1 + C2) / 2 Furthermore, since the surface capacitance and w1 are linearly related, w1 can be fixed when constructing the table, denoted as Wmin. In this case: Cf3 = (C1 – Ca_uint * Wmin) / 2; Cf4 = (C2 – Ca_uint * Wmin) / 2; C = Ca1 + Cf1 + Cf2 ≈Ca1 + Cf3 + Cf4 = Ca_uint * w1 + (C1 – Ca * Wmin) / 2 + (2 – Ca * Wmin) / 2 = Ca_uint * (w1 – Wmin) + (C1 + C2) / 2 = Ca_uint * w1 - Ca_uint * Wmin + (C1 + C2) / 2 Where Ca_uint is the surface capacitance per unit width.

[0035] As can be seen, when generating the capacitance value of a metal layer combination, the metal layer combination can be split into two symmetrical metal layer reconstruction combinations, and then the combined capacitance of each metal layer reconstruction combination can be calculated separately. Then, by using the projected overlap width between the two metal layers in the metal layer combination, the surface capacitance component of the metal layer combination can be calculated. Based on the surface capacitance component and the combined capacitance, the actual capacitance value of the metal layer combination can be calculated.

[0036] Based on the above ideas, the technical solution provided in this embodiment of the application can improve the extraction efficiency of parasitic capacitance of metal layers by using a capacitance lookup table matching method. Specifically, the combined capacitance can be quickly determined in the capacitance lookup table based on the sidewall offset of the metal layer combination. Based on the obtained surface capacitance component, the capacitance value can be quickly determined, reducing the table building time and the matching time of the metal layer combination, thereby improving the extraction efficiency of parasitic capacitance of the metal layer.

[0037] In one embodiment, based on the aforementioned relative positional relationship, the metal layer combination is converted into two sets of symmetrical metal layer reconstruction combinations. Specifically, a first sidewall offset representing the relative positional relationship is identified. While maintaining the first sidewall offset unchanged, the dimensions of the first metal layer and / or the second metal layer are adjusted so that the adjusted first metal layer and the second metal layer form a symmetrical set of metal layer reconstruction combinations. In the formed metal layer reconstruction combinations, the sidewall offsets between the two sets of sidewalls on the same side of the adjusted first metal layer and the second metal layer are both the first sidewall offsets. Simultaneously, a second sidewall offset representing the relative positional relationship is identified. While maintaining the second sidewall offset unchanged, the dimensions of the first metal layer and / or the second metal layer are adjusted so that the adjusted first metal layer and the second metal layer form another symmetrical set of metal layer reconstruction combinations. In the formed other set of metal layer reconstruction combinations, the sidewall offsets between the two sets of sidewalls on the same side of the adjusted first metal layer and the second metal layer are both the second sidewall offsets.

[0038] In one embodiment, see Figure 4 , Figure 4 The left side shows the unconverted metal layer combination A. Figure 4The right side shows two symmetrical metal layer reconstruction combinations A1 and A2 obtained after the conversion. In metal layer combination A, the sidewall offsets on both sides are s1 and s2, respectively. In metal layer reconstruction combination A1, the sidewall offset on both sides is s1, and in metal layer reconstruction combination A2, the sidewall offset on both sides is s2. During the conversion from metal layer combination A to metal layer reconstruction combination A1, the first sidewall offset s1 and the size m1 of the second metal layer are kept constant. The size m2 of the first metal layer is adjusted so that the sidewall offset on both sides of metal layer reconstruction combination A1 is s1. Similarly, during the conversion from metal layer combination A to metal layer reconstruction combination A2, the second sidewall offset s2 and the size m1 of the second metal layer are kept constant. The size m2 of the first metal layer is adjusted so that the sidewall offset on both sides of metal layer reconstruction combination A2 is s2.

[0039] In one embodiment, see Figure 5 , Figure 5 The left side shows the unconverted metal layer combination B. Figure 5 The right side shows two symmetrical metal layer reconstruction combinations, B1 and B2, obtained after the conversion. The sidewall offsets on both sides of metal layer combination B are s1 and s2, respectively. The sidewall offsets on both sides of metal layer reconstruction combination B1 are both s1, and the sidewall offsets on both sides of metal layer reconstruction combination B2 are both s2. During the conversion from metal layer combination B to metal layer reconstruction combination B1, the second sidewall offset s2 is kept constant, and the size of the first metal layer m2 is adjusted so that the sidewall offsets on both sides of metal layer reconstruction combination B1 are both s2. Similarly, during the conversion from metal layer combination B to metal layer reconstruction combination B2, the first sidewall offset s1 is kept constant, and the size of the second metal layer m1 is adjusted so that the sidewall offsets on both sides of metal layer reconstruction combination B2 are both s1.

[0040] To construct the capacitance lookup table, a large number of metal layer combination samples with symmetrical structures can be obtained to ensure the comprehensiveness and applicability of the table. Converting metal layer combinations into samples with symmetrical structures simplifies capacitance matching. Matching corresponding metal layer combination samples by sidewall offset improves matching efficiency. Furthermore, the electric field distribution is more regular in symmetrical metal layer combination samples, facilitating capacitance extraction using a field solver, thus improving the efficiency of constructing the capacitance lookup table and consequently the capacitance extraction efficiency. Subsequently, utilizing the pre-generated capacitance lookup table helps to better handle various complex metal layer combination cases, further improving the capacitance extraction efficiency.

[0041] Since the relative length relationship between the target metal layer and the reference metal layer in each metal layer combination sample affects the sidewall capacitance of the metal layer combination sample, the construction of the capacitance lookup table needs to consider two structural types of each metal layer combination sample, including a first structural type and a second structural type. The first structural type is a metal layer structure where the target metal layer is longer than the reference metal layer (longer at the top and shorter at the bottom), and the second structural type is a metal layer structure where the target metal layer is shorter than the reference metal layer (shorter at the top and longer at the bottom). For example, please refer to [link to relevant documentation]. Figure 6 , Figure 6 The image on the right is a sample of the metal layer combination of the first structural type. Figure 6 The left-hand graph shows a metal layer combination sample of the second structural type. The correlation between the sidewall offset and the combination capacitance of the metal layer combination samples of the two structural types is established respectively.

[0042] In one implementation, when determining the combined capacitor matching each sidewall offset in a pre-generated capacitor lookup table, for any given sidewall offset, it is necessary to determine whether a combined capacitor matching the sidewall offset exists in the capacitor lookup table. Specifically, if it exists, the combined capacitor associated with the target offset is determined as the combined capacitor matching the sidewall offset; if it does not exist, it is necessary to compare the sidewall offset with each sidewall offset recorded in the capacitor lookup table, and generate a combined capacitor matching the sidewall offset based on the comparison result.

[0043] In this embodiment, if the sidewall offset is not greater than the largest sidewall offset in the capacitor lookup table, a first target offset and a second target offset adjacent to the sidewall offset are determined in the capacitor lookup table. A first combined capacitor associated with the first target offset and a second combined capacitor associated with the second target offset are then obtained. A combined capacitor matching the sidewall offset is generated based on the first and second combined capacitors. For example, interpolation calculations can be performed on the first and second combined capacitors to obtain a combined capacitor matching the actual sidewall offset.

[0044] In this embodiment, if the sidewall offset is greater than the maximum sidewall offset in the capacitor lookup table, the maximum sidewall offset is taken as the target offset, and the combined capacitor associated with the maximum sidewall offset is determined as the combined capacitor that matches the sidewall offset.

[0045] This embodiment can adapt to the combined capacitor lookup requirements under different sidewall offset conditions. Since it's difficult to guarantee a perfectly matching combined capacitor for every possible sidewall offset in a real capacitor lookup table, the technical solution provided in this embodiment can determine the combined capacitor matching the sidewall offset based on close sidewall offsets and associated combined capacitors even without an exact match. This ensures the completeness and accuracy of the lookup process, thereby improving the efficiency of capacitor extraction from metal layer combinations. Furthermore, when the sidewall offset is large, the trend of combined capacitor variation is relatively stable. Therefore, for sidewall offsets exceeding the range of the capacitor lookup table, determining the combined capacitor corresponding to the largest sidewall offset as the matching combined capacitor can, to a certain extent, ensure the reasonableness of the lookup results even in the absence of more precise data.

[0046] In one implementation, the unit surface capacitance can be determined based on two sets of symmetrical metal layer combinations. Specifically, two sets of symmetrical metal layer combinations with different widths are obtained. Each set of symmetrical metal layer combinations contains two parallel metal layers with no sidewall offset. The combined capacitance of each set of symmetrical metal layer combinations is generated, and the capacitance difference between the two combined capacitances is calculated. The width difference between the two sets of symmetrical metal layer combinations is determined, and the ratio between the capacitance difference and the width difference is determined as the unit surface capacitance of the metal layer structure characterized by the symmetrical metal layer combination. It should be noted that the metal layers corresponding to the two sets of symmetrical metal layer combinations are at the same process level in the integrated circuit.

[0047] In this embodiment, please refer to Figure 7 , Figure 7 The diagram shows two sets of symmetrical metal layer combinations with different widths. In each symmetrical metal layer combination, the first and second metal layers have the same width. It can be understood that in the case of symmetrical metal layer combinations, since the sidewall capacitances on both sides are essentially the same, they can be considered to cancel each other out after subtraction. Therefore, in the calculation of the combined capacitance, the sidewall capacitance of the symmetrical metal layer combination can be ignored, and only the surface capacitance of the symmetrical metal layer combination is considered. The widths of the two sets of symmetrical metal layer combinations are respectively... and In terms of unit width, it is expressed as Based on the above It can be represented as The above It can be represented as ,in, and It is a positive integer, and Less than Since the metal layers corresponding to the two sets of symmetrical metal layer combinations are at the same level, the unit surface capacitance of the two sets of symmetrical metal layer combinations is the same. The combined capacitances of the two sets of symmetrical metal layer combinations are calculated using the field solver. and Therefore, the unit surface capacitance can be obtained. Or it can be expressed as unit surface capacitance. .

[0048] In one embodiment, the surface capacitance component can also be determined based on the projected overlap width and a specified unit width. Specifically, the width difference between the projected overlap width and the specified unit width is calculated, and the product of the unit surface capacitance and the width difference is determined as the surface capacitance component of the metal layer combination. It should be noted that the aforementioned unit width must be set in a way that ensures it does not exceed the projected overlap width.

[0049] In this embodiment, the aforementioned surface capacitance component can also be understood as the parasitic capacitance between metal layers equal to the incremental width obtained by subtracting the projected overlap width of the first and second metal layers from the unit width. Specifically, the capacitance value of the metal layer combination can be expressed as... ,in, Represents the surface capacitance component. The projection overlap width, per unit width For a metal layer reconstruction combination, the corresponding combined capacitor, Reconstruct the combined capacitor corresponding to the other metal layer combination.

[0050] In one embodiment, the capacitance information value is used to characterize the capacitance value of the metal layer combination, which includes a combined average capacitance and a surface capacitance component. The combined average capacitance is obtained by averaging the combined capacitances determined for each of the two metal layer reconstruction combinations. Specifically, based on the combined capacitances determined for each metal layer reconstruction combination, the combined average capacitance is calculated, and the sum of the combined average capacitance and the surface capacitance component is determined as the capacitance value characterized by the capacitance information value of the metal layer combination.

[0051] In this embodiment, the average of half of the combined capacitance determined by each of the two sets of metal layer reconstruction combinations is taken as the combined average capacitance. Since the combined capacitance of the two sets of metal layer reconstruction combinations includes the sidewall capacitance values ​​on both sides of each combination, and the sidewall capacitance value on one side of each combination corresponds to the sidewall capacitance values ​​on both sides of the metal layer combination, half of the average value of the combined capacitance of the two sets of metal layer reconstruction combinations can be taken as the combined average capacitance of the metal layer combination. Based on the determination of the surface capacitance component, the sidewall capacitance of the metal layer combination is determined by matching the combined capacitance of the metal layer reconstruction combination in the capacitance lookup table. This allows for faster and more accurate acquisition of the capacitance information of the metal layer combination, thereby improving the extraction efficiency of the parasitic capacitance of the metal layer.

[0052] The technical solution provided in one or more embodiments of this application can improve the extraction efficiency of parasitic capacitance of metal layers by using a capacitance lookup table matching method. Specifically, the metal layer combination is adjusted to two sets of reconstructed metal layer combinations with symmetrical sidewall offsets on both sides. The matching combined capacitance is determined in the capacitance lookup table based on the sidewall offsets. After obtaining the surface capacitance component of the metal layer combination, the capacitance value of the metal layer combination is determined based on the surface capacitance component and the aforementioned combined capacitance. In related technologies, the capacitance value is usually determined in the capacitance lookup table based on multiple structural parameters of the metal layer combination. For metal layer combinations with complex structures, a large number of metal layer samples need to be constructed in the capacitance lookup table, and the matching time for metal layer combinations is relatively long. The technical solution provided in this application can quickly determine the combined capacitance in the capacitance lookup table based on the sidewall offset and a small amount of metal layer structural information. Based on obtaining the surface capacitance component, the capacitance value can be quickly determined, reducing the table construction time and the matching time of the metal layer combination, thereby improving the extraction efficiency of parasitic capacitance of the metal layer.

[0053] Please see Figure 8 This application also provides a capacitance value extraction device, the device comprising: The combined capacitor lookup unit 100 is used to determine a combined capacitor that matches each sidewall offset in a pre-generated capacitor lookup table based on the relative positional relationship between the first metal layer and the second metal layer; wherein the first metal layer and the second metal layer are adjacent; the sidewall offset is used to characterize the offset of a set of sidewalls on the same side of the first metal layer and the second metal layer. The sheet capacitance component calculation unit 200 is used to calculate the sheet capacitance components of the first metal layer and the second metal layer based on a preset unit sheet capacitance and the projected overlap width between the first metal layer and the second metal layer. The capacitance calculation unit 300 is used to calculate the capacitance value between the first metal layer and the second metal layer based on the combined capacitance that matches the surface capacitance component and the offset of each sidewall.

[0054] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0055] The capacitance value extraction device in this application embodiment is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, or other devices that can provide the above-mentioned functions.

[0056] Fourthly, this application also provides a computer device, the computer device including a memory and a processor, the memory being used to store a computer program, the computer program being executed by the processor to implement the capacitance value extraction method described in the first aspect.

[0057] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in one embodiment of this application, as shown below. Figure 9 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take a processor 10 as an example.

[0058] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0059] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0060] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0061] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0062] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0063] This application provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method of any embodiment of this application.

[0064] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0065] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0066] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0067] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0068] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0069] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0070] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0071] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0072] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0073] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for extracting capacitance values, characterized in that, The method includes: Based on the relative positional relationship between adjacent first and second metal layers, a combined capacitance matching each sidewall offset is determined in a pre-generated capacitance lookup table. The sidewall offset of one side of two adjacent metal layers represents the offset of one metal layer from another metal layer on that side of a set of sidewalls. For any sidewall offset, the sidewall offset has an associated metal layer combination sample, which includes an adjacent target metal layer and a reference metal layer. The target metal layer has a width of a specified unit width, and in a metal layer combination sample, the sidewall offsets on both sides of the target metal layer and the reference metal layer are the same. The combined capacitance matching the sidewall offset is the combined capacitance of the metal layer combination sample, which includes sidewall capacitance and surface capacitance. Calculate the difference between the projected overlap width between the first metal layer and the second metal layer and the unit width, and calculate the surface capacitance components of the first metal layer and the second metal layer based on the preset unit surface capacitance and the difference. The capacitance value between the first metal layer and the second metal layer is calculated based on the combined capacitance that matches the surface capacitance component and the offset of each sidewall.

2. The method according to claim 1, characterized in that, The capacitance lookup table is pre-generated in the following manner: Obtain samples with multiple metal layer combinations; For each metal layer combination sample, the combined capacitance of the metal layer combination sample is calculated based on the sidewall offset in the metal layer combination sample, and a correlation is established between the combined capacitance and the sidewall offset of the metal layer combination sample. The correlation between the combined capacitance and sidewall offset of each metal layer combination sample is statistically analyzed, and a capacitance lookup table is generated based on the statistical results.

3. The method according to claim 1, characterized in that, The step of determining the combined capacitance that matches each sidewall offset in a pre-generated capacitance lookup table includes: For any sidewall offset, determine in the capacitance lookup table whether there is a target offset that is consistent with the sidewall offset; If present, the combined capacitor associated with the target offset is determined to be a combined capacitor that matches the sidewall offset; If it does not exist, compare the sidewall offset with each sidewall offset recorded in the capacitor lookup table, and generate a combined capacitor that matches the sidewall offset based on the comparison result.

4. The method according to claim 3, characterized in that, Based on the comparison results, a combined capacitor matching the sidewall offset is generated, including: If the sidewall offset is greater than the largest sidewall offset in the capacitor lookup table, then the combined capacitor associated with the largest sidewall offset is determined as the combined capacitor that matches the sidewall offset. If the sidewall offset is not greater than the largest sidewall offset in the capacitor lookup table, then determine the first target offset and the second target offset adjacent to the sidewall offset in the capacitor lookup table, and obtain the first combined capacitor associated with the first target offset and the second combined capacitor associated with the second target offset; generate a combined capacitor that matches the sidewall offset based on the first combined capacitor and the second combined capacitor.

5. The method according to claim 1, characterized in that, The unit surface capacitance is pre-generated in the following manner: Two sets of symmetrical metal layer combinations with different widths are obtained. Each set of symmetrical metal layer combinations contains two metal layers placed in parallel, and the offset of each sidewall of the two metal layers is zero. Generate the combined capacitance for each symmetrical metal layer combination and calculate the capacitance difference between the two combined capacitances. The width difference between the two sets of symmetrical metal layer combinations is determined, and the ratio between the capacitance difference and the width difference is determined as the unit surface capacitance of the metal layer structure characterized by the symmetrical metal layer combination.

6. The method according to claim 1, characterized in that, The calculation of the surface capacitance components of the first metal layer and the second metal layer includes: Calculate the width difference between the projected overlap width and the specified unit width, and determine the product of the unit surface capacitance and the width difference as the surface capacitance components of the first metal layer and the second metal layer.

7. The method according to claim 1 or 6, characterized in that, The capacitance value between the first metal layer and the second metal layer is calculated based on the combined capacitance matching the surface capacitance component and the offset of each sidewall, including: Calculate the combined average capacitance based on the combined capacitance that matches the offset of each sidewall; The sum of the combined average capacitance and the surface capacitance component is determined as the capacitance value between the first metal layer and the second metal layer.

8. A capacitance value extraction device, characterized in that, The device includes: A combined capacitance lookup unit is used to determine, based on the relative positional relationship between a first metal layer and a second metal layer, a combined capacitance matching each sidewall offset in a pre-generated capacitance lookup table; wherein the first metal layer and the second metal layer are adjacent; the sidewall offset is used to characterize the offset of a set of sidewalls on the same side of the first metal layer and the second metal layer; for any sidewall offset, the sidewall offset has an associated metal layer combination sample, the metal layer combination sample includes an adjacent target metal layer and a reference metal layer, the width of the target metal layer is a specified unit width, and in a metal layer combination sample, the sidewall offsets on both sides of the target metal layer and the reference metal layer are the same, the combined capacitance matching the sidewall offset is the combined capacitance of the metal layer combination sample, the combined capacitance includes sidewall capacitance and surface capacitance; A surface capacitance component calculation unit is used to calculate the difference between the projected overlap width between the first metal layer and the second metal layer and the unit width, and to calculate the surface capacitance components of the first metal layer and the second metal layer based on a preset unit surface capacitance and the difference. The capacitance calculation unit is used to calculate the capacitance value between the first metal layer and the second metal layer based on the combined capacitance that matches the surface capacitance component and the offset of each sidewall.

9. A computer device, characterized in that, The computer device includes a memory and a processor, the memory being used to store a computer program that, when executed by the processor, implements the method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, Includes computer instructions for causing a computer to perform the method described in any one of claims 1 to 7.

Images