Fault tree Boolean function equivalent mapping method based on untrained neural network

Abstract

The invention discloses a fault tree Boolean function equivalent mapping method based on an untrained neural network, and relates to the field of fault tree analysis. In order to solve the problems that in the prior art, a Boolean function mapping structure is not beneficial to parallel expansion, the calculation efficiency is limited, and the Boolean function mapping structure is difficult to efficiently realize on high-parallel platforms such as a GPU, the invention provides a method for generating topological structure data by analyzing a fault tree model; the basic events, the intermediate events and the top events are mapped into neurons of an input layer, a hidden layer and an output layer respectively, a feedforward network with fixed weight and bias is constructed, and a logic activation function is defined in nodes to realize Boolean logic propagation. The input layer receives a basic event state vector, outputs a top event result through forward propagation, and can realize large-scale Boolean function mapping on a parallel platform through batch input matrixes. The method is suitable for reliability analysis, minimum cut set simplification, top event probability calculation, parallelization fault tree solving and the like of a large-scale complex system.

Description

Technical Field

[0001] This involves the field of fault tree analysis, and in particular, high-efficiency parallelized fault tree cut set solutions. Background Technology

[0002] Fault Tree Analysis (FTA) is a systematic and safety-oriented analysis method used to describe the causal relationships between a system's top event (usually a system failure) and its underlying events (usually component failures) through a logical structure. Its core lies in using Boolean logic functions to express the system's failure mechanism, thereby enabling quantitative calculation of system reliability, importance assessment, and fault diagnosis.

[0003] In traditional fault tree analysis, evaluating Boolean functions is a core computational process, commonly used for solving minimum cut sets (MCS), calculating the probability of the top event, and importance analysis. This process typically requires logical propagation judgments on a large number of combinations of basic events. For example, in the minimum cut set simplification phase, Boolean judgments must be performed on each candidate cut set to verify whether removing some events still leads to the top event. This means that in large-scale systems containing thousands of basic events and hundreds of thousands of cut sets, Boolean function mapping operations are called frequently, becoming the main performance bottleneck of the entire computational process.

[0004] To improve the efficiency of Boolean propagation in fault trees, researchers have proposed various acceleration algorithms. For example, using a binary decision diagram (BDD) to represent Boolean functions can reduce redundant logical calculations and improve solution efficiency through node sharing. Another example is probabilistic analysis based on the Monte Carlo method, which uses random sampling to achieve an approximate estimate of the probability of the top event, making it suitable for reliability assessment of complex systems. Some researchers have also attempted to decompose complex fault trees into several sub-modules through modular fault tree decomposition and parallel subtree computation to improve parallelism and scalability.

[0005] However, while BDD methods excel in structural compactness, they are prone to state explosion when dealing with deep, complex, large-scale fault trees, leading to a surge in memory consumption. Monte Carlo simulations, though versatile, still require sample-by-sample Boolean propagation, hindering the full utilization of parallel hardware performance. Modular decomposition, while partially parallelizable, suffers from limited overall acceleration due to strong logical interrelationships between modules. Furthermore, existing Boolean mapping methods are mostly based on serial implementations using recursive calls or logic gate traversal, resulting in irregular logical structures that are difficult to compute efficiently on parallel architectures such as GPUs and TPUs.

[0006] In recent years, with the development of artificial intelligence and parallel computing technologies, some studies have attempted to introduce neural network models into system reliability analysis to learn the correspondence between system states and top events. However, these methods mostly rely on supervised training data, requiring a large number of samples and a training process to achieve high Boolean function fitting accuracy. Furthermore, the models have poor interpretability and are not suitable for fault tree analysis scenarios with extremely high security requirements and where logical relationships must be clearly defined.

[0007] In summary, existing technologies suffer from drawbacks such as Boolean function mapping structures being unfavorable for parallel expansion, limited computational efficiency, inability to balance logical equivalence and interpretability, and difficulty in efficient implementation on high-parallel platforms such as GPUs. Summary of the Invention

[0008] To address the shortcomings of existing technologies, such as Boolean function mapping structures being unsuitable for parallel expansion, limited computational efficiency, inability to balance logical equivalence and interpretability, and difficulty in efficient implementation on high-parallel platforms like GPUs, the technical solution provided by this invention is as follows: A fault tree Boolean function equivalent mapping method based on a trainingless neural network includes: The steps involve parsing the input fault tree model, extracting the connection information between basic events, intermediate events, logic gates and top events, establishing the event hierarchy and connection relationships, and generating fault tree topology data. Based on the aforementioned topology data, the basic events, intermediate events, and top events in the fault tree are mapped to neurons in the input layer, hidden layer, and output layer, respectively, and corresponding connections are established to form a structurally equivalent neural network topology. Based on the neural network topology, the steps of constructing a training-free feedforward network structure, setting the connection weights to a fixed value of one and the bias to zero, to obtain a fixed computation structure for Boolean logic propagation are as follows: In the neuron nodes of the computational structure, activation functions are defined according to the logic gate type. The "AND" gate is mapped to the logical AND operation where the output is one when all inputs are one, and the "OR" gate is mapped to the logical OR operation where the output is one when any input is one, thus obtaining a neural network with Boolean logic mapping function. The steps are as follows: inputting the input vector representing the basic event state into the neural network, and obtaining the top event Boolean output or probabilistic output result through forward propagation; The steps of forming a batch input matrix from multiple input vectors and simultaneously performing forward propagation on a parallel computing platform to obtain multiple top event result sets are used to achieve parallel mapping of fault tree Boolean functions.

[0009] Furthermore, in a preferred embodiment, a semantic parsing algorithm is used to automatically identify logic gate types and event dependencies, and an event relationship table conforming to the topological order is generated based on the node hierarchy.

[0010] Furthermore, in a preferred embodiment, by establishing a node index table and defining directed connections, the topology of the neural network is made hierarchically equivalent to the logical structure of a fault tree.

[0011] Furthermore, in a preferred embodiment, all connection weights are set to one, the bias is set to zero, and the network parameters are kept frozen to avoid the backpropagation training process and ensure the determinism and interpretability of the computational logic.

[0012] Furthermore, in a preferred embodiment, the method further includes the step of extending the activation function to a continuously differentiable form, allowing the input signal to take real values ​​between zero and one, in order to achieve an integrated mapping between Boolean logic and probabilistic logic.

[0013] Furthermore, in a preferred embodiment, the method further includes a step of setting different sample input sequences at the input layer to form a matrix batch processing input, thereby enabling synchronous calculation of multiple fault combination scenarios.

[0014] Based on the same inventive concept, the present invention also provides a fault tree Boolean function equivalent mapping device based on a trainingless neural network, comprising: This module parses the input fault tree model, extracts the connection information between basic events, intermediate events, logic gates and top events, establishes the event hierarchy and connection relationship, and generates fault tree topology data. Based on the aforementioned topological data, the basic events, intermediate events, and top events in the fault tree are mapped to neurons in the input layer, hidden layer, and output layer, respectively, and corresponding connection relationships are established to form modules of structurally equivalent neural network topologies. Based on the neural network topology, a training-free feedforward network structure is constructed, with the connection weights set to a fixed value of one and the biases set to zero, to obtain a module with a fixed computational structure for Boolean logic propagation. In the neuron nodes of the computational structure, activation functions are defined according to the logic gate type. The "AND" gate is mapped to the logical AND operation where the output is one when all inputs are one, and the "OR" gate is mapped to the logical OR operation where the output is one when any input is one, thus obtaining a neural network module with Boolean logic mapping function. The module that inputs the input vector representing the basic event state into the neural network and obtains the top event Boolean output or probabilistic output result through forward propagation; This module combines multiple input vectors into a batch input matrix, performs forward propagation simultaneously on a parallel computing platform, and obtains multiple top event result sets to achieve parallel mapping of fault tree Boolean functions.

[0015] Based on the same inventive concept, the present invention also provides a computer storage medium for storing a computer program, wherein when the computer program is read by a computer, the computer executes the method described thereon.

[0016] Based on the same inventive concept, the present invention also provides a computer, including a processor and a storage medium, wherein when the processor reads a computer program stored in the storage medium, the computer executes the method described thereon.

[0017] Based on the same inventive concept, the present invention also provides a computer program product, which, when executed, implements the method described.

[0018] Compared with the prior art, the advantages of the technical solution provided by the present invention are as follows: This invention achieves a structurally equivalent expression of Boolean functions by mapping the logical structure of a fault tree to the topology of a trainingless neural network. This topology mapping transforms the original recursive call-based logical propagation process into a hierarchically parallel feedforward propagation, thus naturally adapting to parallel hardware architectures such as GPUs. Compared to the traditional serial computation mode of Boolean evaluation in fault trees, this mapping structure can maintain high throughput when processing tens of thousands of input samples, significantly improving the overall computational efficiency of Boolean mapping and cutset simplification processes.

[0019] This invention employs a manually defined structure with fixed weights and biases in the design of the neural network, eliminating the need for training. This allows the entire network to directly perform Boolean logic calculations after its initial setup, thus avoiding the complex process of relying on training samples and parameter optimization found in existing neural network methods. Compared to recent deep learning-based fault diagnosis models, this invention achieves stable and deterministic logical responses without a training process, significantly reducing the cost of model building and validation. Simultaneously, it avoids logical inconsistencies caused by parameter randomness, ensuring the system's interpretability and logical rigor.

[0020] This invention achieves a mathematically equivalent expression of Boolean logic gates by designing logical activation functions in neuron nodes. The activation function for each neuron is defined as a logical AND or OR operation, supporting both standard 0-1 Boolean inputs and continuous inputs to adapt to fuzzy logic and probabilistic analysis scenarios. Compared to traditional discrete logic propagation methods, this scalable activation function design not only preserves the clear semantics of Boolean logic but also enables system risk measurement in continuous domains, providing a new computational approach for uncertainty modeling of complex systems.

[0021] This invention utilizes a batch parallel mechanism in the input and output layers, enabling multiple fault combination vectors to be simultaneously input into the neural network for evaluation. Compared to existing sample-by-sample iterative computations based on decision graphs or Monte Carlo methods, this mechanism significantly reduces the number of Boolean propagations, allowing the determination of top events for multiple samples in a single forward propagation. This characteristic demonstrates a significant speedup effect in computationally intensive tasks such as large-scale minimal cut set simplification, system importance ranking, and probability estimation, solving the problem of excessively long computation times for traditional methods with high-dimensional inputs.

[0022] The neural network constructed in this invention is a static, feedforward computation graph, which can be directly implemented using existing deep learning frameworks and has good compatibility with mainstream hardware platforms such as GPUs and TPUs. Compared to traditional Boolean propagation systems that require dedicated logic interpreters or custom solvers, this solution is more convenient in engineering implementation. It can be quickly deployed through standard computing libraries and extended to distributed computing environments, significantly improving the system's integration in engineering analysis software and its practical application feasibility.

[0023] The proposed trainingless neural network Boolean mapping method, while maintaining logical accuracy, breaks through the serial limitation of traditional logic computation, realizing a shift in computational mode from gate-level Boolean propagation to matrix-style batch propagation. This mode combines the interpretability of formal logic with the high parallelism of neural network computation, filling the technical gap between logic analysis methods and deep computing frameworks, and providing a novel approach for the implementation of fault tree analysis on high-performance computing platforms.

[0024] It is applicable to reliability analysis, minimal cut set simplification, top event probability calculation, and parallel fault tree solving of large-scale complex systems. Attached Figure Description

[0025] Figure 1 This is a schematic diagram illustrating the transformation between fault trees and neural networks. Detailed Implementation

[0026] To make the advantages and benefits of the technical solution provided by the present invention clearer, the technical solution provided by the present invention will now be described in further detail with reference to the accompanying drawings, specifically: Implementation Method 1: This implementation method provides a fault tree Boolean function equivalent mapping method based on a trainingless neural network, including: The steps involve parsing the input fault tree model, extracting the connection information between basic events, intermediate events, logic gates and top events, establishing the event hierarchy and connection relationships, and generating fault tree topology data. Based on the aforementioned topology data, the basic events, intermediate events, and top events in the fault tree are mapped to neurons in the input layer, hidden layer, and output layer, respectively, and corresponding connections are established to form a structurally equivalent neural network topology. Based on the neural network topology, the steps of constructing a training-free feedforward network structure, setting the connection weights to a fixed value of one and the bias to zero, to obtain a fixed computation structure for Boolean logic propagation are as follows: In the neuron nodes of the computational structure, activation functions are defined according to the logic gate type. The "AND" gate is mapped to the logical AND operation where the output is one when all inputs are one, and the "OR" gate is mapped to the logical OR operation where the output is one when any input is one, thus obtaining a neural network with Boolean logic mapping function. The steps are as follows: inputting the input vector representing the basic event state into the neural network, and obtaining the top event Boolean output or probabilistic output result through forward propagation; The steps of forming a batch input matrix from multiple input vectors and simultaneously performing forward propagation on a parallel computing platform to obtain multiple top event result sets are used to achieve parallel mapping of fault tree Boolean functions.

[0027] The semantic parsing algorithm automatically identifies logic gate types and event dependencies, and generates an event relationship table that conforms to the topological order based on the node hierarchy.

[0028] By establishing a node index table and defining directed connections, the topology of the neural network is made hierarchically equivalent to the logical structure of a fault tree.

[0029] Set all connection weights to one and biases to zero, and keep the network parameters frozen to avoid backpropagation training and ensure the determinism and interpretability of the computational logic.

[0030] It also includes the step of extending the activation function to a continuously differentiable form, so that the input signal can take real values ​​between zero and one, in order to achieve an integrated mapping between Boolean logic and probabilistic logic.

[0031] It also includes the step of setting different sample input sequences in the input layer to form a matrix batch processing input, thereby enabling synchronous calculation of multiple fault combination scenarios.

[0032] Implementation Method Two: This implementation method is a further detailed description of the technical solution provided in Implementation Method One, specifically: A fault tree Boolean function equivalent mapping method based on untrained neural networks includes the following specific implementation steps.

[0033] First, the fault tree model of the target system is input and parsed. Fault trees are typically used to describe the logical relationships between the top event and multiple basic events in a system. Their structure, from bottom to top, includes basic events, intermediate events, and the top event. Semantic parsing of the input model file extracts the logical type of each event, the types of logic gates, and the causal connections between events. An index table is then created for all nodes to facilitate mapping between them in subsequent steps. During parsing, the hierarchical relationships of events must be determined to ensure that the input of any upper-level event only comes from the output of a lower-level event, thus generating a strict topological sorting result. After parsing, event topology data containing node types, logical relationships, and hierarchical dependencies is obtained, which serves as the input for the next step.

[0034] Then, the logical structure of the fault tree is mapped to the topology of the neural network. Based on the event topology data, each basic event, intermediate event, and top event is mapped to neurons in the input, hidden, and output layers of the neural network, respectively. During the mapping process, the logical connections between events in the fault tree remain unchanged; that is, if two events are logically related in the fault tree, a corresponding directed connection is established in the neural network. The resulting neural network is topologically equivalent to the original fault tree and can accurately express the logical dependencies of the top event on each basic event. The output of this step is a structurally equivalent neural network topology graph, providing a structural foundation for the subsequent construction of a training-free neural network.

[0035] Next, after obtaining the topology, a feedforward neural network without training is constructed. All connection weights are set to one, and all biases are set to zero; no backpropagation or parameter updates are performed. The core function of this network is not to learn the data distribution, but to directly perform Boolean logic propagation with fixed parameters. Because the network has a feedforward structure, the data flow propagates unidirectionally from the input layer to the output layer along the topology, thus achieving the same bottom-up judgment process as fault tree logic propagation. At this point, an executable static neural network computation structure is obtained, providing an execution framework for subsequent activation function design and logical operations.

[0036] Subsequently, activation functions are defined in the neuron nodes to implement Boolean logic operations. For neurons representing "AND" logic, the activation function is defined as the logical AND operation of the input signals; that is, the output is one only when all inputs are one, and the output is zero when any input is zero. For neurons representing "OR" logic, the activation function is defined as the logical OR operation of the input signals; the output is one as long as any input is one. Through these artificially designed activation functions, each neuron can equivalently implement the logic function of a Boolean gate, and the entire network can simulate the Boolean function mapping of a fault tree during forward propagation. Furthermore, to enhance the adaptability of the model, the activation function can be further extended to a continuously differentiable form to accept continuous input values ​​between zero and one. When the input is a continuous value, it represents the confidence or probability level of the occurrence of a basic event, and the network output reflects the probability or risk level of the top event, thus supporting the needs of fuzzy logic or probabilistic analysis. The output of this step is a neural network with logical mapping capabilities, providing the logical basis for the next step of input-output calculation.

[0037] After completing network construction and defining activation functions, the data streams of the input and output layers are processed. Based on the number of basic events in the fault tree, an input vector of corresponding length is constructed, where each element represents the state value of a basic event. The element takes a value of one when the event occurs and zero when it does not occur; when uncertainty needs to be considered in the analysis, the value can be any real number between zero and one. After receiving this vector, the input layer propagates the signal through the hidden layers and generates a result at the output layer. A value of one in the output layer indicates that the top event has occurred, and zero indicates that the top event has not occurred; if the output value is between zero and one, it represents the probability or risk level of the top event occurring. Through this input-output mapping relationship, a complete Boolean function evaluation or probabilistic risk assessment can be completed in a single network computation. The output of this step is the top event evaluation result data, which serves as the basic input for subsequent parallel computation stages.

[0038] To achieve high-efficiency computation, this invention further designs a batch parallel computing mechanism. Multiple different input samples (such as multiple candidate cut sets or different fault combination vectors) are arranged in rows to form an input matrix, which is then input into the input layer of the neural network. Utilizing the parallel computing capabilities of GPUs or multi-core CPUs, the network can process all input samples simultaneously with a single forward propagation and output the corresponding top event result set. Compared to traditional methods based on recursive logic propagation or sample-by-sample Boolean judgment, this batch processing method significantly reduces the number of Boolean function calls, maintaining near-linear scaling computational efficiency even with millions of input samples, thereby greatly improving the throughput of cut set simplification and probabilistic analysis. The parallel Boolean function mapping result set output in this step can be directly input into subsequent minimum cut set selection or system reliability analysis modules, enabling rapid fault tree solving on a high-performance platform.

[0039] Finally, the calculation results are applied and verified. By combining the Boolean results output by the neural network with the system's cut-set simplification algorithm, non-minimum cut sets can be quickly identified and removed, achieving automatic simplification of minimum cut sets in large-scale fault trees. In the top event probability assessment task, by inputting different event probability values ​​and using a continuous activation function, the probability of the top event can be quickly calculated. The results can be used for system risk assessment, importance ranking, or security decision analysis. Experimental results show that this method, while maintaining complete consistency with the original Boolean function logic, can achieve orders-of-magnitude computational speedup on the GPU platform. Compared with traditional serial logic propagation or decision graph methods, it demonstrates significant performance advantages and engineering application value in large-scale system analysis scenarios.

[0040] In summary, this invention constructs a computational framework that can directly execute equivalent Boolean function mappings through steps such as fault tree parsing, topology mapping, construction of a trainingless neural network, definition of logical activation functions, batch input computation, and result verification. The data flow between each step has a strict sequential logic; the output of one process becomes the input of the next, thus forming a complete technical path for efficient parallel Boolean solving on a GPU platform. This ensures both the accuracy and interpretability of Boolean logic and significantly improves the computational efficiency and scalability of fault tree analysis.

[0041] Implementation Method 3: Combination Figure 1 This embodiment describes the technical solution provided above in further detail through specific examples. Specifically: A fault tree Boolean function equivalent mapping method based on untrained neural networks includes the following steps: Step 1: Fault Tree to Neural Network Topology Conversion A method is used to completely and equivalently map the logical structure of a fault tree to the topology of a neural network. For example, leaf nodes representing basic events such as "high-pressure injection pump A failed to start" or "common cause valve B failed to open" in the fault tree will be directly mapped to neurons in the input layer of the neural network; while intermediate events such as "high-pressure injection subsystem failure" correspond to neurons in the hidden layer of the network; finally, the top event located at the top of the fault tree becomes the only output layer neuron of the neural network.

[0042] Step 2: Neural Network Design After topology transformation, a neural network with the same topological structure as the fault tree is obtained. All its internal parameters are frozen to fixed values, and special activation functions are manually modeled to transform the "AND" and "OR" operations in Boolean logic into specific continuous or discrete numerical operations, simulating the Boolean logic behavior of AND and OR gates respectively. This network can directly serve as an equivalent mapping to the corresponding Boolean function of the fault tree without any training. For example, for the "AND gate" logic of "emergency core cooling system startup failure" caused by both "high-pressure injection subsystem failure" and "low-pressure injection subsystem failure," the corresponding neuron activation function is designed to output "1" only when all upstream input signals are "1" (representing subsystem failure). In this way, the entire neural network becomes a computational tool that requires no training and is immediately usable. It directly serves as an equivalent mapping to the corresponding Boolean function of the fault tree, efficiently processing and judging the impact of various fault combinations on the overall function of the emergency core cooling system.

[0043] To further understand, the following detailed description of the fault tree Boolean function equivalent mapping method based on untrained neural networks is provided in conjunction with embodiments. The scope of protection is not limited by the following embodiments.

[0044] Example 1 by Figure 1 Taking the fault tree of the emergency core cooling system of a simplified pressurized water reactor nuclear power plant as an example, a fault tree Boolean function equivalent mapping method based on a non-trained neural network is presented, with the following specific steps: Step 1: Fault tree parsing and topology order generation.

[0045] The fault tree model describing the failure logic of the ECCS system is analyzed, extracting basic events, intermediate events, logic gates, and the top event, and its topology is established. Figure 1 Taking the simplified ECCS fault tree shown as an example, the top event G1 is defined as "ECCS startup failure". The parsing process will identify the physical causes and their logical relationships leading to this top event, for example: Basic Events: X1: High-pressure safety pump A failed to start. X2: Common cause valve B failed to open (this valve affects multiple subsystems) X3: Low-pressure safety injection pump C failed to start. X4: Sensor D fault Intermediate Events: G2: High-pressure injection subsystem failure G3: Low-pressure injection subsystem failure G4: Control signal failure Top Event: G1: ECCS startup failed The input fault tree model is parsed to extract basic events, intermediate events, logic gates, and the top event, and its topology is established. During the parsing process, the hierarchical relationship of each event is determined, and an event dependency table that strictly conforms to the topological order is generated.

[0046] Step 2: Topology Mapping from Fault Tree to Neural Network. Using the fault tree to neural network topology transformation module, each basic event is mapped to an input layer neuron, such as... Figure 1 As shown, each intermediate event or logic gate is mapped to a hidden layer neuron, and the top event is mapped to an output layer neuron. The connections between neurons strictly correspond to the event relationships in the fault tree; that is, the neuron corresponding to any event is only connected to the neuron corresponding to its lower-level input event, thus ensuring complete topological equivalence between the two.

[0047] like Figure 1 As shown, the four basic events representing "high-pressure injection pump A startup failure" (X1), "common cause valve B opening failure" (X2), "low-pressure injection pump C startup failure" (X3), and "sensor D failure" (X4) are mapped to input layer neurons. Each intermediate event or logic gate representing a subsystem failure is mapped to a hidden layer neuron, such as "high-pressure injection subsystem failure" (G2) and "low-pressure injection subsystem failure" (G3). Finally, the top event representing a system-level failure, "ECCS startup failure" (G1), is mapped to an output layer neuron. The connections between neurons strictly correspond to the causal relationships in the ECCS fault tree; that is, the neuron corresponding to any subsystem failure (such as G2) is only connected to the neurons corresponding to its direct cause events (such as X1 and X2) in the lower layer, thus ensuring that the neural network and the fault tree are physically and logically completely equivalent in terms of topology.

[0048] Step 3: Construct an untrained, manually designed neural network. After completing the topology mapping, a feedforward neural network is obtained. This network has the following characteristics: all connection weights are fixed at 1; all biases are fixed at 0; the internal parameters remain frozen and are not involved in any backpropagation training; the network is only used to perform forward Boolean logic computations. Step 4: Activation Function Design. To implement the logical operations of Boolean functions, special activation functions are artificially modeled in the neuron nodes: For the Boolean "AND" operation, the activation function is defined as the logical "AND" operation of the input vector, that is, the output is 1 only when all inputs are 1, otherwise it is 0; For the Boolean "OR" operation, the activation function is defined as the logical "OR" operation of the input vector, that is, the output is 1 as long as there is at least one input of 1.

[0049] The activation function defines the Boolean AND operation as follows, and the neuron outputs: The neuron outputs the following if the Boolean OR operation is defined as follows: Where xi is the neuron input, a vector of elements 0 and 1. It is a Boolean value of 0 or 1.

[0050] For example, the activation function of the OR gate neuron representing "high-pressure injection subsystem failure" (G2) is defined as a logical OR operation. This neuron outputs 1 when at least one of its input neurons X1 (pump A failure) or X2 (valve B failure) is in the state of 1 (indicating a failure). Similarly, the AND gate neuron representing the top event "ECCS startup failure" (G1) outputs 1 only when both its input neurons G2 (high-pressure injection failure) and G3 (low-pressure injection failure) are in the state of 1, indicating a failure to start the entire ECCS system.

[0051] The activation function can be further extended to a customizable prior function, applicable to Boolean inputs, fuzzy logic inputs, probabilistic inputs, or continuous value inputs. Its form includes, but is not limited to, discrete functions, gating functions, logical rule functions, continuously differentiable functions, or combinational functions, to enhance adaptability to different input types.

[0052] Step 5: Input and Output Layer Processing. When the input is a 0-1 binary vector, the input layer neurons receive the state of whether a basic event has occurred, and the output layer neurons output a Boolean value of 0 or 1, representing whether the event has occurred or not. For example, the input vector [1, 0, 0, 0] indicates that only "High-Pressure Pump A Start-up Failure" (X1=1) has occurred, while other basic components are working normally. Through forward computation, the neural network will output 0, which physically means that the "ECCS Start-up Failure" event has not occurred, and the system can still perform its safety functions.

[0053] When the input is a real number in the interval [0,1], the input layer neurons receive this value as the uncertainty or confidence level of the basic event. After forward propagation, the output layer neurons output a real number also in the interval [0,1], which is used to represent the probability or risk level of the top event. In fuzzy logic or probabilistic input scenarios, the network approximates the propagation relationship of Boolean logic through the continuously differentiable activation function, thereby achieving a quantitative assessment of the system's risk level.

[0054] Step 6: Batch Parallel Computation. The method supports large-scale batch input, meaning that input layer neurons can receive multiple vector samples at once. The network performs forward propagation on parallel computing hardware (such as GPUs), thereby simultaneously outputting the top event results corresponding to multiple samples, achieving high parallelism and computational acceleration.

[0055] The method can feed a large number of cutset input vectors representing different failure scenarios into the neural network as a single batch. For example, by taking a 10x4 matrix composed of 10 different cutset vectors (such as [1,0,0,0], [0,1,0,0], ..., [1,1,0,1]) as input, the network can perform a forward propagation on parallel computing hardware such as a GPU to quickly obtain an output vector containing 10 results, each corresponding to whether ECCS will fail to start under a cutset scenario.

[0056] The above description of several specific embodiments further details the technical solution provided by the present invention in order to highlight the advantages and benefits of the technical solution provided by the present invention. However, the above-described specific embodiments are not intended to limit the present invention. Any reasonable modifications and improvements to the present invention, combinations of embodiments, and equivalent substitutions based on the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A fault tree Boolean function equivalent mapping method based on a trainingless neural network, characterized in that, include: The steps involve parsing the input fault tree model, extracting the connection information between basic events, intermediate events, logic gates and top events, establishing the event hierarchy and connection relationships, and generating fault tree topology data. Based on the aforementioned topology data, the basic events, intermediate events, and top events in the fault tree are mapped to neurons in the input layer, hidden layer, and output layer, respectively, and corresponding connections are established to form a structurally equivalent neural network topology. Based on the neural network topology, the steps of constructing a training-free feedforward network structure, setting the connection weights to a fixed value of one and the bias to zero, to obtain a fixed computation structure for Boolean logic propagation are as follows: In the neuron nodes of the computational structure, activation functions are defined according to the logic gate type. The "AND" gate is mapped to the logical AND operation where the output is one when all inputs are one, and the "OR" gate is mapped to the logical OR operation where the output is one when any input is one, thus obtaining a neural network with Boolean logic mapping function. The steps are as follows: inputting the input vector representing the basic event state into the neural network, and obtaining the top event Boolean output or probabilistic output result through forward propagation; The steps of forming a batch input matrix from multiple input vectors and simultaneously performing forward propagation on a parallel computing platform to obtain multiple top event result sets are used to achieve parallel mapping of fault tree Boolean functions.

2. The fault tree Boolean function equivalent mapping method based on a trainingless neural network according to claim 1, characterized in that, The semantic parsing algorithm automatically identifies logic gate types and event dependencies, and generates an event relationship table that conforms to the topological order based on the node hierarchy.

3. The fault tree Boolean function equivalent mapping method based on a trainingless neural network according to claim 1, characterized in that, By establishing a node index table and defining directed connections, the topology of the neural network is made hierarchically equivalent to the logical structure of a fault tree.

4. The fault tree Boolean function equivalent mapping method based on a trainingless neural network according to claim 1, characterized in that, Set all connection weights to one and biases to zero, and keep the network parameters frozen to avoid backpropagation training and ensure the determinism and interpretability of the computational logic.

5. The fault tree Boolean function equivalent mapping method based on a trainingless neural network according to claim 1, characterized in that, It also includes the step of extending the activation function to a continuously differentiable form, so that the input signal can take real values ​​between zero and one, in order to achieve an integrated mapping between Boolean logic and probabilistic logic.

6. The fault tree Boolean function equivalent mapping method based on a trainingless neural network according to claim 1, characterized in that, It also includes the step of setting different sample input sequences in the input layer to form a matrix batch processing input, thereby enabling synchronous calculation of multiple fault combination scenarios.

7. A fault tree Boolean function equivalent mapping device based on a trainingless neural network, characterized in that, include: This module parses the input fault tree model, extracts the connection information between basic events, intermediate events, logic gates and top events, establishes the event hierarchy and connection relationship, and generates fault tree topology data. Based on the aforementioned topological data, the basic events, intermediate events, and top events in the fault tree are mapped to neurons in the input layer, hidden layer, and output layer, respectively, and corresponding connection relationships are established to form modules of structurally equivalent neural network topologies. Based on the neural network topology, a training-free feedforward network structure is constructed, with the connection weights set to a fixed value of one and the biases set to zero, to obtain a module with a fixed computational structure for Boolean logic propagation. In the neuron nodes of the computational structure, activation functions are defined according to the logic gate type. The "AND" gate is mapped to the logical AND operation where the output is one when all inputs are one, and the "OR" gate is mapped to the logical OR operation where the output is one when any input is one, thus obtaining a neural network module with Boolean logic mapping function. The module that inputs the input vector representing the basic event state into the neural network and obtains the top event Boolean output or probabilistic output result through forward propagation; This module combines multiple input vectors into a batch input matrix, performs forward propagation simultaneously on a parallel computing platform, and obtains multiple top event result sets to achieve parallel mapping of fault tree Boolean functions.

8. A computer storage medium for storing computer programs, characterized in that, When the computer program is read by the computer, the computer executes the method of claim 1.

9. A computer, comprising a processor and a storage medium, characterized in that, When the processor reads the computer program stored in the storage medium, the computer executes the method of claim 1.

10. A computer program product, as a computer program, is characterized by: When the computer program is executed, it implements the method of claim 1.

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