Pixel circuit, driving method of pixel circuit and display panel

Abstract

The embodiment of the invention discloses a pixel circuit, a driving method of the pixel circuit and a display panel. The pixel circuit comprises a driving module, and the driving module and a light-emitting module are connected to a first node and connected with a first power supply end; the compensation module and the first control end of the driving module are connected to a second node, the compensation module is connected with a first signal line, the control end of the compensation module is connected with a first scanning line, and the compensation module is used for compensating the threshold voltage of the driving module; the first storage module is connected between the first node and the second node, and the first storage module is used for storing the threshold voltage of the driving module; the second control end of the driving module inputs data voltage; wherein a first scanning signal transmitted by the first scanning line is a global control signal; the duration of the threshold voltage stored by the first storage module is an integral multiple of a frame period. According to the technical scheme provided by the embodiment, the brightness fluctuation depth of the display picture is reduced, screen flicker is inhibited, and the comfort of a user watching the screen is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a driving method for the pixel circuit, and a display panel. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for display panels. Existing display panels suffer from excessive brightness fluctuations, causing screen flicker and affecting user viewing comfort. Summary of the Invention

[0003] This invention provides a pixel circuit, a driving method for the pixel circuit, and a display panel to solve the problem that excessive brightness fluctuations in the displayed image cause screen flickering and affect the user's viewing comfort.

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: This invention provides a pixel circuit, comprising: The driving module is connected to the light-emitting module at the first node and to the first power supply terminal. The compensation module is connected to the first control terminal of the drive module at the second node. The compensation module is connected to the first signal line, and the control terminal of the compensation module is connected to the first scan line. It is used to compensate the threshold voltage of the drive module. A first storage module is connected between a first node and a second node, and is used to store the threshold voltage of the driving module; the second control terminal of the driving module inputs the data voltage. The first scan signal transmitted by the first scan line is a global control signal; the duration for which the first storage module stores the threshold voltage is an integer multiple of the frame period.

[0005] Optionally, the pixel circuitry also includes: The data writing module is connected to the third node via the second control terminal of the driver module. The data writing module is connected to the data line. The control terminal of the data writing module is connected to the second scan line. The data writing module is used to transmit the first initialization voltage to the third node during the reset phase and to transmit the data voltage to the third node during the data writing phase. The first scan signal transmitted by the first scan line is a global control signal during the reset phase and a line-by-line scan signal during the data writing phase.

[0006] Optionally, the pixel circuitry also includes: The second storage module is connected between the third node and the first node, and is used to store data voltage. Preferably, the compensation module includes a first switching transistor, and the first storage module includes a first capacitor; the first terminal of the first switching transistor is connected to a first signal line, the second terminal of the first switching transistor and the first terminal of the first capacitor are connected to a third node, the control terminal of the first switching transistor is connected to a first scan line, and the second terminal of the first capacitor is connected to a first power supply terminal. Preferably, the data writing module includes a second switching transistor, and the second storage module includes a second capacitor; the first terminal of the second switching transistor is connected to the data line, the second terminal of the second switching transistor and the first terminal of the second capacitor are connected to a third node, the control terminal of the second switching transistor is connected to the second scan line, and the second terminal of the second capacitor is connected to the first node.

[0007] Optionally, the pixel circuitry also includes: An initialization module is connected between the initialization line and the anode of the light-emitting module, and the control terminal of the initialization module is connected to the second scan line; the initialization module is used to transmit a second initialization voltage to the anode of the light-emitting module. Preferably, the second initialization voltage is equal to the first initialization voltage; Preferably, the initialization module includes a third switching transistor; the first electrode of the third switching transistor is connected to the initialization line, the second electrode of the third switching transistor is connected to the anode of the light-emitting module, and the control electrode of the third switching transistor is connected to the second scan line. Preferably, the driving module includes a driving transistor, the light-emitting module includes an organic light-emitting diode, the first electrode of the driving transistor is connected to a first power supply terminal, the second electrode of the driving transistor is connected to a first node and the anode of the organic light-emitting diode, and the cathode of the organic light-emitting diode is connected to a second power supply terminal; the first control terminal of the driving transistor is connected to a compensation module at a second node, and the second control terminal of the driving transistor is connected to a data writing module at a third node.

[0008] Optionally, when the first control terminal is the top gate, the second control terminal is the bottom gate; or, when the first control terminal is the bottom gate, the second control terminal is the top gate. Preferably, the data line is used to transmit a first initialization voltage during the reset phase and a data voltage during the data writing phase. Preferably, the second scan signal transmitted by the second scan line during the reset phase is a global control signal; and the second scan signal transmitted by the second scan line during the data writing phase is a line-by-line scan signal. Preferably, the first signal line is used to transmit a reference voltage signal to the second node through the compensation module.

[0009] According to another aspect of the present invention, this embodiment provides a method for driving a pixel circuit, the method being performed by the pixel circuit proposed in any of the first aspects; the method includes: During the compensation phase, the compensation modules in all pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and store the threshold voltage of the driving module through the first storage module; wherein, the storage duration of the threshold voltage in the first storage module is an integer multiple of the frame period; the first scan signal is a global control signal; During the data writing phase, the second control terminal of the drive module receives a data voltage.

[0010] Optionally, during the compensation phase, the compensation modules in all pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and store the threshold voltage of the driving module through the first storage module, including: During the compensation phase of the nth frame, the compensation modules in all pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and store the threshold voltage of the driving module through the first storage module; n is an integer greater than or equal to 1. From frame (n+1) to frame (n+m), the threshold voltage stored in the first storage module of the pixel circuit compensates for the threshold voltage of the driving module; m is an integer greater than or equal to 1. During the compensation stage of the (n+m+1)th frame, the compensation modules in all pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and store the threshold voltage of the driving module through the first storage module. Preferably, during the compensation phase, the first storage module in all pixel circuits simultaneously stores the threshold voltage of the driving module, and the storage duration of the threshold voltage is m times the frame period.

[0011] Optionally, during the data writing phase, the second control terminal of the drive module receives a data voltage, including: During the data writing phase, the data writing module of the pixel circuit transmits data voltage to the second control terminal of the driving module line by line according to the second scan signal; the second scan signal is a line-by-line scan signal during the data writing phase. During the data writing phase, the second storage module in the pixel circuit stores the data voltage of the driving module line by line; Preferably, in the compensation frame, all pixel circuits include a compensation phase and a data writing phase, with the compensation phase set during the idle phase of the data writing phase in all pixel circuits. There is at least one write frame between two adjacent compensation frames, and in the write frame, all pixel circuits do not include the compensation phase; Preferably, in the compensation frame, the compensation stage is set before the data writing stage in the first row of pixel circuits, or after the data writing stage in the last row of pixel circuits.

[0012] Optionally, during the compensation stage, before the compensation modules in all pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and before storing the threshold voltage of the driving module through the first storage module, the following steps are also included: During the reset phase, the data writing modules in all pixel circuits simultaneously initialize the second control terminal of the drive module according to the second scan signal and the first initialization voltage transmitted through the data line. During the reset phase, the initialization modules in all pixel circuits simultaneously initialize the anode of the light-emitting module according to the second initialization voltage transmitted through the initialization line by the second scan signal; wherein, the second scan signal is a global control signal during the reset phase; the first initialization voltage is equal to the second initialization voltage.

[0013] According to another aspect of the present invention, this embodiment provides a display panel, including: a light-emitting module and at least one pixel circuit as described in any of the first aspects; Preferably, the display panel includes a compensation frame and a write frame; in the compensation frame, all pixel circuits include a compensation phase and a data write phase, and the compensation phase is set during the idle phase of the data write phase in all pixel circuits. Preferably, in the compensation frame, the compensation stage is set before the data writing stage in the first row of pixel circuits, or after the data writing stage in the last row of pixel circuits. Preferably, at least one write frame is included between two adjacent compensation frames, and in the write frame, all pixel circuits do not include the compensation phase; Preferably, in the compensation frame and the write frame, the light emission phase of at least a portion of the light-emitting modules and the data writing phase of at least a portion of the pixel circuits are performed simultaneously.

[0014] The pixel circuit provided in this embodiment of the invention includes a driving module, a compensation module, and a first storage module. The compensation module compensates for the threshold voltage of the driving module. Then, the first storage module stores the threshold voltage of the driving module. By setting the first scan signal transmitted by the first scan line as a global control signal, all pixel circuits located in different rows can be compensated simultaneously. The compensation stage and the data writing stage are separated. Then, by setting the duration of the threshold voltage storage in the first storage module to an integer multiple of the frame period, the first storage module of the pixel circuit in the compensation frame stores the threshold voltage for a longer duration. This eliminates the need for a compensation stage in the writing frames between adjacent compensation frames, thereby reducing the duration of the non-light-emitting compensation stage and effectively reducing the brightness fluctuation depth of the light-emitting module during operation, thus effectively reducing the flicker of the light-emitting module. On the other hand, by setting the first scan signal as a global control signal, at least two pixel circuits located in different rows can simultaneously perform threshold voltage compensation, and each compensation module of at least two pixel circuits located in different rows can share a single GIP circuit, reducing the number of GIP circuits in the display panel, thereby reducing the space occupied by the GIP circuits on the display panel bezel and significantly reducing the width of the left and right bezels of the display panel. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of the present invention and these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention; Figure 7 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention; Figure 8This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention; Figure 9 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention; Figure 10 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] Based on the above-mentioned technical problems, this embodiment proposes the following solutions: Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 1The pixel circuit 100 provided in this embodiment of the invention includes: a driving module 1, which is connected to a first node N1 and a first power supply terminal VDD, and a compensation module 2, which is connected to a first control terminal of the driving module 1 and a second node N2, and is connected to a first signal line Ini and a first scan line COM, for compensating the threshold voltage of the driving module 1; a first storage module 3, which is connected between the first node N1 and the second node N2, and is used to store the threshold voltage of the driving module 1; and a second control terminal of the driving module 1 inputs a data voltage; wherein the first scan signal transmitted by the first scan line COM is a global control signal; and the duration for which the first storage module 3 stores the threshold voltage is an integer multiple of the frame period.

[0020] Specifically, the first power supply terminal VDD can transmit a DC voltage, such as a first power supply voltage. The first terminal of the driving module 1 can receive a DC voltage. The first node N1 is the node where the first terminal of the light-emitting module D1 and the second terminal of the driving module 1 are electrically connected. The light-emitting module D1 may include a light-emitting element, such as an organic light-emitting diode (OLED). The second node N2 is the node where the first terminal of the compensation module 2 and the first control terminal of the driving module 1 are electrically connected. The first terminal of the light-emitting module D1 is typically the anode. The driving module 1 may include a driving transistor. The driving current of the driving module 1 is used to drive the light-emitting module D1 to emit light. For example, the first terminal of the driving module 1 can be the drain, and the second terminal of the driving module 1 can be the source; no limitations are imposed here.

[0021] The compensation module 2 compensates for the threshold voltage of the driving module 1. Since the control terminal of the compensation module 2 is connected to the first scan line COM, the first scan signal transmitted by the first scan line COM is a global control signal. At least two pixel circuits 100 located in different rows can simultaneously perform threshold voltage compensation, and each compensation module 2 of at least two pixel circuits 100 located in different rows can share a single gate inlet (GIP) circuit. This reduces the number of GIP circuits in the display panel, thereby reducing the space occupied by the GIP circuits on the display panel's bezel and consequently reducing the width of the left and right bezels of the display panel.

[0022] The display panel can display frames including compensation frames and write frames. The frame period refers to the duration of one display frame; for the pixel circuit 100, it is the interval between two consecutive write data voltages. The frame periods of the compensation frames and write frames can be the same. In the compensation frame, the compensation module 2 of the pixel circuit 100 compensates the threshold voltage of the driving module 1 and stores the threshold voltage through the first storage module 3 of the pixel circuit 100, then proceeds to the data writing stage. In the write frame, the compensation module 2 of the pixel circuit 100 does not need to compensate the threshold voltage of the driving module 1, and the data writing stage can proceed. The duration for which the first storage module 3 stores the threshold voltage is an integer multiple of the frame period, allowing an integer number of write frames to be included between two consecutive compensation frames.

[0023] Because the duration for storing the threshold voltage in the first storage module 3 is set to an integer multiple of the frame period, after the threshold voltage compensation of the driving module 1 of the pixel circuit 100 is performed and the threshold voltage is stored within the period of one display frame of the compensation frame, no threshold voltage compensation is required in the next at least one display frame period, which is then used as a write frame. In the write frame, the threshold voltage stored in the first storage module 3 can maintain the compensation value of the threshold voltage of the driving module 1, thus ensuring both the uniformity of the display panel and significantly reducing the duration of the compensation phase. Since the light-emitting module D1 does not emit light during the compensation phase, and the display panel is in a black state, by setting the first scan signal controlling the compensation module 2 as a global control signal, and the duration for storing the threshold voltage in the first storage module 3 to an integer multiple of the frame period, all pixel circuits 100 located in different rows can be compensated simultaneously. Furthermore, the duration for storing the threshold voltage in the first storage module 3 of the pixel circuit 100 in the compensation frame is relatively long, so that no compensation phase is required between adjacent compensation frames in the write frame, thereby effectively reducing the brightness fluctuation depth of the light-emitting module D1 during operation and effectively reducing the flicker of the light-emitting module D1.

[0024] After the compensation phase, the data writing phase begins. During the data writing phase, the data voltage can be transmitted to the second control terminal of the driver module 1. This configuration ensures that the light-emitting module D1 can emit light after the data voltage is written. During the light-emitting phase, at least two pixel circuits 100 located in different rows can each drive their connected light-emitting modules D1 to emit light simultaneously.

[0025] For example, at least two pixel circuits 100 located in different rows can have some pixel circuits 100 driving the light-emitting module D1 to emit light while others are in the data writing stage. This configuration results in a shorter black screen time on the display panel. This further reduces the brightness fluctuation depth when the light-emitting module D1 is working, thereby reducing the brightness fluctuation depth of the display panel, reducing brightness flicker issues, and improving user comfort when viewing the display panel.

[0026] The pixel circuit 100 provided in this embodiment includes a driving module 1, a compensation module 2, and a first storage module 3. The compensation module 2 compensates for the threshold voltage of the driving module 1. Then, the first storage module 3 stores the threshold voltage of the driving module 1. By setting the first scan signal transmitted by the first scan line COM as a global control signal, all pixel circuits 100 located in different rows can be compensated simultaneously. The compensation stage and the data writing stage are separated. Then, by setting the duration of the threshold voltage storage in the first storage module 3 to an integer multiple of the frame period, the storage duration of the threshold voltage in the first storage module 3 of the pixel circuit 100 of the compensation frame is longer, so that the write frame between adjacent compensation frames does not need a compensation stage, thereby reducing the duration of the non-light-emitting compensation stage, effectively reducing the brightness fluctuation depth when the light-emitting module D1 is working, and effectively reducing the flicker of the light-emitting module D1.

[0027] On the other hand, by setting the first scanning signal as a global control signal, at least two pixel circuits 100 located in different rows can simultaneously perform threshold voltage compensation, and each compensation module 2 of at least two pixel circuits 100 located in different rows can share a GIP circuit, reducing the number of GIP circuits in the display panel, thereby reducing the space occupied by the GIP circuits on the bezel of the display panel and significantly reducing the width of the left and right bezels of the display panel.

[0028] Optional, Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Based on the above embodiments, see [link to other embodiments]. Figure 2 The pixel circuit 100 may further include: a data writing module 4, the data writing module 4 being connected to the second control terminal of the driving module 1 at the third node N3, the data writing module 4 being connected to the data line Data, the control terminal of the data writing module 4 being connected to the second scan line SNW, the data writing module 4 being used to transmit a first initialization voltage to the third node N3 during the reset phase, and to transmit a data voltage to the third node N3 during the data writing phase; wherein, the first scan signal transmitted by the first scan line COM is a global control signal during the reset phase and a line-by-line scan signal during the data writing phase.

[0029] Specifically, the second scan signal transmitted by the second scan line SNW is a line-by-line scan signal during the data writing stage, which enables the data writing stage to proceed line by line. This allows the pixel circuits 100 located in different rows to write data voltage line by line, making it easier to accurately write the data voltage to the pixel circuits 100 of the corresponding row.

[0030] Before the compensation phase of the pixel circuit 100, the pixel circuit 100 also includes a reset phase. During the reset phase, the data writing module 4 transmits a first initialization voltage to the third node N3. This first initialization voltage initializes the second control terminal of the driving module 1. Since the second scan signal is a global control signal during the reset phase, the reset phases of the pixel circuits 100 in each row are performed simultaneously, saving reset time, improving reset efficiency, and thus shortening the reset phase duration when in a black state. This further reduces the brightness fluctuation depth when the light-emitting module D1 is working, thereby reducing brightness flicker on the display panel and improving user comfort when viewing the display panel.

[0031] The data writing module 4 transmits the first initialization voltage to the third node N3 during the reset phase and the data voltage to the third node N3 during the data writing phase. This allows the pixel circuit 100 to reuse the same data line Data during the data writing and reset phases, thereby reducing the number of signal lines connected to the pixel circuit 100 for transmitting the first initialization voltage. This reduces the layout space occupied by the signal lines transmitting the first initialization voltage on the display panel, thereby improving the resolution of the display panel.

[0032] Optional, Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Based on the above embodiments, see [link to other embodiments]. Figure 3 The pixel circuit 100 may also include a second storage module 5, which is connected between the third node N3 and the first node N1, and is used to store data voltage.

[0033] Specifically, during the data writing phase, the data writing module 4 is activated based on the second scan signal transmitted on the second scan line SNW, so that the data voltage Vdata transmitted on the data line Data is transmitted to the second storage module 5 through the activated data writing module 4. The second storage module 5 can store the data voltage Vdata transmitted on the data line Data.

[0034] Optionally, based on the above embodiments, see also... Figure 3 The Data line is used to transmit the first initialization voltage during the reset phase and the data voltage during the data write phase.

[0035] Specifically, this configuration allows the same data line (Data) to be reused for both the data writing and reset phases of the pixel circuit 100. This reduces the number of signal lines connected to the pixel circuit 100 used to transmit the first initialization voltage, thereby reducing the width of the display panel bezel occupied by these signal lines and significantly minimizing the bezel size. Furthermore, this configuration simplifies the structure of the pixel circuit 100, effectively saving layout space and improving the resolution of the display panel.

[0036] Optional, Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Based on the above embodiments, see [link to other embodiments]. Figure 4 The compensation module 2 may include a first switching transistor T2, and the first storage module 3 includes a first capacitor Cst1. The first terminal of the first switching transistor T2 is connected to the first signal line Ini, the second terminal of the first switching transistor T2 and the first terminal of the first capacitor Cst1 are connected to the third node N3, the control terminal of the first switching transistor T2 is connected to the first scan line COM, and the second terminal of the first capacitor Cst1 is connected to the first power supply terminal VDD.

[0037] Specifically, the first switching transistor T2 can be an N-type or P-type switching transistor. When the control electrode of the first switching transistor T2 is turned on according to the first scan signal transmitted on the first scan line COM, the reference voltage signal Vini transmitted on the first signal line Ini is transmitted to the first control terminal of the driving module 1 for compensation of the threshold voltage of the driving module 1. The threshold voltage of the driving module 1 is stored in the first capacitor Cst1. The duration for which the first capacitor Cst1 stores the threshold voltage is an integer multiple of the frame period.

[0038] It should be noted that, Figure 4 The example shown is an N-type switch transistor T2, and no limitation is made here.

[0039] Optionally, based on the above embodiments, see also... Figure 4 The data writing module 4 may include a second switch T4, and the second storage module 5 includes a second capacitor Cst2. The first terminal of the second switch T4 is connected to the data line Data, the second terminal of the second switch T4 and the first terminal of the second capacitor Cst2 are connected to the third node N3, the control terminal of the second switch T4 is connected to the second scan line SNW, and the second terminal of the second capacitor Cst2 is connected to the first node N1.

[0040] Specifically, the second switch T4 can be an N-type or P-type switch. During the data writing phase, when the control electrode of the second switch T4 is turned on according to the second scan signal transmitted on the second scan line SNW, the data voltage transmitted on the data line Data is transmitted to the second control terminal of the driver module 1 and stored in the second capacitor Cst2. During the reset phase, when the control electrode of the second switch T4 is turned on according to the second scan signal transmitted on the second scan line SNW, the first initialization voltage Vref1 transmitted on the data line Data is transmitted to the second control terminal of the driver module 1, resetting the second control terminal of the driver module 1.

[0041] It should be noted that, Figure 4 An example is shown where the second switch T4 is an N-type switch, but no limitation is made here.

[0042] Optional, Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Based on the above embodiments, see [link to other embodiments]. Figure 5 The pixel circuit 100 may further include: an initialization module 6 connected between the initialization line Ref and the anode of the light-emitting module D1, wherein the control terminal of the initialization module 6 is connected to the second scan line SNW; the initialization module 6 is used to transmit a second initialization voltage Vref2 to the anode of the light-emitting module D1. Preferably, the second initialization voltage Vref2 is equal to the first initialization voltage Vref1.

[0043] Specifically, during the reset phase, the initialization module 6 initializes the anode of the light-emitting module D1 based on the second initialization voltage Vref2 transmitted on the second initialization line Ref when the second scan signal transmitted on the second scan line SNW is turned on. The initialization module 6 initializes the anode of the light-emitting module D1 during the initialization phase.

[0044] Optionally, based on the above embodiments, see also... Figure 5 The initialization module 6 includes a third switch transistor T3; the first electrode of the third switch transistor T3 is connected to the initialization line Ref, the second electrode of the third switch transistor T3 is connected to the anode of the light-emitting module D1, and the control electrode of the third switch transistor T3 is connected to the second scan line SNW.

[0045] Specifically, the third switch T3 can be an N-type switch or a P-type switch. During the reset phase, when the third switch T3 is turned on according to the second scan signal transmitted on the second scan line SNW, the second initialization voltage Vref2 transmitted on the initialization line Ref initializes the anode of the light-emitting module D1. The third switch T3 initializes the anode of the light-emitting module D1 during the initialization phase.

[0046] It should be noted that, Figure 5An example is shown where the third switch T3 is an N-type switch, but no limitation is made here.

[0047] Optional, Figure 6 This is a schematic diagram of the driving timing of a pixel circuit according to an embodiment of the present invention. Combined with... Figures 5 to 6 Based on the above embodiments, the driving module 1 includes a driving transistor T1, the light-emitting module D1 includes an organic light-emitting diode, the first terminal of the driving transistor T1 is connected to the first power supply terminal VDD, the second terminal of the driving transistor T1 is connected to the first node N1 and the anode of the organic light-emitting diode, and the cathode of the organic light-emitting diode is connected to the second power supply terminal VSS; the first control terminal of the driving transistor T1 is connected to the compensation module 2 at the second node N2, and the second control terminal of the driving transistor T1 is connected to the data writing module 4 at the third node N3.

[0048] Optional, combined Figures 5 to 6 Based on the above embodiments, the second scan signal transmitted by the second scan line SNW during the reset phase is a global control signal; and the second scan signal transmitted by the second scan line SNW during the data writing phase is a line-by-line scan signal.

[0049] Specifically, since the second scan signal is a global control signal during the reset phase, the reset phases of the pixel circuits 100 in each row are performed simultaneously, saving reset time, improving reset efficiency, and thus shortening the reset phase time when in a black state. During the data writing phase, the second scan signal is a line-by-line scan signal, allowing the pixel circuits 100 to write data line by line. After data writing, the corresponding light-emitting modules D1 of each row of pixel circuits 100 can emit light simultaneously, further reducing the brightness fluctuation depth of the light-emitting modules D1 during operation, thereby reducing brightness flicker on the display panel and improving user comfort when viewing the display panel.

[0050] Optional, combined Figures 5 to 6 Based on the above embodiments, the first signal line Ini is used to transmit the reference voltage signal Vini to the second node N2 through the compensation module 2.

[0051] Specifically, the reference voltage signal Vini is a DC voltage signal. The reference voltage signal Vini is used to compensate for the threshold voltage of drive module 1.

[0052] For example, in combination Figures 5 to 6 The operation of the pixel circuit 100 provided in this embodiment is as follows: In the initial stage t1, the first scan signal transmitted by the first scan line COM is at a low level, and the second scan signal transmitted by the second scan line SNW is at a low level. The first initialization voltage Vref1 is transmitted on the data line Data.

[0053] During the reset phase t2, the light-emitting module D1 does not emit light. The first scan signal transmitted by the first scan line COM is set to a high level, and the second scan signal transmitted by the second scan line SNW is set to a high level. The first switch T2, the second switch T4, and the third switch T3 are all turned on. The first power supply terminal VDD inputs the first power supply voltage to the first terminal of the driver module 1. Because the first switch T2 is turned on, the potential of the second node N2 is the reference voltage signal Vini. Because the second switch T4 is turned on, the potential of the third node N3 is the first initialization voltage Vref1. Because the third switch T3 is turned on, the potential of the first node N1 is the second initialization voltage Vref2. This setting resets both the first capacitor Cst1 and the second capacitor Cst2.

[0054] During compensation phase t3, the first scan signal transmitted by the first scan line COM is at a high level, while the second scan signal transmitted by the second scan line SNW is at a low level. The voltage at the first control terminal of the driving transistor T1 is the reference voltage signal Vini. The potential of the second terminal of the driving transistor T1, i.e., the first node N1, rises from the second initialization voltage Vref2, and the threshold voltage Vth of the driving transistor T1 begins to be compensated. After compensation, the final threshold voltage Vth is stored in the first capacitor Cst1. The bottom gate of the driving transistor T1 is controlled by the first capacitor containing the threshold voltage Vth information, thereby eliminating the process differences of the driving transistors T1 that control different pixel circuits 100 during this compensation phase, approximately resulting in a threshold voltage value of 0 for each driving transistor T1 in the display panel. Since the first scan signal transmitted by the first scan line COM is a global control signal during reset phase t2 and compensation phase t3, the number of groups driven by the GIP circuit is reduced, which can significantly compress the width of the left and right bezels of the display panel.

[0055] During the data writing phase t4, the first scan signal transmitted by the first scan line COM is low, and the first switch T2 is turned off. The second scan signal transmitted by the second scan line SNW is set to high. Both the second switch T4 and the third switch T3 are turned on. The potential of the anode of the light-emitting module D1 is the second initialization voltage Vref2. Because the second switch T4 is turned on, the potential of the third node N3 is the data voltage, causing the data voltage information stored in the second capacitor Cst2 to be transmitted to the second control terminal of the driving transistor T1 and stored in the second capacitor Cst2. The data voltage information stored in the second capacitor Cst2 is: Vdata - Vref.

[0056] During the data writing phase t4, the potential of the anode of the light-emitting module D1 is also initialized simultaneously. That is, when the third switch T3 is turned on, the second initialization voltage Vref2 is written to the anode of the light-emitting module D1, and the anode of the light-emitting module D1 is initialized to the second initialization voltage Vref2. This setting effectively avoids the difference in luminous brightness caused by the difference in potential between the anodes of each light-emitting module D1, thereby improving the uniformity of luminous emission among each light-emitting module D1.

[0057] After data writing stage t4, the light-emitting stage begins. In the light-emitting stage, after the data voltage information is written to the corresponding pixel circuit 100, the light-emitting module D1 connected to that pixel circuit 100 begins to light up. Light-emitting modules D1 located in different rows can light up simultaneously. While the light-emitting modules D1 connected to pixel circuits 100 in some rows enter the light-emitting stage, the pixel circuits 100 in the next row can perform data writing stage t4 row by row. The driving current of the driving transistor T1 is controlled by the data voltage information Vdata-Vref, driving the light-emitting module D1 to emit light. When the driving transistor T1 operates in the saturation region, the driving current is approximately expressed as I=K(Vdata-Vref). 2 In the formula, K is the scaling factor.

[0058] It should be noted that, Figure 6 An example is shown where multiple second scan lines SNW are SnW <1> SnW <2> ,…….and Figure 5 When the pixel circuit 100 in the middle is executed, each second scan line SNW <1> SnW <2> The effective level signal of , ... is high level, and no restrictions are imposed here. Figure 6 In the diagram, t4 can represent the data writing stage of the first row of pixel circuits 100, and t5 can represent the data writing stage of the second row of pixel circuits 100. When the display panel has multiple rows, pixel circuits 100 located in different rows can write data according to the corresponding first scan signal.

[0059] Optionally, based on the above embodiments, see also... Figure 5 and Figure 6 When the first control terminal is the top gate, the second control terminal is the bottom gate; or, when the first control terminal is the bottom gate, the second control terminal is the top gate.

[0060] Specifically, the driving module 1 is a four-terminal device. The driving module 1 has a first control terminal and a second control terminal. In one optional implementation, the first control terminal can be a top gate (TG) and the second control terminal can be a bottom gate (BG). This configuration, due to the lower sensitivity of the bottom gate, results in higher control precision, leading to more accurate writing of data voltage information and improving the display effect of the display panel.

[0061] In another optional implementation, the first control terminal can be a bottom gate (BG) and the second control terminal can be a top gate (TG). Since the bottom gate has lower control sensitivity but higher control precision, when the first control terminal is a bottom gate, the first control terminal has a higher tolerance for threshold voltage compensation errors, which can better improve the display unevenness caused by threshold voltage dispersion, thereby improving the display effect of the display panel.

[0062] This embodiment provides a method for driving a pixel circuit. The method for driving a pixel circuit provided in this embodiment is executed by the pixel circuit 100 proposed in any of the above embodiments. Figure 7 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention. Combined with... Figure 1 and Figure 7 The driving method for the pixel circuit 100 provided in this embodiment includes: S101. During the compensation phase, the compensation modules 2 in all pixel circuits 100 simultaneously compensate the threshold voltage of the driving module 1 according to the first scan signal, and store the threshold voltage of the driving module 1 through the first storage module 3; wherein, the duration for which the first storage module 3 stores the threshold voltage is an integer multiple of the frame period; the first scan signal is a global control signal.

[0063] S102. During the data writing stage, the second control terminal of the drive module 1 inputs a data voltage.

[0064] Optional, Figure 8 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention. (In conjunction with...) Figure 2 and Figure 8 The pixel circuit driving method provided in this embodiment includes: S201. In the compensation stage of the nth frame, the compensation modules 2 in all pixel circuits 100 simultaneously compensate the threshold voltage of the driving module 1 according to the first scanning signal, and store the threshold voltage of the driving module 1 through the first storage module 3; n is an integer greater than or equal to 1.

[0065] S202. From frame n+1 to frame n+m, the threshold voltage stored in the first storage module 3 in the pixel circuit 100 compensates for the threshold voltage of the driving module 1; m is an integer greater than or equal to 1.

[0066] S203. In the compensation stage of the (n+m+1)th frame, the compensation modules 2 in all pixel circuits 100 simultaneously compensate the threshold voltage of the driving module 1 according to the first scanning signal, and store the threshold voltage of the driving module 1 through the first storage module 3.

[0067] Preferably, during the compensation phase, the first storage module 3 in all pixel circuits 100 simultaneously stores the threshold voltage of the driving module 1, and the storage duration of the threshold voltage is m times the frame period.

[0068] S204. During the data writing stage, the second control terminal of the drive module 1 receives a data voltage.

[0069] It should be noted that in this embodiment, the nth frame and the (n+m+1)th frame are both compensation frames, and the (n+1)th to (n+m)th frames are all write frames.

[0070] Optional, Figure 9 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention. Combined with... Figure 3 and Figure 9 The pixel circuit driving method provided in this embodiment includes: S301. During the compensation phase, the compensation modules 2 in all pixel circuits 100 simultaneously compensate the threshold voltage of the driving module 1 according to the first scan signal, and store the threshold voltage of the driving module 1 through the first storage module 3; wherein, the storage duration of the threshold voltage by the first storage module 3 is an integer multiple of the frame period; the first scan signal is a global control signal.

[0071] S302. During the data writing stage, the data writing module 4 of the pixel circuit 100 transmits data voltage to the second control terminal of the driving module 1 line by line according to the second scanning signal; the second scanning signal is a line-by-line scanning signal during the data writing stage; during the data writing stage, the second storage module 5 in the pixel circuit 100 stores the data voltage of the driving module 1 line by line.

[0072] Optionally, based on the above embodiments, see also... Figures 1 to 9 In the compensation frame, all pixel circuits 100 include a compensation phase and a data writing phase, with the compensation phase set during the idle phase of the data writing phase in all pixel circuits 100; there is at least one write frame between two adjacent compensation frames, in which all pixel circuits 100 do not include the compensation phase.

[0073] Specifically, this setting ensures that the threshold voltage storage duration of the driving module 1 of the pixel circuit 100 after the compensation phase in the compensation frame is an integer multiple of the frame period, thus eliminating the need for a compensation phase when writing frames. Since the display panel is in a black state during the compensation phase, there is no black-state compensation phase for the display panel within at least one frame period. This reduces the duration of the black state, thereby reducing the brightness fluctuation depth of the light-emitting module D1 of the display panel, reducing flicker, and ultimately improving the user's viewing comfort. Optionally, based on the above embodiments, see also... Figures 1 to 9In the compensation frame, the compensation stage is set before the data writing stage in the first row pixel circuit 100, or after the data writing stage in the last row pixel circuit 100.

[0074] Specifically, this setting allows the compensation phase to be placed during the idle phase of the overall data writing phase of the compensation frame, improving compensation efficiency, reducing the brightness fluctuation depth when the light-emitting module D1 is working, better suppressing flicker, and improving the comfort of viewing the display panel.

[0075] Optional, Figure 10 This is a flowchart of another pixel circuit driving method provided in an embodiment of the present invention. Combined with... Figure 5 , Figure 6 and Figure 10 The pixel circuit driving method provided in this embodiment includes: S401. During the reset phase, the data writing modules 4 in all pixel circuits 100 simultaneously initialize the second control terminal of the driving module 1 according to the second scan signal and the first initialization voltage Vref1 transmitted through the data line Data; during the reset phase, the initialization modules 6 in all pixel circuits 100 simultaneously initialize the anode of the light-emitting module D1 according to the second scan signal and the second initialization voltage Vref2 transmitted through the initialization line Ref; wherein, the second scan signal is a global control signal during the reset phase; the first initialization voltage Vref1 and the second initialization voltage Vref2 are equal.

[0076] S402. During the compensation phase, the compensation modules 2 in all pixel circuits 100 simultaneously compensate the threshold voltage of the driving module 1 according to the first scan signal, and store the threshold voltage of the driving module 1 through the first storage module 3; wherein, the storage duration of the threshold voltage by the first storage module 3 is an integer multiple of the frame period; the first scan signal is a global control signal.

[0077] S403. During the data writing stage, the data writing module 4 of the pixel circuit 100 transmits data voltage to the second control terminal of the driving module 1 line by line according to the second scanning signal; the second scanning signal is a line-by-line scanning signal during the data writing stage; during the data writing stage, the second storage module 5 in the pixel circuit 100 stores the data voltage of the driving module 1 line by line.

[0078] The pixel circuit driving method provided in this embodiment, by setting a compensation phase, ensures that the compensation modules 2 in all pixel circuits 100 simultaneously compensate the threshold voltage of the driving module 1 according to the first scan signal, and stores the threshold voltage of the driving module 1 through the first storage module 3. The storage duration of the threshold voltage in the first storage module 3 is an integer multiple of the frame period. This setting allows all pixel circuits 100 located in different rows to be compensated simultaneously. The compensation phase and the data writing phase are separated. Furthermore, by setting the storage duration of the threshold voltage in the first storage module 3 to an integer multiple of the frame period, the storage duration of the threshold voltage in the first storage module 3 of the pixel circuit 100 of the compensation frame can be maintained for at least one frame period. This eliminates the need for a compensation phase between adjacent compensation frames, thereby reducing the duration of the non-light-emitting compensation phase. This effectively reduces the brightness fluctuation depth when the light-emitting module D1 is working, effectively reduces the flicker of the light-emitting module D1, improves the display effect of the display panel, and ultimately improves the user's viewing comfort.

[0079] On the other hand, by setting the first scanning signal as a global control signal, at least two pixel circuits 100 located in different rows can simultaneously perform threshold voltage compensation, and each compensation module 2 of at least two pixel circuits 100 located in different rows can share a GIP circuit, reducing the number of GIP circuits in the display panel, thereby reducing the space occupied by the GIP circuits on the bezel of the display panel and significantly reducing the width of the left and right bezels of the display panel.

[0080] This embodiment provides a display panel. Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. See also: Figure 11 The display panel 200 provided in this embodiment includes a light-emitting module and a pixel circuit 100 provided in any of the above embodiments, and has the beneficial effects of the pixel circuit 100 provided in any of the above embodiments, which will not be described again here. The display panel 200 may include the display screen of mobile terminals such as mobile phones, computers, and wearable devices.

[0081] Optionally, based on the above embodiments, the display panel includes a compensation frame and a write frame; in the compensation frame, all pixel circuits include a compensation stage and a data write stage, and the compensation stage is set in the idle stage of the data write stage in all pixel circuits.

[0082] Optionally, based on the above embodiments, in the compensation frame, the compensation stage is set before the data writing stage in the first row of pixel circuits, or after the data writing stage in the last row of pixel circuits.

[0083] Optionally, based on the above embodiments, at least one write frame is included between two adjacent compensation frames, and in the write frame, all pixel circuits do not include the compensation stage.

[0084] Optionally, based on the above embodiments, in the compensation frame and the write frame, the light emission phase of at least a portion of the light-emitting modules and the data writing phase of at least a portion of the pixel circuits are performed simultaneously.

[0085] The display panel provided in this embodiment compensates all pixel circuits simultaneously during the compensation frame. The threshold voltage of the driving module of the compensated pixel circuit is stored for an integer multiple of the frame period, so that no compensation stage is required when writing the frame. Since the display panel is in a black state during the compensation stage, the display panel does not have a black state compensation stage for at least one frame period, reducing the duration of the black state of the display panel, thereby reducing the brightness fluctuation depth of the light-emitting module of the display panel, reducing the flicker of the display panel, and thus improving the user's viewing comfort.

[0086] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: A driving module, wherein the driving module is connected to the light-emitting module at the first node and to the first power supply terminal; A compensation module is provided, wherein the first control terminal of the driving module is connected to the second node, the compensation module is connected to the first signal line, and the control terminal of the compensation module is connected to the first scan line, for compensating the threshold voltage of the driving module. A first storage module is connected between the first node and the second node, and the first storage module is used to store the threshold voltage of the driving module; the second control terminal of the driving module inputs the data voltage. Wherein, the first scan signal transmitted by the first scan line is a global control signal; the duration for which the first storage module stores the threshold voltage is an integer multiple of the frame period.

2. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes: A data writing module is provided, wherein the second control terminal of the driving module is connected to the third node, the data writing module is connected to the data line, and the control terminal of the data writing module is connected to the second scan line. The data writing module is used to transmit a first initialization voltage to the third node during the reset phase and to transmit a data voltage to the third node during the data writing phase. In this process, the first scan signal transmitted by the second scan line is a global control signal during the reset phase and a line-by-line scan signal during the data writing phase.

3. The pixel circuit according to claim 2, characterized in that, The pixel circuit further includes: A second storage module is connected between the third node and the first node, and the second storage module is used to store the data voltage; The compensation module includes a first switching transistor, and the first storage module includes a first capacitor. The first terminal of the first switching transistor is connected to the first signal line, the second terminal of the first switching transistor and the first end of the first capacitor are connected to a third node, the control terminal of the first switching transistor is connected to the first scan line, and the second end of the first capacitor is connected to the first power supply terminal. The data writing module includes a second switching transistor, and the second storage module includes a second capacitor. The first terminal of the second switching transistor is connected to the data line, the second terminal of the second switching transistor and the first terminal of the second capacitor are connected to a third node, the control terminal of the second switching transistor is connected to the second scan line, and the second terminal of the second capacitor is connected to the first node.

4. The pixel circuit according to claim 2, characterized in that, The pixel circuit further includes: An initialization module is connected between the initialization line and the anode of the light-emitting module, and the control terminal of the initialization module is connected to the second scan line; the initialization module is used to transmit a second initialization voltage to the anode of the light-emitting module. The second initialization voltage is equal to the first initialization voltage; Preferably, the initialization module includes a third switching transistor; the first electrode of the third switching transistor is connected to the initialization line, the second electrode of the third switching transistor is connected to the anode of the light-emitting module, and the control electrode of the third switching transistor is connected to the second scan line; Preferably, the driving module includes a driving transistor, the light-emitting module includes an organic light-emitting diode, the first terminal of the driving transistor is connected to the first power supply terminal, the second terminal of the driving transistor is connected to the first node and the anode of the organic light-emitting diode, and the cathode of the organic light-emitting diode is connected to the second power supply terminal; the first control terminal of the driving transistor is connected to the compensation module at the second node, and the second control terminal of the driving transistor is connected to the data writing module at the third node.

5. The pixel circuit according to claim 2, characterized in that, When the first control terminal is the top gate, the second control terminal is the bottom gate; or, when the first control terminal is the bottom gate, the second control terminal is the top gate. The data line is used to transmit the first initialization voltage during the reset phase and the data voltage during the data writing phase.

6. A driving method for a pixel circuit, characterized in that, The method is performed by the pixel circuit according to any one of claims 1 to 5; the method includes: During the compensation phase, the compensation modules in all the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and store the threshold voltage of the driving module through the first storage module; wherein, the duration for which the first storage module stores the threshold voltage is an integer multiple of the frame period; the first scan signal is a global control signal; During the data writing phase, the second control terminal of the drive module receives a data voltage.

7. The driving method for the pixel circuit according to claim 6, characterized in that, During the compensation phase, all compensation modules in the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and store the threshold voltage of the driving module through the first storage module, including: During the compensation phase of the nth frame, the compensation modules in all the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and store the threshold voltage of the driving module through the first storage module; n is an integer greater than or equal to 1. From frame (n+1) to frame (n+m), the threshold voltage stored in the first storage module of the pixel circuit compensates for the threshold voltage of the driving module; m is an integer greater than or equal to 1. During the compensation phase of the (n+m+1)th frame, the compensation modules in all the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and store the threshold voltage of the driving module through the first storage module. Preferably, during the compensation phase, the first storage module in all the pixel circuits simultaneously stores the threshold voltage of the driving module, and the storage duration of the threshold voltage is m times the frame period.

8. The driving method for the pixel circuit according to claim 6, characterized in that, During the data writing phase, the second control terminal of the drive module inputs a data voltage, including: During the data writing phase, the data writing module of the pixel circuit transmits data voltage to the second control terminal of the driving module line by line according to the second scanning signal; the second scanning signal is a line-by-line scanning signal during the data writing phase. During the data writing phase, the second storage module in the pixel circuit stores the data voltage of the driving module line by line; Preferably, in the compensation frame, all the pixel circuits include a compensation phase and a data writing phase, wherein the compensation phase is set during the idle phase of the data writing phase in all the pixel circuits; Between two adjacent compensation frames, there is at least one write frame, in which all the pixel circuits do not include the compensation phase.

9. The driving method for the pixel circuit according to claim 6, characterized in that, Before the compensation phase, in which all the compensation modules in the pixel circuits simultaneously compensate the threshold voltage of the driving module according to the first scan signal, and before storing the threshold voltage of the driving module through the first storage module, the method further includes: During the reset phase, all the data writing modules in the pixel circuits simultaneously initialize the second control terminal of the driving module according to the second scan signal and the first initialization voltage transmitted through the data line; During the reset phase, the initialization modules in all the pixel circuits simultaneously initialize the anode of the light-emitting module according to the second initialization voltage transmitted through the initialization line by the second scan signal; wherein, the second scan signal is a global control signal during the reset phase; and the first initialization voltage is equal to the second initialization voltage.

10. A display panel, characterized in that, include: A light-emitting module and at least one pixel circuit according to any one of claims 1 to 5; Preferably, the display panel includes a compensation frame and a write frame; In the compensation frame, all the pixel circuits include a compensation phase and a data writing phase, wherein the compensation phase is set during the idle phase of the data writing phase in all the pixel circuits; In the compensation frame, the compensation phase is set before the data writing phase in the pixel circuit of the first row, or after the data writing phase in the pixel circuit of the last row. At least one write frame is included between two adjacent compensation frames.

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