Memory transistor equivalent analog circuit

Abstract

The invention relates to the technical field of circuit design, and discloses a memory transistor equivalent analog circuit which comprises a drain input end d, a grid input end g, seven operational amplifiers, three multipliers and a plurality of resistor-capacitor elements. Wherein a drain input signal is processed by the difference and integration circuit to generate a state variable, and then nonlinear transformation is carried out by the extraction and addition circuit; a gate input signal is subjected to threshold operation through a subtraction and addition circuit. And the two paths of signals are subjected to cascade operation by a multiplier and then are fed back and superposed with a drain electrode signal to form final drain electrode current. According to the invention, a physical model of the memory transistor is accurately realized through a general simulation device, a typical pinching lag loop can be output, and a grid voltage regulation characteristic is realized. The circuit has the advantages of being low in cost, adjustable in parameter, easy to build and the like, and can effectively replace a nanoscale physical device to be used for experimental research of nonvolatile storage and neuromorphic calculation.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, specifically to an equivalent analog circuit of a memory transistor. Background Technology

[0002] Memory transistors (MTTs) are a novel type of multi-terminal electronic device that combines the non-volatile resistive switching characteristics of memristors with the gate-controlled characteristics of field-effect transistors (FETs). These devices typically consist of a source, drain, and gate. Their core characteristic lies in the fact that the conductance of the drain-source channel depends not only on the current bias voltage but also on the device's historical electrical state, while the gate voltage can effectively regulate the resistive switching behavior of the channel. In terms of electrical characteristics, memory transistors exhibit a typical pinched hysteresis loop. This unique nonlinear dynamic behavior allows them to simulate the weight update and regulation functions of biological synapses, thus holding significant application potential in constructing high-density non-volatile memories and neuromorphic computing systems.

[0003] In current technologies, the physical realization of memory transistors primarily relies on advanced nanomaterials science and micro / nano fabrication processes. Researchers typically use two-dimensional materials such as molybdenum disulfide and graphene, or transition metal oxides, as channel dielectrics, combining them with ferroelectric thin films or charge trapping layers to construct gate stack structures. Nanoscale devices are then fabricated using semiconductor manufacturing techniques such as physical vapor deposition, atomic layer deposition, and electron beam lithography. In practical application research, the ion migration or charge trapping mechanisms of these nanodevices are often utilized to reproduce synaptic plasticity behaviors such as long-term enhancement and suppression, and these are integrated into array architectures to verify the feasibility of in-memory computing architectures.

[0004] However, the fabrication of memory transistors based on nanofilm materials currently demands extremely high precision in terms of process environment and equipment. Due to the complex material interface engineering and nanoscale patterning processes involved, the device fabrication process is cumbersome and highly sensitive to even minute fluctuations in process parameters. This results in low device yields and significant variations in electrical parameters between different batches. This dependence on expensive nanofabrication facilities and the high difficulty of the fabrication process make it difficult to obtain stable and consistent physical samples of memory transistors at low cost, thus severely hindering extensive and in-depth experimental research on their application characteristics at the circuit and system levels. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an equivalent analog circuit for a memory transistor, which solves the problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution: an equivalent analog circuit for a memory transistor, which is constructed based on a general-purpose integrated operational amplifier, an analog multiplier, and passive devices, and aims to simulate the electrical characteristics of a nanoscale memory transistor through macroscopic hardware circuitry.

[0007] The equivalent analog circuit of the memory transistor includes a drain input terminal d, a gate input terminal g, a source input terminal s, seven integrated operational amplifiers U1 to U7, three analog multipliers A1 to A3, a capacitor C1, a diode D1, twenty-three resistors R1 to R23, and DC voltage sources V1, V2, V3 and Vth; wherein the source input terminal s is grounded.

[0008] In the specific circuit topology: Operational amplifier U1, together with resistors R1 to R5, forms a differential operation unit, whose input terminal is connected to the drain input terminal d, used to extract the drain-source voltage signal; Operational amplifier U2, resistor R6, and capacitor C1 form an integration operation unit, which performs time integration on the output signal of operational amplifier U1 to generate a state variable signal characterizing the internal resistive switching mechanism of the memory transistor; Operational amplifier U3, multiplier A1, diode D1, and resistors R7 to R9 form a square root operation unit, which performs nonlinear transformation on the state variable signal; Operational amplifier U5, together with resistors R13 to R16 and DC voltage sources V1 and V2, forms an addition operation unit, which performs DC bias processing on the output of the square root operation unit.

[0009] For the gate control signal, operational amplifier U6, together with resistors R17 to R20 and DC voltage source Vth, constitutes a subtraction unit to calculate the difference between the voltage at the gate input terminal g and the threshold voltage; operational amplifier U7, together with resistors R21 to R23 and DC voltage source V3, constitutes another addition unit to adjust the level of the output signal of operational amplifier U6.

[0010] In the signal fusion and output stage, multiplier A3 receives the output signals of operational amplifiers U5 and U7 and performs multiplication; multiplier A2 receives the output signals of multiplier A3 and operational amplifier U1 and performs cascaded multiplication to simulate the combined modulation effect of the drain electric field and the gate electric field on the channel conductance; operational amplifier U4, together with resistors R10 to R12, forms an output stage adder circuit, which linearly superimposes the output of multiplier A2 and the output of operational amplifier U1, and generates drain current through the feedback loop formed by resistor R1 and the drain input terminal d.

[0011] A second aspect of the present invention provides a method for realizing a physical model of a memory transistor based on the above-described circuit. This method makes the port characteristics of the circuit conform to the dynamic equation of the memory transistor by setting the parameter matching relationship of the circuit elements.

[0012] The physical model implemented by the circuit defines the drain current. With drain-source voltage Gate-source voltage and internal state variables The functional relationship satisfies the following formula: Wherein, the internal state variable With drain current The following integral relationship exists between them: In the formula, Threshold voltage, to These are the model coefficients. In the circuit described, each model coefficient is determined by the resistance and capacitance values, with the specific mapping relationship as follows: coefficients Determined by the ratio of resistor R10 to resistor R12; coefficient Determined by the ratio of resistor R23 to resistor R21; coefficient Determined by the ratio of resistor R13 to resistor R15; coefficient Determined by the ratio of resistor R13 to resistor R16; coefficient The value is determined by the combination of parameters of resistors R1, R2, R4, R6, and capacitor C1, specifically expressed as follows: .

[0013] To ensure the circuit accurately reproduces the physical model, the resistor values ​​in the circuit must meet specific matching conditions: resistors R2 and R3 have equal resistance; resistors R4 and R5 have equal resistance; resistors R7 and R8 have equal resistance; resistor R9 has equal resistance to the parallel combination of resistors R7 and R8; resistors R13 and R16 have equal resistance; resistors R17, R18, R19, and R20 all have equal resistance; and resistors R22 and R23 have equal resistance.

[0014] The technical solution provided in this invention utilizes general-purpose analog devices to realize a complex mathematical model of a memory transistor. This circuit can generate a typical pinched hysteresis loop, and the area of ​​this hysteresis loop is modulated by the input signal frequency and gate voltage, consistent with the physical characteristics of actual nanodevices. This solution solves the problems of difficulty in obtaining physical memory transistors and high costs, providing a low-cost, repeatable, and parameter-tunable hardware verification platform for experimental research on non-volatile memory and neuromorphic computing circuits.

[0015] This invention provides an equivalent analog circuit for a memory transistor. It offers the following advantages: 1. This invention uses integrated operational amplifiers, analog multipliers, and common components such as resistors and capacitors to construct the hardware circuit, replacing the complex manufacturing process of nanoscale memory transistors. This analog circuit architecture composed of discrete components avoids the dependence of real nanoscale devices on high-precision photolithography and thin-film deposition processes, effectively solving the problems of high difficulty, low yield, and high cost in the preparation of existing memory transistor physical samples. It provides a low-cost, readily available, and stable hardware foundation for the application research of memory transistors in non-volatile storage and neuromorphic computing.

[0016] 2. This invention achieves a precise physical realization of the nonlinear dynamic mathematical model of a memory transistor by cascading differential circuits, integrator circuits, square root circuits, and multiplication circuits. This circuit not only outputs a pinched hysteresis loop with zero-crossing characteristics but also generates a real-time response to dual excitation by drain and gate voltages. Thus, it accurately reproduces the resistive switching storage characteristics and gate control threshold characteristics of the memory transistor on a macroscopic scale, ensuring the consistency between experimental verification results and theoretical predictions based on this equivalent circuit.

[0017] 3. The circuit parameters established in this invention have a clear linear mapping relationship with the mathematical model coefficients. By adjusting the resistance value of a specific resistor or the capacitance value, key performance indicators such as the threshold voltage, nonlinearity, and resistance switching speed of the simulated object can be quantitatively changed. This flexible and adjustable parameter characteristic allows a single circuit scheme to simulate memory transistors under various physical specifications or process conditions. Compared to physical devices with fixed parameters, it is more suitable for prototyping and tolerance analysis of novel memory architectures and neuromorphic computing systems. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the equivalent analog circuit of the memory transistor of the present invention; Figure 2 The present invention relates to a memory transistor frequency control method. Characteristic diagram; Figure 3 The memory transistor of this invention Under regulation Characteristic diagram. Detailed Implementation

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Please see the appendix Figure 1 -Appendix Figure 3 This invention provides an equivalent analog circuit for a memory transistor. This circuit achieves the core electrical characteristics of a memory transistor through precise connections of an integrated operational amplifier, multiplier, resistors, capacitors, diodes, and a DC voltage source. It can directly replace nanoscale memory transistors for experimental and applied research. The following detailed description, in conjunction with the accompanying drawings and specific parameters, illustrates this process: The equivalent analog circuit of the memory transistor in this embodiment includes: 7 integrated operational amplifiers (U1, U2, U3, U4, U5, U6, U7), 3 multipliers (A1, A2, A3), 1 capacitor C1, 23 resistors (R1~R23), 1 diode D1, 4 DC voltage sources (V1, V2, V3, Vth), and three input terminals: drain input terminal d, gate input terminal g, and source input terminal s, where s is grounded. The specific connection relationship of each component is as follows: One end of resistor R1 is connected to the input terminal d, and the other end is connected to one end of resistor R2 and the output terminal of operational amplifier U4. The other end of resistor R2 is connected to the inverting input of operational amplifier U1; One end of resistor R3 is connected to the input terminal d, and the other end is connected to the non-inverting input of operational amplifier U1; The two ends of resistor R4 are connected to the inverting input and the output input of operational amplifier U1, respectively; The non-inverting input of operational amplifier U1 is grounded through resistor R5; The output terminal of operational amplifier U1 is connected to the inverting input of operational amplifier U2 through resistor R6; The two ends of capacitor C1 are connected to the inverting input and the output input of operational amplifier U2, respectively; The non-inverting input of operational amplifier U2 is grounded; The output terminal of operational amplifier U2 is connected to the inverting input of operational amplifier U3 through resistor R7; One end of resistor R8 is connected to the inverting input of operational amplifier U3, and the other end is connected to the output of multiplier A1; The non-inverting input of operational amplifier U3 is grounded through resistor R9; The output terminal of operational amplifier U3 is connected to the anode of diode D1; The cathode of diode D1 is connected to both the X and Y terminals of multiplier A1. One end of resistor R15 is connected to the cathode of diode D1, and the other end is connected to the inverting input of operational amplifier U5; The output of multiplier A1 is connected to the other end of resistor R8; The X terminal of multiplier A2 is connected to the output terminal of multiplier A3, the Y terminal is connected to the output terminal of operational amplifier U1, and the output terminal is connected to one end of resistor R12. The X terminal of multiplier A3 is connected to the output terminal of operational amplifier U7, the Y terminal is connected to the output terminal of operational amplifier U5, and the output terminal is connected to the X terminal of multiplier A2. The inverting input of operational amplifier U4 is connected to one end of resistor R11 and the other end of resistor R12, respectively; One end of resistor R11 is connected to the output terminal of operational amplifier U1; The other end of resistor R12 is connected to the output of multiplier A2; The non-inverting input of operational amplifier U4 is grounded; The two ends of resistor R10 are connected to the inverting input and the output input of operational amplifier U4, respectively; The inverting input of operational amplifier U5 is connected to one end of resistor R14, one end of resistor R16, and one end of resistor R13, respectively. The other end of resistor R14 is connected to the negative terminal of DC voltage source V1, and the positive terminal of DC voltage source V1 is grounded. The other end of resistor R16 is connected to the positive terminal of DC voltage source V2, and the negative terminal of DC voltage source V2 is grounded. The other end of resistor R13 is connected to the output of operational amplifier U5; The output of operational amplifier U5 is connected to the Y terminal of multiplier A3; The inverting input of operational amplifier U6 is connected to one end of resistor R17; The other end of resistor R17 is connected to the positive terminal of DC voltage source Vth, and the negative terminal of DC voltage source Vth is grounded; One end of resistor R18 is connected to input terminal g, and the other end is connected to the non-inverting input of operational amplifier U6; The non-inverting input of operational amplifier U6 is connected to one end of resistor R20, and the other end of resistor R20 is grounded. The two ends of resistor R19 are connected to the inverting input and the output input of operational amplifier U6, respectively; The output terminal of operational amplifier U6 is connected to the inverting input of operational amplifier U7 through resistor R21; One end of resistor R22 is connected to the inverting input of operational amplifier U7, and the other end is connected to the negative terminal of DC voltage source V3, while the positive terminal of DC voltage source V3 is grounded. The two ends of resistor R23 are connected to the inverting input and the output input of operational amplifier U7, respectively; The output of operational amplifier U7 is connected to the X terminal of multiplier A3.

[0021] This circuit satisfies the following resistor matching relationship: , , , ( and in parallel), , , .

[0022] The specific parameter values ​​for each component in this embodiment are as follows: Algorithm formula derivation and simplification 1. Original Mathematical Model The original model of the memory transistor is based on the definition by Sangwan et al. of Northwestern University, and its expression is as follows: in, Drain current, This is the drain-source voltage. Gate-source voltage, Threshold voltage, The height of the Schottky barrier. The initial Schottky barrier height, For the internal state variables of the memory transistor, Boltzmann's constant, Where is the dielectric constant. For electron charge, Doping concentration, and Let be a function, and the remaining variables be the fitting parameters.

[0023] 2. Model Simplification Steps because ,but Equation (2) simplifies to: in and These are the constant coefficients after integration. Substituting equation (4) into equation (1) and rewriting, we get: Taylor expansion and linearization of the natural exponent term in equation (5), and removal of the window function from the rate of change of the internal state variables of the memory transistor, yield a simplified mathematical model: in These are the constant coefficients after integration.

[0024] 3. Circuit corresponding formula Based on the resistor matching conditions and component parameters of this circuit, the corresponding mathematical model expression for the circuit is: 4. Correspondence between model parameters and circuit parameters Comparing equations (6) and (8) and (7) and (9), the correspondence between model constants and circuit element parameters is as follows: Working principle 1. Drain-Source (ds) Signal Processing Add a peak value between input terminals d and s The sinusoidal signal (corresponding to the drain-source voltage) The signal processing flow is as follows: The sinusoidal signal passes through the first differential circuit composed of resistors R1, R2, R3, R4, R5 and operational amplifier U1, and outputs the first signal. The first signal is integrated by a first integrating circuit consisting of resistor R6, capacitor C1 and operational amplifier U2, and the second signal is output. The second signal passes through the first square root circuit composed of resistors R7, R8, R9, diode D1, multiplier A1, and operational amplifier U3, and outputs the third signal. The third signal is passed through the first adder circuit, which consists of resistors R13, R14, R15, R16, DC voltage sources V1 and V2, and operational amplifier U5, to output the fourth signal.

[0025] 2. Gate-Source (GS) Signal Processing A DC modulation signal (corresponding to the gate-source voltage) is applied between the input terminals g and s. The signal processing flow is as follows: The DC modulation signal passes through the first subtraction circuit composed of resistors R17, R18, R19, R20, DC voltage source Vth, and operational amplifier U6, and outputs the fifth signal. The fifth signal is processed by the second adder circuit, which consists of resistors R21, R22, R23, DC voltage source V3, and operational amplifier U7, to output the sixth signal.

[0026] 3. Signal Fusion and Characteristic Output The fourth and sixth signals are multiplied by multiplier A3 to output the seventh signal (corresponding to...). ); The seventh signal is multiplied by the first signal via multiplier A2 to output the eighth signal (corresponding to...). ); The eighth signal is processed by the third adder circuit consisting of resistors R10, R11, R12 and operational amplifier U4 to output the ninth signal; The ninth signal and the input sinusoidal signal create a voltage difference across resistor R1, generating a drain current. Output The relationship conforms to the simplified model shown in equation (8). Experimental verification results The circuit was built according to the above parameters and connection relationships. Based on Multisim simulation, the following experimental results were obtained: when At that time, add to the input terminal ds Sine waves with frequencies of 1Hz, 2Hz, and 5Hz were measured. Characteristic curves as follows Figure 2 As shown, the curve exhibits a pinched hysteresis loop, and the area of ​​the hysteresis loop decreases as the frequency increases.

[0027] When the input sinusoidal signal frequency is 1Hz, set the following respectively: , measured Characteristic curves as follows Figure 3 As shown, the curve exhibits a pinched hysteresis loop, and the area of ​​the hysteresis loop increases with... Increases and decreases.

[0028] The above characteristics are consistent with the theoretical characteristics of memory transistors, proving the effectiveness of this equivalent circuit.

[0029] The equivalent analog circuit of the memory transistor in this embodiment solves the shortcomings of existing nanoscale memory transistors, such as difficulty in implementation, high cost, and stagnation in the laboratory stage. It does not rely on nano-thin film technology and can realize the core function of memory transistors—combining resistive switching performance and dual response capability to drain and gate electrical signals—through conventional analog devices.

[0030] Compared with existing technologies, this circuit has the following advantages: It uses general-purpose analog devices, requires no nanotechnology, is readily available and low-cost, and can be quickly built and repeatedly verified; It can directly replace actual memory transistors for experimental and application circuit design in fields such as non-volatile storage and neuromorphic computing; Even if memory transistors are commercialized in the future, individual nanometer-scale components will still be difficult to obtain. This equivalent circuit can be used as a core module for related circuit designs for a long time and has long-term application value.

[0031] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A memory transistor equivalent analog circuit, characterized in that, include: The system includes a drain input terminal d, a gate input terminal g, a source input terminal s, seven operational amplifiers U1 to U7, three multipliers A1 to A3, a capacitor C1, a diode D1, twenty-three resistors R1 to R23, a DC voltage source V1, a DC voltage source V2, a DC voltage source V3, and a DC voltage source Vth; the source input terminal s is grounded. The operational amplifier U1 and the resistors R1 to R5 constitute a first differential circuit. The input terminals of the first differential circuit are respectively connected to the drain input terminal d and the output terminal of the operational amplifier U4. The operational amplifier U2, the resistor R6, and the capacitor C1 constitute a first integrating circuit, and the input terminal of the first integrating circuit is connected to the output terminal of the operational amplifier U1. The operational amplifier U3, the multiplier A1, the diode D1, and the resistors R7 to R9 constitute a first square root circuit, and the input terminal of the first square root circuit is connected to the output terminal of the operational amplifier U2. The operational amplifier U5 and the resistors R13 to R16 constitute a first adder circuit. The input terminal of the first adder circuit is connected to the output terminal of the first square root circuit, the DC voltage source V1, and the DC voltage source V2, respectively. The operational amplifier U6 and the resistors R17 to R20 constitute a first subtraction circuit. The input terminals of the first subtraction circuit are respectively connected to the gate input terminal g and the DC voltage source Vth. The operational amplifier U7 and the resistors R21 to R23 constitute a second adder circuit. The input terminals of the second adder circuit are respectively connected to the output terminal of the operational amplifier U6 and the DC voltage source V3. The multiplier A2 and the multiplier A3 constitute a multiplication operation circuit, which is connected to the second addition circuit, the first addition circuit, and the output terminal of the operational amplifier U1, respectively. The operational amplifier U4 and the resistors R10 to R12 constitute a third adder circuit. The input terminal of the third adder circuit is connected to the output terminal of the multiplication circuit and the output terminal of the operational amplifier U1, respectively. The output terminal of the third adder circuit is connected to the resistor R1.

2. The equivalent analog circuit of a memory transistor according to claim 1, characterized in that, In the first differential circuit: one end of resistor R1 is connected to the drain input terminal d, and the other end of resistor R1 is connected to one end of resistor R2 and the output terminal of operational amplifier U4; the other end of resistor R2 is connected to the inverting input of operational amplifier U1; one end of resistor R3 is connected to the drain input terminal d, and the other end of resistor R3 is connected to the non-inverting input of operational amplifier U1; both ends of resistor R4 are connected to the inverting input of operational amplifier U1 and the output terminal of operational amplifier U1, respectively; one end of resistor R5 is connected to the non-inverting input of operational amplifier U1, and the other end of resistor R5 is grounded.

3. The equivalent analog circuit of a memory transistor according to claim 1, characterized in that, In the first integrating circuit: one end of the resistor R6 is connected to the output terminal of the operational amplifier U1, and the other end of the resistor R6 is connected to the inverting terminal of the operational amplifier U2; the two ends of the capacitor C1 are respectively connected to the inverting terminal of the operational amplifier U2 and the output terminal of the operational amplifier U2; the non-inverting terminal of the operational amplifier U2 is grounded.

4. The equivalent analog circuit of a memory transistor according to claim 1, characterized in that, In the first square root circuit: one end of resistor R7 is connected to the output terminal of operational amplifier U2, and the other end of resistor R7 is connected to the inverting input of operational amplifier U3; one end of resistor R8 is connected to the inverting input of operational amplifier U3, and the other end of resistor R8 is connected to the output terminal of multiplier A1; one end of resistor R9 is connected to the non-inverting input of operational amplifier U3, and the other end of resistor R9 is grounded; the output terminal of operational amplifier U3 is connected to the anode of diode D1; the cathode of diode D1 is connected to both the X terminal and the Y terminal of multiplier A1; the output terminal of multiplier A1 is connected to the other end of resistor R8.

5. The equivalent analog circuit of a memory transistor according to claim 1, characterized in that, In the first adder circuit: one end of resistor R15 is connected to the cathode of diode D1, and the other end of resistor R15 is connected to the inverting input of operational amplifier U5; one end of resistor R14 is connected to the inverting input of operational amplifier U5, and the other end of resistor R14 is connected to the negative terminal of DC voltage source V1, with the positive terminal of DC voltage source V1 grounded; one end of resistor R16 is connected to the inverting input of operational amplifier U5, and the other end of resistor R16 is connected to the positive terminal of DC voltage source V2, with the negative terminal of DC voltage source V2 grounded; the two ends of resistor R13 are connected to the inverting input and the output terminal of operational amplifier U5, respectively; the non-inverting input of operational amplifier U5 is grounded.

6. The equivalent analog circuit of a memory transistor according to claim 1, characterized in that, In the first subtraction circuit: one end of resistor R17 is connected to the inverting input of operational amplifier U6, and the other end of resistor R17 is connected to the positive terminal of DC voltage source Vth, with the negative terminal of DC voltage source Vth grounded; one end of resistor R18 is connected to the gate input g, and the other end of resistor R18 is connected to the non-inverting input of operational amplifier U6; one end of resistor R20 is connected to the non-inverting input of operational amplifier U6, and the other end of resistor R20 is grounded; the two ends of resistor R19 are respectively connected to the inverting input and the output terminal of operational amplifier U6.

7. The equivalent analog circuit of a memory transistor according to claim 1, characterized in that, In the second adder circuit: one end of resistor R21 is connected to the output terminal of operational amplifier U6, and the other end of resistor R21 is connected to the inverting input of operational amplifier U7; one end of resistor R22 is connected to the inverting input of operational amplifier U7, and the other end of resistor R22 is connected to the negative terminal of DC voltage source V3, and the positive terminal of DC voltage source V3 is grounded; the two ends of resistor R23 are respectively connected to the inverting input of operational amplifier U7 and the output terminal of operational amplifier U7; the non-inverting input of operational amplifier U7 is grounded.

8. The equivalent analog circuit of a memory transistor according to claim 1, characterized in that, In the multiplication circuit: the X terminal of multiplier A3 is connected to the output terminal of operational amplifier U7, the Y terminal of multiplier A3 is connected to the output terminal of operational amplifier U5, the output terminal of multiplier A3 is connected to the X terminal of multiplier A2; the Y terminal of multiplier A2 is connected to the output terminal of operational amplifier U1, and the output terminal of multiplier A2 is connected to one end of resistor R12.

9. The equivalent analog circuit of a memory transistor according to claim 8, characterized in that, In the third adder circuit: the inverting input of the operational amplifier U4 is connected to one end of the resistor R11 and the other end of the resistor R12; the other end of the resistor R11 is connected to the output terminal of the operational amplifier U1; one end of the resistor R12 is connected to the output terminal of the multiplier A2; the non-inverting input of the operational amplifier U4 is grounded; and the two ends of the resistor R10 are connected to the inverting input of the operational amplifier U4 and the output terminal of the operational amplifier U4, respectively.

10. The equivalent analog circuit of a memory transistor according to claim 1, characterized in that, The resistance of resistor R2 is equal to the resistance of resistor R3; the resistance of resistor R4 is equal to the resistance of resistor R5; the resistance of resistor R7 is equal to the resistance of resistor R8; the resistance of resistor R9 is equal to the resistance of resistors R7 and R8 connected in parallel; the resistance of resistor R13 is equal to the resistance of resistor R16; the resistances of resistors R17, R18, R19, and R20 are all equal; the resistance of resistor R22 is equal to the resistance of resistor R23.

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