Hysteresis comparator circuit and hysteresis comparator

Abstract

The invention relates to the technical field of integrated circuits, and provides a hysteresis comparator circuit and a hysteresis comparator, the hysteresis comparator circuit comprises a hysteresis comparator module, a first temperature compensation module and a second temperature compensation module; the hysteresis comparator module comprises a current mirror image unit, an input stage circuit, a return difference introduction circuit and an output stage circuit; the first temperature compensation module is connected with a ninth NMOS tube of the return difference introduction circuit, and the second temperature compensation module is connected with an eighth NMOS tube of the return difference introduction circuit; the current mirror image unit is used for providing zero temperature coefficient current for the hysteresis comparator module; the input stage circuit comprises a forward input end and a reverse input end.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a hysteresis comparator circuit and a hysteresis comparator. Background Technology

[0002] A hysteresis comparator is a comparator with hysteresis lap-loop transfer characteristics. Compared to a single-threshold comparator with only one fixed reference voltage, a hysteresis comparator has two comparison references that change with the output state. Furthermore, its output voltage will lag for a period of time before abruptly changing when the input voltage reaches the threshold voltage. Therefore, it is widely used in circuits with high stability requirements. However, hysteresis comparators are greatly affected by temperature.

[0003] In related technologies, additional complex adjustment circuitry is typically required to achieve adjustable hysteresis in hysteresis comparators. This leads to an increase in the overall integrated circuit area and power consumption, and the inverter structures used in these technologies are not applicable to all scenarios. Therefore, improving the temperature drift of the hysteresis comparator's hysteresis has become an urgent problem to be solved. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, the first objective of this invention is to provide a hysteresis comparator circuit, including a hysteresis comparator module, a first temperature compensation module, and a second temperature compensation module; the hysteresis comparator module includes a current mirror unit, an input stage circuit, a hysteresis introduction circuit, and an output stage circuit; the first temperature compensation module is connected to the ninth NMOS transistor of the hysteresis introduction circuit, and the second temperature compensation module is connected to the eighth NMOS transistor of the hysteresis introduction circuit; the current mirror unit is used to provide a zero-temperature coefficient current to the hysteresis comparator module; the input stage circuit includes a positive input terminal and an inverting input terminal; when the input at the positive input terminal is less than the input at the inverting input terminal, the ninth NMOS transistor of the hysteresis introduction circuit is turned on, and the first temperature compensation module... The compensation module provides a first compensation current to the hysteresis introduction circuit to form a positive hysteresis voltage, and the voltage of the output stage circuit is low. When the input at the positive input terminal is equal to the sum of the input at the inverting input terminal and the positive hysteresis voltage, the hysteresis comparator module flips, and the voltage of the output stage circuit is high. When the input at the positive input terminal is greater than the input at the inverting input terminal, the eighth NMOS transistor of the hysteresis introduction circuit is turned on, the second temperature compensation module provides a second compensation current to the hysteresis introduction circuit to form a negative hysteresis voltage, and the voltage of the output stage circuit is high. When the input at the positive input terminal is equal to the difference between the input at the inverting input terminal and the negative hysteresis voltage, the hysteresis comparator module flips, and the voltage of the output stage circuit is low.

[0005] In addition, the hysteresis comparator circuit according to the above embodiments of the present invention may also have the following additional technical features:

[0006] As an optional embodiment, the current mirror unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first PMOS transistor; the current mirror unit is provided with a zero temperature coefficient current by a bandgap reference source, and is composed of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor.

[0007] As an optional embodiment, the input stage circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a second PMOS transistor; the third PMOS transistor and the fourth PMOS transistor form a first operational amplifier input pair, the fifth NMOS transistor and the sixth NMOS transistor form a second operational amplifier input pair, the second PMOS transistor serves as the tail current source of the current mirror unit to provide input current to the first operational amplifier input pair, and the seventh NMOS transistor serves as the tail current source of the current mirror unit to provide input current to the second operational amplifier input pair; the gates of the third PMOS transistor and the fifth NMOS transistor are connected to the inverting input terminal of the hysteresis comparator circuit, and the gates of the fourth PMOS transistor and the sixth NMOS transistor are connected to the non-inverting input terminal of the hysteresis comparator circuit.

[0008] As an optional embodiment, the hysteresis introduction circuit includes an eighth NMOS transistor and a ninth NMOS transistor; the source of the ninth NMOS transistor is connected to the first temperature compensation module, the gate control signal of the ninth NMOS transistor is the inverted signal voutb of the output voltage vout, and the drain of the ninth NMOS transistor is connected to the drain of the third PMOS transistor; the drain of the eighth NMOS transistor is connected to the second temperature compensation module, the gate control signal of the eighth NMOS transistor is the output voltage vout, and the source of the eighth NMOS transistor is connected to the drain of the third PMOS transistor.

[0009] As an optional embodiment, the output stage circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, and a twentieth NMOS transistor; the source of the thirteenth NMOS transistor is grounded, the source of the fourteenth NMOS transistor is grounded, and the... The gate of the thirteenth NMOS transistor is connected to the gate of the fourteenth NMOS transistor, the drain of the ninth NMOS transistor is connected to the drain of the thirteenth NMOS transistor, and the source of the eighth NMOS transistor is connected to the drain of the thirteenth NMOS transistor. When the input at the positive input terminal is less than the input at the inverting input terminal, the current flowing through the drain of the thirteenth NMOS transistor is the difference between the current flowing through the drain of the third PMOS transistor and the first compensation current provided by the first temperature compensation module, so as to obtain positive hysteresis. When the input at the positive input terminal is greater than the input at the inverting input terminal, the current flowing through the drain of the thirteenth NMOS transistor is the sum of the current flowing through the drain of the third PMOS transistor and the second compensation current provided by the second temperature compensation module, so as to obtain negative hysteresis.

[0010] As an optional embodiment, the first temperature compensation module includes a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a first resistor, a second resistor, a third resistor, and a first operational amplifier; wherein the first resistor, the second resistor, and the third resistor are all positive temperature coefficient resistors; the gate voltages of the nineteenth PMOS transistor, the twentieth PMOS transistor, and the twenty-first PMOS transistor are clamped by the output terminal of the first operational amplifier; the inverting input terminal of the first operational amplifier is connected to the emitter of a parallel PNP transistor (1 in total) and the second resistor; the non-inverting input terminal of the first operational amplifier is connected to the first resistor and the third resistor; and the first resistor is connected to the emitter of a parallel PNP transistor (m in total).

[0011] As an optional embodiment, the current flowing through the first resistor is a first positive temperature coefficient current, and the current flowing through the second and third resistors is a first negative temperature coefficient current; the first positive temperature coefficient current and the first negative temperature coefficient current are superimposed to obtain the first compensation current.

[0012] As an optional embodiment, the second temperature compensation module includes a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a fourth resistor, a fifth resistor, a sixth resistor, and a second operational amplifier; wherein the fourth resistor, the fifth resistor, and the sixth resistor are all positive temperature coefficient resistors; the gate voltages of the sixteenth PMOS transistor, the seventeenth PMOS transistor, and the eighteenth PMOS transistor are clamped by the output terminal of the second operational amplifier; the inverting input terminal of the second operational amplifier is connected to the emitter of a parallel PNP transistor of number one and the fifth resistor; the non-inverting input terminal of the second operational amplifier is connected to the fourth resistor and the sixth resistor; and the fourth resistor is connected to the emitter of a parallel PNP transistor of number m.

[0013] As an optional embodiment, the current flowing through the fourth resistor is the second positive temperature coefficient current, and the current flowing through the fifth and sixth resistors is the second negative temperature coefficient current; the second positive temperature coefficient current and the second negative temperature coefficient current are superimposed to obtain the second compensation current.

[0014] A second objective of this invention is to provide a hysteresis comparator, which includes a hysteresis comparator circuit as described in any of the above.

[0015] As can be seen from the above, the hysteresis comparator circuit and hysteresis comparator provided by the present invention introduce a temperature compensation module to introduce a compensation current with a certain temperature coefficient into the hysteresis comparator circuit. While forming hysteresis, it also compensates for the temperature drift of the current at the input terminal of the hysteresis comparator circuit, thereby forming a zero temperature coefficient current at the output terminal of the hysteresis comparator circuit, which greatly reduces the influence of temperature on the hysteresis comparator circuit hysteresis.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a traditional hysteresis comparator circuit.

[0019] Figure 2 This is a schematic diagram of a hysteresis comparator circuit framework provided in an embodiment of the present invention.

[0020] Figure 3This is a schematic diagram of a hysteresis comparator circuit provided in an embodiment of the present invention.

[0021] Figure 4 A schematic diagram of the first temperature compensation module provided in an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the second temperature compensation module provided in an embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram showing the simulation results of the output voltage of a conventional hysteresis comparator circuit at -40℃.

[0024] Figure 7 This is a schematic diagram showing the simulation results of the output voltage of a traditional hysteresis comparator circuit at 40℃.

[0025] Figure 8 This is a schematic diagram showing the simulation results of the output voltage of a conventional hysteresis comparator circuit at 105℃.

[0026] Figure 9 A schematic diagram of the output voltage simulation results of the hysteresis comparator circuit provided in the embodiment of the present invention under the condition of -40℃.

[0027] Figure 10 A schematic diagram of the output voltage simulation results of the hysteresis comparator circuit provided in the embodiment of the present invention under 40°C conditions.

[0028] Figure 11 A schematic diagram of the output voltage simulation results of the hysteresis comparator circuit provided in the embodiment of the present invention at 105°C.

[0029] Figure label:

[0030] 100 - Hysteresis comparator module, 200 - First temperature compensation module, 300 - Second temperature compensation module, 101 - Current mirror unit, 102 - Input stage circuit, 103 - Hysteresis introduction circuit, 104 - Output stage circuit, NMOS1 - First MMOS transistor, NMOS2 - Second NMOS transistor, NMOS3 - Third NMOS transistor, NMOS4 - Fourth NMOS transistor, NMOS5 - Fifth NMOS transistor, NMOS6 - Sixth NMOS transistor, NMOS7 - Seventh NMOS transistor, NMOS8 - Eighth NMOS transistor, NMOS9-Ninth NMOS transistor, NMOS10-Tenth NMOS transistor, NMOS11-Eleventh NMOS transistor, NMOS12-Twelfth NMOS transistor, NMOS13-Thirteenth NMOS transistor, NMOS14-Fourteenth NMOS transistor, NMOS15-Fifteenth NMOS transistor, NMOS16-Sixteenth NMOS transistor, NMOS17-Seventeenth NMOS transistor, NMOS18-Eighteenth NMOS transistor, NMOS19-Nineteenth NMOS transistor, N MOS20 - twentieth NMOS transistor, NMOS21 - twenty-first NMOS transistor, NMOS22 - twenty-second NMOS transistor, PMOS1 - first PMOS transistor, PMOS2 - second PMOS transistor, PMOS3 - third PMOS transistor, PMOS4 - fourth PMOS transistor, PMOS5 - fifth PMOS transistor, PMOS6 - sixth PMOS transistor, PMOS7 - seventh PMOS transistor, PMOS8 - eighth PMOS transistor, PMOS9 - ninth PMOS transistor, PMOS10 - tenth PMOS transistor, PMOS11 - eleventh PMOS transistor, PMOS12 - twelfth PMOS transistor, PMOS13 - thirteenth PMOS transistor, PMOS14 - fourteenth PMOS transistor, PMOS15 - fifteenth PMOS transistor, PMOS16 - sixteenth PMOS transistor, PMOS17 - seventeenth PMOS transistor, PMOS18 - eighteenth PMOS transistor, PMOS19 - nineteenth PMOS transistor, PMOS20 - twentieth PMOS transistor, PMOS21 - twenty-first PMOS transistor. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0032] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] As described in the background section, in the field of integrated circuits, hysteresis comparators, as comparators with special transmission characteristics, are widely used in various circuits requiring high stability due to their unique hysteresis loop-back feature. Compared with traditional single-threshold comparators, the significant characteristic of hysteresis comparators is that they have two comparison reference voltages that change with the output state: an upper threshold and a lower threshold. When the input voltage varies between these two thresholds, the output voltage remains in a stable state until the input voltage exceeds either the upper or lower threshold, at which point the output voltage will change abruptly. This hysteresis characteristic makes hysteresis comparators excellent in terms of noise immunity and improving circuit stability.

[0034] refer to Figure 1 This is a schematic diagram of a traditional hysteresis comparator circuit.

[0035] In the process of developing this invention, the applicant discovered that existing hysteresis comparators still have some problems that urgently need to be solved in practical applications. First, the hysteresis of a hysteresis comparator (i.e., the difference between the upper and lower threshold values) is easily affected by ambient temperature, causing hysteresis drift. This temperature drift phenomenon severely affects the performance of the hysteresis comparator, reducing its stability and reliability. This temperature drift problem is particularly prominent in temperature-sensitive applications such as automotive electronics and aerospace.

[0036] Secondly, in existing technologies, achieving adjustable hysteresis in a hysteresis comparator typically requires additional complex adjustment circuitry. This not only increases circuit area and power consumption but also complicates the circuit design. Furthermore, most existing hysteresis comparators employ an inverter structure, which may be unsuitable for certain applications, limiting the applicability of hysteresis comparators.

[0037] Therefore, how to improve the hysteresis temperature drift problem of hysteresis comparators, enhance their stability and reliability under different temperature environments, and at the same time simplify circuit design, reduce power consumption and area has become a technical problem that urgently needs to be solved in the field of integrated circuits.

[0038] The technical solution of the present invention will be further described in detail below through specific embodiments.

[0039] refer to Figure 2 This is a schematic diagram of the hysteresis comparator circuit framework provided in an embodiment of the present invention.

[0040] The hysteresis comparator circuit provided in this embodiment of the invention includes a hysteresis comparator module, a first temperature compensation module, and a second temperature compensation module. The hysteresis comparator module mainly includes a current mirror unit, an input stage circuit, a hysteresis introduction circuit, and an output stage circuit. The first temperature compensation module provides a first compensation current to the hysteresis comparator module, and the second temperature compensation module provides a second compensation current to the hysteresis comparator module.

[0041] In this embodiment of the invention, the hysteresis comparator module can be a rail-to-rail hysteresis comparator. A rail-to-rail hysteresis comparator is a special type of comparator that combines rail-to-rail input / output characteristics with hysteresis comparison functionality. Rail-to-rail characteristic refers to the fact that the input and output voltage range can cover the entire power supply voltage range. Traditional comparators typically only operate within a portion of the power supply voltage range, while rail-to-rail comparators can fully utilize the entire power supply voltage range, thereby improving the circuit's flexibility and dynamic range.

[0042] refer to Figure 3 This is a schematic diagram of a hysteresis comparator circuit provided in an embodiment of the present invention.

[0043] The hysteresis comparator circuit provided in this embodiment of the invention includes a hysteresis comparator module, a first temperature compensation module, and a second temperature compensation module. The hysteresis comparator module includes a current mirror unit, an input stage circuit, a hysteresis introduction circuit, and an output stage circuit. The first temperature compensation module is connected to the ninth NMOS transistor of the hysteresis introduction circuit, and the second temperature compensation module is connected to the eighth NMOS transistor of the hysteresis introduction circuit. The current mirror unit is used to provide a zero-temperature coefficient current to the hysteresis comparator module. The input stage circuit includes a positive input terminal and an inverting input terminal. When the input at the positive input terminal is less than the input at the inverting input terminal, the ninth NMOS transistor of the hysteresis introduction circuit is turned on, and the first temperature compensation module provides a zero-temperature coefficient current to the hysteresis comparator module. The hysteresis induction circuit provides a first compensation current to form a positive hysteresis voltage, and the voltage of the output stage circuit is low. When the input at the positive input terminal is equal to the sum of the input at the inverting input terminal and the positive hysteresis voltage, the hysteresis comparator module flips, and the voltage of the output stage circuit is high. When the input at the positive input terminal is greater than the input at the inverting input terminal, the eighth NMOS transistor of the hysteresis induction circuit is turned on, and the second temperature compensation module provides a second compensation current to the hysteresis induction circuit to form a negative hysteresis voltage, and the voltage of the output stage circuit is high. When the input at the positive input terminal is equal to the difference between the input at the inverting input terminal and the negative hysteresis voltage, the hysteresis comparator module flips, and the voltage of the output stage circuit is low.

[0044] As an optional embodiment, the current mirror unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first PMOS transistor; the current mirror unit is provided with a zero temperature coefficient current by a bandgap reference source, and is composed of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor.

[0045] Specifically, the current mirror unit mainly consists of a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first PMOS transistor. These transistors together form a current mirror circuit, used to accurately replicate the zero-temperature coefficient current provided by the bandgap reference source to various critical parts of the comparator. The bandgap reference source ensures that the output current remains constant despite temperature changes, effectively suppressing current drift caused by temperature variations. In the current mirror unit, the first NMOS transistor acts as the input transistor, receiving the zero-temperature coefficient current provided by the bandgap reference source. The second, third, and fourth NMOS transistors act as mirror transistors, accurately replicating the input current to other parts of the comparator through precise size ratio design. The first PMOS transistor and the second PMOS transistor in the input stage circuit form a current mirror. Regarding current distribution and regulation, the current distribution within the comparator can be precisely controlled by adjusting the size ratio of the transistors in the current mirror unit. This regulation mechanism of the present invention not only helps optimize the performance of the comparator but also enables precise control of hysteresis, thereby further improving the hysteresis temperature drift problem.

[0046] As an optional embodiment, the input stage circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a second PMOS transistor; the third PMOS transistor and the fourth PMOS transistor form a first operational amplifier input pair, the fifth NMOS transistor and the sixth NMOS transistor form a second operational amplifier input pair, the second PMOS transistor serves as the tail current source of the current mirror unit to provide input current to the first operational amplifier input pair, and the seventh NMOS transistor serves as the tail current source of the current mirror unit to provide input current to the second operational amplifier input pair; the gates of the third PMOS transistor and the fifth NMOS transistor are connected to the inverting input terminal of the hysteresis comparator circuit, and the gates of the fourth PMOS transistor and the sixth NMOS transistor are connected to the non-inverting input terminal of the hysteresis comparator circuit.

[0047] In the comparator circuit, the gates of the second PMOS transistor and the seventh NMOS transistor are connected to the gates of the first PMOS transistor and the first NMOS transistor (the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor) in the current mirror unit, respectively. These connections ensure that a zero-temperature coefficient current can be stably supplied to the critical parts of the comparator, thereby improving the stability and reliability of the entire circuit.

[0048] As an optional embodiment, the hysteresis introduction circuit includes an eighth NMOS transistor and a ninth NMOS transistor; the source of the ninth NMOS transistor is connected to the first temperature compensation module, the gate control signal of the ninth NMOS transistor is the inverted signal voutb of the output voltage vout, and the drain of the ninth NMOS transistor is connected to the drain of the third PMOS transistor; the drain of the eighth NMOS transistor is connected to the second temperature compensation module, the gate control signal of the eighth NMOS transistor is the output voltage vout, and the source of the eighth NMOS transistor is connected to the drain of the third PMOS transistor.

[0049] Specifically, this embodiment of the invention includes two temperature compensation modules: a first temperature compensation module and a second temperature compensation module, connected to the hysteresis introduction circuit via an eighth NMOS transistor and a ninth NMOS transistor, respectively. The source of the ninth NMOS transistor is connected to the first temperature compensation module, receiving a first compensation current from it. The gate of the ninth NMOS transistor is connected to the inverse signal voutb of the output voltage vout. Here, "inverse signal" refers to a signal opposite in phase to vout. The drain of the ninth NMOS transistor is connected to the drain of a third PMOS transistor. The drain of the eighth NMOS transistor is connected to the second temperature compensation module, receiving a second compensation current from it. The gate of the eighth NMOS transistor is connected to the output voltage vout. It can be understood that the conduction state of the eighth NMOS transistor is controlled by the output voltage vout. The source of the eighth NMOS transistor is also connected to the drain of the third PMOS transistor, sharing this connection point with the ninth NMOS transistor.

[0050] Through the circuit connections described above, the eighth and ninth NMOS transistors together constitute the key structure of the hysteresis introduction circuit. Their on / off states are controlled by the output voltage vout and its inverted signal voutb, respectively, and are connected to the drain of the first operational amplifier input pair PMOS3 in the input stage circuit. This allows the current provided by the temperature compensation module to be introduced into the input stage circuit of the hysteresis comparator, thereby achieving the introduction of the hysteresis voltage.

[0051] As an optional embodiment, the output stage circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, and a twentieth NMOS transistor; the source of the thirteenth NMOS transistor is grounded, the source of the fourteenth NMOS transistor is grounded, the gate of the thirteenth NMOS transistor is connected to the gate of the fourteenth NMOS transistor, the drain of the thirteenth NMOS transistor is connected to the drain of the ninth NMOS transistor, and the drain of the thirteenth NMOS transistor is connected to the source of the eighth NMOS transistor.

[0052] When the input at the positive input terminal is less than the input at the negative input terminal, the current flowing through the drain of the thirteenth NMOS transistor is the difference between the current flowing through the drain of the third PMOS transistor and the first compensation current provided by the first temperature compensation module, thus obtaining positive hysteresis; when the input at the positive input terminal is greater than the input at the negative input terminal, the current flowing through the drain of the thirteenth NMOS transistor is the sum of the current flowing through the drain of the third PMOS transistor and the second compensation current provided by the second temperature compensation module, thus obtaining negative hysteresis.

[0053] Specifically, the first temperature compensation module is connected to the source of the ninth PMOS transistor, the gate control signal of the ninth PMOS transistor is the inverse signal voutb of the output voltage vout, and the drain of the ninth PMOS transistor is connected to the drain of the thirteenth NMOS transistor and the drain of the third PMOS transistor, so that the current flowing through the drain of the thirteenth NMOS transistor is the difference between the current flowing through the drain of the third PMOS transistor and the first compensation current provided by the first temperature compensation module, thereby obtaining positive hysteresis. That is, when vinp is less than vinn, the inverted signal voutb of the comparator output voltage vout is high voltage, controlling the ninth NMOS transistor to turn on. Since the current flowing through the drain of the thirteenth NMOS transistor is the difference between the current flowing through the drain of the third PMOS transistor and the first compensation current provided by the first temperature compensation module, and the current flowing through the drain of the fourteenth NMOS transistor is the current flowing through the drain of the fourth PMOS transistor, the current flowing through the drain of the thirteenth NMOS transistor is less than the current flowing through the drain of the fourteenth NMOS transistor. Since the gates of the thirteenth and fourteenth NMOS transistors are connected together and their sources are both grounded, Vgs are equal. The thirteenth NMOS transistor operates in the deep linear region, and the fourteenth NMOS transistor operates in the saturation region.

[0054] Furthermore, as vimp gradually increases, the current flowing through the thirteenth NMOS transistor gradually increases, while the current flowing through the fourteenth NMOS transistor gradually decreases. Due to the existence of the first compensation current, the current flowing through the thirteenth NMOS transistor will only exceed the current flowing through the fourteenth NMOS transistor when the positive input voltage vimp equals the sum of the negative input voltage vinn and the positive hysteresis value, at which point the comparator (hysteresis comparator module) will flip.

[0055] As an optional embodiment, the second temperature compensation module is connected to the drain of the eighth NMOS transistor. The gate control signal of the eighth NMOS transistor is the output voltage vout. The source of the eighth NMOS transistor is connected to the drains of the thirteenth NMOS transistor and the third PMOS transistor, so that the current flowing through the drain of the thirteenth NMOS transistor is the sum of the current flowing through the drain of the third PMOS transistor and the second compensation current provided by the second temperature compensation module, thereby obtaining a negative hysteresis. When vin is greater than vinn, the comparator output voltage vout is high, controlling the eighth NMOS transistor to conduct. Since the current flowing through the drain of the thirteenth NMOS transistor is the sum of the current flowing through the drain of the third PMOS transistor and the second compensation current provided by the second temperature compensation module, and the current flowing through the drain of the fourteenth NMOS transistor is the same as the current flowing through the drain of the fourth PMOS transistor, the current flowing through the drain of the thirteenth NMOS transistor is greater than the current flowing through the drain of the fourteenth NMOS transistor. Since the gates of the 13th and 14th NMOS transistors are connected together and their sources are both grounded, Vgs are equal. The 13th NMOS transistor operates in the saturation region, while the 14th NMOS transistor operates in the deep linear region. As vimp gradually decreases, the current flowing through the 14th NMOS transistor gradually increases, while the current flowing through the 13th NMOS transistor gradually decreases. Due to the presence of a second compensation current, the current flowing through the drain of the 14th NMOS transistor will only exceed the current flowing through the drain of the 13th NMOS transistor when the positive input voltage vimp equals the difference between the negative input voltage vinn and the negative hysteresis value. At this point, the comparator (hysteresis comparator module) flips.

[0056] refer to Figure 4 This is a schematic diagram of the first temperature compensation module provided in an embodiment of the present invention.

[0057] As an optional embodiment, the first temperature compensation module includes a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a first resistor, a second resistor, a third resistor, and a first operational amplifier; wherein the first resistor, the second resistor, and the third resistor are all positive temperature coefficient resistors; the gate voltages of the nineteenth PMOS transistor, the twentieth PMOS transistor, and the twenty-first PMOS transistor are clamped by the output terminal of the first operational amplifier; the inverting input terminal of the first operational amplifier is connected to the emitter of a parallel PNP transistor (1 in total) and the second resistor; the non-inverting input terminal of the first operational amplifier is connected to the first resistor and the third resistor; and the first resistor is connected to the emitter of a parallel PNP transistor (m in total).

[0058] Specifically, the gate voltages of the nineteenth PMOS transistor, the twentieth PMOS transistor, and the twenty-first PMOS transistor are clamped by the output of the first operational amplifier (Op-Amp1) to maintain stability, and together they constitute a current mirror structure.

[0059] The gate and drain of the 21st NMOS transistor are connected together, and the gate of the 22nd NMOS transistor is also connected together, forming a pair of current mirrors, thereby outputting the first compensation current through the drain of the 22nd NMOS transistor.

[0060] The inverting input of the first operational amplifier (Op-Amp1) is connected to the emitter of one parallel PNP transistor and a second resistor. The non-inverting input of the first operational amplifier (Op-Amp1) is connected to a first resistor and a third resistor. Under the negative feedback of the operational amplifier, the voltages at the connection points of the second and third resistors to the operational amplifier are equal, both being the emitter-base junction voltage VBE formed by the base (B) and emitter (E) of the PNP transistor. Since VBE has a negative temperature coefficient, and the second and third resistors have positive temperature coefficients, the current flowing through the second resistor (and the third resistor), VBE / R2 (VBE / R3), is the first negative temperature coefficient current. This results in the voltage across the first resistor being the difference ΔVBE between the base (B) and emitter (E) voltages of the two PNP transistors. Since ΔVBE and R1 both have positive temperature coefficients, the current flowing through the first resistor, ΔVBE / R1, is the first positive temperature coefficient current. The first resistor is connected to the emitter of m parallel PNP transistors. Where m represents the number of PNP transistors connected in parallel, which can be adjusted according to actual needs.

[0061] As an optional embodiment, the current flowing through the first resistor is a first positive temperature coefficient current, and the current flowing through the second and third resistors is a first negative temperature coefficient current; the first positive temperature coefficient current and the first negative temperature coefficient current are superimposed to obtain the first compensation current.

[0062] Specifically, under the action of the operational amplifier, the current flowing through the first resistor is ΔVBE / R1. Since both ΔVBE and R1 have positive temperature coefficients, the current flowing through the first resistor, ΔVBE / R1, is the first positive temperature coefficient current. The current flowing through the second (or third) resistor is VBE / R2 (VBE / R3). Since VBE has a negative temperature coefficient, and the second and third resistors have positive temperature coefficients, the current flowing through the second (or third) resistor, VBE / R2 (VBE / R3), is the first negative temperature coefficient current. The final compensation current provided by the twenty-second NMOS transistor is the result of the superposition of these two currents. The temperature coefficient of the compensation current is determined by the temperature coefficient of the current flowing through the third PMOS transistor.

[0063] refer to Figure 5 This is a schematic diagram of the second temperature compensation module provided in an embodiment of the present invention.

[0064] As an optional embodiment, the second temperature compensation module includes a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a fourth resistor, a fifth resistor, a sixth resistor, and a second operational amplifier; wherein the fourth resistor, the fifth resistor, and the sixth resistor are all positive temperature coefficient resistors; the gate voltages of the sixteenth PMOS transistor, the seventeenth PMOS transistor, and the eighteenth PMOS transistor are clamped by the output terminal of the second operational amplifier; the inverting input terminal of the second operational amplifier is connected to the emitter of a parallel PNP transistor of number one and the fifth resistor; the non-inverting input terminal of the second operational amplifier is connected to the fourth resistor and the sixth resistor; and the fourth resistor is connected to the emitter of a parallel PNP transistor of number m.

[0065] Specifically, the gate voltages of the sixteenth, seventeenth, and eighteenth PMOS transistors are all clamped by the output of the second operational amplifier (Op-Amp2) to maintain stability, and together they form a current mirror structure. The gate and drain of the sixteenth PMOS transistor are connected together, and also connected to the gates of the seventeenth and eighteenth PMOS transistors, forming a current mirror, thereby outputting a second compensation current through the drain of the eighteenth PMOS transistor.

[0066] The inverting input of the second operational amplifier (Op-Amp2) is connected to the emitter of one parallel PNP transistor and the fifth resistor. The non-inverting input of the second operational amplifier (Op-Amp2) is connected to the fourth and sixth resistors. Under the negative feedback of the operational amplifier, the voltages at the connection points of the fifth and sixth resistors to the operational amplifier are equal, both being the emitter-base junction voltage VBE formed by the base (B) and emitter (E) of the PNP transistor. Since VBE has a negative temperature coefficient, and the fifth and fourth resistors have positive temperature coefficients, the current flowing through the fifth resistor (sixth resistor), VBE / R5 (VBE / R6), is a second negative temperature coefficient current. This makes the voltage across the fourth resistor the difference ΔVBE between the base (B) and emitter (E) voltages of the two PNP transistors. Since ΔVBE and R4 both have positive temperature coefficients, the current flowing through the fourth resistor, ΔVBE / R4, is a second positive temperature coefficient current.

[0067] As an optional embodiment, the current flowing through the fourth resistor is the second positive temperature coefficient current, and the current flowing through the fifth and sixth resistors is the second negative temperature coefficient current; the second positive temperature coefficient current and the second negative temperature coefficient current are superimposed to obtain the second compensation current.

[0068] Specifically, under the action of the operational amplifier, the current flowing through the fourth resistor is ΔVBE / R4. Since both ΔVBE and R4 have positive temperature coefficients, the current flowing through the fourth resistor, ΔVBE / R4, is the second positive temperature coefficient current. The current flowing through the fifth (sixth) resistor is VBE / R5 (VBE / R6). Since VBE has a negative temperature coefficient, and the fifth and sixth resistors have positive temperature coefficients, the current flowing through the fifth (sixth) resistor, VBE / R5 (VBE / R6), is the second negative temperature coefficient current. The final second compensation current provided by the twenty-second NMOS transistor is the result of the superposition of these two currents. The temperature coefficient of the compensation current is determined by the temperature coefficient of the current flowing through the third PMOS transistor.

[0069] The temperature coefficient of the compensation current is the key to improving the hysteresis comparator circuit of the hysteresis temperature drift type in this invention.

[0070] Refer again Figure 3Taking the first temperature compensation module as an example, when the voltage vimp at the positive input terminal of the comparator is lower than the voltage vinn at the negative input terminal, according to circuit analysis principles, the current flowing through the drain of the third PMOS transistor at the negative input terminal of the comparator minus the first compensation current provided by the first temperature compensation module is the current flowing through the drain of the thirteenth NMOS transistor, and the current flowing through the drain of the fourth PMOS transistor at the positive input terminal of the comparator is the current flowing through the drain of the fourteenth NMOS transistor. According to the comparator's principle, as the voltage vimp at the positive input terminal gradually increases, the current flowing through the drain of the thirteenth NMOS transistor gradually increases, and the current flowing through the drain of the fourteenth NMOS transistor gradually decreases, until the voltage vimp at the positive input terminal is exactly equal to the voltage vinn at the negative input terminal plus the positive hysteresis voltage. At this point, the current flowing through the thirteenth NMOS transistor is greater than the current flowing through the fourteenth NMOS transistor, and the comparator completes one flip.

[0071] refer to Figure 6 The diagram shows the simulation results of the output voltage of the hysteresis comparator circuit provided by the traditional structure at -40℃. Figure 7 A schematic diagram showing the simulation results of the output voltage of the hysteresis comparator circuit provided for the traditional structure at 40°C. Figure 8 A schematic diagram showing the simulated output voltage of a hysteresis comparator circuit with a traditional structure at 105°C. Figure 6 It can be seen that, under conditions of -40℃, the positive hysteresis voltage of a conventional hysteresis comparator circuit is 95mV, and the negative hysteresis voltage is -83mV; from Figure 7 It can be seen that, under 40℃ conditions, the positive hysteresis voltage of the traditional hysteresis comparator circuit is 114mV, and the negative hysteresis voltage is -102mV; from Figure 8 It can be seen that, at 105℃, the positive hysteresis voltage of a conventional hysteresis comparator circuit is 121mV, and the negative hysteresis voltage is -110mV. The temperature drift of the positive hysteresis comparator circuit is 23%, and the temperature drift of the negative hysteresis comparator circuit is 26.5%. For a hysteresis comparator with high requirements, the temperature drift specification does not meet the requirements.

[0072] Simulation results show that the hysteresis of a conventional rail-to-rail comparator changes with increasing temperature, therefore it is necessary to study the temperature coefficient of the drain current flowing through the thirteenth NMOS transistor.

[0073] In specific implementation, I NMOS13 =I PMOS3 -I 第一温度补偿模块 Furthermore, by taking the partial derivatives of both sides of the equation, we obtain:

[0074]

[0075] It can be seen that only when the current I flowing through the thirteenth NMOS transistor... NMOS13 Temperature will not affect the comparator's switching, i.e., change its hysteresis, if there is no significant change with increasing temperature. To meet this condition, then:

[0076]

[0077] The temperature coefficient of the first compensation current provided by the first temperature compensation module is required to be equal to the drain current I of the third PMOS transistor flowing through the inverting input terminal of the comparator. PMOS3 The temperature coefficients are equal. Because the third PMOS transistor operates in the saturation region, the current flowing through it is:

[0078]

[0079] Taking the partial derivative of the above equation, we get:

[0080]

[0081] All parameters in the above formula can be found in the model file at specific values ​​at room temperature. This allows for the calculation of the temperature coefficient of the first compensation current provided by the first temperature compensation module. Subsequently, the values ​​of the first, second, and third resistors in the first temperature compensation module are adjusted. Simulation results can be referenced. Figures 9-11 .

[0082] Similarly, when the voltage vimp at the comparator's positive input is higher than the voltage vinn at the negative input, according to circuit analysis, the sum of the current flowing through the drain of the third PMOS transistor at the negative input and the current provided by the second temperature compensation module equals the current flowing through the drain of the thirteenth NMOS transistor. The current flowing through the drain of the fourth PMOS transistor at the positive input is the same as the current flowing through the drain of the fourteenth NMOS transistor. From the comparator's principle, as the voltage vimp at the positive input gradually decreases, the current flowing through the drain of the thirteenth NMOS transistor gradually decreases, while the current flowing through the drain of the fourteenth NMOS transistor gradually increases, until the voltage vimp at the positive input is exactly equal to the voltage vinn at the negative input minus the reverse hysteresis. At this point, the current flowing through the drain of the thirteenth NMOS transistor is less than the current flowing through the drain of the fourteenth NMOS transistor, and the comparator completes one flip. From circuit analysis, I... NMOS13 =I PMOS3 +I 第二温度补偿模块 Further, by taking partial derivatives on both sides of the equation, we obtain:

[0083]

[0084] Similarly, when the current I flowing through the drain of the thirteenth NMOS transistor... NMOS13Temperature will not affect the comparator's switching, i.e., change its hysteresis, if there is no significant change with increasing temperature. To meet this condition, then:

[0085]

[0086] The temperature coefficient of the second compensation current provided by the second temperature compensation module is required to be equal to the current I flowing through the drain of the third PMOS transistor. NMOS13 The absolute values ​​of their temperature coefficients are equal, but their trends are opposite. Because the third PMOS transistor operates in the saturation region, the current flowing through it is:

[0087]

[0088] Taking the partial derivative of the above equation, we get:

[0089]

[0090] All parameters in the above formula can be found in the model file at specific values ​​at room temperature. This allows for the calculation of the temperature coefficient of the current provided by the second temperature compensation module. Subsequently, the values ​​of the fourth, fifth, and sixth resistors in the second temperature compensation module are adjusted. Simulation results can be referenced. Figures 9-11 .

[0091] Furthermore, since the hysteresis comparator circuit of the present invention has adjustable hysteresis, the values ​​of the first resistor, the second resistor, and the third resistor can be adjusted simultaneously according to different application scenarios, thereby adjusting the magnitude of the hysteresis.

[0092] It should be noted that the values ​​of the fourth, fifth, and sixth resistors can also be adjusted simultaneously according to different application scenarios to adjust the hysteresis. Figures 9-11 The simulation example uses a resistance value set with a hysteresis value of 100mV as the target.

[0093] refer to Figure 9 This is a schematic diagram of the output voltage simulation results of the hysteresis comparator circuit provided in the embodiment of the present invention under the condition of -40℃. Figure 10 A schematic diagram of the output voltage simulation results of the hysteresis comparator circuit provided in the embodiment of the present invention under 40°C conditions. Figure 11 A schematic diagram of the output voltage simulation results of the hysteresis comparator circuit provided in the embodiment of the present invention at 105°C.

[0094] Depend on Figure 9 It can be seen that the positive hysteresis voltage of the hysteresis comparator circuit is 101mV and the negative hysteresis voltage is -100mV at -40℃; from Figure 10 It can be seen that, under 40℃ conditions, the positive hysteresis voltage of the hysteresis comparator circuit is 105mV, and the negative hysteresis voltage is -104mV; from Figure 11 It can be seen that, at 105℃, the positive hysteresis voltage of the hysteresis comparator circuit is 100mV, and the negative hysteresis voltage is -106mV. The temperature drift of the positive hysteresis of the hysteresis comparator circuit is 4%, and the temperature drift of the negative hysteresis of the hysteresis comparator circuit is 5.8%.

[0095] Will Figures 9-11 and Figures 6-8 The simulation results show that the hysteresis comparator circuit provided by the present invention introduces a temperature compensation module to introduce a compensation current with a certain temperature coefficient into the hysteresis comparator circuit. While forming hysteresis, it also compensates for the temperature drift of the current at the input terminal of the hysteresis comparator circuit, thereby forming a zero temperature coefficient current at the output terminal of the hysteresis comparator circuit, which greatly reduces the influence of temperature on the hysteresis comparator circuit hysteresis.

[0096] Based on the same inventive concept, corresponding to the hysteresis comparator circuit of any of the above embodiments, the present invention also provides a hysteresis comparator, including the hysteresis comparator circuit as described above.

[0097] The hysteresis comparator in the above embodiment introduces a temperature compensation module to introduce a compensation current with a certain temperature coefficient into the hysteresis comparator circuit. While forming hysteresis, it also compensates for the temperature drift of the current at the input terminal of the hysteresis comparator circuit, thereby forming a zero temperature coefficient current at the output terminal of the hysteresis comparator circuit, which greatly reduces the influence of temperature on the hysteresis comparator circuit hysteresis.

[0098] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Rather, the steps depicted in the flowchart may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0099] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0100] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this invention should have the ordinary meaning understood by those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0101] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest sense, thereby encompassing all such modifications and equivalent structures and functions.

Claims

1. A hysteresis comparator circuit, characterized in that, The system includes a hysteresis comparator module (100), a first temperature compensation module (200), and a second temperature compensation module (300). The hysteresis comparator module (100) includes a current mirror unit (101), an input stage circuit (102), a hysteresis introduction circuit (103), and an output stage circuit (104). The first temperature compensation module (200) is connected to the ninth NMOS transistor (NMOS9) of the hysteresis introduction circuit (103), and the second temperature compensation module (300) is connected to the eighth NMOS transistor (NMOS8) of the hysteresis introduction circuit (103). The current mirror unit (101) is used to provide a zero temperature coefficient current to the hysteresis comparator module (100). The input stage circuit (102) includes a positive input terminal and an inverting input terminal. When the input at the positive input terminal is less than the input at the negative input terminal, the ninth NMOS transistor (NMOS9) of the hysteresis introduction circuit (103) is turned on, and the first temperature compensation module (200) provides a first compensation current to the hysteresis introduction circuit (103) to form a positive hysteresis voltage, and the voltage of the output stage circuit (104) is low; when the input at the positive input terminal is equal to the sum of the input at the negative input terminal and the positive hysteresis voltage, the hysteresis comparator module (100) flips, and the voltage of the output stage circuit (104) is high; When the input at the positive input terminal is greater than the input at the negative input terminal, the eighth NMOS transistor (NMOS8) of the hysteresis introduction circuit (103) is turned on, and the second temperature compensation module (300) provides a second compensation current to the hysteresis introduction circuit (103) to form a negative hysteresis voltage, and the voltage of the output stage circuit (104) is high. When the input at the positive input terminal is equal to the difference between the input at the negative input terminal and the negative hysteresis voltage, the hysteresis comparator module (100) flips, and the voltage of the output stage circuit (104) is low.

2. The hysteresis comparator circuit according to claim 1, characterized in that, The current mirror unit (101) includes a first NMOS transistor (NMOS1), a second NMOS transistor (NMOS2), a third NMOS transistor (NMOS3), a fourth NMOS transistor (NMOS4), and a first PMOS transistor (PMOS1); The current mirror unit (101) is provided with a zero temperature coefficient current by a bandgap reference source and is composed of the first NMOS transistor (NMOS1), the second NMOS transistor (NMOS2), the third NMOS transistor (NMOS3), and the fourth NMOS transistor (NMOS4).

3. The hysteresis comparator circuit according to claim 2, characterized in that, The input stage circuit (102) includes a third PMOS transistor (PMOS3), a fourth PMOS transistor (PMOS4), a fifth NMOS transistor (NMOS5), a sixth NMOS transistor (NMOS6), a seventh NMOS transistor (NMOS7), and a second PMOS transistor (PMOS2); The third PMOS transistor (PMOS3) and the fourth PMOS transistor (PMOS4) form the first operational amplifier input pair, and the fifth NMOS transistor (NMOS5) and the sixth NMOS transistor (NMOS6) form the second operational amplifier input pair. The second PMOS transistor (PMOS2) serves as the tail current source of the current mirror unit (101) to provide input current to the first operational amplifier input pair, and the seventh NMOS transistor (NMOS7) serves as the tail current source of the current mirror unit (101) to provide input current to the second operational amplifier input pair. The gates of the third PMOS transistor (PMOS3) and the fifth NMOS transistor (NMOS5) are connected to the inverting input terminal of the hysteresis comparator circuit, and the gates of the fourth PMOS transistor (PMOS4) and the sixth NMOS transistor (NMOS6) are connected to the non-inverting input terminal of the hysteresis comparator circuit.

4. The hysteresis comparator circuit according to claim 3, characterized in that, The hysteresis introduction circuit (103) includes the eighth NMOS transistor (NMOS8) and the ninth NMOS transistor (NMOS9); The source of the ninth NMOS transistor (NMOS9) is connected to the first temperature compensation module (200), the gate control signal of the ninth NMOS transistor (NMOS9) is the inverted signal voutb of the output voltage vout, and the drain of the ninth NMOS transistor (NMOS9) is connected to the drain of the third PMOS transistor (PMOS3); the drain of the eighth NMOS transistor (NMOS8) is connected to the second temperature compensation module (300), the gate control signal of the eighth NMOS transistor (NMOS8) is the output voltage vout, and the source of the eighth NMOS transistor (NMOS8) is connected to the drain of the third PMOS transistor (PMOS3).

5. The hysteresis comparator circuit according to claim 4, characterized in that, The output stage circuit (104) includes a fifth PMOS transistor (PMOS5), a sixth PMOS transistor (PMOS6), a seventh PMOS transistor (PMOS7), an eighth PMOS transistor (PMOS8), a ninth PMOS transistor (PMOS9), a tenth PMOS transistor (PMOS10), an eleventh PMOS transistor (PMOS11), a twelfth PMOS transistor (PMOS12), a thirteenth PMOS transistor (PMOS13), a fourteenth PMOS transistor (PMOS14), a fifteenth PMOS transistor (PMOS15), a tenth NMOS transistor (NMOS10), an eleventh NMOS transistor (NMOS11), a twelfth NMOS transistor (NMOS12), a thirteenth NMOS transistor (NMOS13), a fourteenth NMOS transistor (NMOS14), and a fifteenth NMOS transistor (PMOS15). The transistors are: NMOS15, NMOS16, NMOS17, NMOS18, NMOS19, and NMOS20; the source of the thirteenth NMOS transistor (NMOS13) is grounded, the source of the fourteenth NMOS transistor (NMOS14) is grounded, the gate of the thirteenth NMOS transistor (NMOS13) is connected to the gate of the fourteenth NMOS transistor (NMOS14), the drain of the ninth NMOS transistor (NMOS9) is connected to the drain of the thirteenth NMOS transistor (NMOS13), and the source of the eighth NMOS transistor (NMOS8) is connected to the drain of the thirteenth NMOS transistor (NMOS13). When the input at the positive input terminal is less than the input at the negative input terminal, the current flowing through the drain of the thirteenth NMOS transistor (NMOS13) is the difference between the current flowing through the drain of the third PMOS transistor (PMOS3) and the first compensation current provided by the first temperature compensation module (200) to obtain positive hysteresis. When the input at the positive input terminal is greater than the input at the negative input terminal, the current flowing through the drain of the thirteenth NMOS transistor (NMOS13) is the sum of the current flowing through the drain of the third PMOS transistor (PMOS3) and the second compensation current provided by the second temperature compensation module (300) to obtain a negative hysteresis.

6. The hysteresis comparator circuit according to claim 5, characterized in that, The first temperature compensation module (200) includes a nineteenth PMOS transistor (PMOS19), a twentieth PMOS transistor (PMOS20), a twenty-first PMOS transistor (PMOS21), a twenty-first NMOS transistor (NMOS21), a twenty-second NMOS transistor (NMOS22), a first resistor, a second resistor, a third resistor, and a first operational amplifier; wherein the first resistor, the second resistor, and the third resistor are all positive temperature coefficient resistors; The gate voltages of the nineteenth PMOS transistor (PMOS19), the twentieth PMOS transistor (PMOS20), and the twenty-first PMOS transistor (PMOS21) are clamped by the output of the first operational amplifier. The inverting input of the first operational amplifier is connected to the emitter of a parallel PNP transistor (1) and the second resistor. The non-inverting input of the first operational amplifier is connected to the first resistor and the third resistor. The first resistor is connected to the emitter of a parallel PNP transistor (m).

7. The hysteresis comparator circuit according to claim 6, characterized in that, The current flowing through the first resistor is a first positive temperature coefficient current, and the current flowing through the second resistor and the third resistor is a first negative temperature coefficient current. The first positive temperature coefficient current and the first negative temperature coefficient current are superimposed to obtain the first compensation current.

8. The hysteresis comparator circuit according to claim 5, characterized in that, The second temperature compensation module (300) includes a sixteenth PMOS transistor (PMOS16), a seventeenth PMOS transistor (PMOS17), an eighteenth PMOS transistor (PMOS18), a fourth resistor, a fifth resistor, a sixth resistor, and a second operational amplifier; wherein the fourth resistor, the fifth resistor, and the sixth resistor are all positive temperature coefficient resistors; The gate voltages of the sixteenth PMOS transistor (PMOS16), the seventeenth PMOS transistor (PMOS17), and the eighteenth PMOS transistor (PMOS18) are clamped by the output of the second operational amplifier. The inverting input of the second operational amplifier is connected to the emitter of a parallel PNP transistor (1) and the fifth resistor. The non-inverting input of the second operational amplifier is connected to the fourth resistor and the sixth resistor. The fourth resistor is connected to the emitter of a parallel PNP transistor (m).

9. The hysteresis comparator circuit according to claim 8, characterized in that, The current flowing through the fourth resistor is the second positive temperature coefficient current, and the current flowing through the fifth resistor and the sixth resistor is the second negative temperature coefficient current. The second positive temperature coefficient current and the second negative temperature coefficient current are superimposed to obtain the second compensation current.

10. A hysteresis comparator, characterized in that, Includes the hysteresis comparator circuit as described in any one of claims 1-9.

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