Circuit structure for quickly locking phase-locked loop and control method thereof
By using a capacitive digital-to-analog converter module and a fast-locking loop filter, the control voltage of the voltage-controlled oscillator is quickly set using the charge-sharing principle, which solves the problem of long phase-locked loop locking time and achieves low-cost, low-power phase-locked loop fast locking while maintaining high-precision frequency signal quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUIBU MICROELECTRONICS (NANJING) CO LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-05-12
AI Technical Summary
How to reduce the locking time of a phase-locked loop (PLL) without affecting the phase noise in the locked state? Design a low-cost, low-power PLL structure.
A capacitor-type digital-to-analog converter module is used to quickly set the control voltage of the voltage-controlled oscillator through the charge-sharing principle. Combined with a fast-locking loop filter, the phase-locked loop can be fast-locked, and the capacitor in the loop filter can be reused without the need for additional area.
It achieves fast locking of the phase-locked loop, reduces locking time, and maintains high precision and low power consumption, while also being low-cost.
Smart Images
Figure CN122026901A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic circuit technology, and relates to phase-locked loop (PLL) circuit technology, and particularly to a circuit structure and control method for fast PLL locking. Background Technology
[0002] A phase-locked loop (PLL) is a feedback control system that uses voltage generated by phase synchronization to regulate a voltage-controlled oscillator (VCO) to produce a target frequency. The lock-in time of a PLL refers to the time required for the PLL to switch from one target frequency to another. A shorter lock-in time means a faster frequency switching speed, thus improving the overall system efficiency. The lock-in time of a PLL is mainly limited by the loop bandwidth; a higher loop bandwidth can significantly reduce the lock-in time. However, a higher loop bandwidth will worsen the phase noise of the PLL's output frequency signal, reducing frequency accuracy. Reducing the lock-in time without affecting the phase noise in the locked state is a challenge in PLL circuit design.
[0003] Therefore, how to design a phase-locked loop structure that can achieve fast locking and has low power consumption and low cost has become an urgent problem to be solved in this field. Summary of the Invention
[0004] To address the aforementioned problems, this invention discloses a circuit structure and control method for achieving fast locking of a phase-locked loop (PLL), which can reduce the time required for PLL frequency switching at low cost and low power consumption without deteriorating the output phase noise of the PLL in the locked state.
[0005] To achieve the above objectives, the technical solution of the present invention is as follows:
[0006] A circuit structure for fast phase-locked loop (PLL) locking includes: a voltage-controlled oscillator (VCO), a frequency divider, a phase detector, and a fast-lock loop filter; the output port of the frequency divider and an external reference source are respectively connected to the two input ports of the phase detector, the output port of the phase detector is connected to the input port of the fast-lock loop filter, the output port of the loop filter is connected to the input port of the VCO, and the output port of the VCO is connected to the input port of the frequency divider.
[0007] The fast-locking loop filter includes resistor R0, resistor R1, capacitor C1, capacitor C2, and a capacitive digital-to-analog converter module. The first port of resistor R0 is connected to the first port of capacitor C1 and the first port of resistor R1. The second port of resistor R0 is connected to the first port of the capacitive digital-to-analog converter module. The second port of the capacitive digital-to-analog converter is grounded. The third port of the capacitive digital-to-analog converter is connected to the power supply. The second port of capacitor C1 is grounded. The second port of resistor R1 is connected to the first port of capacitor C2. The second port of capacitor C2 is grounded. The capacitive digital-to-analog converter module also includes N digital control ports. The input control signals of the digital control ports include three states: capacitor state, grounded state, and power-connected state.
[0008] Furthermore, the first port of resistor R0 is the input port of the fast lock-in loop filter, and the second port of resistor R1 is the output port of the fast lock-in loop filter.
[0009] Furthermore, the capacitive digital-to-analog converter module comprises N sub-units. The first port of each sub-unit is connected to each other to form the first port of the capacitive digital-to-analog converter module. The second port of each sub-unit is connected to each other to form the second port of the capacitive digital-to-analog converter module. The third port of each sub-unit is connected to each other to form the third port of the capacitive digital-to-analog converter module. The digital control port of the i-th sub-unit constitutes the i-th digital control port of the capacitive digital-to-analog converter module.
[0010] Furthermore, each subunit includes a capacitor Cu and a capacitor connection selection module. The first port of capacitor Cu is connected to the second port of the capacitor connection selection module, and the second port of capacitor Cu constitutes the second port of the subunit. The third port of capacitor Cu is connected to the power supply, and the first port of the capacitor connection selection module constitutes the digital control port of the subunit. When the digital control port is in capacitor mode, the capacitor connection selection module controls the first port of capacitor Cu to connect to the first port of the subunit. When the digital control port is in ground mode, the capacitor connection selection module controls the first port of capacitor Cu to be grounded. When the digital control port is in power supply mode, the capacitor connection selection module controls the first port of capacitor Cu to be connected to the power supply.
[0011] The present invention also provides a control method for a circuit structure of phase-locked loop fast locking, comprising the following steps:
[0012] When in the state of a normal loop filter capacitor, the control capacitor-type digital-to-analog converter module is equivalent to a normal capacitor;
[0013] When it is necessary to quickly set the initial value of the control voltage:
[0014] Based on the target control voltage set as required, set the digital control ports of k sub-units in the capacitor-type digital-to-analog converter module to the power-on state, and set the digital control ports of the remaining Nk sub-units to the ground state.
[0015] The digital control ports of all N sub-units in the capacitive digital-to-analog converter module are set to capacitor state. The final control voltage becomes the target voltage value. After the phase-locked loop locks, the capacitive digital-to-analog converter module switches to the ordinary loop filter capacitor state.
[0016] Furthermore, the way to control the capacitive digital-to-analog converter module as equivalent to a regular capacitor is as follows: set all N control signals S of the capacitive digital-to-analog converter module to the capacitor state, and connect the first port of the capacitor Cu in all sub-units to the second port of the resistor R0 in the loop filter.
[0017] The beneficial effects of this invention are as follows:
[0018] The circuit structure and method for achieving fast locking of a phase-locked loop (PLL) proposed in this invention employs a capacitive digital-to-analog converter (DAC) module. Based on the charge-sharing principle, it can quickly and accurately set the control voltage of the voltage-controlled oscillator (VCO), thereby achieving fast locking without degrading the phase noise of the PLL output frequency signal. Since this structure reuses the capacitors in the loop filter, it requires no additional area, offering high precision and low cost. Furthermore, this structure has no static power consumption, providing a low-power advantage. Therefore, the solution proposed in this invention has good application value and potential in scenarios requiring short locking times. Attached Figure Description
[0019] Figure 1 A schematic diagram of the circuit structure for rapid phase-locked loop locking provided by the present invention;
[0020] Figure 2 A schematic diagram of the fast-lock loop filter;
[0021] Figure 3 This is a schematic diagram of the structure of a capacitive digital-to-analog converter module;
[0022] Figure 4 This is a schematic diagram of the structure of a sub-unit of a capacitive digital-to-analog converter module. Detailed Implementation
[0023] The technical solutions provided by the present invention will be described in detail below with reference to specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.
[0024] like Figure 1As shown, the present invention provides a fast-locking phase-locked loop (PLL) circuit structure, including a loop filter based on a capacitor-type digital-to-analog converter (DAC) module capable of rapidly preset voltage. Specifically, the circuit structure includes a voltage-controlled oscillator (VCO), a frequency divider, a phase detector, and a fast-locking loop filter. The output port of the VCO is connected to the input port of the frequency divider. The output port of the frequency divider is connected to the first input port of the phase detector, and an external reference source is connected to the second input port of the phase detector. The output port of the phase detector is connected to the input port of the fast-locking loop filter. The output port of the loop filter is connected to the input port of the VCO.
[0025] like Figure 2 As shown, the fast lock-in loop filter includes resistors R0 and R1, capacitors C1 and C2, and a capacitive digital-to-analog converter (DAC) module. The first port of resistor R0 is connected to the first ports of capacitors C1 and R1. The second port of resistor R0 is connected to the first port of the DAC module, which is grounded. The third port of the DAC is connected to the power supply. The second port of capacitor C1 is grounded. The second port of resistor R1 is connected to the first port of capacitor C2, which is also grounded. The DAC module also includes N digital control ports. Furthermore, the first port of resistor R0 is the input port of the fast lock-in loop filter, and the second port of resistor R1 is the output port.
[0026] like Figure 3 As shown, the capacitive digital-to-analog converter module comprises N sub-unit modules. The first ports of each sub-unit are connected to form the first port of the capacitive digital-to-analog converter module, the second ports of each sub-unit are connected to form the second port of the capacitive digital-to-analog converter module, and the third ports of each sub-unit are connected to form the third port of the capacitive digital-to-analog converter module. The digital control port of the i-th sub-unit forms the i-th digital control port of the capacitive digital-to-analog converter module. The input control signal of this digital control port has three states: capacitor state, ground state, and power supply state.
[0027] like Figure 4As shown, the sub-unit of the capacitive digital-to-analog converter module includes a capacitor Cu and a capacitor connection selection module. The first port of capacitor Cu is connected to the second port of the capacitor connection selection module, thus forming the second port of this sub-unit. The third port of capacitor Cu is connected to the power supply. The first port of the capacitor connection selection module forms the digital control port of this sub-unit. When the digital control port is in capacitor mode (S=0), the capacitor connection selection module controls the first port of capacitor Cu to connect to the first port of this sub-unit; when the digital control port is in ground mode (S=2), the capacitor connection selection module controls the first port of capacitor Cu to be grounded; when the digital control port is in power-connected mode (S=1), the capacitor connection selection module controls the first port of capacitor Cu to be connected to the power supply. In this example, the capacitor connection selection module is implemented using a 2x4 decoder.
[0028] This capacitive digital-to-analog converter (DAC) module has two operating modes. The first mode is the loop filter capacitor mode. This mode is used after the phase-locked loop (PLL) is locked. When all N control signals S of the DAC module are set to capacitor state, i.e., the first port of capacitor Cu in all sub-units is connected to the second port of resistor R0 in the loop filter, the DAC module is equivalent to a regular capacitor. The second operating mode is the voltage DAC mode. This mode is used to quickly set the initial value of the control voltage. This mode consists of two stages:
[0029] Phase 1: Based on the target control voltage set according to the requirements, set the digital control ports of k sub-units in the capacitor-type digital-to-analog converter module to the power-on state, and set the digital control ports of the remaining Nk sub-units to the ground state; k and N are both integers, and k≦N.
[0030] The second stage involves setting the digital control ports of all N sub-units in the capacitive digital-to-analog converter module to capacitor mode. Based on the charge sharing effect, the final control voltage will become the target voltage value. After this, the capacitive digital-to-analog converter module will also switch to ordinary loop filter capacitor mode, i.e., the first mode mentioned above.
[0031] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.
Claims
1. A circuit structure for fast phase-locked loop (PLL) locking, characterized in that, include: The system includes a voltage-controlled oscillator, a frequency divider, a phase detector, and a fast-locked loop filter. The output port of the frequency divider and an external reference source are connected to the two input ports of the phase detector, respectively. The output port of the phase detector is connected to the input port of the fast-locked loop filter, the output port of the loop filter is connected to the input port of the voltage-controlled oscillator, and the output port of the voltage-controlled oscillator is connected to the input port of the frequency divider. The fast-locking loop filter includes resistor R0, resistor R1, capacitor C1, capacitor C2, and a capacitive digital-to-analog converter module. The first port of resistor R0 is connected to the first port of capacitor C1 and the first port of resistor R1. The second port of resistor R0 is connected to the first port of the capacitive digital-to-analog converter module. The second port of the capacitive digital-to-analog converter is grounded. The third port of the capacitive digital-to-analog converter is connected to the power supply. The second port of capacitor C1 is grounded. The second port of resistor R1 is connected to the first port of capacitor C2. The second port of capacitor C2 is grounded. The capacitive digital-to-analog converter module also includes N digital control ports. The input control signals of the digital control ports include three states: capacitor state, grounded state, and power-connected state.
2. The circuit structure for rapid phase-locked loop locking according to claim 1, characterized in that, The first port of resistor R0 is the input port of the fast lock-in loop filter, and the second port of resistor R1 is the output port of the fast lock-in loop filter.
3. The circuit structure for rapid phase-locked loop locking according to claim 1, characterized in that, The capacitive digital-to-analog converter module contains N sub-units. The first port of each sub-unit is connected to each other to form the first port of the capacitive digital-to-analog converter module. The second port of each sub-unit is connected to each other to form the second port of the capacitive digital-to-analog converter module. The third port of each sub-unit is connected to each other to form the third port of the capacitive digital-to-analog converter module. The digital control port of the i-th sub-unit forms the i-th digital control port of the capacitive digital-to-analog converter module.
4. The circuit structure for rapid phase-locked loop locking according to claim 3, characterized in that, Each subunit contains a capacitor Cu and a capacitor connection selection module. The first port of capacitor Cu is connected to the second port of the capacitor connection selection module, and the second port of capacitor Cu constitutes the second port of the subunit. The third port of capacitor Cu is connected to the power supply. The first port of the capacitor connection selection module constitutes the digital control port of the subunit. When the digital control port is in capacitor mode, the capacitor connection selection module controls the first port of capacitor Cu to connect to the first port of the subunit. When the digital control port is in ground mode, the capacitor connection selection module controls the first port of capacitor Cu to be grounded. When the digital control port is in power supply mode, the capacitor connection selection module controls the first port of capacitor Cu to be connected to the power supply.
5. A control method for a circuit structure with rapid phase-locked loop locking, characterized in that, The circuit structure for implementing the fast locking of the phase-locked loop according to any one of claims 1-4 includes the following steps: When in the state of a normal loop filter capacitor, the control capacitor-type digital-to-analog converter module is equivalent to a normal capacitor; When it is necessary to quickly set the initial value of the control voltage: Based on the target control voltage set as required, set the digital control ports of k sub-units in the capacitor-type digital-to-analog converter module to the power-on state, and set the digital control ports of the remaining Nk sub-units to the ground state. The digital control ports of all N sub-units in the capacitive digital-to-analog converter module are set to capacitor state. The final control voltage becomes the target voltage value. After the phase-locked loop locks, the capacitive digital-to-analog converter module switches to the capacitor state of the ordinary loop filter.
6. The control method for the circuit structure of rapid phase-locked loop locking according to claim 5, characterized in that, The way to control the capacitive digital-to-analog converter module as equivalent to a regular capacitor is as follows: set all N control signals S of the capacitive digital-to-analog converter module to the capacitor state, and connect the first port of the capacitor Cu in all sub-units to the second port of the resistor R0 in the loop filter.