Fast recovery MOSFET structure and manufacturing method thereof

Abstract

The invention relates to a fast recovery MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, and belongs to the technical field of power devices. The epitaxial layer is arranged on the substrate; at least two body regions are arranged in the epitaxial layer, and a partition structure is formed between the two body regions; an active region and an accumulation type channel are arranged in the body region, and the accumulation type channel is located on one side close to the partition structure; the gate structures are arranged on the epitaxial layer, and the number of the gate structures is at least two; the source dielectric layer is arranged on the partition structure and covers the accumulation type channel and the partition structure; the source dielectric layer is located between the two gate structures; and the source electrode is arranged on the source region and the source dielectric layer. According to the invention, the partition structure, the accumulation type channel and the source dielectric layer are arranged, so that the accumulation type channel is opened when the voltage of the source electrode and the voltage of the drain electrode are greater than a threshold value, thereby inhibiting the opening of a parasitic PN diode, and achieving high reliability and low loss while guaranteeing high voltage resistance and high frequency performance.

Description

Technical Field

[0001] This invention belongs to the field of power device technology, and in particular relates to a fast recovery MOSFET structure and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC) power MOSFETs, as a new generation of wide-bandgap power devices, possess advantages such as high voltage withstand capability, low on-resistance, and high switching speed, and have been widely used in new energy vehicles, power conversion, and industrial drives. However, SiC MOSFET devices inevitably exhibit a parasitic body diode structure. Due to the characteristics of SiC material, its parasitic body diode has a high forward conduction voltage, typically exceeding 2.5 V, and exhibits large reverse recovery charge and fast reverse recovery speed, making it more prone to drastic reverse recovery processes under high-frequency operating conditions.

[0003] The aforementioned characteristics of parasitic body diodes can lead to several adverse effects. For example, high forward voltage drop causes significant conduction losses, reducing system efficiency; large current spikes and overvoltages generated during reverse recovery can exacerbate electromagnetic interference (EMI) in devices and systems, and even increase stress and failure risk of switching transistors; the turn-on of the parasitic diode can also trigger additional losses caused by the body diode's turn-on-turn-off, limiting the application performance of SiC MOSFETs in high-frequency, high-efficiency topologies. Therefore, suppressing the adverse effects of parasitic body diodes and improving the reverse conduction characteristics of devices are of great significance for improving the overall performance of SiC devices and their power systems.

[0004] To address the aforementioned issues, existing technologies have proposed integrating a Schottky diode (SBD) structure within a SiC MOSFET. This involves introducing a Schottky channel with low forward voltage drop and no reverse recovery charge to replace the conduction path of the parasitic diode. While integrating an SBD can improve reverse conduction characteristics to some extent, this approach still has several limitations. For example, integrating an SBD requires additional doping and metal contact processes, increasing device manufacturing complexity and cost. Furthermore, the SBD region may introduce additional leakage current and occupy chip area, limiting device design freedom. Under high temperature and high pressure conditions, the long-term reliability of the SBD remains a challenge.

[0005] Therefore, there is an urgent need to develop a fast recovery MOSFET structure and its manufacturing method to solve the problems in the existing technology. Summary of the Invention

[0006] The purpose of this invention is to provide a MOSFET structure and its manufacturing method. By setting a partitioned structure, an accumulation channel, and a source dielectric layer, the accumulation channel turns on when the source voltage minus the drain voltage is greater than a threshold, thus suppressing the turn-on of the parasitic PN diode. This solves the problem of bipolar degradation and reverse recovery caused by the conduction of the parasitic PN junction when the power MOSFET operates in the third quadrant as mentioned in the background art. While ensuring high withstand voltage and high frequency performance, it also has high reliability and low loss.

[0007] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0008] A fast recovery MOSFET structure, comprising:

[0009] Substrate;

[0010] An epitaxial layer is disposed on the substrate; the epitaxial layer has at least two body regions, and a partition structure is formed between the two body regions; a source region and an accumulation channel are disposed in the body regions, and the accumulation channel is located on the side close to the partition structure;

[0011] The gate structure is disposed on the epitaxial layer, and at least two gates are provided.

[0012] A source dielectric layer is disposed on the partitioned structure, covering the accumulation channel and the partitioned structure; the source dielectric layer is located between the two gate structures.

[0013] The source electrode is located on the source region and the source dielectric layer.

[0014] Furthermore, when the source voltage is less than the drain voltage, the accumulation channel is in a depletion state; when the source voltage minus the drain voltage is greater than a threshold, the accumulation channel is in an on state.

[0015] Furthermore, the epitaxial layer is of a first conductivity type, the body region is of a second conductivity type, the source region is of a first conductivity type, and the accumulation channel is of a first conductivity type.

[0016] Furthermore, the accumulation channel is completely depleted by the bulk region when Vds is greater than 0;

[0017] The thickness and doping concentration of the accumulation channel satisfy the following formula:

[0018] ;

[0019] Among them, H c The thickness of the accumulation channel; ε s N is the dielectric constant of the semiconductor; b For bulk region doping concentration; N c V represents the cumulative channel doping concentration. biq represents the built-in potential of the semiconductor PN junction, and q represents the electron charge.

[0020] Furthermore, the thickness of the source dielectric layer is 30nm-80nm, or the thickness of the source dielectric layer is the same as the thickness of the gate dielectric layer.

[0021] Furthermore, it also includes:

[0022] A gate-source isolation layer covers the gate structure; the source electrode is also covered by the gate-source isolation layer;

[0023] The drain is located on the back side of the substrate.

[0024] A method for manufacturing a fast recovery MOSFET structure includes the following steps:

[0025] A substrate is provided; wherein the substrate includes a substrate and an epitaxial layer disposed on the substrate, the epitaxial layer being of a first conductivity type;

[0026] Construct at least two bulk regions of the second conductivity type in the epitaxial layer and form a partitioned structure;

[0027] Construct a source region of the first conductivity type in the bulk region;

[0028] An accumulation channel is constructed in the body region near the partition structure; wherein the accumulation channel is of a first conductivity type;

[0029] A gate structure and a source dielectric layer covering an accumulation channel and a partitioned structure are constructed on the epitaxial layer.

[0030] Furthermore, the accumulation channel is formed by ion implantation, wherein the total ion implantation dose satisfies:

[0031] ;

[0032] Among them, D c For the total injected dose, H c For the thickness of the accumulation channel, N b For the bulk doping concentration, N c This represents the cumulative channel doping concentration.

[0033] Furthermore, the construction of the gate structure and the source dielectric layer covering the accumulation channel and partition structure on the epitaxial layer includes the following steps:

[0034] Construct a dielectric layer and a gate material on the epitaxial layer;

[0035] Etch the gate material to form the gate electrode;

[0036] The dielectric layer is etched to form a source dielectric layer and a gate dielectric layer; wherein the source dielectric layer covers an accumulation channel and a partitioned structure.

[0037] Furthermore, it also includes the following steps:

[0038] A gate-source isolation layer is constructed on the gate structure;

[0039] A drain electrode is constructed on the back side of the substrate;

[0040] Construct the source electrode on the source region and the source dielectric layer.

[0041] The present invention has the following advantages:

[0042] (1) This application provides a partitioned structure, an accumulation channel, and a source dielectric layer between two gate structures. The partitioned structure is located between two body regions, and the source dielectric layer is located on the partitioned structure. This allows the accumulation channel to turn on when the source voltage minus the drain voltage exceeds a threshold value. The current then flows from the source through the accumulation channel, epitaxial layer, substrate, and finally to the drain, thereby suppressing the turn-on of the parasitic body diode. Therefore, this application solves the problem of bipolar degradation and reverse recovery caused by the conduction of the parasitic PN junction when the power MOSFET operates in the third quadrant.

[0043] (2) When the source voltage is less than the drain voltage, the accumulation channel of this application is depleted, the current does not flow through the accumulation channel, and it does not affect the normal operation of the power MOSFET.

[0044] Therefore, this application ensures high voltage resistance and high frequency performance while also possessing high reliability and low loss.

[0045] Other features and advantages of the present invention will be disclosed in detail in the following detailed description and accompanying drawings. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the cell structure of the fast recovery MOSFET proposed in this invention;

[0047] Figure 2 A schematic diagram showing the current flow when the source voltage minus the drain voltage is greater than a threshold.

[0048] Figure 3 This is a schematic diagram showing the current flow when the source voltage is less than the drain voltage.

[0049] Figure 4 This is the initial substrate of the present invention;

[0050] Figure 5 This is a structural diagram showing the formation of the first body region and the second body region in this invention;

[0051] Figure 6 This is a structural diagram showing the formation of the first source region and the second source region in this invention;

[0052] Figure 7 This is a structural diagram showing the formation of the first accumulation channel and the second accumulation channel in this invention;

[0053] Figure 8 This is a structural diagram of the deposited dielectric layer and gate material of the present invention;

[0054] Figure 9 This is a structural diagram of the gate structure of the present invention;

[0055] Figure 10 This is a structural diagram of the present invention after the source dielectric layer and the gate dielectric layer have been formed;

[0056] Figure 11 This is a structural diagram of the present invention after the gate-source isolation layer is formed;

[0057] Figure 12 This is a structural diagram of the present invention after the drain electrode has been formed;

[0058] Figure 13 This is a simulation comparison of the static characteristics of the fast recovery MOSFET proposed in this invention and a conventional MOSFET in the third quadrant.

[0059] Figure 14 This is a simulation comparison of the reverse recovery characteristics of the fast recovery MOSFET proposed in this invention and a conventional MOSFET.

[0060] The markings in the figure are as follows: 1. Substrate; 2. Epitaxial layer; 301. First body region; 302. Second body region; 401. First source region; 402. Second source region; 501. First accumulation channel; 502. Second accumulation channel; 6. Gate dielectric layer; 7. Gate electrode; 8. Source dielectric layer; 9. Gate-source isolation layer; 10. Drain; 11. Source. Detailed Implementation

[0061] To better understand the purpose, structure, and function of this invention, the invention will be described in further detail below with reference to the accompanying drawings.

[0062] A MOSFET structure, comprising:

[0063] Substrate 1;

[0064] An epitaxial layer 2 is disposed on the substrate 1; the epitaxial layer 2 has at least two body regions, and a partition structure is formed between the two body regions; a source region and an accumulation channel are disposed in the body regions, and the accumulation channel is located on the side close to the partition structure;

[0065] A gate structure is disposed on the epitaxial layer 2, and at least two gate structures are disposed thereon.

[0066] A source dielectric layer 8 is disposed on the partition structure, covering the accumulation channel and the partition structure; the source dielectric layer 8 is located between the two gate structures.

[0067] Source 11 is located on the source region and source medium layer 8.

[0068] Wherein, the epitaxial layer is of the first conductivity type, the body region is of the second conductivity type, the source region is of the first conductivity type, and the accumulation channel is of the first conductivity type.

[0069] Specifically, such as Figure 1 The diagram shows a single-cell structure of this application. The body region includes a first body region 301 and a second body region 302; the partition structure is located between the first body region 301 and the second body region 302; the source region includes a first source region 401 and a second source region 402; the accumulation channel includes a first accumulation channel 501 and a second accumulation channel 502. The first source region 401 is located in the first body region 301, and the second source region 402 is located in the second body region 302; the accumulation channels are all located at the edges of the body regions, close to the partition structure; the source dielectric layer 8 covers the first accumulation channel 501, the partition structure, and the second accumulation channel 502. The source region is adjacent to the accumulation channel.

[0070] like Figure 2 As shown, when the source voltage minus the drain voltage is greater than a threshold, the accumulation channel is turned on. Specifically, the threshold is related to the thickness of the source dielectric layer 8, and the value of the threshold can be obtained through existing technology, which will not be elaborated here. In this embodiment, when the gate-source voltage Vds is less than -1.4V, the accumulation channel is turned on, and the current starts from the source 11, passes through the accumulation channel, the epitaxial layer 2, the substrate 1, and finally to the drain 10, thereby suppressing the turn-on of the parasitic diode.

[0071] like Figure 3 As shown, when the source voltage is less than the drain voltage, the accumulating channel is completely depleted, and the current does not flow through the accumulating channel, thus not affecting the normal operation of the power MOSFET.

[0072] In summary, this application solves the bipolar degradation and reverse recovery problems caused by parasitic PN junction conduction during third-quadrant operation of power MOSFETs, thereby improving their reliability and reducing losses. Third-quadrant operation refers to the condition where the source voltage is greater than the drain voltage, i.e., Vds < 0.

[0073] In this embodiment, the accumulation channel is completely depleted by the body region when Vds is greater than 0.

[0074] The thickness and doping concentration of the accumulation channel satisfy the following formula:

[0075] ;

[0076] Among them, H c The thickness of the accumulation channel is typically around 0.2 μm; ε s N is the dielectric constant of the semiconductor; b For bulk region doping concentration; N c V represents the cumulative channel doping concentration. bi q represents the built-in potential of the semiconductor PN junction, and q represents the electron charge.

[0077] In this embodiment, the thickness of the source dielectric layer 8 is 30nm-80nm, which can be consistent with the thickness of the gate dielectric layer 6. The thickness of the gate dielectric layer 6 can be set as needed, which is prior art and will not be described in detail here.

[0078] Also includes:

[0079] A gate-source isolation layer 9 covers the gate structure;

[0080] Drain 10 is disposed on the back side of substrate 1.

[0081] The gate structure includes a gate dielectric layer 6 located on the epitaxial layer 2 and a gate electrode 7 located on the gate dielectric layer 6.

[0082] A method for manufacturing a fast recovery MOSFET structure, such as Figures 4 to 12 As shown, it includes the following steps:

[0083] A substrate is provided; wherein the substrate includes a substrate 1 and an epitaxial layer 2 disposed on the substrate 1, the epitaxial layer 2 being of a first conductivity type;

[0084] At least two body regions are constructed in the epitaxial layer 2 to form a partitioned structure; the body regions are of the second conductivity type, and the body regions in adjacent cell structures do not contact each other;

[0085] Construct a source region of the first conductivity type in the bulk region;

[0086] An accumulation channel is constructed in the body region near the partition structure; wherein the accumulation channel is of a first conductivity type;

[0087] A gate structure and a source dielectric layer 8 covering the accumulation channel and partitioned structure are constructed on the epitaxial layer 2;

[0088] A gate-source isolation layer 9 is constructed on the gate structure;

[0089] A drain electrode 10 is constructed on the back side of substrate 1;

[0090] Source electrode 11 is constructed on the source region and source dielectric layer 8.

[0091] In this embodiment, the back side of the substrate 1 is the surface of the substrate 1 that is away from the epitaxial layer 2. In this embodiment, the gate-source isolation layer 9 can be formed by PECVD or LPCVD deposition, and the thickness can be selected from 0.6um to 2um. The drain electrode 10 can be made of Ni, Al, Ti, or a stack of the above-mentioned multilayer metals, and the deposition method can be sputtering or evaporation. The source electrode 11 can be made of Ni, Al, Ti, or a stack of the above-mentioned multilayer metals, and the deposition method can be sputtering or evaporation. Specifically, the structure of the body region, source region, gate-source isolation layer 9, or drain electrode 10 can refer to the prior art, and will not be described in detail in this application.

[0092] In this embodiment, as Figures 8 to 10 As shown, the construction of the gate structure and the source dielectric layer 8 covering the accumulation channel on the epitaxial layer 2 includes the following steps:

[0093] A dielectric layer and a gate material are constructed on epitaxial layer 2;

[0094] Etch the gate material to obtain the desired gate pattern and form the gate electrode 7;

[0095] The dielectric layer is etched to form a source dielectric layer 8 and a gate dielectric layer 6; wherein the source dielectric layer 8 covers the accumulation channel and partition structure.

[0096] In this embodiment, the dielectric layer and the gate material can be formed by PECVD deposition. The dielectric layer material can be silicon dioxide, and the thickness can be between 30nm and 100nm. The gate material can be polycrystalline silicon.

[0097] The accumulation channel is formed by ion implantation, wherein the total ion implantation dose satisfies:

[0098] D c =H c (N c +N b );

[0099] Among them, D c For the total injected dose, H c For the thickness of the accumulation channel, N b For the bulk doping concentration, N c This represents the cumulative channel doping concentration.

[0100] like Figure 13 As shown and Figure 14This application addresses the issue of parasitic body diode turn-on by setting a partition structure, an accumulation channel, and a source dielectric layer 8 between two gate structures, with the partition structure positioned between the two body regions and the source dielectric layer 8 positioned on the partition structure. This allows the accumulation channel to turn on when the source voltage is greater than the drain voltage, with current flowing from the source 11 through the accumulation channel, epitaxial layer 2, substrate 1, and finally to the drain 10, thereby suppressing the turn-on of the parasitic body diode. This solves the problem of bipolar degradation and reverse recovery caused by parasitic PN junction conduction when the power MOSFET operates in the third quadrant. When the source voltage is less than the drain voltage, the accumulation channel in this application is depleted, and current does not flow through the accumulation channel, thus not affecting the normal operation of the power MOSFET.

[0101] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

[0102] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A fast recovery MOSFET structure, characterized in that, include: Substrate; An epitaxial layer is disposed on the substrate; the epitaxial layer has at least two body regions, and a partition structure is formed between the two body regions; a source region and an accumulation channel are disposed in the body regions, and the accumulation channel is located on the side close to the partition structure; The gate structure is disposed on the epitaxial layer, and at least two gates are provided. A source dielectric layer is disposed on the partitioned structure, covering the accumulation channel and the partitioned structure; the source dielectric layer is located between the two gate structures. The source electrode is located on the source region and the source dielectric layer.

2. The fast recovery MOSFET structure according to claim 1, characterized in that, When the source voltage is less than the drain voltage, the accumulation channel is in a depleted state; when the source voltage minus the drain voltage is greater than a threshold, the accumulation channel is in an open state.

3. The fast recovery MOSFET structure according to claim 2, characterized in that, The epitaxial layer is of the first conductivity type, the body region is of the second conductivity type, the source region is of the first conductivity type, and the accumulation channel is of the first conductivity type.

4. The fast recovery MOSFET structure according to any one of claims 1-3, characterized in that, The accumulative channel is completely depleted by the volume region when Vds is greater than 0; The thickness and doping concentration of the accumulation channel satisfy the following equation: ； Among them, H c The thickness of the accumulation channel; ε s N is the dielectric constant of the semiconductor; b For bulk region doping concentration; N c V represents the cumulative channel doping concentration. bi q represents the built-in potential of the semiconductor PN junction, and q represents the electron charge.

5. The fast recovery MOSFET structure according to claim 4, characterized in that, The thickness of the source dielectric layer is 30nm-80nm, or the thickness of the source dielectric layer is the same as the thickness of the gate dielectric layer.

6. The fast recovery MOSFET structure according to any one of claims 1-3 or 5, characterized in that, Also includes: A gate-source isolation layer covers the gate structure; wherein the source electrode is also covered by the gate-source isolation layer; The drain is located on the back side of the substrate.

7. A method for manufacturing a fast recovery MOSFET structure, characterized in that, Includes the following steps: A substrate is provided; wherein the substrate includes a substrate and an epitaxial layer disposed on the substrate, the epitaxial layer being of a first conductivity type; Construct at least two bulk regions of the second conductivity type in the epitaxial layer and form a partitioned structure; Construct a source region of the first conductivity type in the bulk region; An accumulation channel is constructed in the body region near the partition structure; wherein the accumulation channel is of a first conductivity type; A gate structure and a source dielectric layer covering an accumulation channel and a partitioned structure are constructed on the epitaxial layer.

8. The method for manufacturing a fast recovery MOSFET structure according to claim 7, characterized in that, The accumulation channel is formed by ion implantation, wherein the total ion implantation dose satisfies: ； Among them, D c For the total injected dose, H c For the thickness of the accumulation channel, N b For the bulk doping concentration, N c This represents the cumulative channel doping concentration.

9. The method for manufacturing a fast recovery MOSFET structure according to claim 7 or 8, characterized in that, The process of constructing a gate structure and a source dielectric layer covering an accumulation channel and a partitioned structure on an epitaxial layer includes the following steps: Construct a dielectric layer and a gate material on the epitaxial layer; Etch the gate material to form the gate electrode; The dielectric layer is etched to form a source dielectric layer and a gate dielectric layer; wherein the source dielectric layer covers an accumulation channel and a partitioned structure.

10. The method for manufacturing a fast recovery MOSFET structure according to claim 9, characterized in that, It also includes the following steps: A gate-source isolation layer is constructed on the gate structure; A drain electrode is constructed on the back side of the substrate; Construct the source electrode on the source region and the source dielectric layer.

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