Wafer-level MOS (Metal Oxide Semiconductor) driving compound semiconductor combined device and manufacturing method thereof

Abstract

The invention provides a wafer-level MOS (Metal Oxide Semiconductor) driving compound semiconductor combined device and a manufacturing method thereof. The device comprises a composite substrate with a vertical laminated structure, and a semiconductor epitaxial layer, a lattice buffer layer and a compound semiconductor laminated layer are sequentially arranged from top to bottom. The enhanced MOSFET is integrated on a semiconductor epitaxial layer, and the depletion mode HEMT is formed by laminating compound semiconductors. The source electrode of the MOSFET is connected with the compound semiconductor lamination layer through a conductive interconnection structure penetrating through the lattice buffer layer, and the back surface of the device is provided with a drain electrode which is connected with an internal channel of the HEMT through a back surface through hole. Through wafer-level vertical integration, bonding leads in traditional packaging are eliminated, parasitic inductance is remarkably reduced, and the device size is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a wafer-level MOS-driven compound semiconductor combination device and its manufacturing method. Background Technology

[0002] As representatives of third-generation wide-bandgap semiconductor materials, compound semiconductors (such as gallium nitride, GaN) have become core materials for next-generation power semiconductor devices due to their excellent physical properties, such as high critical breakdown electric field, high electron saturation drift velocity, and high electron mobility. In existing technologies, mature compound semiconductor high electron mobility transistors (HEMTs) are typically depletion-mode (D-mode, normally-on) devices. This is because the polarization effect naturally present at the heterojunction interface generates a high concentration of two-dimensional electron gas (2DEG), causing the device to be in the on-state at zero gate voltage. However, in most power conversion applications, for safety and circuit design considerations, power switching devices are required to have normally-off characteristics.

[0003] To address this issue, the industry commonly employs a cascode structure to achieve normally-off characteristics. The traditional approach typically involves packaging a low-voltage enhancement-mode silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET) in series with a high-voltage depletion-mode compound semiconductor (HEMT). Specifically, the drain of the MOSFET is connected to the source of the HEMT, with the MOSFET's source serving as the source of the overall device, and the MOSFET's gate serving as the gate of the overall device, while the HEMT's gate is connected to the MOSFET's source.

[0004] However, this traditional package-level integration solution based on discrete devices has the following significant drawbacks:

[0005] First, the two independent dies need to be connected by metal bonding wires. These bonding wires introduce significant parasitic inductance. During the high-frequency, high-speed switching of the devices, this parasitic inductance can cause voltage overshoot, oscillations, increased switching losses, and may even lead to false turn-on, severely impacting system stability and efficiency.

[0006] Secondly, integrating two independent chips within the package complicates the packaging structure, increasing the difficulty and cost of the packaging process.

[0007] Finally, because it needs to accommodate two chips and bonding wires, the size of the packaged device is limited by physical space and cannot be further reduced, which does not meet the current urgent needs of power electronic devices for high power density and miniaturization.

[0008] Therefore, there is an urgent need for a wafer-level MOS-driven compound semiconductor combination device and its manufacturing method that can achieve wafer-level integration, eliminate parasitic inductance of inter-chip bonding lines, and effectively reduce package size. Summary of the Invention

[0009] This application provides a wafer-level MOS-driven compound semiconductor combination device and its formation method to solve the problems of large parasitic inductance, complex packaging process and large device size caused by the use of discrete device packaging in the prior art.

[0010] This application provides a wafer-level MOS-driven compound semiconductor combination device, comprising:

[0011] A composite substrate having a vertically stacked structure, wherein, from the first surface of the composite substrate to the second surface, there are sequentially a semiconductor epitaxial layer, a lattice buffer layer, and a compound semiconductor stack.

[0012] An enhanced metal-oxide-semiconductor field-effect transistor is integrated on the semiconductor epitaxial layer;

[0013] A depletion-type high electron mobility transistor, comprising the aforementioned compound semiconductor stack;

[0014] The gate electrode of the enhanced metal-oxide-semiconductor field-effect transistor is led out to the first side of the combined device, and the source of the enhanced metal-oxide-semiconductor field-effect transistor is connected to the side of the compound semiconductor stack near the first side through a conductive interconnect structure that penetrates the lattice buffer layer.

[0015] The second side of the combined device is provided with a drain electrode, which is connected to the internal channel of the depletion-type high electron mobility transistor through a second-side via penetrating the bottom of the compound semiconductor stack.

[0016] Preferably, the material of the semiconductor epitaxial layer is silicon.

[0017] Preferably, the compound semiconductor stack includes a barrier layer and a channel layer stacked from the first surface to the second surface.

[0018] Preferably, both the barrier layer and the channel layer are nitride semiconductor materials.

[0019] Preferably, the barrier layer is made of aluminum gallium nitride, and the channel layer is made of gallium nitride.

[0020] Preferably, a dielectric layer is disposed between the conductive interconnect structure and the barrier layer.

[0021] Preferably, the second through-hole penetrates the channel layer and terminates at the interface between the barrier layer and the channel layer.

[0022] Preferably, the combined device is a normally-off device.

[0023] This application also provides a method for manufacturing a wafer-level MOS-driven compound semiconductor combination device as described above, comprising the following steps:

[0024] Step 1: Provide a composite substrate, wherein the composite substrate, from its first surface to its second surface, includes at least a semiconductor epitaxial layer, a lattice buffer layer, and a compound semiconductor stack, wherein the material of the semiconductor epitaxial layer is different from the material of the compound semiconductor stack.

[0025] Step 2: Remove part of the semiconductor epitaxial layer to form an enhancement-mode metal-oxide-semiconductor field-effect transistor structure in the removed region. The enhancement-mode metal-oxide-semiconductor field-effect transistor structure includes a source region and a gate region.

[0026] Step 3: Form a source interconnect structure. The source interconnect structure extends from the source region to the lattice buffer layer, penetrates the lattice buffer layer, and stops at the side of the compound semiconductor stack near the first surface, thereby realizing the connection between the source region and the compound semiconductor stack.

[0027] Step 4: Form a first-side metallization structure above the semiconductor epitaxial layer. The first-side metallization structure includes a gate electrode connected to the gate region and a source electrode connected to the source region.

[0028] Step 5: Etch the second side of the composite substrate to form a second-side via that penetrates the bottom material of the compound semiconductor stack. The second-side via exposes the heterojunction interface inside the compound semiconductor stack.

[0029] Step 6: Form a second metallized electrode. The second metallized electrode fills the second through-hole and covers the second side of the composite substrate, serving as the drain of the combined device.

[0030] Preferably, in step one, the material of the semiconductor epitaxial layer is silicon.

[0031] Preferably, in step one, the compound semiconductor stack includes a barrier layer and a channel layer stacked from the first surface to the second surface.

[0032] Preferably, in step one, both the barrier layer and the channel layer are nitride semiconductor materials.

[0033] Preferably, in step one, the barrier layer is made of aluminum gallium nitride, and the channel layer is made of gallium nitride.

[0034] Preferably, in step two, the semiconductor epitaxial layer is used to manufacture a driving transistor, and the compound semiconductor stack is used to form a depletion-type device.

[0035] Preferably, in step three, the source interconnect structure is formed using a source bus etching process.

[0036] Preferably, in step three, the source bus etching process controls the etching depth so that it passes through the lattice buffer layer and stops on the side of the compound semiconductor stack near the first surface to form interconnect vias.

[0037] Preferably, in step three, after etching to form the interconnect vias and before forming the conductive material, the step further includes forming a dielectric layer on the surface of the compound semiconductor stack exposed at the bottom of the interconnect vias.

[0038] Preferably, in step five, the process of forming the second via includes: etching from one side of the channel layer in the normally open device region, with the etching depth penetrating the channel layer and reaching the interface between the barrier layer and the channel layer.

[0039] As described above, the wafer-level MOS-driven compound semiconductor combination device and its manufacturing method of the present invention have the following beneficial effects:

[0040] The wafer-level MOS driver compound semiconductor combination device provided in this application achieves a series connection between a low-voltage enhancement-mode driver transistor and a high-voltage depletion-mode power transistor directly during the wafer fabrication stage through a vertically stacked integration method. This structure eliminates the parasitic inductance caused by inter-chip bonding leads in traditional discrete device packaging, significantly reduces voltage oscillations and switching losses during high-frequency switching, and improves system reliability. Simultaneously, the device significantly reduces package size, achieving higher power density. Furthermore, the large-area metallized electrode on the back directly contacts the channel layer, not only reducing on-resistance but also greatly enhancing the device's heat dissipation capability. Attached Figure Description

[0041] Figure 1 The diagram shows a process flow diagram of the wafer-level MOS-driven compound semiconductor combination device and its formation method according to the present invention.

[0042] Figure 2 The diagram shows a structural schematic of the composite substrate stage in the wafer-level MOS-driven compound semiconductor combined device and its formation method of the present invention.

[0043] Figure 3The diagram shows a structural schematic of the stage of forming an enhanced metal-oxide-semiconductor field-effect transistor structure in the wafer-level MOS-driven compound semiconductor combined device and its forming method of the present invention.

[0044] Figure 4 The diagram shows a schematic representation of the etching stage for forming source interconnect vias in the wafer-level MOS-driven compound semiconductor combination device and its formation method of the present invention.

[0045] Figure 5 The diagram shows a schematic representation of the stage of forming a dielectric layer in the source interconnect via in the wafer-level MOS-driven compound semiconductor combination device and its formation method of the present invention.

[0046] Figure 6 The diagram shows a structural schematic of the first surface metallization structure formation stage in the wafer-level MOS-driven compound semiconductor combination device and its formation method of the present invention.

[0047] Figure 7 The diagram shows a cross-sectional structure after the formation of the second metallized electrode in the wafer-level MOS-driven compound semiconductor combination device and its formation method of the present invention.

[0048] Figure 8 The diagram shown is a three-dimensional structural schematic of the wafer-level MOS-driven compound semiconductor combination device of the present invention. Detailed Implementation

[0049] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] This application provides a wafer-level MOS-driven compound semiconductor combination device. For example... Figure 7 and Figure 8 As shown, the combined device includes:

[0051] The composite substrate has a vertical stacked structure, and from the first surface of the composite substrate to the second surface, there are sequentially a semiconductor epitaxial layer 104, a lattice buffer layer 103 and a compound semiconductor stack.

[0052] An enhancement-mode metal-oxide-semiconductor field-effect transistor 105 is integrated on a semiconductor epitaxial layer 104; a depletion-mode high electron mobility transistor is composed of a compound semiconductor stack.

[0053] The gate electrode 107 of the enhancement-mode metal-oxide-semiconductor field-effect transistor 105 is led out to the first surface of the combined device, and the source of the enhancement-mode metal-oxide-semiconductor field-effect transistor 105 is connected to the side of the compound semiconductor stack near the first surface through a conductive interconnect structure (as part of the source electrode 108) that penetrates the lattice buffer layer 103.

[0054] The second side of the combined device is provided with a drain electrode 109, which is connected to the internal channel of the depletion-type high electron mobility transistor through a second-side via penetrating the bottom of the compound semiconductor stack.

[0055] like Figure 8 As shown, this structure can directly adopt traditional mature packaging methods, such as soldering the back drain electrode 109 to the package substrate or frame, while the front gate electrode 107 and source electrode 108 are connected to the pins via metal leads. This vertically stacked three-dimensional integrated architecture, compared to traditional planar multi-chip packaging, not only reduces the power module package size and achieves ultra-high power density, but more importantly, it eliminates the bonding leads between the MOSFET and the GaN chip at the physical level, thereby minimizing interconnect parasitic inductance and resistance. For high-frequency power conversion applications, this means cleaner switching waveforms, lower switching losses, and higher system stability.

[0056] In some embodiments, the semiconductor epitaxial layer 104 is made of silicon. The choice of material for the semiconductor epitaxial layer 104 is diverse to suit different driving circuit requirements. Besides monocrystalline silicon, the layer may also include polycrystalline silicon, amorphous silicon, microcrystalline silicon, or combinations thereof. Furthermore, to improve transistor carrier mobility, the semiconductor epitaxial layer 104 may employ strained silicon technology or a silicon-on-insulator (SOI) structure to reduce leakage current and parasitic capacitance. In some high-performance applications, the semiconductor epitaxial layer 104 material may also be replaced with germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), or other III-IV group semiconductor materials compatible with CMOS processes. The crystal orientation of the semiconductor epitaxial layer 104 can be selected according to hole or electron mobility optimization requirements. <100> , <110> or <111> Crystal facets.

[0057] In some embodiments, such as Figure 2 As shown, the compound semiconductor stack includes a barrier layer 102 and a channel layer 101 stacked from the first surface to the second surface.

[0058] In some embodiments, both the barrier layer 102 and the channel layer 101 are nitride semiconductor materials. The nitride semiconductor materials are not limited to binary compounds, but may include one or more combinations selected from gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and their ternary or quaternary solid solutions, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN).

[0059] In addition to the nitride semiconductor materials described above, in other embodiments, the materials for the compound semiconductor stack (barrier layer 102 and channel layer 101) can also be selected from other III-V compound semiconductor systems, as long as they can form a heterojunction and generate conductive channels (such as 2DEG or 2DHG) through band engineering. Specific material combinations may include, but are not limited to:

[0060] Arsenide-based systems: such as gallium arsenide (GaAs), aluminum arsenide (AlAs), indium arsenide (InAs), and their ternary or quaternary alloys. Typical combinations include aluminum gallium arsenide / gallium arsenide (AlGaAs / GaAs) heterojunctions or indium aluminum arsenide / indium gallium arsenide (InAlAs / InGaAs) heterojunctions.

[0061] Phosphide-based systems: such as indium phosphide (InP), gallium phosphide (GaP), and their alloys. For example, indium gallium phosphide / gallium arsenide (InGaP / GaAs) or indium phosphide / indium gallium arsenide (InP / InGaAs).

[0062] Antimonide-based systems: such as indium antimonide (InSb), gallium antimonide (GaSb), aluminum antimonide (AlSb), and their alloys. This system is typically used for ultra-high mobility or narrow bandgap applications.

[0063] Oxide semiconductor systems include gallium oxide (Ga₂O₃), aluminum oxide (Al₂O₃), indium oxide (In₂O₃), and their alloys (such as aluminum gallium oxide, AlGaO). Wide-bandgap oxide semiconductors combined with oxides with different bandgap structures (such as Al₂O₃ or AlGaO) can also form high-electron-mobility transistor structures.

[0064] The aforementioned materials can be selected based on the requirements for lattice matching, bandgap width difference, and carrier mobility. The compound semiconductor stack can be undoped or may include a modulated doped layer to further adjust the channel carrier concentration. Furthermore, the stack structure is not limited to a simple two-layer structure, but can also be a multilayer composite epitaxial structure including spacer layers, capping layers, or transition layers.

[0065] In some embodiments, the barrier layer 102 is made of aluminum gallium nitride (AlN), and the channel layer 101 is made of gallium nitride (GaN). The barrier layer 102 typically has a wider bandgap than the channel layer 101. In AlGaN / GaN heterojunctions, the AlGaN layer thickness and aluminum composition are key parameters for precise control, determining the polarization electric field strength at the interface and thus controlling the device's two-dimensional electron gas (2DEG) areal density. To further improve lattice matching and electron confinement effects, the barrier layer 102 can be designed as a multilayer structure, such as including an ultrathin aluminum nitride (AlN) intercalation layer, or employing a graded composition AlGaN layer.

[0066] In some embodiments, such as Figure 5 and Figure 7 As shown, a dielectric layer 106 is disposed between the conductive interconnect structure and the barrier layer 102. This dielectric layer 106 introduces a metal-insulator-semiconductor (MIS) capacitive coupling structure, effectively suppressing gate leakage current and improving interface reliability. A wide range of materials can be selected for the dielectric layer 106, including but not limited to silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), and silicon carbonitride (SiCN). To obtain higher capacitive coupling efficiency, high-k materials are preferred, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), strontium titanate (SrTiO3), or combinations thereof.

[0067] In some embodiments, such as Figure 7 As shown, the second via penetrates the channel layer 101 and terminates at the interface between the barrier layer 102 and the channel layer 101. This deep via design ensures that the back drain electrode 109 can directly contact the highly conductive 2DEG channel in a vertical manner, minimizing the on-state resistance (Ron). To improve ohmic contact, a locally highly doped region can be introduced at the bottom interface of the via, for example, by ion implantation of silicon (Si) or germanium (Ge) followed by annealing activation.

[0068] In some embodiments, the combined device is a normally-off device. This combined device utilizes the enhancement-mode characteristics of a low-voltage E-MOSFET 105 to cut off the current path when the gate voltage is zero, thereby making the entire cascaded system normally-off.

[0069] This application also provides a method for forming a wafer-level MOS-driven compound semiconductor combination device as described above. Figure 1 A schematic diagram of the formation method is shown.

[0070] Step 1: Provide a composite substrate. The composite substrate, from its first side to its second side, includes at least a semiconductor epitaxial layer 104, a lattice buffer layer 103, and a compound semiconductor stack. The material of the semiconductor epitaxial layer 104 is different from the material of the compound semiconductor stack.

[0071] In some embodiments, in step one, such as Figure 2 As shown, the composite substrate includes, from bottom to top, a channel layer 101, a barrier layer 102, a lattice buffer layer 103, and a semiconductor epitaxial layer 104. The semiconductor epitaxial layer 104 is made of silicon. The composite substrate can be fabricated using layer transfer technology or wafer bonding technology. For example, a compound semiconductor stack (channel layer 101 and barrier layer 102) and a lattice buffer layer 103 are grown on a first substrate, a silicon layer is fabricated on a second substrate, and the two are bonded together using an oxide dielectric layer or direct bonding technology, and the auxiliary substrate is removed. Alternatively, heteroepitaxial growth can be used, where a high-quality silicon epitaxial layer is grown on top of the lattice buffer layer 103 using buffer technology or lateral epitaxial overgrowth technology.

[0072] In some embodiments, in step one, the compound semiconductor stack includes a barrier layer 102 and a channel layer 101 stacked from the first surface to the second surface.

[0073] In some embodiments, in step one, both the barrier layer 102 and the channel layer 101 are nitride semiconductor materials.

[0074] In addition to the nitride semiconductor materials described above, in other embodiments, the materials for the compound semiconductor stack (barrier layer 102 and channel layer 101) can also be selected from other III-V compound semiconductor systems, as long as they can form a heterojunction and generate conductive channels (such as 2DEG or 2DHG) through band engineering. Specific material combinations may include, but are not limited to:

[0075] Arsenide-based systems: such as gallium arsenide (GaAs), aluminum arsenide (AlAs), indium arsenide (InAs), and their ternary or quaternary alloys. Typical combinations include aluminum gallium arsenide / gallium arsenide (AlGaAs / GaAs) heterojunctions or indium aluminum arsenide / indium gallium arsenide (InAlAs / InGaAs) heterojunctions.

[0076] Phosphide-based systems: such as indium phosphide (InP), gallium phosphide (GaP), and their alloys. For example, indium gallium phosphide / gallium arsenide (InGaP / GaAs) or indium phosphide / indium gallium arsenide (InP / InGaAs).

[0077] Antimonide-based systems: such as indium antimonide (InSb), gallium antimonide (GaSb), aluminum antimonide (AlSb), and their alloys. This system is typically used for ultra-high mobility or narrow bandgap applications.

[0078] Oxide semiconductor systems include gallium oxide (Ga₂O₃), aluminum oxide (Al₂O₃), indium oxide (In₂O₃), and their alloys (such as aluminum gallium oxide, AlGaO). Wide-bandgap oxide semiconductors combined with oxides with different bandgap structures (such as Al₂O₃ or AlGaO) can also form high-electron-mobility transistor structures.

[0079] The aforementioned materials can be selected based on the requirements for lattice matching, bandgap width difference, and carrier mobility. The compound semiconductor stack can be undoped or may include a modulated doped layer to further adjust the channel carrier concentration. Furthermore, the stack structure is not limited to a simple two-layer structure, but can also be a multilayer composite epitaxial structure including spacer layers, capping layers, or transition layers.

[0080] In some embodiments, in step one, the barrier layer 102 is made of aluminum gallium nitride, and the channel layer 101 is made of gallium nitride. Compound semiconductor stack growth is typically performed on silicon, silicon carbide (SiC), or sapphire substrates using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). Precursor gases include trimethylgallium (TMGa), triethylgallium (TEGa), trimethylaluminum (TMAl), ammonia (NH3), etc. The lattice buffer layer 103 is used to filter dislocations and manage thermal stress, and typically includes a low-temperature nucleation layer (such as AlN) and a stress compensation layer (such as an AlGaN / GaN superlattice, a graded AlGaN layer, or a low-temperature GaN layer).

[0081] Step 2: Remove part of the semiconductor epitaxial layer 104 and form an enhancement-mode metal-oxide-semiconductor field-effect transistor structure 105 in the removed area. The enhancement-mode metal-oxide-semiconductor field-effect transistor structure 105 includes a source region and a gate region.

[0082] In some embodiments, in step two, such as Figure 3 As shown, a portion of the semiconductor epitaxial layer 104 is removed to form an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) structure 105. The semiconductor epitaxial layer 104 is used to fabricate the driver transistor, and the compound semiconductor stack is used to form a depletion-mode device. The enhancement-mode MOSFET 105 is manufactured in a manner fully compatible with standard CMOS production line processes. First, the active region is defined using shallow trench isolation (STI) technology. The STI filling material can be high-density plasma (HDP) oxide, flowable chemical vapor deposition (FCVD) oxide, or spin-coated glass (SOG). Subsequently, well implantation (e.g., boron or indium for P-wells, phosphorus or arsenic for N-wells) is performed to set the channel doping concentration and threshold voltage.

[0083] The formation method of the gate stack structure can be flexibly selected, mainly including the "Gate-Last" process and the "Gate-First" process.

[0084] If the "Gate-Last" process (also known as the replacement gate process) is used, a dummy gate made of polysilicon is first formed. After the source / drain processes and interlayer dielectric deposition are completed, this dummy gate is removed and replaced with a metal gate. In this process, the gate dielectric layer includes an interface layer (IL) and a high-k dielectric layer. The interface layer can be formed into silicon dioxide or silicon oxynitride through chemical oxidation or thermal oxidation. The high-k dielectric layer is formed by atomic layer deposition (ALD) or metal-organic chemical vapor deposition (MOCVD), and the material can be selected from hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), tantalum oxide (HfTaO), titanium oxide (HfTiO), zirconium oxide (HfZrO), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), or combinations thereof. The gate electrode is deposited sequentially on the High-k dielectric layer: a work function metal layer (such as TiN, TaN, TiAl for adjusting the threshold voltage) and a fill metal layer (such as Al, W or Cu).

[0085] If a "Gate-First" process is used, the manufacturing process sequentially includes gate dielectric layer formation, gate conductive material deposition, gate patterning etching, source / drain extension region (LDD) implantation, sidewall formation, and deep source / drain implantation. First, a gate dielectric layer is formed on the surface of the semiconductor epitaxial layer. For conventional polysilicon gate processes, the gate dielectric layer can be formed into silicon dioxide (SiO2) or silicon oxynitride (SiON) through thermal oxidation or plasma nitriding. For advanced high-k metal gate (HKMG) gate-first processes, atomic layer deposition (ALD) is used to form a high-dielectric-constant dielectric, with the material selected from the aforementioned hafnium oxide (HfO2)-based material system. Subsequently, a gate conductive layer is deposited on the gate dielectric layer. The conductive layer is typically composed of polysilicon (Poly-Si) or amorphous silicon (a-Si), deposited using low-pressure chemical vapor deposition (LPCVD), with silane (SiH4) or disilane (Si2H6) as the precursor. The polysilicon layer can be in-situ doped or subsequently doped by ion implantation (N-type phosphorus / arsenic doping, P-type boron doping) to reduce resistivity. In the HKMG gate-first process, one or more metal layers (such as titanium nitride TiN, tantalum nitride TaN) are deposited between the polysilicon and the high-k dielectric as diffusion barrier layers and work function adjustment layers. Next, the gate pattern is defined by photolithography, and the gate conductive layer and gate dielectric layer are anisotropically etched using reactive ion etching (RIE) or inductively coupled plasma (ICP) etching to form a gate stack structure with vertical sidewall profiles.

[0086] Regardless of the gate process used, spacer formation typically involves depositing a dielectric layer (such as silicon oxide, silicon nitride, silicon carbonitride SiCN, silicon carbonoxylate SiOC, or silicon carbonoxylate SiOCN) and then etching back. Using the patterned gate as an implantation mask, low-energy, low-dose ion implantation is performed to form a lightly doped drain (LDD) structure, designed to suppress short-channel effects. The source / drain regions are formed through high-concentration self-aligned ion implantation (such as As, P, BF2), followed by spike annealing, laser annealing (LSA), or millisecond annealing to activate impurities and repair lattice damage. To further reduce parasitic resistance, a self-aligned silicide process can also be implemented, where a low-resistance metal silicide layer is formed on top of the source, drain, and polysilicon gates through metal deposition (selected from nickel silicide NiSi, cobalt silicide CoSi, titanium silicide TiSi, or tungsten silicide WSi) and thermal reaction.

[0087] Step 3: Forming a source interconnect structure. The source interconnect structure extends from the source region to the lattice buffer layer 103, penetrates the lattice buffer layer 103, and stops at the side of the compound semiconductor stack near the first surface, thereby realizing the connection between the source region and the compound semiconductor stack.

[0088] In some embodiments, in step three, such as Figure 4 As shown, the source interconnect structure is formed using a source bus etching process.

[0089] In some embodiments, in step three, the source bus etching process controls the etching depth, allowing it to penetrate the lattice buffer layer 103 and remain on the side of the compound semiconductor stack closest to the first surface (i.e., the surface of the barrier layer 102) to form interconnect vias. This step involves high aspect ratio via etching. Inductively coupled plasma (ICP) dry etching can be used. In-situ optical emission spectroscopy can be used to monitor the intensity changes of emission lines of specific elements (such as Al or Ga) in the plasma, or self-stopping can be achieved by using different material interlayer etching selectivity ratios to ensure that the bottom surface of the via is smooth and does not damage the underlying barrier layer 102.

[0090] In some embodiments, in step three, such as Figure 5As shown, after etching to form interconnect vias and before forming conductive material, the process includes forming a dielectric layer 106 on the surface of the compound semiconductor stack exposed at the bottom of the interconnect vias. The dielectric layer 106 deposition covers not only the bottom of the vias but also the sidewalls. Atomic layer deposition (ALD) is preferably used, utilizing its surface self-limiting reaction characteristics to achieve uniform, dense, and precisely controllable film growth within deep holes. A wide range of materials can be selected for the dielectric layer 106, including standard dielectric materials, high-k materials, and their composite structures. Specifically, the dielectric layer 106 can be selected from silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOC), or silicon carbonitride (SiOCN). More preferably, a high-k dielectric material is used to obtain higher capacitive coupling efficiency and suppress leakage current. Furthermore, the dielectric layer 106 can be a single material layer or a multilayer stacked structure. After the dielectric layer 106 is formed, conductive interconnect material fills the vias. Conductive materials may include adhesion / barrier layers (such as Ti / TiN, Ta / TaN) and low-resistivity filler metals (such as W, Co, Cu, Al). The filling process may employ chemical vapor deposition (CVD) or electrochemical plating (ECP), followed by removal of excess metal from the surface via chemical mechanical polishing (CMP) or etching back.

[0091] Step 4: A first metallization structure is formed above the semiconductor epitaxial layer 104. The first metallization structure includes a gate electrode 107 connected to the gate region and a source electrode 108 connected to the source region.

[0092] In some embodiments, such as Figure 6 As shown, gate electrode 107 and source electrode 108 are formed. The first-side metallization typically employs a multilayer interconnect system. This includes depositing interlayer dielectrics (ILDs, such as TEOS oxide, FSG, low-k porous materials), photolithographically etching contact holes and trenches, and metal filling. The metallization system can be an aluminum-copper alloy (AlCu) with a titanium / titanium nitride (Ti / TiN) substrate, or a copper interconnect based on a dual damask process. Finally, a passivation layer (such as PSG, SiNx) is deposited, and pad openings are formed.

[0093] Step 5: Etch the second side of the composite substrate to form a second-side via that penetrates the bottom material of the compound semiconductor stack. The second-side via exposes the heterojunction interface inside the compound semiconductor stack.

[0094] In some embodiments, step five, the formation process of the second via includes: etching from one side of the channel layer 101 in the normally open device region, the etching depth penetrating the channel layer 101 to reach the interface between the barrier layer 102 and the channel layer 101. Before performing the back-side processing, it is typically necessary to bond the front side of the wafer to an operating substrate (such as glass or silicon wafer) using a temporary bonding material to provide mechanical support, and this may involve thinning the back-side substrate material.

[0095] Step 6: Form the second metallized electrode, such as... Figure 7 As shown, the second-side metallized electrode (i.e., drain electrode 109) fills the second-side via and covers the second side of the composite substrate, serving as the drain of the combined device. The back electrode formation prioritizes low ohmic contact resistance and high heat dissipation performance. Metal deposition includes sputtering (PVD) or evaporation to form a multilayer metal stack, typically Ti / Al / Ni / Au, Ti / Al / Mo / Au, or Ti / Al / Pt / Au. Other electrode materials well-known to those skilled in the art can also be used, without specific limitations here. After metal deposition, rapid thermal annealing (RTA) is performed in a nitrogen or protective atmosphere, with the temperature range typically optimized based on the metal system and semiconductor characteristics. Finally, the large-area back metal serves not only as the drain electrical lead but also as a highly efficient heat dissipation interface, which can be directly soldered to the package lead frame or heat sink.

[0096] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0097] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer-level MOS-driven compound semiconductor combination device, characterized in that, include: A composite substrate having a vertically stacked structure, wherein, from the first surface of the composite substrate to the second surface, there are sequentially a semiconductor epitaxial layer, a lattice buffer layer, and a compound semiconductor stack. An enhanced metal-oxide-semiconductor field-effect transistor is integrated on the semiconductor epitaxial layer; A depletion-type high electron mobility transistor, comprising the aforementioned compound semiconductor stack; The gate electrode of the enhanced metal-oxide-semiconductor field-effect transistor is led out to the first side of the combined device, and the source of the enhanced metal-oxide-semiconductor field-effect transistor is connected to the side of the compound semiconductor stack near the first side through a conductive interconnect structure that penetrates the lattice buffer layer. The second side of the combined device is provided with a drain electrode, which is connected to the internal channel of the depletion-type high electron mobility transistor through a second-side via penetrating the bottom of the compound semiconductor stack.

2. The wafer-level MOS-driven compound semiconductor combination device according to claim 1, characterized in that: The material of the semiconductor epitaxial layer is silicon.

3. The wafer-level MOS-driven compound semiconductor combination device according to claim 1, characterized in that: The compound semiconductor stack includes a barrier layer and a channel layer stacked from the first surface to the second surface.

4. The wafer-level MOS-driven compound semiconductor combination device according to claim 3, characterized in that: Both the barrier layer and the channel layer are nitride semiconductor materials.

5. The wafer-level MOS-driven compound semiconductor combination device according to claim 4, characterized in that: The barrier layer is made of aluminum gallium nitride, and the channel layer is made of gallium nitride.

6. The wafer-level MOS-driven compound semiconductor combination device according to claim 3, characterized in that: A dielectric layer is disposed between the conductive interconnect structure and the barrier layer.

7. The wafer-level MOS-driven compound semiconductor combination device according to claim 3, characterized in that: The second through-hole penetrates the channel layer and terminates at the interface between the barrier layer and the channel layer.

8. The wafer-level MOS-driven compound semiconductor combination device according to claim 1, characterized in that: The combined device is a normally off type device.

9. A method for manufacturing a wafer-level MOS-driven compound semiconductor combination device, characterized in that, At least including: Step 1: Provide a composite substrate, wherein the composite substrate, from its first surface to its second surface, includes at least a semiconductor epitaxial layer, a lattice buffer layer, and a compound semiconductor stack, wherein the material of the semiconductor epitaxial layer is different from the material of the compound semiconductor stack. Step 2: Remove part of the semiconductor epitaxial layer to form an enhancement-mode metal-oxide-semiconductor field-effect transistor structure in the removed region. The enhancement-mode metal-oxide-semiconductor field-effect transistor structure includes a source region and a gate region. Step 3: Form a source interconnect structure. The source interconnect structure extends from the source region to the lattice buffer layer, penetrates the lattice buffer layer, and stops at the side of the compound semiconductor stack near the first surface, thereby realizing the connection between the source region and the compound semiconductor stack. Step 4: Form a first-side metallization structure above the semiconductor epitaxial layer. The first-side metallization structure includes a gate electrode connected to the gate region and a source electrode connected to the source region. Step 5: Etch the second side of the composite substrate to form a second-side via that penetrates the bottom material of the compound semiconductor stack. The second-side via exposes the heterojunction interface inside the compound semiconductor stack. Step 6: Form a second metallized electrode. The second metallized electrode fills the second through-hole and covers the second side of the composite substrate, serving as the drain of the combined device.

10. The method for manufacturing a wafer-level MOS-driven compound semiconductor combination device according to claim 9, characterized in that: In step one, the material of the semiconductor epitaxial layer is silicon.

11. The method for manufacturing a wafer-level MOS-driven compound semiconductor combination device according to claim 9, characterized in that: In step one, the compound semiconductor stack includes a barrier layer and a channel layer stacked from the first surface to the second surface.

12. The method for manufacturing a wafer-level MOS-driven compound semiconductor combination device according to claim 11, characterized in that: In step one, both the barrier layer and the channel layer are nitride semiconductor materials.

13. The method for manufacturing a wafer-level MOS-driven compound semiconductor combination device according to claim 12, characterized in that: In step one, the barrier layer is made of aluminum gallium nitride, and the channel layer is made of gallium nitride.

14. The method for manufacturing a wafer-level MOS-driven compound semiconductor combination device according to claim 9, characterized in that: In step two, the semiconductor epitaxial layer is used to manufacture the driving transistor, and the compound semiconductor stack is used to form a depletion-type device.

15. The method for manufacturing a wafer-level MOS-driven compound semiconductor combination device according to claim 9, characterized in that: In step three, the source interconnect structure is formed using a source bus etching process.

16. The method for manufacturing a wafer-level MOS-driven compound semiconductor combination device according to claim 15, characterized in that: In step three, the source bus etching process controls the etching depth so that it passes through the lattice buffer layer and stops on the side of the compound semiconductor stack near the first surface to form interconnect vias.

17. The method for manufacturing a wafer-level MOS-driven compound semiconductor combination device according to claim 16, characterized in that: In step three, after etching to form the interconnect vias and before forming the conductive material, a dielectric layer is formed on the surface of the compound semiconductor stack exposed at the bottom of the interconnect vias.

18. The method for manufacturing a wafer-level MOS-driven compound semiconductor combination device according to claim 11, characterized in that: In step five, the formation process of the second via includes: etching from one side of the channel layer in the normally open device region, with the etching depth penetrating the channel layer and reaching the interface between the barrier layer and the channel layer.

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