Wafer cutting method

Abstract

The invention discloses a wafer cutting method. The wafer cutting method comprises the following steps: forming a protective layer on the front surface of a wafer; removing the part, corresponding to the scribing channel of the wafer, in the protective layer to expose the scribing channel; carrying out physical cutting on a scribing channel at the edge of the wafer along an inherent cleavage surface of the wafer, wherein the size of the physical cutting is far smaller than the diameter of the wafer; cleavage is carried out along the scribing channel, and the wafer is cut into a plurality of chips; and removing the protective layer to obtain a cut chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer dicing method. Background Technology

[0002] Chip dicing is a critical step in semiconductor manufacturing. Its function is to divide a whole wafer into independent chip units, which can then be bonded, packaged, and processed in subsequent processes. This process directly affects the yield, reliability, and production cost of the chip.

[0003] Currently, wafer dicing methods mainly include mechanical dicing, laser dicing, plasma dicing, and cleaving. Mechanical dicing uses diamond blades for scribing and splitting, which is relatively inexpensive, but it easily generates mechanical stress and microcracks in the dicing kerf. For brittle materials, this can lead to edge damage or latent fracture of the chip. Laser dicing uses a high-energy laser beam to locally heat and remove material, offering advantages such as non-contact and high precision. However, when processing low-melting-point, low-thermal-conductivity, or easily decomposed semiconductor materials, such as gallium arsenide (GaAs) or indium phosphide (InP), the slag formed by the melting and resolidification of the material can adhere to the sidewalls of the dicing kerf and the chip surface, introducing contamination that is difficult to remove and affecting subsequent packaging processes or device performance.

[0004] Cleavage cutting is a specific process for crystalline materials with obvious cleavage planes, such as III-V compound semiconductors. This method utilizes the inherent cleavage planes of the crystal, applying mechanical stress to cause the wafer to fracture along a specific crystal orientation, thereby obtaining a smooth, mirror-like separation surface. Theoretically, this avoids the heat-affected zone and slag contamination associated with laser processing. However, cleavage cutting still has significant drawbacks in practical applications: First, during the cleavage fracture process, micron or submicron-sized debris is easily generated at the fracture edge, which can splatter and contaminate adjacent chip functional areas. Second, this process requires the cutting direction to be precisely aligned with the inherent cleavage planes of the crystal; any slight misalignment can lead to a rough fracture surface, the generation of particulate matter, or even uncontrolled chip cracking, causing chip damage. Therefore, although cleavage cutting has unique advantages for specific materials, its inherent contamination risks and stringent process control requirements limit its widespread application and further improvement in yield.

[0005] In summary, the existing technology has not yet provided a wafer dicing solution that is suitable for semiconductor materials that are prone to slag or debris contamination, and can simultaneously ensure high cleanliness and high process tolerance. Summary of the Invention

[0006] This application provides a wafer dicing method that, by forming an isolation protective layer on the front side of the wafer before cleaving and performing micron-level physical dicing only at the edges, effectively prevents cleaving debris from contaminating the chip area, while providing tolerance for cleaving alignment deviations, thereby significantly improving dicing cleanliness and process yield. Simultaneously, this protective layer reduces the risk of inherent cleavage plane breakage in functional areas caused by wafer substrate defects.

[0007] This application discloses a wafer dicing method, comprising the following steps: forming a protective layer on the front side of a wafer; removing a portion of the protective layer corresponding to the scribe lines of the wafer, exposing the scribe lines; performing physical dicing along the inherent cleavage plane of the wafer on the scribe lines at the edge of the wafer, wherein the size of the physical dicing is much smaller than the diameter of the wafer; performing cleaving along the scribe lines to dice the wafer into multiple chips; and removing the protective layer to obtain the diced chips.

[0008] According to the wafer dicing method of this application, the chip area is fully covered and isolated by a protective layer, exposing only the scribing area. This physically prevents debris generated during the dicing process from entering the chip functional area. At the same time, only a very small physical cut is made at the edge of the wafer, avoiding contamination introduced by large-area mechanical contact. This achieves a dual improvement in dicing cleanliness and process tolerance.

[0009] In the wafer dicing method disclosed in this application, the wafer material includes gallium arsenide, indium phosphide, or zinc sulfide. According to the wafer dicing method of this application, for compound semiconductor materials such as gallium arsenide, indium phosphide, and zinc sulfide, which have significant crystal anisotropy, their inherent cleavage surface characteristics are fully utilized to achieve a flat dicing surface without thermal damage or microcracks, avoiding the heat-affected zone caused by laser cutting or the edge chipping defects caused by mechanical cutting.

[0010] In the wafer dicing method disclosed in this application, the thickness of the wafer is 100 μm to 800 μm, and the diameter of the wafer is greater than or equal to 2 inches. The wafer dicing method of this application is applicable to the typical thickness and size specifications of conventional compound semiconductor wafers, and also takes into account the wafer dicing requirements after thinning processes, ensuring universality and portability across different process nodes and product generations.

[0011] In the wafer dicing method disclosed in this application, the protective layer is made of organic or inorganic materials, and the thickness of the protective layer is 0.1 μm to 10 μm. According to the wafer dicing method of this application, organic materials, such as photoresist, are easy to remove by spin coating and development, while inorganic materials, such as silicon oxide or silicon nitride, have higher hardness and better compatibility with etching processes. The thickness of 0.1 to 10 μm ensures physical isolation without causing stress mismatch or difficulty in removal due to excessive film thickness, thus achieving a balance between process flexibility and protective reliability.

[0012] In the wafer dicing method disclosed in this application, the scribing track has etched grooves, which are V-grooves or U-grooves. According to the wafer dicing method of this application, by thinning or grooving the scribing track, stress concentration points are provided for subsequent cleavage fracture, thereby reducing the external force required for cleavage, reducing the amount of debris generated, and improving the consistency of the dicing. Furthermore, V-grooves can provide sharp stress concentration points, which is beneficial for cleavage to extend along a precise crystal orientation, while U-grooves, while providing stress guidance, retain a certain structural strength to avoid accidental fracture during processing or handling. The two shapes can be flexibly selected according to material properties and process requirements.

[0013] In the wafer dicing method disclosed in this application, the width of the scribe line is between 10 μm and 500 μm. According to the wafer dicing method of this application, the width range of the scribe line covers a variety of design scenarios, from the narrow scribe lines of high-density integrated chips to the wide scribe lines required for power devices. At the same time, it provides sufficient deviation tolerance for the cleavage alignment process and can avoid the breakage of non-cleavage surfaces due to alignment errors.

[0014] In the wafer dicing method disclosed in this application, the size of the physical cut is between 1 μm and 1 mm. According to the wafer dicing method of this application, by performing local cutting at the micron to sub-millimeter level at the wafer edge, an initial crack initiation point for cleavage fracture is provided. This satisfies the cleavage initiation condition and controls the contact area between the dicing blade and the wafer to the redundant area at the wafer edge, thus avoiding the introduction of contamination into most of the scribing traces and the chip area at the center of the wafer.

[0015] In the wafer dicing method disclosed in this application, the removal of the portion of the protective layer corresponding to the scribe line on the wafer is achieved by developing and / or etching the protective layer. According to the wafer dicing method of this application, for protective layers of photosensitive organic materials, the pattern can be directly obtained using an exposure and development process; for protective layers of non-photosensitive organic or inorganic materials, a photolithography mask + etching process can be used. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the steps of the wafer dicing method involved in this application;

[0017] Figure 2 A top view of a wafer with the protective layer removed from the scribing lines;

[0018] Figure 3 A side cross-sectional view of an embodiment of a wafer with the protective layer removed from the scribing traces;

[0019] Figure 4 A side cross-sectional view of another embodiment of a wafer with the protective layer on the scribing track removed;

[0020] Figure 5 Another top view of the wafer with the protective layer removed from the scribing lines. Detailed Implementation

[0021] The present application will be further described below with reference to specific embodiments and accompanying drawings. It is to be understood that the illustrative embodiments of this disclosure are merely for explaining the present application and not for limiting it. Furthermore, for ease of description, the accompanying drawings show only the parts relevant to the present application, and not all of the structures or processes.

[0022] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Although the description of this application is presented in conjunction with preferred embodiments, this does not mean that the features of this invention are limited to this embodiment. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of this application. To provide a thorough understanding of this application, many specific details will be included in the following description. This application may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of this application, some specific details will be omitted in the description. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0023] Unless the context otherwise specifies, the terms “contains,” “has,” and “includes” are synonyms. The phrase “A / B” means “A or B.” The phrase “A and / or B” means “(A and B) or (A or B).”

[0024] It should be understood that although terms such as "first," "second," etc., may be used herein to describe various components, units, or data, these components, units, or data should not be limited by these terms. These terms are used merely to distinguish one feature from another. For example, without departing from the scope of the exemplary embodiments, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature.

[0025] It should be understood that although directional terms such as "up," "down," "left," and "right" may be used here to describe the positional relationship between the various components, these directional terms are only for the convenience of understanding and are not intended to limit the scope of protection of this application.

[0026] It should be noted that in this specification, similar reference numerals and letters in the accompanying drawings indicate similar items. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic diagram illustrating the steps of the wafer dicing method involved in this application. Figure 1 As shown, the wafer dicing method involved in this application includes the following five steps:

[0029] Step S1: Form a protective layer on the front side of the wafer;

[0030] Step S2: Remove the portion of the protective layer corresponding to the scribe line on the wafer, exposing the scribe line.

[0031] Step S3: Physically cut along the inherent cleavage plane of the wafer on the scribing path at the edge of the wafer. The size of the physical cut is much smaller than the diameter of the wafer.

[0032] Step S4: Cleave along the scribing lines to cut the wafer into multiple chips;

[0033] Step S5: Remove the protective layer to obtain the cut chip.

[0034] The wafers used in this application are preferably semiconductor materials with inherent cleavage planes, especially those semiconductor materials that are prone to generating slag, debris, or thermal damage during conventional laser cutting, including but not limited to gallium arsenide (GaAs), indium phosphide (InP), or zinc sulfide (ZnS). These materials have characteristics such as low melting points, easy decomposition, and low thermal conductivity, thus causing significant slag problems during laser cutting. However, due to their excellent crystal cleavage properties, they are particularly suitable for cleavage cutting processes.

[0035] The wafer thickness in this application can be between 100μm and 800μm, a range that covers wafers processed using thinning techniques to wafers of standard thickness. The lateral dimensions of the wafers range from 2 inches and above, such as common sizes like 3 inches, 4 inches, 6 inches, 8 inches, and 12 inches. In other words, the wafer dicing method described in this application is applicable to dicing wafers of various thicknesses and lateral dimensions, from wafers to wafers of standard thickness.

[0036] Regarding step S1, a protective layer is formed on the front side of the wafer. In this application, the protective layer is a key functional layer for ensuring the cleanliness of the dicing process. Its core function is to physically isolate the chip area of ​​the wafer from debris contamination generated during the dicing process. Simultaneously, this protective layer reduces the risk of inherent dicing plane breakage in the functional area caused by defects in the wafer substrate. The materials for this protective layer can be divided into two main categories: organic materials and inorganic materials, with different materials corresponding to different formation processes.

[0037] Specifically, in this application, the organic material used as the protective layer can be a photosensitive polymer material, such as commercially available photoresist. The process for forming the protective layer typically employs spin coating, where liquid organic material is drop-coated onto the center of a wafer, and then evenly spread through high-speed rotation, followed by baking to solidify and form a solid film. Alternatively, non-photosensitive polymer materials, such as polyimide, can be used. Inorganic materials mainly include silicon dioxide (…). ), silicon nitride ( ) or aluminum oxide ( Inorganic material thin films can be fabricated using processes such as plasma-enhanced chemical vapor deposition (PECVD), sputtering, or atomic layer deposition (ALD). The thickness of the protective layer can be prepared from 0.1 μm to 10 μm. This thickness ensures physical isolation without causing stress mismatch or difficulty in removal due to excessive film thickness, thus achieving a balance between process flexibility and protective reliability.

[0038] Regarding step S2, the portion of the protective layer corresponding to the scribe lines on the wafer is removed, exposing the scribe lines. The scribe lines on a wafer, also known as dicing lines, are reserved areas located between adjacent chips on the wafer, used to separate the wafer into individual chips during the wafer dicing process. In semiconductor fabrication, the scribe lines serve as non-working areas between functional chips, providing space for dicing blades, laser beams, or cleavage stress to avoid damage to the chip areas on the wafer. For protective layers formed from photosensitive organic materials, patterning can be achieved directly through ultraviolet exposure and development processes, removing the portion of the protective layer corresponding to the scribe lines while retaining the protective layer for the chip areas. For protective layers made from non-photosensitive organic materials, such as polyimide, a layer of photoresist is coated on top as a mask. After exposure and development, the organic material is etched using the photoresist pattern as a mask (e.g., oxygen plasma etching), thereby achieving pattern transfer and exposing the scribe lines. For the protective layer of inorganic materials, the patterning can be similar to that of non-photosensitive organic materials, using photolithography masks combined with etching processes to expose the scribing lines.

[0039] In this application, the width of the scribing trace is set between 10μm and 500μm. This range of scribing trace widths covers a variety of design scenarios, from narrow scribing traces in high-density integrated chips to wide scribing traces required for power devices. At the same time, it provides sufficient tolerance for deviations in the cleavage alignment process and can avoid breakage of non-cleavage surfaces due to alignment errors.

[0040] Figure 2 A top view of a wafer with the protective layer removed from the scribe lines, wherein wafer 1 includes multiple chip regions 2 divided by scribe lines 3.

[0041] Figure 3 and Figure 4These are side cross-sectional views of two different embodiments of a wafer with the protective layer on the scribing track removed. Figure 3 In the embodiment shown, a portion of the protective layer corresponding to the scribing 3 on wafer 1 is removed, and the protective layer 4 only covers the chip area of ​​wafer 1. Figure 4 The illustrated embodiments and Figure 3 The difference is that, Figure 4 The scribe line 3 in the text is an etching groove etched downwards from the wafer surface, while Figure 3 The scribing lines do not have etched grooves. It should be noted that... Figure 4 The etching grooves shown can be etched during the wafer fabrication stage or during the removal of the protective layer on the scribing traces.

[0042] Regarding step S3, physical cutting is performed along the inherent cleavage plane of the wafer on the scribing path at the edge of the wafer, and the size of the physical cut is much smaller than the diameter of the wafer. Figure 5 Another top view of a wafer with the protective layer on the scribing traces removed, wherein wafer 1 includes a chip region 2 located at the center of the wafer ( Figure 5 The region enclosed by dark zigzag lines in the middle) and the edge region 5 located at the periphery of the wafer 1. Physical cuts are made along the inherent cleavage planes of the wafer 1 on the scribing traces in the edge region 5 of the wafer 1, for example, along... Figure 5 Physical cutting is performed in the area and direction indicated by the middle arrow. Specific physical cutting methods can include mechanical scribing / cutting using diamond or similar cutting tools, or laser cutting using a high-energy laser beam. Cutting is performed only on the scribing lines in redundant areas at the wafer edge (i.e., areas where no complete and functional chips have been fabricated), along a direction aligned with the inherent cleavage plane of the crystal. The cut is much smaller than the wafer diameter. Here, "much smaller" means the size difference is at least two orders of magnitude, or at least a hundred times. Preferably, the length of the physical cut is between 1 μm and 1 mm. This edge micro-cutting method introduces only a tiny initiation point locally on the wafer to provide precise stress guidance for subsequent cleaving, without requiring large-area mechanical scribing or laser ablation of most of the scribing line area inside the wafer. This avoids particle contamination, mechanical damage, or slag residue introduced by direct contact between the cutting tool and the chip area of ​​the wafer body, ensuring the cleanliness and precision of the cleaving process. Regarding step S4, cleaving is performed along the scribing lines to cut the wafer into multiple chips. Utilizing the anisotropic properties of wafer materials, by applying appropriate external force or temperature gradient, the cracks generated by physical cutting in step S3 are caused to propagate along the direction of scribing track 3, thereby cutting the wafer into multiple independent chips. More specifically, this can be achieved by first propagating along... Figure 5The wafer is cut into multiple strips in the transverse direction indicated by the arrows, and then micro-cutting is performed on the longitudinal scribing lines of each strip, resulting in multiple independent chips. During this process, the etching grooves in the scribing lines 3 help concentrate stress and guide crack paths, ensuring cutting accuracy. Preferably, the etching grooves in the scribing lines 3 are V-grooves or U-grooves. V-grooves provide sharp stress concentration points, which is beneficial for cleavage propagation along precise crystal orientations, while U-grooves provide stress guidance while maintaining a certain structural strength, preventing accidental breakage during processing or handling. The two shapes can be flexibly selected according to material properties and process requirements. During cleavage, the protective layer not only prevents contaminants from contaminating the chip surface, but also, through the difference in the thickness of the protective layer (the chip portion has a protective layer, while the protective layer in the scribing area is removed), provides stress guidance for cleavage fracture, facilitating the cleavage process.

[0043] Regarding step S5, the protective layer is removed to obtain the diced chip. The final step is to thoroughly remove the residual protective layer on the front side of the wafer to obtain a clean and complete chip. In this step, multiple chips after dicing can be cleaned first to remove surface contaminants, and then the protective layer can be removed. By cleaning the diced chip with the protective layer, the risk of particles and other contaminants being washed into the chip area from the scribe lines during the cleaning process is avoided. Particle contamination inside the scribe lines can be specifically removed while protecting the chip area, ensuring that the scribe lines do not become a source of contamination for subsequent processes. Cleaning can be performed by placing the diced chip with the protective layer in an acetone solution and using an ultrasonic cleaning process. For protective layers formed from organic materials such as photoresist, conventional photoresist removal processes in the art can be used, such as plasma photoresist removal. For protective layers formed from inorganic materials, such as silicon dioxide, cleaning and removal of the protective layer can be completed in a one-step wet process, for example, by immersing the diced chip in a diluted hydrofluoric acid solution. This process can achieve two functions simultaneously: on the one hand, hydrofluoric acid etching solution removes the silicon dioxide protective layer on the chip surface; on the other hand, during the removal of the protective layer, the debris generated by cleavage is carried away with the protective layer and no separate cleaning step is required.

[0044] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Where there is no conflict, the embodiments and features described in the embodiments of this application can be combined with each other. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer dicing method, characterized in that, Includes the following steps: A protective layer is formed on the front side of the wafer; Remove the portion of the protective layer corresponding to the scribing traces on the wafer to expose the scribing traces; Physical cuts are made along the inherent cleavage plane of the wafer on the scribing marks at the edge of the wafer, and the size of the physical cuts is much smaller than the diameter of the wafer. The wafer is cut into multiple chips by cleaving along the scribing lines; Remove the protective layer to obtain the cut chip.

2. The wafer dicing method according to claim 1, characterized in that, The wafer is made of materials including gallium arsenide, indium phosphide, or zinc sulfide.

3. The wafer dicing method according to claim 1, characterized in that, The wafer has a thickness of 100 μm to 800 μm and a diameter of 2 inches or more.

4. The wafer dicing method according to claim 1, characterized in that, The protective layer is made of organic or inorganic materials, and its thickness is 0.1 μm to 10 μm.

5. The wafer dicing method according to claim 1, characterized in that, The scribing has etched grooves.

6. The wafer dicing method according to claim 5, characterized in that, The etching groove is a V-shaped groove or a U-shaped groove.

7. The wafer dicing method according to claim 1, characterized in that, The width of the scribing line is between 10μm and 500μm.

8. The wafer dicing method according to claim 1, characterized in that, The size of the physical cut is between 1μm and 1mm.

9. The wafer dicing method according to claim 1, characterized in that, The removal of the portion of the protective layer corresponding to the scribe line on the wafer is achieved by developing and / or etching the protective layer.

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